diff options
169 files changed, 1065 insertions, 390 deletions
diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index 3f4266637733..84353fd09428 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -35,7 +35,7 @@ properties: reg: minItems: 2 - maxItems: 3 + maxItems: 4 "#clock-cells": description: @@ -43,6 +43,10 @@ properties: clocks. const: 1 + '#reset-cells': + description: ID of the controller reset line + const: 1 + required: - compatible - reg @@ -60,6 +64,8 @@ allOf: - description: scu base address - description: misc scu base address + '#reset-cells': false + - if: properties: compatible: @@ -70,6 +76,7 @@ allOf: items: - description: scu base address - description: misc scu base address + - description: reset base address - description: pb scu base address additionalProperties: false @@ -83,3 +90,19 @@ examples: <0x1fb00000 0x1000>; #clock-cells = <1>; }; + + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + scuclk: clock-controller@1fa20000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fa20000 0x0 0x400>, + <0x0 0x1fb00000 0x0 0x90>, + <0x0 0x1fb00830 0x0 0x8>, + <0x0 0x1fbe3400 0x0 0xfc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml new file mode 100644 index 000000000000..97b96a1a5825 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Legacy Clock Block on Freescale QorIQ Platforms + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + These nodes are deprecated. Kernels should continue to support + device trees with these nodes, but new device trees should not use them. + + Most of the bindings are from the common clock binding[1]. + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + enum: + - fsl,qoriq-core-pll-1.0 + - fsl,qoriq-core-pll-2.0 + - fsl,qoriq-core-mux-1.0 + - fsl,qoriq-core-mux-2.0 + - fsl,qoriq-sysclk-1.0 + - fsl,qoriq-sysclk-2.0 + - fsl,qoriq-platform-pll-1.0 + - fsl,qoriq-platform-pll-2.0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + clock-output-names: + minItems: 1 + maxItems: 8 + + '#clock-cells': + minimum: 0 + maximum: 1 + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,qoriq-sysclk-1.0 + - fsl,qoriq-sysclk-2.0 + then: + properties: + '#clock-cells': + const: 0 + + - if: + properties: + compatible: + contains: + enum: + - fsl,qoriq-core-pll-1.0 + - fsl,qoriq-core-pll-2.0 + then: + properties: + '#clock-cells': + const: 1 + description: | + * 0 - equal to the PLL frequency + * 1 - equal to the PLL frequency divided by 2 + * 2 - equal to the PLL frequency divided by 4 + diff --git a/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml new file mode 100644 index 000000000000..95a3e3b24267 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml @@ -0,0 +1,207 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock Block on Freescale QorIQ Platforms + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + Freescale QorIQ chips take primary clocking input from the external + SYSCLK signal. The SYSCLK input (frequency) is multiplied using + multiple phase locked loops (PLL) to create a variety of frequencies + which can then be passed to a variety of internal logic, including + cores and peripheral IP blocks. + Please refer to the Reference Manual for details. + + All references to "1.0" and "2.0" refer to the QorIQ chassis version to + which the chip complies. + + Chassis Version Example Chips + --------------- ------------- + 1.0 p4080, p5020, p5040 + 2.0 t4240 + + Clock Provider + + The clockgen node should act as a clock provider, though in older device + trees the children of the clockgen node are the clock providers. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,p2041-clockgen + - fsl,p3041-clockgen + - fsl,p4080-clockgen + - fsl,p5020-clockgen + - fsl,p5040-clockgen + - const: fsl,qoriq-clockgen-1.0 + - items: + - enum: + - fsl,t1023-clockgen + - fsl,t1024-clockgen + - fsl,t1040-clockgen + - fsl,t1042-clockgen + - fsl,t2080-clockgen + - fsl,t2081-clockgen + - fsl,t4240-clockgen + - const: fsl,qoriq-clockgen-2.0 + - items: + - enum: + - fsl,b4420-clockgen + - fsl,b4860-clockgen + - const: fsl,b4-clockgen + - items: + - enum: + - fsl,ls1012a-clockgen + - fsl,ls1021a-clockgen + - fsl,ls1028a-clockgen + - fsl,ls1043a-clockgen + - fsl,ls1046a-clockgen + - fsl,ls1088a-clockgen + - fsl,ls2080a-clockgen + - fsl,lx2160a-clockgen + + reg: + maxItems: 1 + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + '#clock-cells': + const: 2 + description: | + The first cell of the clock specifier is the clock type, and the + second cell is the clock index for the specified type. + + Type# Name Index Cell + 0 sysclk must be 0 + 1 cmux index (n in CLKCnCSR) + 2 hwaccel index (n in CLKCGnHWACSR) + 3 fman 0 for fm1, 1 for fm2 + 4 platform pll n=pll/(n+1). For example, when n=1, + that means output_freq=PLL_freq/2. + 5 coreclk must be 0 + + clock-frequency: + description: Input system clock frequency (SYSCLK) + + clocks: + items: + - description: + sysclk may be provided as an input clock. Either clock-frequency + or clocks must be provided. + - description: + A second input clock, called "coreclk", may be provided if + core PLLs are based on a different input clock from the + platform PLL. + minItems: 1 + + clock-names: + items: + - const: sysclk + - const: coreclk + +patternProperties: + '^mux[0-9]@[a-f0-9]+$': + deprecated: true + $ref: fsl,qoriq-clock-legacy.yaml + + '^sysclk(-[a-z0-9]+)?$': + deprecated: true + $ref: fsl,qoriq-clock-legacy.yaml + + '^pll[0-9]@[a-f0-9]+$': + deprecated: true + $ref: fsl,qoriq-clock-legacy.yaml + + '^platform\-pll@[a-f0-9]+$': + deprecated: true + $ref: fsl,qoriq-clock-legacy.yaml + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + /* clock provider example */ + global-utilities@e1000 { + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; + reg = <0xe1000 0x1000>; + clock-frequency = <133333333>; + #clock-cells = <2>; + }; + + - | + /* Legacy example */ + global-utilities@e1000 { + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; + reg = <0xe1000 0x1000>; + ranges = <0x0 0xe1000 0x1000>; + clock-frequency = <133333333>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <2>; + + sysclk: sysclk { + compatible = "fsl,qoriq-sysclk-1.0"; + clock-output-names = "sysclk"; + #clock-cells = <0>; + }; + + pll0: pll0@800 { + compatible = "fsl,qoriq-core-pll-1.0"; + reg = <0x800 0x4>; + #clock-cells = <1>; + clocks = <&sysclk>; + clock-output-names = "pll0", "pll0-div2"; + }; + + pll1: pll1@820 { + compatible = "fsl,qoriq-core-pll-1.0"; + reg = <0x820 0x4>; + #clock-cells = <1>; + clocks = <&sysclk>; + clock-output-names = "pll1", "pll1-div2"; + }; + + mux0: mux0@0 { + compatible = "fsl,qoriq-core-mux-1.0"; + reg = <0x0 0x4>; + #clock-cells = <0>; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; + clock-output-names = "cmux0"; + }; + + mux1: mux1@20 { + compatible = "fsl,qoriq-core-mux-1.0"; + reg = <0x20 0x4>; + #clock-cells = <0>; + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; + clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; + clock-output-names = "cmux1"; + }; + + platform-pll@c00 { + #clock-cells = <1>; + reg = <0xc00 0x4>; + compatible = "fsl,qoriq-platform-pll-1.0"; + clocks = <&sysclk>; + clock-output-names = "platform-pll", "platform-pll-div2"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml index c77111d10f90..9c3913f9092c 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml @@ -14,9 +14,11 @@ maintainers: properties: compatible: - enum: - - mediatek,mt7622-pciesys - - mediatek,mt7629-pciesys + oneOf: + - items: + - const: mediatek,mt7622-pciesys + - const: syscon + - const: mediatek,mt7629-pciesys reg: maxItems: 1 @@ -38,7 +40,7 @@ additionalProperties: false examples: - | clock-controller@1a100800 { - compatible = "mediatek,mt7622-pciesys"; + compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0x1a100800 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml index 4cf8d3af9803..db13d51a4903 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml @@ -39,6 +39,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml index 0af1c569eb32..d786f1e2d007 100644 --- a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml @@ -40,38 +40,11 @@ required: additionalProperties: false examples: - # Clock controller node: - | - m10v-clk-ctrl@1d021000 { + clock-controller@1d021000 { compatible = "socionext,milbeaut-m10v-ccu"; reg = <0x1d021000 0x4000>; #clock-cells = <1>; clocks = <&clki40mhz>; }; - - # Required an external clock for Clock controller node: - - | - clocks { - clki40mhz: clki40mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - }; - /* other clocks */ - }; - - # The clock consumer shall specify the desired clock-output of the clock - # controller as below by specifying output-id in its "clk" phandle cell. - # 2: uart - # 4: 32-bit timer - # 7: UHS-I/II - - | - serial@1e700010 { - compatible = "socionext,milbeaut-usio-uart"; - reg = <0x1e700010 0x10>; - interrupts = <0 141 0x4>, <0 149 0x4>; - interrupt-names = "rx", "tx"; - clocks = <&clk 2>; - }; - ... diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt deleted file mode 100644 index 10119d9ef4b1..000000000000 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ /dev/null @@ -1,212 +0,0 @@ -* Clock Block on Freescale QorIQ Platforms - -Freescale QorIQ chips take primary clocking input from the external -SYSCLK signal. The SYSCLK input (frequency) is multiplied using -multiple phase locked loops (PLL) to create a variety of frequencies -which can then be passed to a variety of internal logic, including -cores and peripheral IP blocks. -Please refer to the Reference Manual for details. - -All references to "1.0" and "2.0" refer to the QorIQ chassis version to -which the chip complies. - -Chassis Version Example Chips ---------------- ------------- -1.0 p4080, p5020, p5040 -2.0 t4240, b4860 - -1. Clock Block Binding - -Required properties: -- compatible: Should contain a chip-specific clock block compatible - string and (if applicable) may contain a chassis-version clock - compatible string. - - Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: - * "fsl,p2041-clockgen" - * "fsl,p3041-clockgen" - * "fsl,p4080-clockgen" - * "fsl,p5020-clockgen" - * "fsl,p5040-clockgen" - * "fsl,t1023-clockgen" - * "fsl,t1024-clockgen" - * "fsl,t1040-clockgen" - * "fsl,t1042-clockgen" - * "fsl,t2080-clockgen" - * "fsl,t2081-clockgen" - * "fsl,t4240-clockgen" - * "fsl,b4420-clockgen" - * "fsl,b4860-clockgen" - * "fsl,ls1012a-clockgen" - * "fsl,ls1021a-clockgen" - * "fsl,ls1028a-clockgen" - * "fsl,ls1043a-clockgen" - * "fsl,ls1046a-clockgen" - * "fsl,ls1088a-clockgen" - * "fsl,ls2080a-clockgen" - * "fsl,lx2160a-clockgen" - Chassis-version clock strings include: - * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks - * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks -- reg: Describes the address of the device's resources within the - address space defined by its parent bus, and resource zero - represents the clock register set - -Optional properties: -- ranges: Allows valid translation between child's address space and - parent's. Must be present if the device has sub-nodes. -- #address-cells: Specifies the number of cells used to represent - physical base addresses. Must be present if the device has - sub-nodes and set to 1 if present -- #size-cells: Specifies the number of cells used to represent - the size of an address. Must be present if the device has - sub-nodes and set to 1 if present -- clock-frequency: Input system clock frequency (SYSCLK) -- clocks: If clock-frequency is not specified, sysclk may be provided - as an input clock. Either clock-frequency or clocks must be - provided. - A second input clock, called "coreclk", may be provided if - core PLLs are based on a different input clock from the - platform PLL. -- clock-names: Required if a coreclk is present. Valid names are - "sysclk" and "coreclk". - -2. Clock Provider - -The clockgen node should act as a clock provider, though in older device -trees the children of the clockgen node are the clock providers. - -When the clockgen node is a clock provider, #clock-cells = <2>. -The first cell of the clock specifier is the clock type, and the -second cell is the clock index for the specified type. - - Type# Name Index Cell - 0 sysclk must be 0 - 1 cmux index (n in CLKCnCSR) - 2 hwaccel index (n in CLKCGnHWACSR) - 3 fman 0 for fm1, 1 for fm2 - 4 platform pll n=pll/(n+1). For example, when n=1, - that means output_freq=PLL_freq/2. - 5 coreclk must be 0 - -3. Example - - clockgen: global-utilities@e1000 { - compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; - clock-frequency = <133333333>; - reg = <0xe1000 0x1000>; - #clock-cells = <2>; - }; - - fman@400000 { - ... - clocks = <&clockgen 3 0>; - ... - }; -} -4. Legacy Child Nodes - -NOTE: These nodes are deprecated. Kernels should continue to support -device trees with these nodes, but new device trees should not use them. - -Most of the bindings are from the common clock binding[1]. - [1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : Should include one of the following: - * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) - * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) - * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) - * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) - * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). - It takes parent's clock-frequency as its clock. - * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). - It takes parent's clock-frequency as its clock. - * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) - * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) -- #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single - clock-specifier cell may take the following values: - * 0 - equal to the PLL frequency - * 1 - equal to the PLL frequency divided by 2 - * 2 - equal to the PLL frequency divided by 4 - -Recommended properties: -- clocks: Should be the phandle of input parent clock -- clock-names: From common clock binding, indicates the clock name -- clock-output-names: From common clock binding, indicates the names of - output clocks -- reg: Should be the offset and length of clock block base address. - The length should be 4. - -Legacy Example: -/ { - clockgen: global-utilities@e1000 { - compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; - ranges = <0x0 0xe1000 0x1000>; - clock-frequency = <133333333>; - reg = <0xe1000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - sysclk: sysclk { - #clock-cells = <0>; - compatible = "fsl,qoriq-sysclk-1.0"; - clock-output-names = "sysclk"; - }; - - pll0: pll0@800 { - #clock-cells = <1>; - reg = <0x800 0x4>; - compatible = "fsl,qoriq-core-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "pll0", "pll0-div2"; - }; - - pll1: pll1@820 { - #clock-cells = <1>; - reg = <0x820 0x4>; - compatible = "fsl,qoriq-core-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "pll1", "pll1-div2"; - }; - - mux0: mux0@0 { - #clock-cells = <0>; - reg = <0x0 0x4>; - compatible = "fsl,qoriq-core-mux-1.0"; - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; - clock-output-names = "cmux0"; - }; - - mux1: mux1@20 { - #clock-cells = <0>; - reg = <0x20 0x4>; - compatible = "fsl,qoriq-core-mux-1.0"; - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; - clock-output-names = "cmux1"; - }; - - platform-pll: platform-pll@c00 { - #clock-cells = <1>; - reg = <0xc00 0x4>; - compatible = "fsl,qoriq-platform-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "platform-pll", "platform-pll-div2"; - }; - }; -}; - -Example for legacy clock consumer: - -/ { - cpu0: PowerPC,e5500@0 { - ... - clocks = <&mux0>; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt deleted file mode 100644 index aaaf02ca2a6a..000000000000 --- a/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt +++ /dev/null @@ -1,63 +0,0 @@ -Spreadtrum SC9860 Clock Binding ------------------------- - -Required properties: -- compatible: should contain the following compatible strings: - - "sprd,sc9860-pmu-gate" - - "sprd,sc9860-pll" - - "sprd,sc9860-ap-clk" - - "sprd,sc9860-aon-prediv" - - "sprd,sc9860-apahb-gate" - - "sprd,sc9860-aon-gate" - - "sprd,sc9860-aonsecure-clk" - - "sprd,sc9860-agcp-gate" - - "sprd,sc9860-gpu-clk" - - "sprd,sc9860-vsp-clk" - - "sprd,sc9860-vsp-gate" - - "sprd,sc9860-cam-clk" - - "sprd,sc9860-cam-gate" - - "sprd,sc9860-disp-clk" - - "sprd,sc9860-disp-gate" - - "sprd,sc9860-apapb-gate" - -- #clock-cells: must be 1 - -- clocks : Should be the input parent clock(s) phandle for the clock, this - property here just simply shows which clock group the clocks' - parents are in, since each clk node would represent many clocks - which are defined in the driver. The detailed dependency - relationship (i.e. how many parents and which are the parents) - are implemented in driver code. - -Optional properties: - -- reg: Contain the registers base address and length. It must be configured - only if no 'sprd,syscon' under the node. - -- sprd,syscon: phandle to the syscon which is in the same address area with - the clock, and so we can get regmap for the clocks from the - syscon device. - -Example: - - pmu_gate: pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - sprd,syscon = <&pmu_regs>; - clocks = <&ext_26m>; - #clock-cells = <1>; - }; - - pll: pll { - compatible = "sprd,sc9860-pll"; - sprd,syscon = <&ana_regs>; - clocks = <&pmu_gate 0>; - #clock-cells = <1>; - }; - - ap_clk: clock-controller@20000000 { - compatible = "sprd,sc9860-ap-clk"; - reg = <0 0x20000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>, - <&pmu_gate 0>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml new file mode 100644 index 000000000000..502cd723511f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 clock + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + compatible: + enum: + - sprd,sc9860-agcp-gate + - sprd,sc9860-aonsecure-clk + - sprd,sc9860-aon-gate + - sprd,sc9860-aon-prediv + - sprd,sc9860-apahb-gate + - sprd,sc9860-apapb-gate + - sprd,sc9860-ap-clk + - sprd,sc9860-cam-clk + - sprd,sc9860-cam-gate + - sprd,sc9860-disp-clk + - sprd,sc9860-disp-gate + - sprd,sc9860-gpu-clk + - sprd,sc9860-pll + - sprd,sc9860-pmu-gate + - sprd,sc9860-vsp-clk + - sprd,sc9860-vsp-gate + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + '#clock-cells': + const: 1 + + sprd,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the syscon which is in the same address area with the + clock, and so we can get regmap for the clocks from the syscon device + +required: + - compatible + - clocks + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-agcp-gate + - sprd,sc9860-aon-gate + - sprd,sc9860-apahb-gate + - sprd,sc9860-apapb-gate + - sprd,sc9860-cam-gate + - sprd,sc9860-disp-gate + - sprd,sc9860-gpu-clk + - sprd,sc9860-pll + - sprd,sc9860-pmu-gate + - sprd,sc9860-vsp-gate + then: + properties: + clocks: + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-aonsecure-clk + - sprd,sc9860-cam-clk + - sprd,sc9860-disp-clk + - sprd,sc9860-vsp-clk + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-aon-prediv + - sprd,sc9860-ap-clk + then: + properties: + clocks: + minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-aonsecure-clk + - sprd,sc9860-aon-prediv + - sprd,sc9860-ap-clk + - sprd,sc9860-cam-clk + - sprd,sc9860-disp-clk + - sprd,sc9860-gpu-clk + - sprd,sc9860-vsp-clk + then: + required: + - reg + properties: + sprd,syscon: false + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-agcp-gate + - sprd,sc9860-aon-gate + - sprd,sc9860-apahb-gate + - sprd,sc9860-apapb-gate + - sprd,sc9860-cam-gate + - sprd,sc9860-disp-gate + - sprd,sc9860-pll + - sprd,sc9860-pmu-gate + - sprd,sc9860-vsp-gate + then: + required: + - sprd,syscon + properties: + reg: false + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmu-gate { + compatible = "sprd,sc9860-pmu-gate"; + clocks = <&ext_26m>; + #clock-cells = <1>; + sprd,syscon = <&pmu_regs>; + }; + + clock-controller@20000000 { + compatible = "sprd,sc9860-ap-clk"; + reg = <0 0x20000000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>, <&pmu_gate 0>; + #clock-cells = <1>; + }; + }; +... diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3e9099504fad..3c3e0b969020 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -514,6 +514,7 @@ config CLK_KUNIT_TEST config CLK_GATE_KUNIT_TEST tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS depends on KUNIT + depends on !S390 default KUNIT_ALL_TESTS help Kunit test for the basic clk gate type. diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index ccc394692671..22fbea61c3dc 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -5,7 +5,11 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/property.h> +#include <linux/reset-controller.h> #include <dt-bindings/clock/en7523-clk.h> +#include <dt-bindings/reset/airoha,en7581-reset.h> + +#define RST_NR_PER_BANK 32 #define REG_PCI_CONTROL 0x88 #define REG_PCI_CONTROL_PERSTOUT BIT(29) @@ -33,13 +37,14 @@ #define REG_PCIE1_MEM_MASK 0x0c #define REG_PCIE2_MEM 0x10 #define REG_PCIE2_MEM_MASK 0x14 -#define REG_PCIE_RESET_OPEN_DRAIN 0x018c -#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0) #define REG_NP_SCU_PCIC 0x88 #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) +#define REG_RST_CTRL2 0x00 +#define REG_RST_CTRL1 0x04 + struct en_clk_desc { int id; const char *name; @@ -57,6 +62,7 @@ struct en_clk_desc { u8 div_shift; u16 div_val0; u8 div_step; + u8 div_offset; }; struct en_clk_gate { @@ -64,10 +70,21 @@ struct en_clk_gate { struct clk_hw hw; }; +struct en_rst_data { + const u16 *bank_ofs; + const u16 *idx_map; + void __iomem *base; + struct reset_controller_dev rcdev; +}; + struct en_clk_soc_data { const struct clk_ops pcie_ops; - int (*hw_init)(struct platform_device *pdev, void __iomem *base, - void __iomem *np_base); + struct { + const u16 *bank_ofs; + const u16 *idx_map; + u16 idx_map_nr; + } reset; + int (*hw_init)(struct platform_device *pdev, void __iomem *np_base); }; static const u32 gsw_base[] = { 400000000, 500000000 }; @@ -90,6 +107,7 @@ static const struct en_clk_desc en7523_base_clks[] = { .div_bits = 3, .div_shift = 0, .div_step = 1, + .div_offset = 1, }, { .id = EN7523_CLK_EMI, .name = "emi", @@ -103,6 +121,7 @@ static const struct en_clk_desc en7523_base_clks[] = { .div_bits = 3, .div_shift = 0, .div_step = 1, + .div_offset = 1, }, { .id = EN7523_CLK_BUS, .name = "bus", @@ -116,6 +135,7 @@ static const struct en_clk_desc en7523_base_clks[] = { .div_bits = 3, .div_shift = 0, .div_step = 1, + .div_offset = 1, }, { .id = EN7523_CLK_SLIC, .name = "slic", @@ -156,18 +176,82 @@ static const struct en_clk_desc en7523_base_clks[] = { .div_bits = 3, .div_shift = 0, .div_step = 1, + .div_offset = 1, }, { .id = EN7523_CLK_CRYPTO, .name = "crypto", .base_reg = REG_CRYPTO_CLKSRC, .base_bits = 1, - .base_shift = 8, + .base_shift = 0, .base_values = emi_base, .n_base_values = ARRAY_SIZE(emi_base), } }; +static const u16 en7581_rst_ofs[] = { + REG_RST_CTRL2, + REG_RST_CTRL1, +}; + +static const u16 en7581_rst_map[] = { + /* RST_CTRL2 */ + [EN7581_XPON_PHY_RST] = 0, + [EN7581_CPU_TIMER2_RST] = 2, + [EN7581_HSUART_RST] = 3, + [EN7581_UART4_RST] = 4, + [EN7581_UART5_RST] = 5, + [EN7581_I2C2_RST] = 6, + [EN7581_XSI_MAC_RST] = 7, + [EN7581_XSI_PHY_RST] = 8, + [EN7581_NPU_RST] = 9, + [EN7581_I2S_RST] = 10, + [EN7581_TRNG_RST] = 11, + [EN7581_TRNG_MSTART_RST] = 12, + [EN7581_DUAL_HSI0_RST] = 13, + [EN7581_DUAL_HSI1_RST] = 14, + [EN7581_HSI_RST] = 15, + [EN7581_DUAL_HSI0_MAC_RST] = 16, + [EN7581_DUAL_HSI1_MAC_RST] = 17, + [EN7581_HSI_MAC_RST] = 18, + [EN7581_WDMA_RST] = 19, + [EN7581_WOE0_RST] = 20, + [EN7581_WOE1_RST] = 21, + [EN7581_HSDMA_RST] = 22, + [EN7581_TDMA_RST] = 24, + [EN7581_EMMC_RST] = 25, + [EN7581_SOE_RST] = 26, + [EN7581_PCIE2_RST] = 27, + [EN7581_XFP_MAC_RST] = 28, + [EN7581_USB_HOST_P1_RST] = 29, + [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, + /* RST_CTRL1 */ + [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, + [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, + [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, + [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, + [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, + [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, + [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, + [EN7581_UART_RST] = RST_NR_PER_BANK + 12, + [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, + [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, + [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, + [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, + [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, + [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, + [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, + [EN7581_FE_RST] = RST_NR_PER_BANK + 21, + [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, + [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, + [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, + [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, + [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, + [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, + [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, + [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, +}; + static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) { const struct en_clk_desc *desc = &en7523_base_clks[i]; @@ -202,7 +286,7 @@ static u32 en7523_get_div(void __iomem *base, int i) if (!val && desc->div_val0) return desc->div_val0; - return (val + 1) * desc->div_step; + return (val + desc->div_offset) * desc->div_step; } static int en7523_pci_is_enabled(struct clk_hw *hw) @@ -279,9 +363,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, cg->base = np_base; cg->hw.init = &init; - if (init.ops->disable) - init.ops->disable(&cg->hw); - init.ops->unprepare(&cg->hw); + if (init.ops->unprepare) + init.ops->unprepare(&cg->hw); if (clk_hw_register(dev, &cg->hw)) return NULL; @@ -299,23 +382,6 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) return (val & mask) == mask; } -static int en7581_pci_prepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - usleep_range(5000, 10000); - - return 0; -} - static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -332,23 +398,6 @@ static int en7581_pci_enable(struct clk_hw *hw) return 0; } -static void en7581_pci_unprepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val | mask, np_base + REG_RESET_CONTROL1); - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2; - writel(val | mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - msleep(100); -} - static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -364,13 +413,12 @@ static void en7581_pci_disable(struct clk_hw *hw) } static int en7581_clk_hw_init(struct platform_device *pdev, - void __iomem *base, void __iomem *np_base) { void __iomem *pb_base; u32 val; - pb_base = devm_platform_ioremap_resource(pdev, 2); + pb_base = devm_platform_ioremap_resource(pdev, 3); if (IS_ERR(pb_base)) return PTR_ERR(pb_base); @@ -387,10 +435,6 @@ static int en7581_clk_hw_init(struct platform_device *pdev, writel(0x28000000, pb_base + REG_PCIE2_MEM); writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK); - val = readl(base + REG_PCIE_RESET_OPEN_DRAIN); - writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK, - base + REG_PCIE_RESET_OPEN_DRAIN); - return 0; } @@ -423,6 +467,95 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } +static int en7523_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); + void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 val; + + val = readl(addr); + if (assert) + val |= BIT(id % RST_NR_PER_BANK); + else + val &= ~BIT(id % RST_NR_PER_BANK); + writel(val, addr); + + return 0; +} + +static int en7523_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return en7523_reset_update(rcdev, id, true); +} + +static int en7523_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return en7523_reset_update(rcdev, id, false); +} + +static int en7523_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); + void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; + + return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); +} + +static int en7523_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); + + if (reset_spec->args[0] >= rcdev->nr_resets) + return -EINVAL; + + return rst_data->idx_map[reset_spec->args[0]]; +} + +static const struct reset_control_ops en7523_reset_ops = { + .assert = en7523_reset_assert, + .deassert = en7523_reset_deassert, + .status = en7523_reset_status, +}; + +static int en7523_reset_register(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data) +{ + struct device *dev = &pdev->dev; + struct en_rst_data *rst_data; + void __iomem *base; + + /* no reset lines available */ + if (!soc_data->reset.idx_map_nr) + return 0; + + base = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(base)) + return PTR_ERR(base); + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->bank_ofs = soc_data->reset.bank_ofs; + rst_data->idx_map = soc_data->reset.idx_map; + rst_data->base = base; + + rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr; + rst_data->rcdev.of_xlate = en7523_reset_xlate; + rst_data->rcdev.ops = &en7523_reset_ops; + rst_data->rcdev.of_node = dev->of_node; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.dev = dev; + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int en7523_clk_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -441,7 +574,7 @@ static int en7523_clk_probe(struct platform_device *pdev) soc_data = device_get_match_data(&pdev->dev); if (soc_data->hw_init) { - r = soc_data->hw_init(pdev, base, np_base); + r = soc_data->hw_init(pdev, np_base); if (r) return r; } @@ -456,11 +589,17 @@ static int en7523_clk_probe(struct platform_device *pdev) r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); + return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n", + pdev->name); + + r = en7523_reset_register(pdev, soc_data); + if (r) { + of_clk_del_provider(node); + return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n", + pdev->name); + } - return r; + return 0; } static const struct en_clk_soc_data en7523_data = { @@ -474,11 +613,14 @@ static const struct en_clk_soc_data en7523_data = { static const struct en_clk_soc_data en7581_data = { .pcie_ops = { .is_enabled = en7581_pci_is_enabled, - .prepare = en7581_pci_prepare, .enable = en7581_pci_enable, - .unprepare = en7581_pci_unprepare, .disable = en7581_pci_disable, }, + .reset = { + .bank_ofs = en7581_rst_ofs, + .idx_map = en7581_rst_map, + .idx_map_nr = ARRAY_SIZE(en7581_rst_map), + }, .hw_init = en7581_clk_hw_init, }; diff --git a/drivers/clk/clk-fractional-divider_test.c b/drivers/clk/clk-fractional-divider_test.c index 929eec927548..25fa35d89c1a 100644 --- a/drivers/clk/clk-fractional-divider_test.c +++ b/drivers/clk/clk-fractional-divider_test.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Kunit test for clock fractional divider + * Kunit tests for clk fractional divider */ #include <linux/clk-provider.h> #include <kunit/test.h> @@ -144,4 +144,5 @@ static struct kunit_suite clk_fd_approximation_suite = { kunit_test_suites( &clk_fd_approximation_suite ); +MODULE_DESCRIPTION("Kunit tests for clk fractional divider"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/clk-gate_test.c b/drivers/clk/clk-gate_test.c index c96d93b19ddf..e276cd974750 100644 --- a/drivers/clk/clk-gate_test.c +++ b/drivers/clk/clk-gate_test.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Kunit test for clk gate basic type + * Kunit tests for clk gate */ #include <linux/clk.h> #include <linux/clk-provider.h> @@ -461,4 +461,5 @@ kunit_test_suites( &clk_gate_test_hiword_suite, &clk_gate_test_enabled_suite ); +MODULE_DESCRIPTION("Kunit tests for clk gate"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 39e2b5ff4f51..fbbea66d9cba 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Kunit test for clk rate management + * Kunit tests for clk framework */ #include <linux/clk.h> #include <linux/clk-provider.h> @@ -2674,4 +2674,5 @@ kunit_test_suites( &clk_single_parent_mux_test_suite, &clk_uncached_test_suite ); +MODULE_DESCRIPTION("Kunit tests for clk framework"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index 27eecb6d3a53..15859132c769 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -165,4 +165,6 @@ static struct platform_driver clk_mt2701_aud_drv = { }, }; module_platform_driver(clk_mt2701_aud_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/clk-mt2701-bdp.c index b25703ec8dc0..e203dca70786 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -106,4 +106,6 @@ static struct platform_driver clk_mt2701_bdp_drv = { }, }; module_platform_driver(clk_mt2701_bdp_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 BDP clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 056d1e8459da..f6e1fdc9ee0a 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -60,4 +60,6 @@ static struct platform_driver clk_mt2701_eth_drv = { }, }; module_platform_driver(clk_mt2701_eth_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 Ethernet clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index d25687f6c9b4..5e04975433ea 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -57,4 +57,6 @@ static struct platform_driver clk_mt2701_g3d_drv = { }, }; module_platform_driver(clk_mt2701_g3d_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 GPU g3d clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index cbd5ece3e9e9..c7b38d066403 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,4 +57,6 @@ static struct platform_driver clk_mt2701_hif_drv = { }, }; module_platform_driver(clk_mt2701_hif_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 HIFSYS clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/clk-mt2701-img.c index 2768360b213e..ce13b79a7994 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -54,4 +54,6 @@ static struct platform_driver clk_mt2701_img_drv = { }, }; module_platform_driver(clk_mt2701_img_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/clk-mt2701-mm.c index 2b990b5a0422..903592be56b5 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -87,4 +87,6 @@ static struct platform_driver clk_mt2701_mm_drv = { .id_table = clk_mt2701_mm_id_table, }; module_platform_driver(clk_mt2701_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 MultiMedia ddp clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/clk-mt2701-vdec.c index 57711b953b7f..591091fb2151 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -59,4 +59,6 @@ static struct platform_driver clk_mt2701_vdec_drv = { }, }; module_platform_driver(clk_mt2701_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 12d9560eb4ba..1e88ad8b93f4 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -1037,4 +1037,6 @@ static int __init clk_mt2701_init(void) } arch_initcall(clk_mt2701_init); + +MODULE_DESCRIPTION("MediaTek MT2701 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c index 43272dc744c7..66987d205eee 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -163,4 +163,6 @@ static struct platform_driver clk_mt2712_apmixed_drv = { }, }; module_platform_driver(clk_mt2712_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT2712 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/clk-mt2712-bdp.c index 1b54b1f3808d..93c5453e4392 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -76,4 +76,6 @@ static struct platform_driver clk_mt2712_bdp_drv = { }, }; module_platform_driver(clk_mt2712_bdp_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 BDP clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/clk-mt2712-img.c index 1fecc0f68f0e..84abd0515fd2 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -54,4 +54,6 @@ static struct platform_driver clk_mt2712_img_drv = { }, }; module_platform_driver(clk_mt2712_img_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediatek/clk-mt2712-jpgdec.c index 019080d6d0f0..89be9082adba 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt2712_jpgdec_drv = { }, }; module_platform_driver(clk_mt2712_jpgdec_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 JPEG Decoder clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/clk-mt2712-mfg.c index 39161516cf21..f7e0d0ebf665 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -49,4 +49,6 @@ static struct platform_driver clk_mt2712_mfg_drv = { }, }; module_platform_driver(clk_mt2712_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c index 15cb61fe2d2f..248529d3134d 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -128,4 +128,6 @@ static struct platform_driver clk_mt2712_mm_drv = { .id_table = clk_mt2712_mm_id_table, }; module_platform_driver(clk_mt2712_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 MultiMedia ddp clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/clk-mt2712-vdec.c index e1dd38fc2b3c..a063f1f0aa52 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -62,4 +62,6 @@ static struct platform_driver clk_mt2712_vdec_drv = { }, }; module_platform_driver(clk_mt2712_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/clk-mt2712-venc.c index ef6608a5db38..5b15df0a26f5 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -51,4 +51,6 @@ static struct platform_driver clk_mt2712_venc_drv = { }, }; module_platform_driver(clk_mt2712_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index a8d12a1210fc..91af45160aa4 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1000,4 +1000,6 @@ static struct platform_driver clk_mt2712_drv = { }, }; module_platform_driver(clk_mt2712_drv); + +MODULE_DESCRIPTION("MediaTek MT2712 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c index 901bf793c272..3e481c697eff 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -76,4 +76,6 @@ static struct platform_driver clk_mt6765_audio_drv = { }, }; module_platform_driver(clk_mt6765_audio_drv); + +MODULE_DESCRIPTION("MediaTek MT6765 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/clk-mt6765-cam.c index 19cedfa832bc..fed9c789d9fa 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -57,4 +57,6 @@ static struct platform_driver clk_mt6765_cam_drv = { }, }; module_platform_driver(clk_mt6765_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT6765 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/clk-mt6765-img.c index 16e20c61932e..34bb89ffd2dd 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -53,4 +53,6 @@ static struct platform_driver clk_mt6765_img_drv = { }, }; module_platform_driver(clk_mt6765_img_drv); + +MODULE_DESCRIPTION("MediaTek MT6765 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediatek/clk-mt6765-mipi0a.c index cc5bb0c95f08..957eb494fee5 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt6765_mipi0a_drv = { }, }; module_platform_driver(clk_mt6765_mipi0a_drv); + +MODULE_DESCRIPTION("MediaTek MT6765 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/clk-mt6765-mm.c index fc5842e13b78..099540fcfc76 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -79,4 +79,6 @@ static struct platform_driver clk_mt6765_mm_drv = { }, }; module_platform_driver(clk_mt6765_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT6765 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c index d6e036795b0a..64f3451d0aee 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -52,4 +52,6 @@ static struct platform_driver clk_mt6765_vcodec_drv = { }, }; module_platform_driver(clk_mt6765_vcodec_drv); + +MODULE_DESCRIPTION("MediaTek MT6765 Video Codec clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c index 9c7f7407d798..d53731e7933f 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -873,4 +873,6 @@ static int __init clk_mt6765_init(void) } arch_initcall(clk_mt6765_init); + +MODULE_DESCRIPTION("MediaTek MT6765 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c index 66ae6421e27e..3d23b8e29af6 100644 --- a/drivers/clk/mediatek/clk-mt6779-aud.c +++ b/drivers/clk/mediatek/clk-mt6779-aud.c @@ -110,6 +110,7 @@ static struct platform_driver clk_mt6779_aud_drv = { .of_match_table = of_match_clk_mt6779_aud, }, }; - module_platform_driver(clk_mt6779_aud_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/clk-mt6779-cam.c index 7b1a40d891ad..e76b2c4f548e 100644 --- a/drivers/clk/mediatek/clk-mt6779-cam.c +++ b/drivers/clk/mediatek/clk-mt6779-cam.c @@ -61,6 +61,7 @@ static struct platform_driver clk_mt6779_cam_drv = { .of_match_table = of_match_clk_mt6779_cam, }, }; - module_platform_driver(clk_mt6779_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/clk-mt6779-img.c index 1c53209f60a9..0c5971f3966a 100644 --- a/drivers/clk/mediatek/clk-mt6779-img.c +++ b/drivers/clk/mediatek/clk-mt6779-img.c @@ -55,4 +55,6 @@ static struct platform_driver clk_mt6779_img_drv = { }; module_platform_driver(clk_mt6779_img_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/clk-mt6779-ipe.c index 784bc08ace5e..9c1a9f1b0f3e 100644 --- a/drivers/clk/mediatek/clk-mt6779-ipe.c +++ b/drivers/clk/mediatek/clk-mt6779-ipe.c @@ -57,4 +57,6 @@ static struct platform_driver clk_mt6779_ipe_drv = { }; module_platform_driver(clk_mt6779_ipe_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 Image Processing Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/clk-mt6779-mfg.c index 040e4c45fa5f..3cc82b59117f 100644 --- a/drivers/clk/mediatek/clk-mt6779-mfg.c +++ b/drivers/clk/mediatek/clk-mt6779-mfg.c @@ -52,4 +52,6 @@ static struct platform_driver clk_mt6779_mfg_drv = { }; module_platform_driver(clk_mt6779_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c index 5e17e441f679..97d437a6f98f 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -106,4 +106,6 @@ static struct platform_driver clk_mt6779_mm_drv = { }; module_platform_driver(clk_mt6779_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 MultiMedia mdp/ddp clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/clk-mt6779-vdec.c index a411c23512b7..a9122e627aa5 100644 --- a/drivers/clk/mediatek/clk-mt6779-vdec.c +++ b/drivers/clk/mediatek/clk-mt6779-vdec.c @@ -64,4 +64,6 @@ static struct platform_driver clk_mt6779_vdec_drv = { }; module_platform_driver(clk_mt6779_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/clk-mt6779-venc.c index f14512d284d6..2cd032648eb1 100644 --- a/drivers/clk/mediatek/clk-mt6779-venc.c +++ b/drivers/clk/mediatek/clk-mt6779-venc.c @@ -55,4 +55,6 @@ static struct platform_driver clk_mt6779_venc_drv = { }; module_platform_driver(clk_mt6779_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT6779 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index ffedb1fe3c67..819253b97a02 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1330,4 +1330,6 @@ static int __init clk_mt6779_init(void) } arch_initcall(clk_mt6779_init); + +MODULE_DESCRIPTION("MediaTek MT6779 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6795-mm.c b/drivers/clk/mediatek/clk-mt6795-mm.c index ced6e310d694..dd1708d689dc 100644 --- a/drivers/clk/mediatek/clk-mt6795-mm.c +++ b/drivers/clk/mediatek/clk-mt6795-mm.c @@ -97,5 +97,5 @@ static struct platform_driver clk_mt6795_mm_drv = { }; module_platform_driver(clk_mt6795_mm_drv); -MODULE_DESCRIPTION("MediaTek MT6795 MultiMedia clocks driver"); +MODULE_DESCRIPTION("MediaTek MT6795 MMSYS clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/clk-mt6797-img.c index e1c1ee692a1d..0ec0cf2154dc 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt6797_img_drv = { }, }; module_platform_driver(clk_mt6797_img_drv); + +MODULE_DESCRIPTION("MediaTek MT6797 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/clk-mt6797-mm.c index 5b0a77530b62..f5701e965792 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -100,4 +100,6 @@ static struct platform_driver clk_mt6797_mm_drv = { .id_table = clk_mt6797_mm_id_table, }; module_platform_driver(clk_mt6797_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT6797 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/clk-mt6797-vdec.c index 0ed6710ab88e..c967d5e25c7d 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -61,4 +61,6 @@ static struct platform_driver clk_mt6797_vdec_drv = { }, }; module_platform_driver(clk_mt6797_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT6797 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/clk-mt6797-venc.c index 93d1da7423fe..f6fac5db65b0 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -52,4 +52,6 @@ static struct platform_driver clk_mt6797_venc_drv = { }, }; module_platform_driver(clk_mt6797_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT6797 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index f12d4e9ff0bb..fb59e71af58e 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -708,4 +708,6 @@ static int __init clk_mt6797_init(void) } arch_initcall(clk_mt6797_init); + +MODULE_DESCRIPTION("MediaTek MT6797 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index 42bade71e2f8..b7bf626e4d14 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -156,4 +156,6 @@ static struct platform_driver clk_mt7622_aud_drv = { }, }; module_platform_driver(clk_mt7622_aud_drv); + +MODULE_DESCRIPTION("MediaTek MT7622 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 62fdf127e77d..fa4876317a8d 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -86,4 +86,6 @@ static struct platform_driver clk_mt7622_eth_drv = { }, }; module_platform_driver(clk_mt7622_eth_drv); + +MODULE_DESCRIPTION("MediaTek MT7622 Ethernet clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index b4a520ce362c..8e57582454c2 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -98,4 +98,6 @@ static struct platform_driver clk_mt7622_hif_drv = { }, }; module_platform_driver(clk_mt7622_hif_drv); + +MODULE_DESCRIPTION("MediaTek MT7622 HIF clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 1bfedc988cfe..29ea93abaac5 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -157,4 +157,6 @@ static struct platform_driver clk_mt7629_eth_drv = { }; builtin_platform_driver(clk_mt7629_eth_drv); + +MODULE_DESCRIPTION("MediaTek MT7629 Ethernet clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index dd1be946a8f0..96d1a82ad75f 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -93,4 +93,6 @@ static struct platform_driver clk_mt7629_hif_drv = { }, }; module_platform_driver(clk_mt7629_hif_drv); + +MODULE_DESCRIPTION("MediaTek MT2701 HIF clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index b8a1f01bc974..baf94e7bea37 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -698,4 +698,6 @@ static int clk_mt7629_init(void) } arch_initcall(clk_mt7629_init); + +MODULE_DESCRIPTION("MediaTek MT7629 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c index 98739877f430..e8211eb4e09e 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -99,4 +99,6 @@ static struct platform_driver clk_mt7981_apmixed_drv = { }, }; builtin_platform_driver(clk_mt7981_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT7981 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-eth.c b/drivers/clk/mediatek/clk-mt7981-eth.c index fb1a8c9242ef..e8cb247db0ce 100644 --- a/drivers/clk/mediatek/clk-mt7981-eth.c +++ b/drivers/clk/mediatek/clk-mt7981-eth.c @@ -114,4 +114,6 @@ static struct platform_driver clk_mt7981_eth_drv = { }, }; module_platform_driver(clk_mt7981_eth_drv); + +MODULE_DESCRIPTION("MediaTek MT7981 Ethernet clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/mediatek/clk-mt7981-infracfg.c index 18bf4e8be457..b2b055151297 100644 --- a/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -204,4 +204,6 @@ static struct platform_driver clk_mt7981_infracfg_drv = { }, }; module_platform_driver(clk_mt7981_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT7981 infracfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/mediatek/clk-mt7981-topckgen.c index 493aa11d3a17..72f2f4f30e85 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -420,4 +420,6 @@ static struct platform_driver clk_mt7981_topckgen_drv = { }, }; module_platform_driver(clk_mt7981_topckgen_drv); + +MODULE_DESCRIPTION("MediaTek MT7981 top clock generators driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c index 7f807fbdfcb9..93751abe6be8 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -97,4 +97,6 @@ static struct platform_driver clk_mt7986_apmixed_drv = { }, }; builtin_platform_driver(clk_mt7986_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT7986 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c index 84bc24511504..b644b4ca4710 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -313,4 +313,6 @@ static struct platform_driver clk_mt7986_topckgen_drv = { }, }; module_platform_driver(clk_mt7986_topckgen_drv); + +MODULE_DESCRIPTION("MediaTek MT7986 top clock generators driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediatek/clk-mt7988-apmixed.c index baf9564351a3..63d33a78cb48 100644 --- a/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -111,4 +111,6 @@ static struct platform_driver clk_mt7988_apmixed_drv = { }, }; builtin_platform_driver(clk_mt7988_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT7988 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c index c8c023afe3e5..6c2bebabb4de 100644 --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -295,4 +295,6 @@ static struct platform_driver clk_mt7988_infracfg_drv = { .remove_new = mtk_clk_simple_remove, }; module_platform_driver(clk_mt7988_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT7988 infracfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7988-topckgen.c b/drivers/clk/mediatek/clk-mt7988-topckgen.c index 760f8e0d2f26..7300e9694582 100644 --- a/drivers/clk/mediatek/clk-mt7988-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c @@ -322,4 +322,6 @@ static struct platform_driver clk_mt7988_topckgen_drv = { }, }; module_platform_driver(clk_mt7988_topckgen_drv); + +MODULE_DESCRIPTION("MediaTek MT7988 top clock generators driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c index fca41f50d6ba..adf576786696 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -142,4 +142,6 @@ static struct platform_driver clk_mt8167_apmixed_drv = { }, }; builtin_platform_driver(clk_mt8167_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8167 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/clk-mt8167-aud.c index a5181f4eb34a..d1a42ff549c1 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -61,4 +61,6 @@ static struct platform_driver clk_mt8167_audsys_drv = { }, }; module_platform_driver(clk_mt8167_audsys_drv); + +MODULE_DESCRIPTION("MediaTek MT8167 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/clk-mt8167-img.c index 02fa52d8aabb..888ac3bdeacb 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -53,4 +53,6 @@ static struct platform_driver clk_mt8167_imgsys_drv = { }, }; module_platform_driver(clk_mt8167_imgsys_drv); + +MODULE_DESCRIPTION("MediaTek MT8167 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c index a5b5ee7ac805..e873766f130c 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -51,4 +51,6 @@ static struct platform_driver clk_mt8167_mfgcfg_drv = { }, }; module_platform_driver(clk_mt8167_mfgcfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8167 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/clk-mt8167-mm.c index 9b0c6b3343b9..38deedffaacf 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -92,4 +92,6 @@ static struct platform_driver clk_mt8167_mm_drv = { .id_table = clk_mt8167_mm_id_table, }; module_platform_driver(clk_mt8167_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT8167 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/clk-mt8167-vdec.c index 1e1e76743180..c3c892bb8334 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -60,4 +60,6 @@ static struct platform_driver clk_mt8167_vdec_drv = { }, }; module_platform_driver(clk_mt8167_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8167 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index 270221c6e6e8..5c94995f859c 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -894,4 +894,6 @@ static struct platform_driver clk_mt8167_drv = { }, }; module_platform_driver(clk_mt8167_drv); + +MODULE_DESCRIPTION("MediaTek MTì8167 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c index 2f2f074e231a..ecc8b0063ea5 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -98,7 +98,17 @@ CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", static int clk_mt8173_infracfg_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - int r; + int r, i; + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!infra_clk_data) + return -ENOMEM; + } else { + for (i = 0; i < CLK_INFRA_NR_CLK; i++) + if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) + infra_clk_data->hws[i] = ERR_PTR(-ENOENT); + } r = mtk_clk_register_gates(&pdev->dev, node, infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data); diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c index 2b261c0e2b61..551adbfd7ac9 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -192,4 +192,6 @@ static struct platform_driver clk_mt8183_apmixed_drv = { }, }; builtin_platform_driver(clk_mt8183_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8183 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c index 716b26825ef0..30a20e8ba84b 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -108,4 +108,6 @@ static struct platform_driver clk_mt8183_audio_drv = { }, }; module_platform_driver(clk_mt8183_audio_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/clk-mt8183-cam.c index b0f8e4242a63..f16c3aa3c911 100644 --- a/drivers/clk/mediatek/clk-mt8183-cam.c +++ b/drivers/clk/mediatek/clk-mt8183-cam.c @@ -58,4 +58,6 @@ static struct platform_driver clk_mt8183_cam_drv = { }, }; module_platform_driver(clk_mt8183_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/clk-mt8183-img.c index 6e177d2e8872..32ee6a1867fc 100644 --- a/drivers/clk/mediatek/clk-mt8183-img.c +++ b/drivers/clk/mediatek/clk-mt8183-img.c @@ -58,4 +58,6 @@ static struct platform_driver clk_mt8183_img_drv = { }, }; module_platform_driver(clk_mt8183_img_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/clk-mt8183-ipu0.c index 0b61c7af8aea..dc2916c4e0dc 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu0.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c @@ -51,4 +51,6 @@ static struct platform_driver clk_mt8183_ipu_core0_drv = { }, }; module_platform_driver(clk_mt8183_ipu_core0_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Pri. Image Processing Unit clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/clk-mt8183-ipu1.c index 544b1ca0e1c5..9c63e4c592d0 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu1.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c @@ -51,4 +51,6 @@ static struct platform_driver clk_mt8183_ipu_core1_drv = { }, }; module_platform_driver(clk_mt8183_ipu_core1_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Sec. Image Processing Unit clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c index 7f53674f393c..54a50eda1719 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c @@ -49,4 +49,6 @@ static struct platform_driver clk_mt8183_ipu_adl_drv = { }, }; module_platform_driver(clk_mt8183_ipu_adl_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Image Processing Unit ADL driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c index fb03ad2d8f6a..99a817d3be6c 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c @@ -118,4 +118,6 @@ static struct platform_driver clk_mt8183_ipu_conn_drv = { }, }; module_platform_driver(clk_mt8183_ipu_conn_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Image Processing Unit Bus clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c index ba504e19d420..c89c3d58fedc 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt8183_mfg_drv = { }, }; module_platform_driver(clk_mt8183_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/clk-mt8183-mm.c index 8aaddcfee568..59acf1e2951b 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -102,4 +102,6 @@ static struct platform_driver clk_mt8183_mm_drv = { .id_table = clk_mt8183_mm_id_table, }; module_platform_driver(clk_mt8183_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/clk-mt8183-vdec.c index 8c99ae89834f..48a8ef3f69aa 100644 --- a/drivers/clk/mediatek/clk-mt8183-vdec.c +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c @@ -62,4 +62,6 @@ static struct platform_driver clk_mt8183_vdec_drv = { }, }; module_platform_driver(clk_mt8183_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/clk-mt8183-venc.c index a8e0220902ae..8f36688dfa14 100644 --- a/drivers/clk/mediatek/clk-mt8183-venc.c +++ b/drivers/clk/mediatek/clk-mt8183-venc.c @@ -54,4 +54,6 @@ static struct platform_driver clk_mt8183_venc_drv = { }, }; module_platform_driver(clk_mt8183_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT8183 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 934d5a15acfc..27eee4ef2c0f 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -906,4 +906,6 @@ static struct platform_driver clk_mt8183_drv = { }, }; module_platform_driver(clk_mt8183_drv) + +MODULE_DESCRIPTION("MediaTek MT8183 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c index fff64a8fd557..6f7127003e4f 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -192,4 +192,6 @@ static struct platform_driver clk_mt8186_apmixed_drv = { }, }; module_platform_driver(clk_mt8186_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/clk-mt8186-cam.c index effd2900d2e8..0082f0d9286b 100644 --- a/drivers/clk/mediatek/clk-mt8186-cam.c +++ b/drivers/clk/mediatek/clk-mt8186-cam.c @@ -89,4 +89,6 @@ static struct platform_driver clk_mt8186_cam_drv = { }, }; module_platform_driver(clk_mt8186_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-img.c b/drivers/clk/mediatek/clk-mt8186-img.c index 71b0571e6351..0583a18805ce 100644 --- a/drivers/clk/mediatek/clk-mt8186-img.c +++ b/drivers/clk/mediatek/clk-mt8186-img.c @@ -67,4 +67,6 @@ static struct platform_driver clk_mt8186_img_drv = { }, }; module_platform_driver(clk_mt8186_img_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c index 640ccb553274..2a2a6bb23205 100644 --- a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c @@ -66,4 +66,6 @@ static struct platform_driver clk_mt8186_imp_iic_wrap_drv = { }, }; module_platform_driver(clk_mt8186_imp_iic_wrap_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 I2C Wrapper clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/mediatek/clk-mt8186-infra_ao.c index 837304cd0ed7..d7239875fb15 100644 --- a/drivers/clk/mediatek/clk-mt8186-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c @@ -238,4 +238,6 @@ static struct platform_driver clk_mt8186_infra_ao_drv = { }, }; module_platform_driver(clk_mt8186_infra_ao_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 infracfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/clk-mt8186-ipe.c index 60739e225cb6..77bdd2806517 100644 --- a/drivers/clk/mediatek/clk-mt8186-ipe.c +++ b/drivers/clk/mediatek/clk-mt8186-ipe.c @@ -54,4 +54,6 @@ static struct platform_driver clk_mt8186_ipe_drv = { }, }; module_platform_driver(clk_mt8186_ipe_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 Image Processing Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mdp.c b/drivers/clk/mediatek/clk-mt8186-mdp.c index 9a335f2285ce..fb47d6bacf7f 100644 --- a/drivers/clk/mediatek/clk-mt8186-mdp.c +++ b/drivers/clk/mediatek/clk-mt8186-mdp.c @@ -79,4 +79,6 @@ static struct platform_driver clk_mt8186_mdp_drv = { }, }; module_platform_driver(clk_mt8186_mdp_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 Multimedia Data Path clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mfg.c b/drivers/clk/mediatek/clk-mt8186-mfg.c index 7618dad9e0e0..64cdee1fddd4 100644 --- a/drivers/clk/mediatek/clk-mt8186-mfg.c +++ b/drivers/clk/mediatek/clk-mt8186-mfg.c @@ -48,4 +48,6 @@ static struct platform_driver clk_mt8186_mfg_drv = { }, }; module_platform_driver(clk_mt8186_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/clk-mt8186-mm.c index 44ed504a8069..403566187e64 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -78,4 +78,6 @@ static struct platform_driver clk_mt8186_mm_drv = { .id_table = clk_mt8186_mm_id_table, }; module_platform_driver(clk_mt8186_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/mediatek/clk-mt8186-topckgen.c index 8e385d6bfef2..eb9f51e77ca8 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -732,4 +732,6 @@ static struct platform_driver clk_mt8186_topck_drv = { }, }; module_platform_driver(clk_mt8186_topck_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 top clock generators driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-vdec.c b/drivers/clk/mediatek/clk-mt8186-vdec.c index 0b814e8e107f..25465704ddfb 100644 --- a/drivers/clk/mediatek/clk-mt8186-vdec.c +++ b/drivers/clk/mediatek/clk-mt8186-vdec.c @@ -87,4 +87,6 @@ static struct platform_driver clk_mt8186_vdec_drv = { }, }; module_platform_driver(clk_mt8186_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-venc.c b/drivers/clk/mediatek/clk-mt8186-venc.c index 9493e51af3e2..647dd66a3ce0 100644 --- a/drivers/clk/mediatek/clk-mt8186-venc.c +++ b/drivers/clk/mediatek/clk-mt8186-venc.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt8186_venc_drv = { }, }; module_platform_driver(clk_mt8186_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-wpe.c b/drivers/clk/mediatek/clk-mt8186-wpe.c index a0174eabef4a..47f96e088361 100644 --- a/drivers/clk/mediatek/clk-mt8186-wpe.c +++ b/drivers/clk/mediatek/clk-mt8186-wpe.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt8186_wpe_drv = { }, }; module_platform_driver(clk_mt8186_wpe_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 Warp Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c index 1dc3d2bad42d..5ac035bbe684 100644 --- a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c +++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c @@ -47,4 +47,6 @@ static struct platform_driver clk_mt8188_adsp_audio26m_drv = { }, }; module_platform_driver(clk_mt8188_adsp_audio26m_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 AudioDSP clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c index 41ab4d6896a4..85d573d96081 100644 --- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -152,4 +152,6 @@ static struct platform_driver clk_mt8188_apmixed_drv = { }, }; module_platform_driver(clk_mt8188_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-cam.c b/drivers/clk/mediatek/clk-mt8188-cam.c index f78f564aa27e..a6a6581f0461 100644 --- a/drivers/clk/mediatek/clk-mt8188-cam.c +++ b/drivers/clk/mediatek/clk-mt8188-cam.c @@ -115,6 +115,7 @@ static struct platform_driver clk_mt8188_cam_drv = { .of_match_table = of_match_clk_mt8188_cam, }, }; - module_platform_driver(clk_mt8188_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-ccu.c b/drivers/clk/mediatek/clk-mt8188-ccu.c index 428dcc4818c2..9532fc652f01 100644 --- a/drivers/clk/mediatek/clk-mt8188-ccu.c +++ b/drivers/clk/mediatek/clk-mt8188-ccu.c @@ -45,6 +45,7 @@ static struct platform_driver clk_mt8188_ccu_drv = { .of_match_table = of_match_clk_mt8188_ccu, }, }; - module_platform_driver(clk_mt8188_ccu_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Camera Control Unit clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-img.c b/drivers/clk/mediatek/clk-mt8188-img.c index 76c64a8992a4..00ad6d7884ae 100644 --- a/drivers/clk/mediatek/clk-mt8188-img.c +++ b/drivers/clk/mediatek/clk-mt8188-img.c @@ -107,6 +107,7 @@ static struct platform_driver clk_mt8188_imgsys_main_drv = { .of_match_table = of_match_clk_mt8188_imgsys_main, }, }; - module_platform_driver(clk_mt8188_imgsys_main_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c index 66946784cdba..7b713f4cd662 100644 --- a/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c @@ -79,4 +79,6 @@ static struct platform_driver clk_mt8188_imp_iic_wrap_drv = { }; module_platform_driver(clk_mt8188_imp_iic_wrap_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 I2C Wrapper clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c index f590178737cb..face3e191464 100644 --- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c @@ -220,4 +220,6 @@ static struct platform_driver clk_mt8188_infra_ao_drv = { }, }; module_platform_driver(clk_mt8188_infra_ao_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 infracfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-ipe.c b/drivers/clk/mediatek/clk-mt8188-ipe.c index 54fe6b689b47..fa439af34359 100644 --- a/drivers/clk/mediatek/clk-mt8188-ipe.c +++ b/drivers/clk/mediatek/clk-mt8188-ipe.c @@ -49,4 +49,6 @@ static struct platform_driver clk_mt8188_ipe_drv = { }; module_platform_driver(clk_mt8188_ipe_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Image Processing Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c b/drivers/clk/mediatek/clk-mt8188-mfg.c index 1c8ef4c6820f..ec562e7d459d 100644 --- a/drivers/clk/mediatek/clk-mt8188-mfg.c +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c @@ -46,4 +46,6 @@ static struct platform_driver clk_mt8188_mfgcfg_drv = { }; module_platform_driver(clk_mt8188_mfgcfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-peri_ao.c b/drivers/clk/mediatek/clk-mt8188-peri_ao.c index a8214e42b8e5..e4339885b062 100644 --- a/drivers/clk/mediatek/clk-mt8188-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8188-peri_ao.c @@ -56,4 +56,6 @@ static struct platform_driver clk_mt8188_peri_ao_drv = { }, }; module_platform_driver(clk_mt8188_peri_ao_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 pericfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c index f7ec599b20af..2ccc8a1c98f9 100644 --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -1354,4 +1354,6 @@ static struct platform_driver clk_mt8188_topck_drv = { }, }; module_platform_driver(clk_mt8188_topck_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 top clock generators driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c index db5855d133ac..bf388997c3f8 100644 --- a/drivers/clk/mediatek/clk-mt8188-vdec.c +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c @@ -89,4 +89,6 @@ static struct platform_driver clk_mt8188_vdec_drv = { }; module_platform_driver(clk_mt8188_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c index d252e198678c..935371fbf1d2 100644 --- a/drivers/clk/mediatek/clk-mt8188-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c @@ -104,4 +104,6 @@ static struct platform_driver clk_mt8188_vdo0_drv = { .id_table = clk_mt8188_vdo0_id_table, }; module_platform_driver(clk_mt8188_vdo0_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Video Output 0 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vdo1.c b/drivers/clk/mediatek/clk-mt8188-vdo1.c index 7b72d54086db..fb24c9026fd8 100644 --- a/drivers/clk/mediatek/clk-mt8188-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8188-vdo1.c @@ -151,4 +151,6 @@ static struct platform_driver clk_mt8188_vdo1_drv = { .id_table = clk_mt8188_vdo1_id_table, }; module_platform_driver(clk_mt8188_vdo1_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Video Output 1 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c b/drivers/clk/mediatek/clk-mt8188-venc.c index 5b1713908ed2..4df8d4e05159 100644 --- a/drivers/clk/mediatek/clk-mt8188-venc.c +++ b/drivers/clk/mediatek/clk-mt8188-venc.c @@ -51,6 +51,7 @@ static struct platform_driver clk_mt8188_venc1_drv = { .of_match_table = of_match_clk_mt8188_venc1, }, }; - module_platform_driver(clk_mt8188_venc1_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c index e7b02b26fefb..310792108793 100644 --- a/drivers/clk/mediatek/clk-mt8188-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c @@ -111,4 +111,6 @@ static struct platform_driver clk_mt8188_vpp0_drv = { .id_table = clk_mt8188_vpp0_id_table, }; module_platform_driver(clk_mt8188_vpp0_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Video Processing Pipe 0 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c index e8f0f7eca097..0aa10aaa0292 100644 --- a/drivers/clk/mediatek/clk-mt8188-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c @@ -106,4 +106,6 @@ static struct platform_driver clk_mt8188_vpp1_drv = { .id_table = clk_mt8188_vpp1_id_table, }; module_platform_driver(clk_mt8188_vpp1_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Video Processing Pipe 1 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-wpe.c b/drivers/clk/mediatek/clk-mt8188-wpe.c index f394ec049872..fbac440363cc 100644 --- a/drivers/clk/mediatek/clk-mt8188-wpe.c +++ b/drivers/clk/mediatek/clk-mt8188-wpe.c @@ -100,6 +100,7 @@ static struct platform_driver clk_mt8188_wpe_drv = { .of_match_table = of_match_clk_mt8188_wpe, }, }; - module_platform_driver(clk_mt8188_wpe_drv); + +MODULE_DESCRIPTION("MediaTek MT8188 Warp Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c index 5bce67bf701d..b438ebad998d 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -118,4 +118,6 @@ static struct platform_driver clk_mt8192_aud_drv = { }, }; module_platform_driver(clk_mt8192_aud_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 audio clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/clk-mt8192-cam.c index a2c0142273a8..3eed4a7b6d8e 100644 --- a/drivers/clk/mediatek/clk-mt8192-cam.c +++ b/drivers/clk/mediatek/clk-mt8192-cam.c @@ -106,4 +106,6 @@ static struct platform_driver clk_mt8192_cam_drv = { }, }; module_platform_driver(clk_mt8192_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c index ee52b5b748e7..13a435332752 100644 --- a/drivers/clk/mediatek/clk-mt8192-img.c +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -69,4 +69,6 @@ static struct platform_driver clk_mt8192_img_drv = { }, }; module_platform_driver(clk_mt8192_img_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c index a97b6e8d97ac..45585f2edd50 100644 --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c @@ -118,4 +118,6 @@ static struct platform_driver clk_mt8192_imp_iic_wrap_drv = { }, }; module_platform_driver(clk_mt8192_imp_iic_wrap_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 I2C Wrapper clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c index 56ce58ac01ad..da2e2d83cd25 100644 --- a/drivers/clk/mediatek/clk-mt8192-ipe.c +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -56,4 +56,6 @@ static struct platform_driver clk_mt8192_ipe_drv = { }, }; module_platform_driver(clk_mt8192_ipe_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 Image Processing Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/clk-mt8192-mdp.c index bad2f3d439f5..be674d6c31d7 100644 --- a/drivers/clk/mediatek/clk-mt8192-mdp.c +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c @@ -81,4 +81,6 @@ static struct platform_driver clk_mt8192_mdp_drv = { }, }; module_platform_driver(clk_mt8192_mdp_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 Multimedia Data Path clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c index 666b401e778c..2da969f4ca6b 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -51,4 +51,6 @@ static struct platform_driver clk_mt8192_mfg_drv = { }, }; module_platform_driver(clk_mt8192_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c index b294184c5183..2b9c1c4524c2 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -100,4 +100,6 @@ static struct platform_driver clk_mt8192_mm_drv = { .id_table = clk_mt8192_mm_id_table, }; module_platform_driver(clk_mt8192_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c index 52d6f0babf12..bc5ce987b76c 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -63,4 +63,6 @@ static struct platform_driver clk_mt8192_msdc_drv = { }, }; module_platform_driver(clk_mt8192_msdc_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 MMC/SD Controller clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c index 72c8a8722b11..e017d30a8832 100644 --- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -49,4 +49,6 @@ static struct platform_driver clk_mt8192_scp_adsp_drv = { }, }; module_platform_driver(clk_mt8192_scp_adsp_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 SCP AudioDSP clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c index cc514068bcdb..fcb34b1dcdab 100644 --- a/drivers/clk/mediatek/clk-mt8192-vdec.c +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -93,4 +93,6 @@ static struct platform_driver clk_mt8192_vdec_drv = { }, }; module_platform_driver(clk_mt8192_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/clk-mt8192-venc.c index 9f6fff2dd753..98d58a9397cd 100644 --- a/drivers/clk/mediatek/clk-mt8192-venc.c +++ b/drivers/clk/mediatek/clk-mt8192-venc.c @@ -52,4 +52,6 @@ static struct platform_driver clk_mt8192_venc_drv = { }, }; module_platform_driver(clk_mt8192_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index e395c04632bc..bce2298ebc8d 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1029,4 +1029,6 @@ static struct platform_driver clk_mt8192_drv = { .remove_new = mtk_clk_simple_remove, }; module_platform_driver(clk_mt8192_drv); + +MODULE_DESCRIPTION("MediaTek MT8192 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 44a4c85a67ef..049ae8123e34 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -230,4 +230,6 @@ static struct platform_driver clk_mt8195_apmixed_drv = { }, }; module_platform_driver(clk_mt8195_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c index 79762bc85cd7..b1b562e44cb4 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -110,4 +110,6 @@ static struct platform_driver clk_mt8195_apusys_pll_drv = { }, }; module_platform_driver(clk_mt8195_apusys_pll_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 AI Processing Unit PLL clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/clk-mt8195-cam.c index 24cd6a2092b6..7c8f77817616 100644 --- a/drivers/clk/mediatek/clk-mt8195-cam.c +++ b/drivers/clk/mediatek/clk-mt8195-cam.c @@ -142,4 +142,6 @@ static struct platform_driver clk_mt8195_cam_drv = { }, }; module_platform_driver(clk_mt8195_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/clk-mt8195-ccu.c index 24dab128507a..f78afd7b6ade 100644 --- a/drivers/clk/mediatek/clk-mt8195-ccu.c +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt8195_ccu_drv = { }, }; module_platform_driver(clk_mt8195_ccu_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Camera Control Unit clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/clk-mt8195-img.c index c7dc3e9d133d..a59c082ef522 100644 --- a/drivers/clk/mediatek/clk-mt8195-img.c +++ b/drivers/clk/mediatek/clk-mt8195-img.c @@ -96,4 +96,6 @@ static struct platform_driver clk_mt8195_img_drv = { }, }; module_platform_driver(clk_mt8195_img_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 imgsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c index 94912d45509e..54557f1b0681 100644 --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c @@ -66,4 +66,6 @@ static struct platform_driver clk_mt8195_imp_iic_wrap_drv = { }, }; module_platform_driver(clk_mt8195_imp_iic_wrap_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 I2C Wrapper clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index dfba6eb61ccf..165fe92c6f61 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -240,4 +240,6 @@ static struct platform_driver clk_mt8195_infra_ao_drv = { }, }; module_platform_driver(clk_mt8195_infra_ao_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 infracfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/clk-mt8195-ipe.c index 21e76e5ad376..38a23d88370b 100644 --- a/drivers/clk/mediatek/clk-mt8195-ipe.c +++ b/drivers/clk/mediatek/clk-mt8195-ipe.c @@ -51,4 +51,6 @@ static struct platform_driver clk_mt8195_ipe_drv = { }, }; module_platform_driver(clk_mt8195_ipe_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Image Processing Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c index 4951574abf2a..e19968eeb346 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -49,4 +49,6 @@ static struct platform_driver clk_mt8195_mfg_drv = { }, }; module_platform_driver(clk_mt8195_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediatek/clk-mt8195-peri_ao.c index 39069aaf6bcd..fc341030f10b 100644 --- a/drivers/clk/mediatek/clk-mt8195-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c @@ -62,4 +62,6 @@ static struct platform_driver clk_mt8195_peri_ao_drv = { }, }; module_platform_driver(clk_mt8195_peri_ao_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 pericfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c index 2b94d75be295..1f37bde97d90 100644 --- a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c @@ -47,4 +47,6 @@ static struct platform_driver clk_mt8195_scp_adsp_drv = { }, }; module_platform_driver(clk_mt8195_scp_adsp_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 SCP AudioDSP clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 8f713a3341a9..704498c40349 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1361,4 +1361,6 @@ static struct platform_driver clk_mt8195_topck_drv = { }, }; module_platform_driver(clk_mt8195_topck_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 top clock generators driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/clk-mt8195-vdec.c index d266a6d3b603..9e4cc1a82cbe 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdec.c +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c @@ -104,4 +104,6 @@ static struct platform_driver clk_mt8195_vdec_drv = { }, }; module_platform_driver(clk_mt8195_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index 34fc318c146c..6e9c3ef19502 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -113,4 +113,6 @@ static struct platform_driver clk_mt8195_vdo0_drv = { .id_table = clk_mt8195_vdo0_id_table, }; module_platform_driver(clk_mt8195_vdo0_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Video Output 0 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index e400631e1dbe..422e5729386c 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -140,4 +140,6 @@ static struct platform_driver clk_mt8195_vdo1_drv = { .id_table = clk_mt8195_vdo1_id_table, }; module_platform_driver(clk_mt8195_vdo1_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Video Output 1 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c index 93093fadfd0d..db7a6ce97ed0 100644 --- a/drivers/clk/mediatek/clk-mt8195-venc.c +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -69,4 +69,6 @@ static struct platform_driver clk_mt8195_venc_drv = { }, }; module_platform_driver(clk_mt8195_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c index 81725fcb3a72..77d9aaf47a25 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -106,4 +106,6 @@ static struct platform_driver clk_mt8195_vpp0_drv = { .id_table = clk_mt8195_vpp0_id_table, }; module_platform_driver(clk_mt8195_vpp0_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Video Processing Pipe 0 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c index 867fde4e575b..18ca8f1d9538 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -104,4 +104,6 @@ static struct platform_driver clk_mt8195_vpp1_drv = { .id_table = clk_mt8195_vpp1_id_table, }; module_platform_driver(clk_mt8195_vpp1_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Video Processing Pipe 1 clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/clk-mt8195-wpe.c index 7324738179a4..9c45a2fed0ce 100644 --- a/drivers/clk/mediatek/clk-mt8195-wpe.c +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c @@ -143,4 +143,6 @@ static struct platform_driver clk_mt8195_wpe_drv = { }, }; module_platform_driver(clk_mt8195_wpe_drv); + +MODULE_DESCRIPTION("MediaTek MT8195 Warp Engine clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c index 9b0bc5daeac0..f41b991a0178 100644 --- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -163,4 +163,6 @@ static struct platform_driver clk_mt8365_apmixed_drv = { }, }; builtin_platform_driver(clk_mt8365_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8365 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-apu.c b/drivers/clk/mediatek/clk-mt8365-apu.c index 4f10ce1531d2..934060e6d9e9 100644 --- a/drivers/clk/mediatek/clk-mt8365-apu.c +++ b/drivers/clk/mediatek/clk-mt8365-apu.c @@ -53,4 +53,6 @@ static struct platform_driver clk_mt8365_apu_drv = { }, }; module_platform_driver(clk_mt8365_apu_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 AI Processing Unit clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-cam.c b/drivers/clk/mediatek/clk-mt8365-cam.c index fe428a4f1d37..c8fe5f5bb06c 100644 --- a/drivers/clk/mediatek/clk-mt8365-cam.c +++ b/drivers/clk/mediatek/clk-mt8365-cam.c @@ -55,4 +55,6 @@ static struct platform_driver clk_mt8365_cam_drv = { }, }; module_platform_driver(clk_mt8365_cam_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 Camera clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-mfg.c b/drivers/clk/mediatek/clk-mt8365-mfg.c index 4a590284f7e2..5355f725363d 100644 --- a/drivers/clk/mediatek/clk-mt8365-mfg.c +++ b/drivers/clk/mediatek/clk-mt8365-mfg.c @@ -61,4 +61,6 @@ static struct platform_driver clk_mt8365_mfg_drv = { }, }; module_platform_driver(clk_mt8365_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 GPU mfg clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c index 3f62ec750733..8201949bfdae 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -92,4 +92,6 @@ static struct platform_driver clk_mt8365_mm_drv = { .id_table = clk_mt8365_mm_id_table, }; module_platform_driver(clk_mt8365_mm_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-vdec.c b/drivers/clk/mediatek/clk-mt8365-vdec.c index 233924837c3b..1be0b3faa2c3 100644 --- a/drivers/clk/mediatek/clk-mt8365-vdec.c +++ b/drivers/clk/mediatek/clk-mt8365-vdec.c @@ -61,4 +61,6 @@ static struct platform_driver clk_mt8365_vdec_drv = { }, }; module_platform_driver(clk_mt8365_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 Video Decoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-venc.c b/drivers/clk/mediatek/clk-mt8365-venc.c index cc063f18e56b..4228ddec5657 100644 --- a/drivers/clk/mediatek/clk-mt8365-venc.c +++ b/drivers/clk/mediatek/clk-mt8365-venc.c @@ -50,4 +50,6 @@ static struct platform_driver clk_mt8365_venc_drv = { }, }; module_platform_driver(clk_mt8365_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 Video Encoders clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index ac45e4cc9bcd..485b525b8acd 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -812,4 +812,6 @@ static struct platform_driver clk_mt8365_drv = { .remove_new = mtk_clk_simple_remove, }; module_platform_driver(clk_mt8365_drv); + +MODULE_DESCRIPTION("MediaTek MT8365 main clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c index 3161a0b021ee..2297259da89a 100644 --- a/drivers/clk/mxs/clk-ref.c +++ b/drivers/clk/mxs/clk-ref.c @@ -66,12 +66,7 @@ static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, tmp = tmp * 18 + rate / 2; do_div(tmp, rate); - frac = tmp; - - if (frac < 18) - frac = 18; - else if (frac > 35) - frac = 35; + frac = clamp(tmp, 18, 35); tmp = parent_rate; tmp *= 18; @@ -91,12 +86,7 @@ static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, tmp = tmp * 18 + rate / 2; do_div(tmp, rate); - frac = tmp; - - if (frac < 18) - frac = 18; - else if (frac > 35) - frac = 35; + frac = clamp(tmp, 18, 35); spin_lock_irqsave(&mxs_lock, flags); diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index d0f870eff0d6..e00f270bc6aa 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -61,7 +61,7 @@ #define LPC32XX_USB_CLK_CTRL 0xF4 #define LPC32XX_USB_CLK_STS 0xF8 -static struct regmap_config lpc32xx_scb_regmap_config = { +static const struct regmap_config lpc32xx_scb_regmap_config = { .name = "scb", .reg_bits = 32, .val_bits = 32, diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 25b8e1a80ddc..700a1be9ec47 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -611,6 +611,7 @@ static const struct of_device_id sifive_prci_of_match[] = { {.compatible = "sifive,fu740-c000-prci", .data = &prci_clk_fu740}, {} }; +MODULE_DEVICE_TABLE(of, sifive_prci_of_match); static struct platform_driver sifive_prci_driver = { .driver = { diff --git a/drivers/clk/sophgo/clk-cv1800.c b/drivers/clk/sophgo/clk-cv1800.c index 2da4c24621cf..e0c4dc347579 100644 --- a/drivers/clk/sophgo/clk-cv1800.c +++ b/drivers/clk/sophgo/clk-cv1800.c @@ -1534,4 +1534,5 @@ static struct platform_driver cv1800_clk_driver = { }, }; module_platform_driver(cv1800_clk_driver); +MODULE_DESCRIPTION("Sophgo CV1800 series SoCs clock controller"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c index 762f0961f17f..0f218161704f 100644 --- a/drivers/clk/sprd/common.c +++ b/drivers/clk/sprd/common.c @@ -109,4 +109,5 @@ int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw) } EXPORT_SYMBOL_GPL(sprd_clk_probe); +MODULE_DESCRIPTION("Spreadtrum clock infrastructure"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c index b2b32fa2d7c3..c385ca2f4a74 100644 --- a/drivers/clk/versatile/clk-vexpress-osc.c +++ b/drivers/clk/versatile/clk-vexpress-osc.c @@ -119,4 +119,5 @@ static struct platform_driver vexpress_osc_driver = { .probe = vexpress_osc_probe, }; module_platform_driver(vexpress_osc_driver); +MODULE_DESCRIPTION("Clock driver for Versatile Express OSC clock generators"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c index 60a3ed7c7263..d983fab12756 100644 --- a/drivers/clk/xilinx/xlnx_vcu.c +++ b/drivers/clk/xilinx/xlnx_vcu.c @@ -68,7 +68,7 @@ struct xvcu_device { struct clk_hw_onecell_data *clk_data; }; -static struct regmap_config vcu_settings_regmap_config = { +static const struct regmap_config vcu_settings_regmap_config = { .name = "regmap", .reg_bits = 32, .val_bits = 32, diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h new file mode 100644 index 000000000000..6544a1790b83 --- /dev/null +++ b/include/dt-bindings/reset/airoha,en7581-reset.h @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ + +/* RST_CTRL2 */ +#define EN7581_XPON_PHY_RST 0 +#define EN7581_CPU_TIMER2_RST 1 +#define EN7581_HSUART_RST 2 +#define EN7581_UART4_RST 3 +#define EN7581_UART5_RST 4 +#define EN7581_I2C2_RST 5 +#define EN7581_XSI_MAC_RST 6 +#define EN7581_XSI_PHY_RST 7 +#define EN7581_NPU_RST 8 +#define EN7581_I2S_RST 9 +#define EN7581_TRNG_RST 10 +#define EN7581_TRNG_MSTART_RST 11 +#define EN7581_DUAL_HSI0_RST 12 +#define EN7581_DUAL_HSI1_RST 13 +#define EN7581_HSI_RST 14 +#define EN7581_DUAL_HSI0_MAC_RST 15 +#define EN7581_DUAL_HSI1_MAC_RST 16 +#define EN7581_HSI_MAC_RST 17 +#define EN7581_WDMA_RST 18 +#define EN7581_WOE0_RST 19 +#define EN7581_WOE1_RST 20 +#define EN7581_HSDMA_RST 21 +#define EN7581_TDMA_RST 22 +#define EN7581_EMMC_RST 23 +#define EN7581_SOE_RST 24 +#define EN7581_PCIE2_RST 25 +#define EN7581_XFP_MAC_RST 26 +#define EN7581_USB_HOST_P1_RST 27 +#define EN7581_USB_HOST_P1_U3_PHY_RST 28 +/* RST_CTRL1 */ +#define EN7581_PCM1_ZSI_ISI_RST 29 +#define EN7581_FE_PDMA_RST 30 +#define EN7581_FE_QDMA_RST 31 +#define EN7581_PCM_SPIWP_RST 32 +#define EN7581_CRYPTO_RST 33 +#define EN7581_TIMER_RST 34 +#define EN7581_PCM1_RST 35 +#define EN7581_UART_RST 36 +#define EN7581_GPIO_RST 37 +#define EN7581_GDMA_RST 38 +#define EN7581_I2C_MASTER_RST 39 +#define EN7581_PCM2_ZSI_ISI_RST 40 +#define EN7581_SFC_RST 41 +#define EN7581_UART2_RST 42 +#define EN7581_GDMP_RST 43 +#define EN7581_FE_RST 44 +#define EN7581_USB_HOST_P0_RST 45 +#define EN7581_GSW_RST 46 +#define EN7581_SFC2_PCM_RST 47 +#define EN7581_PCIE0_RST 48 +#define EN7581_PCIE1_RST 49 +#define EN7581_CPU_TIMER_RST 50 +#define EN7581_PCIE_HB_RST 51 +#define EN7581_XPON_MAC_RST 52 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ |