diff options
51 files changed, 6216 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml new file mode 100644 index 000000000000..fb190db61525 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35 series SoC based platforms + +maintainers: + - Jacky Huang <ychuang3@nuvoton.com> + +description: | + Boards with an ARMv8 based Nuvoton MA35 series SoC shall have + the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: MA35D1 based boards + items: + - enum: + - nuvoton,ma35d1-iot + - nuvoton,ma35d1-som + - const: nuvoton,ma35d1 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml index 6871483947c5..d386744c8815 100644 --- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml +++ b/Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml# +$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NPCM Platforms diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ad8e51aa01b0..b63ff591ef8f 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -15,12 +15,13 @@ properties: oneOf: - items: - enum: - - st,stm32mp157-syscfg - - st,stm32mp151-pwr-mcu - - st,stm32-syscfg - st,stm32-power-config + - st,stm32-syscfg - st,stm32-tamp - st,stm32f4-gcan + - st,stm32mp151-pwr-mcu + - st,stm32mp157-syscfg + - st,stm32mp25-syscfg - const: syscon - items: - const: st,stm32-tamp diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4af5b8f4f803..4466b455bffa 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -161,6 +161,12 @@ properties: - const: phytec,phycore-stm32mp157c-som - const: st,stm32mp157 + - description: ST STM32MP257 based Boards + items: + - enum: + - st,stm32mp257f-ev1 + - const: st,stm32mp257 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..8f0c43683729 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module + +maintainers: + - Chi-Fang Li <cfli0@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. + maxItems: 5 + items: + enum: + - integer + - fractional + - spread-spectrum + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + + clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 1ab0f8dde477..2120ef71a78d 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -27,6 +27,8 @@ properties: - st,stm32mp135-pinctrl - st,stm32mp157-pinctrl - st,stm32mp157-z-pinctrl + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl '#address-cells': const: 1 @@ -56,7 +58,7 @@ properties: Indicates the SOC package used. More details in include/dt-bindings/pinctrl/stm32-pinfunc.h $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800] patternProperties: '^gpio@[0-9a-f]*$': diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml new file mode 100644 index 000000000000..34c5c1c08ec1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Reset Controller + +maintainers: + - Chi-Fang Li <cfli0@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +description: + The system reset controller can be used to reset various peripheral + controllers in MA35D1 SoC. + +properties: + compatible: + items: + - const: nuvoton,ma35d1-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + # system reset controller node: + - | + + system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x40460000 0x200>; + #reset-cells = <1>; + }; +... + diff --git a/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml new file mode 100644 index 000000000000..a76af0f6009b --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Min-Jen Chen <mjchen@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +allOf: + - $ref: serial.yaml + +properties: + compatible: + const: nuvoton,ma35d1-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + + serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x40700000 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART0_GATE>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml index 94e72f25b331..23e7e4ea01ff 100644 --- a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml +++ b/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Global Control Registers block in Nuvoton SoCs diff --git a/Documentation/process/maintainer-handbooks.rst b/Documentation/process/maintainer-handbooks.rst index d783060b4cc6..fe24cb665fb7 100644 --- a/Documentation/process/maintainer-handbooks.rst +++ b/Documentation/process/maintainer-handbooks.rst @@ -15,5 +15,6 @@ Contents: :numbered: :maxdepth: 2 - maintainer-tip maintainer-netdev + maintainer-soc + maintainer-tip diff --git a/Documentation/process/maintainer-soc.rst b/Documentation/process/maintainer-soc.rst new file mode 100644 index 000000000000..49f08289d62c --- /dev/null +++ b/Documentation/process/maintainer-soc.rst @@ -0,0 +1,177 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============= +SoC Subsystem +============= + +Overview +-------- + +The SoC subsystem is a place of aggregation for SoC-specific code. +The main components of the subsystem are: + +* devicetrees for 32- & 64-bit ARM and RISC-V +* 32-bit ARM board files (arch/arm/mach*) +* 32- & 64-bit ARM defconfigs +* SoC-specific drivers across architectures, in particular for 32- & 64-bit + ARM, RISC-V and Loongarch + +These "SoC-specific drivers" do not include clock, GPIO etc drivers that have +other top-level maintainers. The drivers/soc/ directory is generally meant +for kernel-internal drivers that are used by other drivers to provide SoC- +specific functionality like identifying an SoC revision or interfacing with +power domains. + +The SoC subsystem also serves as an intermediate location for changes to +drivers/bus, drivers/firmware, drivers/reset and drivers/memory. The addition +of new platforms, or the removal of existing ones, often go through the SoC +tree as a dedicated branch covering multiple subsystems. + +The main SoC tree is housed on git.kernel.org: + https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/ + +Clearly this is quite a wide range of topics, which no one person, or even +small group of people are capable of maintaining. Instead, the SoC subsystem +is comprised of many submaintainers, each taking care of individual platforms +and driver subdirectories. +In this regard, "platform" usually refers to a series of SoCs from a given +vendor, for example, Nvidia's series of Tegra SoCs. Many submaintainers operate +on a vendor level, responsible for multiple product lines. For several reasons, +including acquisitions/different business units in a company, things vary +significantly here. The various submaintainers are documented in the +MAINTAINERS file. + +Most of these submaintainers have their own trees where they stage patches, +sending pull requests to the main SoC tree. These trees are usually, but not +always, listed in MAINTAINERS. The main SoC maintainers can be reached via the +alias soc@kernel.org if there is no platform-specific maintainer, or if they +are unresponsive. + +What the SoC tree is not, however, is a location for architecture-specific code +changes. Each architecture has its own maintainers that are responsible for +architectural details, CPU errata and the like. + +Information for (new) Submaintainers +------------------------------------ + +As new platforms spring up, they often bring with them new submaintainers, +many of whom work for the silicon vendor, and may not be familiar with the +process. + +Devicetree ABI Stability +~~~~~~~~~~~~~~~~~~~~~~~~ + +Perhaps one of the most important things to highlight is that dt-bindings +document the ABI between the devicetree and the kernel. +Please read Documentation/devicetree/bindings/ABI.rst. + +If changes are being made to a devicetree that are incompatible with old +kernels, the devicetree patch should not be applied until the driver is, or an +appropriate time later. Most importantly, any incompatible changes should be +clearly pointed out in the patch description and pull request, along with the +expected impact on existing users, such as bootloaders or other operating +systems. + +Driver Branch Dependencies +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +A common problem is synchronizing changes between device drivers and devicetree +files. Even if a change is compatible in both directions, this may require +coordinating how the changes get merged through different maintainer trees. + +Usually the branch that includes a driver change will also include the +corresponding change to the devicetree binding description, to ensure they are +in fact compatible. This means that the devicetree branch can end up causing +warnings in the "make dtbs_check" step. If a devicetree change depends on +missing additions to a header file in include/dt-bindings/, it will fail the +"make dtbs" step and not get merged. + +There are multiple ways to deal with this: + +* Avoid defining custom macros in include/dt-bindings/ for hardware constants + that can be derived from a datasheet -- binding macros in header files should + only be used as a last resort if there is no natural way to define a binding + +* Use literal values in the devicetree file in place of macros even when a + header is required, and change them to the named representation in a + following release + +* Defer the devicetree changes to a release after the binding and driver have + already been merged + +* Change the bindings in a shared immutable branch that is used as the base for + both the driver change and the devicetree changes + +* Add duplicate defines in the devicetree file guarded by an #ifndef section, + removing them in a later release + +Devicetree Naming Convention +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The general naming scheme for devicetree files is as follows. The aspects of a +platform that are set at the SoC level, like CPU cores, are contained in a file +named $soc.dtsi, for example, jh7100.dtsi. Integration details, that will vary +from board to board, are described in $soc-$board.dts. An example of this is +jh7100-beaglev-starlight.dts. Often many boards are variations on a theme, and +frequently there are intermediate files, such as jh7100-common.dtsi, which sit +between the $soc.dtsi and $soc-$board.dts files, containing the descriptions of +common hardware. + +Some platforms also have System on Modules, containing an SoC, which are then +integrated into several different boards. For these platforms, $soc-$som.dtsi +and $soc-$som-$board.dts are typical. + +Directories are usually named after the vendor of the SoC at the time of its +inclusion, leading to some historical directory names in the tree. + +Validating Devicetree Files +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +``make dtbs_check`` can be used to validate that devicetree files are compliant +with the dt-bindings that describe the ABI. Please read the section +"Running checks" of Documentation/devicetree/bindings/writing-schema.rst for +more information on the validation of devicetrees. + +For new platforms, or additions to existing ones, ``make dtbs_check`` should not +add any new warnings. For RISC-V, as it has the advantage of being a newer +architecture, ``make dtbs_check W=1`` is required to not add any new warnings. +If in any doubt about a devicetree change, reach out to the devicetree +maintainers. + +Branches and Pull Requests +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Just as the main SoC tree has several branches, it is expected that +submaintainers will do the same. Driver, defconfig and devicetree changes should +all be split into separate branches and appear in separate pull requests to the +SoC maintainers. Each branch should be usable by itself and avoid +regressions that originate from dependencies on other branches. + +Small sets of patches can also be sent as separate emails to soc@kernel.org, +grouped into the same categories. + +If changes do not fit into the normal patterns, there can be additional +top-level branches, e.g. for a treewide rework, or the addition of new SoC +platforms including dts files and drivers. + +Branches with a lot of changes can benefit from getting split up into separate +topics branches, even if they end up getting merged into the same branch of the +SoC tree. An example here would be one branch for devicetree warning fixes, one +for a rework and one for newly added boards. + +Another common way to split up changes is to send an early pull request with the +majority of the changes at some point between rc1 and rc4, following up with one +or more smaller pull requests towards the end of the cycle that can add late +changes or address problems identified while testing the first set. + +While there is no cut-off time for late pull requests, it helps to only send +small branches as time gets closer to the merge window. + +Pull requests for bugfixes for the current release can be sent at any time, but +again having multiple smaller branches is better than trying to combine too many +patches into one pull request. + +The subject line of a pull request should begin with "[GIT PULL]" and made using +a signed tag, rather than a branch. This tag should contain a short description +summarising the changes in the pull request. For more detail on sending pull +requests, please see Documentation/maintainer/pull-requests.rst. diff --git a/MAINTAINERS b/MAINTAINERS index 467a794e90c1..e712fa257161 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1627,6 +1627,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained C: irc://irc.libera.chat/armlinux T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git +F: Documentation/process/maintainer-soc.rst F: arch/arm/boot/dts/Makefile F: arch/arm64/boot/dts/Makefile @@ -2493,6 +2494,18 @@ F: drivers/rtc/rtc-ab8500.c F: drivers/rtc/rtc-pl031.c F: drivers/soc/ux500/ +ARM/NUVOTON MA35 ARCHITECTURE +M: Jacky Huang <ychuang3@nuvoton.com> +M: Shan-Chun Hung <schung@nuvoton.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/*/*ma35* +F: Documentation/devicetree/bindings/*/*ma35* +F: arch/arm64/boot/dts/nuvoton/*ma35* +F: drivers/*/*/*ma35* +F: drivers/*/*ma35* +K: ma35d1 + ARM/NUVOTON NPCM ARCHITECTURE M: Avi Fishman <avifishman70@gmail.com> M: Tomer Maimon <tmaimon77@gmail.com> @@ -2504,7 +2517,6 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* -F: Documentation/devicetree/bindings/arm/npcm/* F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml F: arch/arm/boot/dts/nuvoton/nuvoton-npcm* F: arch/arm/mach-npcm/ @@ -2823,6 +2835,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-nex F: arch/arm/boot/dts/st/stm32* F: arch/arm/mach-stm32/ F: drivers/clocksource/armv7m_systick.c +F: arch/arm64/boot/dts/st/ N: stm32 N: stm diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..6069120199bb 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -225,6 +225,14 @@ config ARCH_S32 endif +config ARCH_MA35 + bool "Nuvoton MA35 Architecture" + select GPIOLIB + select PINCTRL + select RESET_CONTROLLER + help + This enables support for the ARMv8 based Nuvoton MA35 series SoCs. + config ARCH_NPCM bool "Nuvoton NPCM Architecture" select PINCTRL @@ -277,6 +285,20 @@ config ARCH_INTEL_SOCFPGA Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, Agilex and eASIC N5X. +config ARCH_STM32 + bool "STMicroelectronics STM32 SoC Family" + select GPIOLIB + select PINCTRL + select PINCTRL_STM32MP257 + select ARM_SMC_MBOX + select ARM_SCMI_PROTOCOL + select COMMON_CLK_SCMI + help + This enables support for ARMv8 based STMicroelectronics + STM32 family, including: + - STM32MP25: + - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. + config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" select IRQ_FASTEOI_HIERARCHY_HANDLERS diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 7b107fa7414b..30dd6347a929 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,6 +27,7 @@ subdir-y += renesas subdir-y += rockchip subdir-y += socionext subdir-y += sprd +subdir-y += st subdir-y += synaptics subdir-y += tesla subdir-y += ti diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile index a99dab90472a..3bc9787801a5 100644 --- a/arch/arm64/boot/dts/nuvoton/Makefile +++ b/arch/arm64/boot/dts/nuvoton/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MA35) += ma35d1-iot-512m.dtb +dtb-$(CONFIG_ARCH_MA35) += ma35d1-som-256m.dtb dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts new file mode 100644 index 000000000000..b89e2be6abae --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung <schung@nuvoton.com> + * Jacky huang <ychuang3@nuvoton.com> + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-IoT"; + compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts new file mode 100644 index 000000000000..a1ebddecb7f8 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung <schung@nuvoton.com> + * Jacky huang <ychuang3@nuvoton.com> + */ + +/dts-v1/; +#include "ma35d1.dtsi" + +/ { + model = "Nuvoton MA35D1-SOM"; + compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + mem: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */ + }; + + clk_hxt: clock-hxt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk_hxt"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&clk { + assigned-clocks = <&clk CAPLL>, + <&clk DDRPLL>, + <&clk APLL>, + <&clk EPLL>, + <&clk VPLL>; + assigned-clock-rates = <800000000>, + <266000000>, + <180000000>, + <500000000>, + <102000000>; + nuvoton,pll-mode = "integer", + "fractional", + "integer", + "integer", + "integer"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi new file mode 100644 index 000000000000..781cdae566a0 --- /dev/null +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Shan-Chun Hung <schung@nuvoton.com> + * Jacky huang <ychuang3@nuvoton.com> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/nuvoton,ma35d1-clk.h> +#include <dt-bindings/reset/nuvoton,ma35d1-reset.h> + +/ { + compatible = "nuvoton,ma35d1"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@50801000 { + compatible = "arm,gic-400"; + reg = <0x0 0x50801000 0 0x1000>, /* GICD */ + <0x0 0x50802000 0 0x2000>, /* GICC */ + <0x0 0x50804000 0 0x2000>, /* GICH */ + <0x0 0x50806000 0 0x2000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + interrupt-parent = <&gic>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sys: system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x0 0x40460000 0x0 0x200>; + #reset-cells = <1>; + }; + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x00000000 0x40460200 0x0 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + }; + + uart0: serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40700000 0x0 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART0_GATE>; + status = "disabled"; + }; + + uart1: serial@40710000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40710000 0x0 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART1_GATE>; + status = "disabled"; + }; + + uart2: serial@40720000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40720000 0x0 0x100>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART2_GATE>; + status = "disabled"; + }; + + uart3: serial@40730000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40730000 0x0 0x100>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART3_GATE>; + status = "disabled"; + }; + + uart4: serial@40740000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40740000 0x0 0x100>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART4_GATE>; + status = "disabled"; + }; + + uart5: serial@40750000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40750000 0x0 0x100>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART5_GATE>; + status = "disabled"; + }; + + uart6: serial@40760000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40760000 0x0 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART6_GATE>; + status = "disabled"; + }; + + uart7: serial@40770000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40770000 0x0 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART7_GATE>; + status = "disabled"; + }; + + uart8: serial@40780000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40780000 0x0 0x100>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART8_GATE>; + status = "disabled"; + }; + + uart9: serial@40790000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40790000 0x0 0x100>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART9_GATE>; + status = "disabled"; + }; + + uart10: serial@407a0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407a0000 0x0 0x100>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART10_GATE>; + status = "disabled"; + }; + + uart11: serial@407b0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407b0000 0x0 0x100>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART11_GATE>; + status = "disabled"; + }; + + uart12: serial@407c0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407c0000 0x0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART12_GATE>; + status = "disabled"; + }; + + uart13: serial@407d0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407d0000 0x0 0x100>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART13_GATE>; + status = "disabled"; + }; + + uart14: serial@407e0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407e0000 0x0 0x100>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART14_GATE>; + status = "disabled"; + }; + + uart15: serial@407f0000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x407f0000 0x0 0x100>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART15_GATE>; + status = "disabled"; + }; + + uart16: serial@40880000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x0 0x40880000 0x0 0x100>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk UART16_GATE>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile new file mode 100644 index 000000000000..881fe1296c58 --- /dev/null +++ b/arch/arm64/boot/dts/st/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi new file mode 100644 index 000000000000..d34a1d5e79c0 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi new file mode 100644 index 000000000000..5268a4321841 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi new file mode 100644 index 000000000000..af48e82efe8a --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi new file mode 100644 index 000000000000..e6fa596211f5 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257.dtsi b/arch/arm64/boot/dts/st/stm32mp257.dtsi new file mode 100644 index 000000000000..5c5000d3d9db --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts new file mode 100644 index 000000000000..39b4726cc098 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi new file mode 100644 index 000000000000..5e83a6926485 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xf.dtsi b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi new file mode 100644 index 000000000000..5e83a6926485 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 000000000000..abdbc7aebc7f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AI>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 000000000000..2e0d4d349d14 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AK>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 000000000000..2406e972554c --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AL>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a24609e14d50..4968feb2812c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -52,12 +52,14 @@ CONFIG_ARCH_NXP=y CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_MXC=y CONFIG_ARCH_S32=y +CONFIG_ARCH_MA35=y CONFIG_ARCH_NPCM=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_STM32=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TESLA_FSD=y @@ -461,6 +463,8 @@ CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_STM32=y +CONFIG_SERIAL_STM32_CONSOLE=y CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_OWL=y CONFIG_SERIAL_DEV_BUS=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c0c8e526a1e9..93f38a8178ba 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -478,6 +478,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mstar/Kconfig" source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" +source "drivers/clk/nuvoton/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/ralink/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0aebef17edc6..7cb000549b61 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -106,6 +106,7 @@ endif obj-y += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_ARCH_MA35) += nuvoton/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ diff --git a/drivers/clk/nuvoton/Kconfig b/drivers/clk/nuvoton/Kconfig new file mode 100644 index 000000000000..fe4b7f62f467 --- /dev/null +++ b/drivers/clk/nuvoton/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for Nuvoton SoC family. + +config COMMON_CLK_NUVOTON + bool "Nuvoton clock controller common support" + depends on ARCH_MA35 || COMPILE_TEST + default y + help + Say y here to enable common clock controller for Nuvoton platforms. + +if COMMON_CLK_NUVOTON + +config CLK_MA35D1 + bool "Nuvoton MA35D1 clock controller support" + default y + help + Build the clock controller driver for MA35D1 SoC. + +endif diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile new file mode 100644 index 000000000000..c3c59dd9f2aa --- /dev/null +++ b/drivers/clk/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o +obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o +obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c new file mode 100644 index 000000000000..bb8c23d2b895 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li <cfli0@nuvoton.com> + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/regmap.h> +#include <linux/spinlock.h> + +#include "clk-ma35d1.h" + +struct ma35d1_adc_clk_div { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u32 mask; + const struct clk_div_table *table; + /* protects concurrent access to clock divider registers */ + spinlock_t *lock; +}; + +static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw) +{ + return container_of(_hw, struct ma35d1_adc_clk_div, hw); +} + +static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + unsigned int val; + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + val = readl_relaxed(dclk->reg) >> dclk->shift; + val &= clk_div_mask(dclk->width); + val += 1; + return divider_recalc_rate(hw, parent_rate, val, dclk->table, + CLK_DIVIDER_ROUND_CLOSEST, dclk->width); +} + +static long ma35d1_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) +{ + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + return divider_round_rate(hw, rate, prate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); +} + +static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) +{ + int value; + unsigned long flags = 0; + u32 data; + struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); + + value = divider_get_val(rate, parent_rate, dclk->table, + dclk->width, CLK_DIVIDER_ROUND_CLOSEST); + + spin_lock_irqsave(dclk->lock, flags); + + data = readl_relaxed(dclk->reg); + data &= ~(clk_div_mask(dclk->width) << dclk->shift); + data |= (value - 1) << dclk->shift; + data |= dclk->mask; + writel_relaxed(data, dclk->reg); + + spin_unlock_irqrestore(dclk->lock, flags); + return 0; +} + +static const struct clk_ops ma35d1_adc_clkdiv_ops = { + .recalc_rate = ma35d1_clkdiv_recalc_rate, + .round_rate = ma35d1_clkdiv_round_rate, + .set_rate = ma35d1_clkdiv_set_rate, +}; + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + struct clk_hw *parent_hw, spinlock_t *lock, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit) +{ + struct ma35d1_adc_clk_div *div; + struct clk_init_data init; + struct clk_div_table *table; + struct clk_parent_data pdata = { .index = 0 }; + u32 max_div, min_div; + struct clk_hw *hw; + int ret; + int i; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + max_div = clk_div_mask(width) + 1; + min_div = 1; + + table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL); + if (!table) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < max_div; i++) { + table[i].val = min_div + i; + table[i].div = 2 * table[i].val; + } + table[max_div].val = 0; + table[max_div].div = 0; + + memset(&init, 0, sizeof(init)); + init.name = name; + init.ops = &ma35d1_adc_clkdiv_ops; + init.flags |= flags; + pdata.hw = parent_hw; + init.parent_data = &pdata; + init.num_parents = 1; + + div->reg = reg; + div->shift = shift; + div->width = width; + div->mask = mask_bit ? BIT(mask_bit) : 0; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + hw = &div->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + return hw; +} +EXPORT_SYMBOL_GPL(ma35d1_reg_adc_clkdiv); diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c new file mode 100644 index 000000000000..ff3fb8b87c24 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li <cfli0@nuvoton.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/container_of.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/math64.h> +#include <linux/slab.h> +#include <linux/units.h> +#include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + +#include "clk-ma35d1.h" + +/* PLL frequency limits */ +#define PLL_FREF_MAX_FREQ (200 * HZ_PER_MHZ) +#define PLL_FREF_MIN_FREQ (1 * HZ_PER_MHZ) +#define PLL_FREF_M_MAX_FREQ (40 * HZ_PER_MHZ) +#define PLL_FREF_M_MIN_FREQ (10 * HZ_PER_MHZ) +#define PLL_FCLK_MAX_FREQ (2400 * HZ_PER_MHZ) +#define PLL_FCLK_MIN_FREQ (600 * HZ_PER_MHZ) +#define PLL_FCLKO_MAX_FREQ (2400 * HZ_PER_MHZ) +#define PLL_FCLKO_MIN_FREQ (85700 * HZ_PER_KHZ) +#define PLL_SS_RATE 0x77 +#define PLL_SLOPE 0x58CFA + +#define REG_PLL_CTL0_OFFSET 0x0 +#define REG_PLL_CTL1_OFFSET 0x4 +#define REG_PLL_CTL2_OFFSET 0x8 + +/* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */ +#define SPLL0_CTL0_FBDIV GENMASK(7, 0) +#define SPLL0_CTL0_INDIV GENMASK(11, 8) +#define SPLL0_CTL0_OUTDIV GENMASK(13, 12) +#define SPLL0_CTL0_PD BIT(16) +#define SPLL0_CTL0_BP BIT(17) + +/* bit fields for REG_CLK_PLLxCTL0 ~ REG_CLK_PLLxCTL2, where x = 2 ~ 5 */ +#define PLL_CTL0_FBDIV GENMASK(10, 0) +#define PLL_CTL0_INDIV GENMASK(17, 12) +#define PLL_CTL0_MODE GENMASK(19, 18) +#define PLL_CTL0_SSRATE GENMASK(30, 20) +#define PLL_CTL1_PD BIT(0) +#define PLL_CTL1_BP BIT(1) +#define PLL_CTL1_OUTDIV GENMASK(6, 4) +#define PLL_CTL1_FRAC GENMASK(31, 24) +#define PLL_CTL2_SLOPE GENMASK(23, 0) + +#define INDIV_MIN 1 +#define INDIV_MAX 63 +#define FBDIV_MIN 16 +#define FBDIV_MAX 2047 +#define FBDIV_FRAC_MIN 1600 +#define FBDIV_FRAC_MAX 204700 +#define OUTDIV_MIN 1 +#define OUTDIV_MAX 7 + +#define PLL_MODE_INT 0 +#define PLL_MODE_FRAC 1 +#define PLL_MODE_SS 2 + +struct ma35d1_clk_pll { + struct clk_hw hw; + u32 id; + u8 mode; + void __iomem *ctl0_base; + void __iomem *ctl1_base; + void __iomem *ctl2_base; +}; + +static inline struct ma35d1_clk_pll *to_ma35d1_clk_pll(struct clk_hw *_hw) +{ + return container_of(_hw, struct ma35d1_clk_pll, hw); +} + +static unsigned long ma35d1_calc_smic_pll_freq(u32 pll0_ctl0, + unsigned long parent_rate) +{ + u32 m, n, p, outdiv; + u64 pll_freq; + + if (pll0_ctl0 & SPLL0_CTL0_BP) + return parent_rate; + + n = FIELD_GET(SPLL0_CTL0_FBDIV, pll0_ctl0); + m = FIELD_GET(SPLL0_CTL0_INDIV, pll0_ctl0); + p = FIELD_GET(SPLL0_CTL0_OUTDIV, pll0_ctl0); + outdiv = 1 << p; + pll_freq = (u64)parent_rate * n; + div_u64(pll_freq, m * outdiv); + return pll_freq; +} + +static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) +{ + unsigned long pll_freq, x; + u32 m, n, p; + + if (reg_ctl[1] & PLL_CTL1_BP) + return parent_rate; + + n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]); + m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]); + p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]); + + if (mode == PLL_MODE_INT) { + pll_freq = (u64)parent_rate * n; + div_u64(pll_freq, m * p); + } else { + x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]); + /* 2 decimal places floating to integer (ex. 1.23 to 123) */ + n = n * 100 + ((x * 100) / FIELD_MAX(PLL_CTL1_FRAC)); + pll_freq = div_u64(parent_rate * n, 100 * m * p); + } + return pll_freq; +} + +static int ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, unsigned long rate, + unsigned long parent_rate, u32 *reg_ctl, + unsigned long *freq) +{ + unsigned long min_diff = ULONG_MAX; + int fbdiv_min, fbdiv_max; + int p, m, n; + + *freq = 0; + if (rate < PLL_FCLKO_MIN_FREQ || rate > PLL_FCLKO_MAX_FREQ) + return -EINVAL; + + if (pll->mode == PLL_MODE_INT) { + fbdiv_min = FBDIV_MIN; + fbdiv_max = FBDIV_MAX; + } else { + fbdiv_min = FBDIV_FRAC_MIN; + fbdiv_max = FBDIV_FRAC_MAX; + } + + for (m = INDIV_MIN; m <= INDIV_MAX; m++) { + for (n = fbdiv_min; n <= fbdiv_max; n++) { + for (p = OUTDIV_MIN; p <= OUTDIV_MAX; p++) { + unsigned long tmp, fout, fclk, diff; + + tmp = div_u64(parent_rate, m); + if (tmp < PLL_FREF_M_MIN_FREQ || + tmp > PLL_FREF_M_MAX_FREQ) + continue; /* constrain */ + + fclk = div_u64(parent_rate * n, m); + /* for 2 decimal places */ + if (pll->mode != PLL_MODE_INT) + fclk = div_u64(fclk, 100); + + if (fclk < PLL_FCLK_MIN_FREQ || + fclk > PLL_FCLK_MAX_FREQ) + continue; /* constrain */ + + fout = div_u64(fclk, p); + if (fout < PLL_FCLKO_MIN_FREQ || + fout > PLL_FCLKO_MAX_FREQ) + continue; /* constrain */ + + diff = abs(rate - fout); + if (diff < min_diff) { + reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) | + FIELD_PREP(PLL_CTL0_FBDIV, n); + reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p); + *freq = fout; + min_diff = diff; + if (min_diff == 0) + break; + } + } + } + } + if (*freq == 0) + return -EINVAL; /* cannot find even one valid setting */ + return 0; +} + +static int ma35d1_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3] = { 0 }; + unsigned long pll_freq; + int ret; + + if (parent_rate < PLL_FREF_MIN_FREQ || parent_rate > PLL_FREF_MAX_FREQ) + return -EINVAL; + + ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq); + if (ret != 0) + return ret; + + switch (pll->mode) { + case PLL_MODE_INT: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_INT); + break; + case PLL_MODE_FRAC: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_FRAC); + break; + case PLL_MODE_SS: + reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_SS) | + FIELD_PREP(PLL_CTL0_SSRATE, PLL_SS_RATE); + reg_ctl[2] = FIELD_PREP(PLL_CTL2_SLOPE, PLL_SLOPE); + break; + } + reg_ctl[1] |= PLL_CTL1_PD; + + writel_relaxed(reg_ctl[0], pll->ctl0_base); + writel_relaxed(reg_ctl[1], pll->ctl1_base); + writel_relaxed(reg_ctl[2], pll->ctl2_base); + return 0; +} + +static unsigned long ma35d1_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3]; + unsigned long pll_freq; + + if (parent_rate < PLL_FREF_MIN_FREQ || parent_rate > PLL_FREF_MAX_FREQ) + return 0; + + switch (pll->id) { + case CAPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate); + return pll_freq; + case DDRPLL: + case APLL: + case EPLL: + case VPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + reg_ctl[1] = readl_relaxed(pll->ctl1_base); + pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate); + return pll_freq; + } + return 0; +} + +static long ma35d1_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 reg_ctl[3] = { 0 }; + unsigned long pll_freq; + long ret; + + if (*parent_rate < PLL_FREF_MIN_FREQ || *parent_rate > PLL_FREF_MAX_FREQ) + return -EINVAL; + + ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq); + if (ret < 0) + return ret; + + switch (pll->id) { + case CAPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], *parent_rate); + return pll_freq; + case DDRPLL: + case APLL: + case EPLL: + case VPLL: + reg_ctl[0] = readl_relaxed(pll->ctl0_base); + reg_ctl[1] = readl_relaxed(pll->ctl1_base); + pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate); + return pll_freq; + } + return 0; +} + +static int ma35d1_clk_pll_is_prepared(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val = readl_relaxed(pll->ctl1_base); + + return !(val & PLL_CTL1_PD); +} + +static int ma35d1_clk_pll_prepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + val = readl_relaxed(pll->ctl1_base); + val &= ~PLL_CTL1_PD; + writel_relaxed(val, pll->ctl1_base); + return 0; +} + +static void ma35d1_clk_pll_unprepare(struct clk_hw *hw) +{ + struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw); + u32 val; + + val = readl_relaxed(pll->ctl1_base); + val |= PLL_CTL1_PD; + writel_relaxed(val, pll->ctl1_base); +} + +static const struct clk_ops ma35d1_clk_pll_ops = { + .is_prepared = ma35d1_clk_pll_is_prepared, + .prepare = ma35d1_clk_pll_prepare, + .unprepare = ma35d1_clk_pll_unprepare, + .set_rate = ma35d1_clk_pll_set_rate, + .recalc_rate = ma35d1_clk_pll_recalc_rate, + .round_rate = ma35d1_clk_pll_round_rate, +}; + +static const struct clk_ops ma35d1_clk_fixed_pll_ops = { + .recalc_rate = ma35d1_clk_pll_recalc_rate, + .round_rate = ma35d1_clk_pll_round_rate, +}; + +struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, + struct clk_hw *parent_hw, void __iomem *base) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = {}; + struct ma35d1_clk_pll *pll; + struct clk_hw *hw; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->id = id; + pll->mode = u8mode; + pll->ctl0_base = base + REG_PLL_CTL0_OFFSET; + pll->ctl1_base = base + REG_PLL_CTL1_OFFSET; + pll->ctl2_base = base + REG_PLL_CTL2_OFFSET; + + init.name = name; + init.flags = 0; + pdata.hw = parent_hw; + init.parent_data = &pdata; + init.num_parents = 1; + + if (id == CAPLL || id == DDRPLL) + init.ops = &ma35d1_clk_fixed_pll_ops; + else + init.ops = &ma35d1_clk_pll_ops; + + pll->hw.init = &init; + hw = &pll->hw; + + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + return hw; +} +EXPORT_SYMBOL_GPL(ma35d1_reg_clk_pll); diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c new file mode 100644 index 000000000000..f1fe7edd21b5 --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -0,0 +1,1059 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li <cfli0@nuvoton.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + +#include "clk-ma35d1.h" + +static DEFINE_SPINLOCK(ma35d1_lock); + +#define PLL_MAX_NUM 5 + +/* Clock Control Registers Offset */ +#define REG_CLK_PWRCTL 0x00 +#define REG_CLK_SYSCLK0 0x04 +#define REG_CLK_SYSCLK1 0x08 +#define REG_CLK_APBCLK0 0x0c +#define REG_CLK_APBCLK1 0x10 +#define REG_CLK_APBCLK2 0x14 +#define REG_CLK_CLKSEL0 0x18 +#define REG_CLK_CLKSEL1 0x1c +#define REG_CLK_CLKSEL2 0x20 +#define REG_CLK_CLKSEL3 0x24 +#define REG_CLK_CLKSEL4 0x28 +#define REG_CLK_CLKDIV0 0x2c +#define REG_CLK_CLKDIV1 0x30 +#define REG_CLK_CLKDIV2 0x34 +#define REG_CLK_CLKDIV3 0x38 +#define REG_CLK_CLKDIV4 0x3c +#define REG_CLK_CLKOCTL 0x40 +#define REG_CLK_STATUS 0x50 +#define REG_CLK_PLL0CTL0 0x60 +#define REG_CLK_PLL2CTL0 0x80 +#define REG_CLK_PLL2CTL1 0x84 +#define REG_CLK_PLL2CTL2 0x88 +#define REG_CLK_PLL3CTL0 0x90 +#define REG_CLK_PLL3CTL1 0x94 +#define REG_CLK_PLL3CTL2 0x98 +#define REG_CLK_PLL4CTL0 0xa0 +#define REG_CLK_PLL4CTL1 0xa4 +#define REG_CLK_PLL4CTL2 0xa8 +#define REG_CLK_PLL5CTL0 0xb0 +#define REG_CLK_PLL5CTL1 0xb4 +#define REG_CLK_PLL5CTL2 0xb8 +#define REG_CLK_CLKDCTL 0xc0 +#define REG_CLK_CLKDSTS 0xc4 +#define REG_CLK_CDUPB 0xc8 +#define REG_CLK_CDLOWB 0xcc +#define REG_CLK_CKFLTRCTL 0xd0 +#define REG_CLK_TESTCLK 0xf0 +#define REG_CLK_PLLCTL 0x40 + +#define PLL_MODE_INT 0 +#define PLL_MODE_FRAC 1 +#define PLL_MODE_SS 2 + +static const struct clk_parent_data ca35clk_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "capll", }, + { .fw_name = "ddrpll", }, +}; + +static const struct clk_parent_data sysclk0_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data sysclk1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data axiclk_sel_clks[] = { + { .fw_name = "capll_div2", }, + { .fw_name = "capll_div4", }, +}; + +static const struct clk_parent_data ccap_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "vpll", }, + { .fw_name = "apll", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data sdh_sel_clks[] = { + { .fw_name = "syspll", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data dcu_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data gfx_sel_clks[] = { + { .fw_name = "epll", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data dbg_sel_clks[] = { + { .fw_name = "hirc", }, + { .fw_name = "syspll", }, +}; + +static const struct clk_parent_data timer0_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer2_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer3_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer4_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer5_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer6_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer7_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer8_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer9_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer10_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data timer11_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, +}; + +static const struct clk_parent_data uart_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "sysclk1_div2", }, +}; + +static const struct clk_parent_data wdt0_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wdt1_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wdt2_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wwdt0_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wwdt1_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data wwdt2_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, +}; + +static const struct clk_parent_data spi0_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data spi1_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data spi2_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data spi3_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data qspi0_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data qspi1_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, +}; + +static const struct clk_parent_data i2s0_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, +}; + +static const struct clk_parent_data i2s1_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, +}; + +static const struct clk_parent_data can_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "vpll", }, +}; + +static const struct clk_parent_data cko_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "hirc", }, + { .fw_name = "lirc", }, + { .fw_name = "capll_div4", }, + { .fw_name = "syspll", }, + { .fw_name = "ddrpll", }, + { .fw_name = "epll_div2", }, + { .fw_name = "apll", }, + { .fw_name = "vpll", }, +}; + +static const struct clk_parent_data smc_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "pclk4", }, +}; + +static const struct clk_parent_data kpi_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, +}; + +static const struct clk_div_table ip_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {0, 0}, +}; + +static const struct clk_div_table eadc_div_table[] = { + {0, 2}, {1, 4}, {2, 6}, {3, 8}, {4, 10}, + {5, 12}, {6, 14}, {7, 16}, {8, 18}, + {9, 20}, {10, 22}, {11, 24}, {12, 26}, + {13, 28}, {14, 30}, {15, 32}, {0, 0}, +}; + +static struct clk_hw *ma35d1_clk_fixed(const char *name, int rate) +{ + return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); +} + +static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, + const struct clk_parent_data *pdata, + int num_pdata) +{ + return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, + void __iomem *reg, u8 shift, u8 width, + const struct clk_parent_data *pdata, + int num_pdata) +{ + return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) +{ + return devm_clk_hw_register_divider(dev, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_divider_pow2(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width) +{ + return devm_clk_hw_register_divider(dev, name, parent, + CLK_DIVIDER_POWER_OF_TWO, reg, shift, + width, 0, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_divider_table(struct device *dev, const char *name, + const char *parent, void __iomem *reg, + u8 shift, u8 width, + const struct clk_div_table *table) +{ + return devm_clk_hw_register_divider_table(dev, name, parent, 0, + reg, shift, width, 0, + table, &ma35d1_lock); +} + +static struct clk_hw *ma35d1_clk_fixed_factor(struct device *dev, const char *name, + const char *parent, unsigned int mult, + unsigned int div) +{ + return devm_clk_hw_register_fixed_factor(dev, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static struct clk_hw *ma35d1_clk_gate(struct device *dev, const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return devm_clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, + reg, shift, 0, &ma35d1_lock); +} + +static int ma35d1_get_pll_setting(struct device_node *clk_node, u32 *pllmode) +{ + const char *of_str; + int i; + + for (i = 0; i < PLL_MAX_NUM; i++) { + if (of_property_read_string_index(clk_node, "nuvoton,pll-mode", i, &of_str)) + return -EINVAL; + if (!strcmp(of_str, "integer")) + pllmode[i] = PLL_MODE_INT; + else if (!strcmp(of_str, "fractional")) + pllmode[i] = PLL_MODE_FRAC; + else if (!strcmp(of_str, "spread-spectrum")) + pllmode[i] = PLL_MODE_SS; + else + return -EINVAL; + } + return 0; +} + +static int ma35d1_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *clk_node = pdev->dev.of_node; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + void __iomem *clk_base; + static struct clk_hw **hws; + static struct clk_hw_onecell_data *ma35d1_hw_data; + u32 pllmode[PLL_MAX_NUM]; + int ret; + + ma35d1_hw_data = devm_kzalloc(dev, + struct_size(ma35d1_hw_data, hws, CLK_MAX_IDX), + GFP_KERNEL); + if (!ma35d1_hw_data) + return -ENOMEM; + + ma35d1_hw_data->num = CLK_MAX_IDX; + hws = ma35d1_hw_data->hws; + + clk_base = devm_ioremap_resource(dev, res); + if (IS_ERR(clk_base)) + return PTR_ERR(clk_base); + + ret = ma35d1_get_pll_setting(clk_node, pllmode); + if (ret < 0) { + dev_err(dev, "Invalid PLL setting!\n"); + return -EINVAL; + } + + hws[HXT] = ma35d1_clk_fixed("hxt", 24000000); + hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt", + clk_base + REG_CLK_PWRCTL, 0); + hws[LXT] = ma35d1_clk_fixed("lxt", 32768); + hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt", + clk_base + REG_CLK_PWRCTL, 1); + hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000); + hws[HIRC_GATE] = ma35d1_clk_gate(dev, "hirc_gate", "hirc", + clk_base + REG_CLK_PWRCTL, 2); + hws[LIRC] = ma35d1_clk_fixed("lirc", 32000); + hws[LIRC_GATE] = ma35d1_clk_gate(dev, "lirc_gate", "lirc", + clk_base + REG_CLK_PWRCTL, 3); + + hws[CAPLL] = ma35d1_reg_clk_pll(dev, CAPLL, pllmode[0], "capll", + hws[HXT], clk_base + REG_CLK_PLL0CTL0); + hws[SYSPLL] = ma35d1_clk_fixed("syspll", 180000000); + hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", + hws[HXT], clk_base + REG_CLK_PLL2CTL0); + hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", + hws[HXT], clk_base + REG_CLK_PLL3CTL0); + hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", + hws[HXT], clk_base + REG_CLK_PLL4CTL0); + hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", + hws[HXT], clk_base + REG_CLK_PLL5CTL0); + + hws[EPLL_DIV2] = ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2); + hws[EPLL_DIV4] = ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4); + hws[EPLL_DIV8] = ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8); + + hws[CA35CLK_MUX] = ma35d1_clk_mux_parent(dev, "ca35clk_mux", + clk_base + REG_CLK_CLKSEL0, 0, 2, + ca35clk_sel_clks, + ARRAY_SIZE(ca35clk_sel_clks)); + hws[AXICLK_DIV2] = ma35d1_clk_fixed_factor(dev, "capll_div2", "ca35clk_mux", 1, 2); + hws[AXICLK_DIV4] = ma35d1_clk_fixed_factor(dev, "capll_div4", "ca35clk_mux", 1, 4); + + hws[AXICLK_MUX] = ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_CLKDIV0, + 26, 1, axiclk_sel_clks, + ARRAY_SIZE(axiclk_sel_clks)); + hws[SYSCLK0_MUX] = ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CLK_CLKSEL0, + 2, 1, sysclk0_sel_clks, + ARRAY_SIZE(sysclk0_sel_clks)); + hws[SYSCLK1_MUX] = ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CLK_CLKSEL0, + 4, 1, sysclk1_sel_clks, + ARRAY_SIZE(sysclk1_sel_clks)); + hws[SYSCLK1_DIV2] = ma35d1_clk_fixed_factor(dev, "sysclk1_div2", "sysclk1_mux", 1, 2); + + /* HCLK0~3 & PCLK0~4 */ + hws[HCLK0] = ma35d1_clk_fixed_factor(dev, "hclk0", "sysclk1_mux", 1, 1); + hws[HCLK1] = ma35d1_clk_fixed_factor(dev, "hclk1", "sysclk1_mux", 1, 1); + hws[HCLK2] = ma35d1_clk_fixed_factor(dev, "hclk2", "sysclk1_mux", 1, 1); + hws[PCLK0] = ma35d1_clk_fixed_factor(dev, "pclk0", "sysclk1_mux", 1, 1); + hws[PCLK1] = ma35d1_clk_fixed_factor(dev, "pclk1", "sysclk1_mux", 1, 1); + hws[PCLK2] = ma35d1_clk_fixed_factor(dev, "pclk2", "sysclk1_mux", 1, 1); + + hws[HCLK3] = ma35d1_clk_fixed_factor(dev, "hclk3", "sysclk1_mux", 1, 2); + hws[PCLK3] = ma35d1_clk_fixed_factor(dev, "pclk3", "sysclk1_mux", 1, 2); + hws[PCLK4] = ma35d1_clk_fixed_factor(dev, "pclk4", "sysclk1_mux", 1, 2); + + hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); + hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000); + + /* DDR */ + hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 4); + hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", + clk_base + REG_CLK_SYSCLK0, 5); + + hws[CAN0_MUX] = ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKSEL4, + 16, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN0_DIV] = ma35d1_clk_divider_table(dev, "can0_div", "can0_mux", + clk_base + REG_CLK_CLKDIV0, + 0, 3, ip_div_table); + hws[CAN0_GATE] = ma35d1_clk_gate(dev, "can0_gate", "can0_div", + clk_base + REG_CLK_SYSCLK0, 8); + hws[CAN1_MUX] = ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKSEL4, + 17, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN1_DIV] = ma35d1_clk_divider_table(dev, "can1_div", "can1_mux", + clk_base + REG_CLK_CLKDIV0, + 4, 3, ip_div_table); + hws[CAN1_GATE] = ma35d1_clk_gate(dev, "can1_gate", "can1_div", + clk_base + REG_CLK_SYSCLK0, 9); + hws[CAN2_MUX] = ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKSEL4, + 18, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN2_DIV] = ma35d1_clk_divider_table(dev, "can2_div", "can2_mux", + clk_base + REG_CLK_CLKDIV0, + 8, 3, ip_div_table); + hws[CAN2_GATE] = ma35d1_clk_gate(dev, "can2_gate", "can2_div", + clk_base + REG_CLK_SYSCLK0, 10); + hws[CAN3_MUX] = ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKSEL4, + 19, 1, can_sel_clks, ARRAY_SIZE(can_sel_clks)); + hws[CAN3_DIV] = ma35d1_clk_divider_table(dev, "can3_div", "can3_mux", + clk_base + REG_CLK_CLKDIV0, + 12, 3, ip_div_table); + hws[CAN3_GATE] = ma35d1_clk_gate(dev, "can3_gate", "can3_div", + clk_base + REG_CLK_SYSCLK0, 11); + + hws[SDH0_MUX] = ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKSEL0, + 16, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); + hws[SDH0_GATE] = ma35d1_clk_gate(dev, "sdh0_gate", "sdh0_mux", + clk_base + REG_CLK_SYSCLK0, 16); + hws[SDH1_MUX] = ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKSEL0, + 18, 2, sdh_sel_clks, ARRAY_SIZE(sdh_sel_clks)); + hws[SDH1_GATE] = ma35d1_clk_gate(dev, "sdh1_gate", "sdh1_mux", + clk_base + REG_CLK_SYSCLK0, 17); + + hws[NAND_GATE] = ma35d1_clk_gate(dev, "nand_gate", "hclk1", + clk_base + REG_CLK_SYSCLK0, 18); + + hws[USBD_GATE] = ma35d1_clk_gate(dev, "usbd_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 19); + hws[USBH_GATE] = ma35d1_clk_gate(dev, "usbh_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 20); + hws[HUSBH0_GATE] = ma35d1_clk_gate(dev, "husbh0_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 21); + hws[HUSBH1_GATE] = ma35d1_clk_gate(dev, "husbh1_gate", "usbphy0", + clk_base + REG_CLK_SYSCLK0, 22); + + hws[GFX_MUX] = ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL0, + 26, 1, gfx_sel_clks, ARRAY_SIZE(gfx_sel_clks)); + hws[GFX_GATE] = ma35d1_clk_gate(dev, "gfx_gate", "gfx_mux", + clk_base + REG_CLK_SYSCLK0, 24); + hws[VC8K_GATE] = ma35d1_clk_gate(dev, "vc8k_gate", "sysclk0_mux", + clk_base + REG_CLK_SYSCLK0, 25); + hws[DCU_MUX] = ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL0, + 24, 1, dcu_sel_clks, ARRAY_SIZE(dcu_sel_clks)); + hws[DCU_GATE] = ma35d1_clk_gate(dev, "dcu_gate", "dcu_mux", + clk_base + REG_CLK_SYSCLK0, 26); + hws[DCUP_DIV] = ma35d1_clk_divider_table(dev, "dcup_div", "vpll", + clk_base + REG_CLK_CLKDIV0, + 16, 3, ip_div_table); + + hws[EMAC0_GATE] = ma35d1_clk_gate(dev, "emac0_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 27); + hws[EMAC1_GATE] = ma35d1_clk_gate(dev, "emac1_gate", "epll_div2", + clk_base + REG_CLK_SYSCLK0, 28); + + hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0, + 12, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP0_DIV] = ma35d1_clk_divider(dev, "ccap0_div", "ccap0_mux", + clk_base + REG_CLK_CLKDIV1, 8, 4); + hws[CCAP0_GATE] = ma35d1_clk_gate(dev, "ccap0_gate", "ccap0_div", + clk_base + REG_CLK_SYSCLK0, 29); + hws[CCAP1_MUX] = ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CLKSEL0, + 14, 1, ccap_sel_clks, ARRAY_SIZE(ccap_sel_clks)); + hws[CCAP1_DIV] = ma35d1_clk_divider(dev, "ccap1_div", "ccap1_mux", + clk_base + REG_CLK_CLKDIV1, + 12, 4); + hws[CCAP1_GATE] = ma35d1_clk_gate(dev, "ccap1_gate", "ccap1_div", + clk_base + REG_CLK_SYSCLK0, 30); + + hws[PDMA0_GATE] = ma35d1_clk_gate(dev, "pdma0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 0); + hws[PDMA1_GATE] = ma35d1_clk_gate(dev, "pdma1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 1); + hws[PDMA2_GATE] = ma35d1_clk_gate(dev, "pdma2_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 2); + hws[PDMA3_GATE] = ma35d1_clk_gate(dev, "pdma3_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 3); + + hws[WH0_GATE] = ma35d1_clk_gate(dev, "wh0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 4); + hws[WH1_GATE] = ma35d1_clk_gate(dev, "wh1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 5); + + hws[HWS_GATE] = ma35d1_clk_gate(dev, "hws_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 6); + + hws[EBI_GATE] = ma35d1_clk_gate(dev, "ebi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 7); + + hws[SRAM0_GATE] = ma35d1_clk_gate(dev, "sram0_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 8); + hws[SRAM1_GATE] = ma35d1_clk_gate(dev, "sram1_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 9); + + hws[ROM_GATE] = ma35d1_clk_gate(dev, "rom_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 10); + + hws[TRA_GATE] = ma35d1_clk_gate(dev, "tra_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 11); + + hws[DBG_MUX] = ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL0, + 27, 1, dbg_sel_clks, ARRAY_SIZE(dbg_sel_clks)); + hws[DBG_GATE] = ma35d1_clk_gate(dev, "dbg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 12); + + hws[CKO_MUX] = ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL4, + 24, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks)); + hws[CKO_DIV] = ma35d1_clk_divider_pow2(dev, "cko_div", "cko_mux", + clk_base + REG_CLK_CLKOCTL, 0, 4); + hws[CKO_GATE] = ma35d1_clk_gate(dev, "cko_gate", "cko_div", + clk_base + REG_CLK_SYSCLK1, 13); + + hws[GTMR_GATE] = ma35d1_clk_gate(dev, "gtmr_gate", "hirc", + clk_base + REG_CLK_SYSCLK1, 14); + + hws[GPA_GATE] = ma35d1_clk_gate(dev, "gpa_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 16); + hws[GPB_GATE] = ma35d1_clk_gate(dev, "gpb_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 17); + hws[GPC_GATE] = ma35d1_clk_gate(dev, "gpc_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 18); + hws[GPD_GATE] = ma35d1_clk_gate(dev, "gpd_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 19); + hws[GPE_GATE] = ma35d1_clk_gate(dev, "gpe_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 20); + hws[GPF_GATE] = ma35d1_clk_gate(dev, "gpf_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 21); + hws[GPG_GATE] = ma35d1_clk_gate(dev, "gpg_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 22); + hws[GPH_GATE] = ma35d1_clk_gate(dev, "gph_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 23); + hws[GPI_GATE] = ma35d1_clk_gate(dev, "gpi_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 24); + hws[GPJ_GATE] = ma35d1_clk_gate(dev, "gpj_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 25); + hws[GPK_GATE] = ma35d1_clk_gate(dev, "gpk_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 26); + hws[GPL_GATE] = ma35d1_clk_gate(dev, "gpl_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 27); + hws[GPM_GATE] = ma35d1_clk_gate(dev, "gpm_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 28); + hws[GPN_GATE] = ma35d1_clk_gate(dev, "gpn_gate", "hclk0", + clk_base + REG_CLK_SYSCLK1, 29); + + hws[TMR0_MUX] = ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKSEL1, + 0, 3, timer0_sel_clks, + ARRAY_SIZE(timer0_sel_clks)); + hws[TMR0_GATE] = ma35d1_clk_gate(dev, "tmr0_gate", "tmr0_mux", + clk_base + REG_CLK_APBCLK0, 0); + hws[TMR1_MUX] = ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKSEL1, + 4, 3, timer1_sel_clks, + ARRAY_SIZE(timer1_sel_clks)); + hws[TMR1_GATE] = ma35d1_clk_gate(dev, "tmr1_gate", "tmr1_mux", + clk_base + REG_CLK_APBCLK0, 1); + hws[TMR2_MUX] = ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKSEL1, + 8, 3, timer2_sel_clks, + ARRAY_SIZE(timer2_sel_clks)); + hws[TMR2_GATE] = ma35d1_clk_gate(dev, "tmr2_gate", "tmr2_mux", + clk_base + REG_CLK_APBCLK0, 2); + hws[TMR3_MUX] = ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKSEL1, + 12, 3, timer3_sel_clks, + ARRAY_SIZE(timer3_sel_clks)); + hws[TMR3_GATE] = ma35d1_clk_gate(dev, "tmr3_gate", "tmr3_mux", + clk_base + REG_CLK_APBCLK0, 3); + hws[TMR4_MUX] = ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKSEL1, + 16, 3, timer4_sel_clks, + ARRAY_SIZE(timer4_sel_clks)); + hws[TMR4_GATE] = ma35d1_clk_gate(dev, "tmr4_gate", "tmr4_mux", + clk_base + REG_CLK_APBCLK0, 4); + hws[TMR5_MUX] = ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKSEL1, + 20, 3, timer5_sel_clks, + ARRAY_SIZE(timer5_sel_clks)); + hws[TMR5_GATE] = ma35d1_clk_gate(dev, "tmr5_gate", "tmr5_mux", + clk_base + REG_CLK_APBCLK0, 5); + hws[TMR6_MUX] = ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKSEL1, + 24, 3, timer6_sel_clks, + ARRAY_SIZE(timer6_sel_clks)); + hws[TMR6_GATE] = ma35d1_clk_gate(dev, "tmr6_gate", "tmr6_mux", + clk_base + REG_CLK_APBCLK0, 6); + hws[TMR7_MUX] = ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKSEL1, + 28, 3, timer7_sel_clks, + ARRAY_SIZE(timer7_sel_clks)); + hws[TMR7_GATE] = ma35d1_clk_gate(dev, "tmr7_gate", "tmr7_mux", + clk_base + REG_CLK_APBCLK0, 7); + hws[TMR8_MUX] = ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKSEL2, + 0, 3, timer8_sel_clks, + ARRAY_SIZE(timer8_sel_clks)); + hws[TMR8_GATE] = ma35d1_clk_gate(dev, "tmr8_gate", "tmr8_mux", + clk_base + REG_CLK_APBCLK0, 8); + hws[TMR9_MUX] = ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKSEL2, + 4, 3, timer9_sel_clks, + ARRAY_SIZE(timer9_sel_clks)); + hws[TMR9_GATE] = ma35d1_clk_gate(dev, "tmr9_gate", "tmr9_mux", + clk_base + REG_CLK_APBCLK0, 9); + hws[TMR10_MUX] = ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CLKSEL2, + 8, 3, timer10_sel_clks, + ARRAY_SIZE(timer10_sel_clks)); + hws[TMR10_GATE] = ma35d1_clk_gate(dev, "tmr10_gate", "tmr10_mux", + clk_base + REG_CLK_APBCLK0, 10); + hws[TMR11_MUX] = ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CLKSEL2, + 12, 3, timer11_sel_clks, + ARRAY_SIZE(timer11_sel_clks)); + hws[TMR11_GATE] = ma35d1_clk_gate(dev, "tmr11_gate", "tmr11_mux", + clk_base + REG_CLK_APBCLK0, 11); + + hws[UART0_MUX] = ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CLKSEL2, + 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART0_DIV] = ma35d1_clk_divider(dev, "uart0_div", "uart0_mux", + clk_base + REG_CLK_CLKDIV1, + 16, 4); + hws[UART0_GATE] = ma35d1_clk_gate(dev, "uart0_gate", "uart0_div", + clk_base + REG_CLK_APBCLK0, 12); + hws[UART1_MUX] = ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CLKSEL2, + 18, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART1_DIV] = ma35d1_clk_divider(dev, "uart1_div", "uart1_mux", + clk_base + REG_CLK_CLKDIV1, + 20, 4); + hws[UART1_GATE] = ma35d1_clk_gate(dev, "uart1_gate", "uart1_div", + clk_base + REG_CLK_APBCLK0, 13); + hws[UART2_MUX] = ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CLKSEL2, + 20, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART2_DIV] = ma35d1_clk_divider(dev, "uart2_div", "uart2_mux", + clk_base + REG_CLK_CLKDIV1, + 24, 4); + hws[UART2_GATE] = ma35d1_clk_gate(dev, "uart2_gate", "uart2_div", + clk_base + REG_CLK_APBCLK0, 14); + hws[UART3_MUX] = ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CLKSEL2, + 22, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART3_DIV] = ma35d1_clk_divider(dev, "uart3_div", "uart3_mux", + clk_base + REG_CLK_CLKDIV1, + 28, 4); + hws[UART3_GATE] = ma35d1_clk_gate(dev, "uart3_gate", "uart3_div", + clk_base + REG_CLK_APBCLK0, 15); + hws[UART4_MUX] = ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CLKSEL2, + 24, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART4_DIV] = ma35d1_clk_divider(dev, "uart4_div", "uart4_mux", + clk_base + REG_CLK_CLKDIV2, + 0, 4); + hws[UART4_GATE] = ma35d1_clk_gate(dev, "uart4_gate", "uart4_div", + clk_base + REG_CLK_APBCLK0, 16); + hws[UART5_MUX] = ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CLKSEL2, + 26, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART5_DIV] = ma35d1_clk_divider(dev, "uart5_div", "uart5_mux", + clk_base + REG_CLK_CLKDIV2, + 4, 4); + hws[UART5_GATE] = ma35d1_clk_gate(dev, "uart5_gate", "uart5_div", + clk_base + REG_CLK_APBCLK0, 17); + hws[UART6_MUX] = ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CLKSEL2, + 28, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART6_DIV] = ma35d1_clk_divider(dev, "uart6_div", "uart6_mux", + clk_base + REG_CLK_CLKDIV2, + 8, 4); + hws[UART6_GATE] = ma35d1_clk_gate(dev, "uart6_gate", "uart6_div", + clk_base + REG_CLK_APBCLK0, 18); + hws[UART7_MUX] = ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CLKSEL2, + 30, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART7_DIV] = ma35d1_clk_divider(dev, "uart7_div", "uart7_mux", + clk_base + REG_CLK_CLKDIV2, + 12, 4); + hws[UART7_GATE] = ma35d1_clk_gate(dev, "uart7_gate", "uart7_div", + clk_base + REG_CLK_APBCLK0, 19); + hws[UART8_MUX] = ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CLKSEL3, + 0, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART8_DIV] = ma35d1_clk_divider(dev, "uart8_div", "uart8_mux", + clk_base + REG_CLK_CLKDIV2, + 16, 4); + hws[UART8_GATE] = ma35d1_clk_gate(dev, "uart8_gate", "uart8_div", + clk_base + REG_CLK_APBCLK0, 20); + hws[UART9_MUX] = ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CLKSEL3, + 2, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART9_DIV] = ma35d1_clk_divider(dev, "uart9_div", "uart9_mux", + clk_base + REG_CLK_CLKDIV2, + 20, 4); + hws[UART9_GATE] = ma35d1_clk_gate(dev, "uart9_gate", "uart9_div", + clk_base + REG_CLK_APBCLK0, 21); + hws[UART10_MUX] = ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_CLKSEL3, + 4, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART10_DIV] = ma35d1_clk_divider(dev, "uart10_div", "uart10_mux", + clk_base + REG_CLK_CLKDIV2, + 24, 4); + hws[UART10_GATE] = ma35d1_clk_gate(dev, "uart10_gate", "uart10_div", + clk_base + REG_CLK_APBCLK0, 22); + hws[UART11_MUX] = ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_CLKSEL3, + 6, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART11_DIV] = ma35d1_clk_divider(dev, "uart11_div", "uart11_mux", + clk_base + REG_CLK_CLKDIV2, + 28, 4); + hws[UART11_GATE] = ma35d1_clk_gate(dev, "uart11_gate", "uart11_div", + clk_base + REG_CLK_APBCLK0, 23); + hws[UART12_MUX] = ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_CLKSEL3, + 8, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART12_DIV] = ma35d1_clk_divider(dev, "uart12_div", "uart12_mux", + clk_base + REG_CLK_CLKDIV3, + 0, 4); + hws[UART12_GATE] = ma35d1_clk_gate(dev, "uart12_gate", "uart12_div", + clk_base + REG_CLK_APBCLK0, 24); + hws[UART13_MUX] = ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_CLKSEL3, + 10, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART13_DIV] = ma35d1_clk_divider(dev, "uart13_div", "uart13_mux", + clk_base + REG_CLK_CLKDIV3, + 4, 4); + hws[UART13_GATE] = ma35d1_clk_gate(dev, "uart13_gate", "uart13_div", + clk_base + REG_CLK_APBCLK0, 25); + hws[UART14_MUX] = ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_CLKSEL3, + 12, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART14_DIV] = ma35d1_clk_divider(dev, "uart14_div", "uart14_mux", + clk_base + REG_CLK_CLKDIV3, + 8, 4); + hws[UART14_GATE] = ma35d1_clk_gate(dev, "uart14_gate", "uart14_div", + clk_base + REG_CLK_APBCLK0, 26); + hws[UART15_MUX] = ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_CLKSEL3, + 14, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART15_DIV] = ma35d1_clk_divider(dev, "uart15_div", "uart15_mux", + clk_base + REG_CLK_CLKDIV3, + 12, 4); + hws[UART15_GATE] = ma35d1_clk_gate(dev, "uart15_gate", "uart15_div", + clk_base + REG_CLK_APBCLK0, 27); + hws[UART16_MUX] = ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_CLKSEL3, + 16, 2, uart_sel_clks, ARRAY_SIZE(uart_sel_clks)); + hws[UART16_DIV] = ma35d1_clk_divider(dev, "uart16_div", "uart16_mux", + clk_base + REG_CLK_CLKDIV3, + 16, 4); + hws[UART16_GATE] = ma35d1_clk_gate(dev, "uart16_gate", "uart16_div", + clk_base + REG_CLK_APBCLK0, 28); + + hws[RTC_GATE] = ma35d1_clk_gate(dev, "rtc_gate", "lxt", + clk_base + REG_CLK_APBCLK0, 29); + hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", + clk_base + REG_CLK_APBCLK0, 30); + + hws[KPI_MUX] = ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL4, + 30, 1, kpi_sel_clks, ARRAY_SIZE(kpi_sel_clks)); + hws[KPI_DIV] = ma35d1_clk_divider(dev, "kpi_div", "kpi_mux", + clk_base + REG_CLK_CLKDIV4, + 24, 8); + hws[KPI_GATE] = ma35d1_clk_gate(dev, "kpi_gate", "kpi_div", + clk_base + REG_CLK_APBCLK0, 31); + + hws[I2C0_GATE] = ma35d1_clk_gate(dev, "i2c0_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 0); + hws[I2C1_GATE] = ma35d1_clk_gate(dev, "i2c1_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 1); + hws[I2C2_GATE] = ma35d1_clk_gate(dev, "i2c2_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 2); + hws[I2C3_GATE] = ma35d1_clk_gate(dev, "i2c3_gate", "pclk0", + clk_base + REG_CLK_APBCLK1, 3); + hws[I2C4_GATE] = ma35d1_clk_gate(dev, "i2c4_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 4); + hws[I2C5_GATE] = ma35d1_clk_gate(dev, "i2c5_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 5); + + hws[QSPI0_MUX] = ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CLKSEL4, + 8, 2, qspi0_sel_clks, ARRAY_SIZE(qspi0_sel_clks)); + hws[QSPI0_GATE] = ma35d1_clk_gate(dev, "qspi0_gate", "qspi0_mux", + clk_base + REG_CLK_APBCLK1, 6); + hws[QSPI1_MUX] = ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CLKSEL4, + 10, 2, qspi1_sel_clks, ARRAY_SIZE(qspi1_sel_clks)); + hws[QSPI1_GATE] = ma35d1_clk_gate(dev, "qspi1_gate", "qspi1_mux", + clk_base + REG_CLK_APBCLK1, 7); + + hws[SMC0_MUX] = ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKSEL4, + 28, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); + hws[SMC0_DIV] = ma35d1_clk_divider(dev, "smc0_div", "smc0_mux", + clk_base + REG_CLK_CLKDIV1, + 0, 4); + hws[SMC0_GATE] = ma35d1_clk_gate(dev, "smc0_gate", "smc0_div", + clk_base + REG_CLK_APBCLK1, 12); + hws[SMC1_MUX] = ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKSEL4, + 29, 1, smc_sel_clks, ARRAY_SIZE(smc_sel_clks)); + hws[SMC1_DIV] = ma35d1_clk_divider(dev, "smc1_div", "smc1_mux", + clk_base + REG_CLK_CLKDIV1, + 4, 4); + hws[SMC1_GATE] = ma35d1_clk_gate(dev, "smc1_gate", "smc1_div", + clk_base + REG_CLK_APBCLK1, 13); + + hws[WDT0_MUX] = ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKSEL3, + 20, 2, wdt0_sel_clks, ARRAY_SIZE(wdt0_sel_clks)); + hws[WDT0_GATE] = ma35d1_clk_gate(dev, "wdt0_gate", "wdt0_mux", + clk_base + REG_CLK_APBCLK1, 16); + hws[WDT1_MUX] = ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKSEL3, + 24, 2, wdt1_sel_clks, ARRAY_SIZE(wdt1_sel_clks)); + hws[WDT1_GATE] = ma35d1_clk_gate(dev, "wdt1_gate", "wdt1_mux", + clk_base + REG_CLK_APBCLK1, 17); + hws[WDT2_MUX] = ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKSEL3, + 28, 2, wdt2_sel_clks, ARRAY_SIZE(wdt2_sel_clks)); + hws[WDT2_GATE] = ma35d1_clk_gate(dev, "wdt2_gate", "wdt2_mux", + clk_base + REG_CLK_APBCLK1, 18); + + hws[WWDT0_MUX] = ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CLKSEL3, + 22, 2, wwdt0_sel_clks, ARRAY_SIZE(wwdt0_sel_clks)); + hws[WWDT1_MUX] = ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CLKSEL3, + 26, 2, wwdt1_sel_clks, ARRAY_SIZE(wwdt1_sel_clks)); + hws[WWDT2_MUX] = ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CLKSEL3, + 30, 2, wwdt2_sel_clks, ARRAY_SIZE(wwdt2_sel_clks)); + + hws[EPWM0_GATE] = ma35d1_clk_gate(dev, "epwm0_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 24); + hws[EPWM1_GATE] = ma35d1_clk_gate(dev, "epwm1_gate", "pclk2", + clk_base + REG_CLK_APBCLK1, 25); + hws[EPWM2_GATE] = ma35d1_clk_gate(dev, "epwm2_gate", "pclk1", + clk_base + REG_CLK_APBCLK1, 26); + + hws[I2S0_MUX] = ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKSEL4, + 12, 2, i2s0_sel_clks, ARRAY_SIZE(i2s0_sel_clks)); + hws[I2S0_GATE] = ma35d1_clk_gate(dev, "i2s0_gate", "i2s0_mux", + clk_base + REG_CLK_APBCLK2, 0); + hws[I2S1_MUX] = ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKSEL4, + 14, 2, i2s1_sel_clks, ARRAY_SIZE(i2s1_sel_clks)); + hws[I2S1_GATE] = ma35d1_clk_gate(dev, "i2s1_gate", "i2s1_mux", + clk_base + REG_CLK_APBCLK2, 1); + + hws[SSMCC_GATE] = ma35d1_clk_gate(dev, "ssmcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 2); + hws[SSPCC_GATE] = ma35d1_clk_gate(dev, "sspcc_gate", "pclk3", + clk_base + REG_CLK_APBCLK2, 3); + + hws[SPI0_MUX] = ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKSEL4, + 0, 2, spi0_sel_clks, ARRAY_SIZE(spi0_sel_clks)); + hws[SPI0_GATE] = ma35d1_clk_gate(dev, "spi0_gate", "spi0_mux", + clk_base + REG_CLK_APBCLK2, 4); + hws[SPI1_MUX] = ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKSEL4, + 2, 2, spi1_sel_clks, ARRAY_SIZE(spi1_sel_clks)); + hws[SPI1_GATE] = ma35d1_clk_gate(dev, "spi1_gate", "spi1_mux", + clk_base + REG_CLK_APBCLK2, 5); + hws[SPI2_MUX] = ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKSEL4, + 4, 2, spi2_sel_clks, ARRAY_SIZE(spi2_sel_clks)); + hws[SPI2_GATE] = ma35d1_clk_gate(dev, "spi2_gate", "spi2_mux", + clk_base + REG_CLK_APBCLK2, 6); + hws[SPI3_MUX] = ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKSEL4, + 6, 2, spi3_sel_clks, ARRAY_SIZE(spi3_sel_clks)); + hws[SPI3_GATE] = ma35d1_clk_gate(dev, "spi3_gate", "spi3_mux", + clk_base + REG_CLK_APBCLK2, 7); + + hws[ECAP0_GATE] = ma35d1_clk_gate(dev, "ecap0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 8); + hws[ECAP1_GATE] = ma35d1_clk_gate(dev, "ecap1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 9); + hws[ECAP2_GATE] = ma35d1_clk_gate(dev, "ecap2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 10); + + hws[QEI0_GATE] = ma35d1_clk_gate(dev, "qei0_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 12); + hws[QEI1_GATE] = ma35d1_clk_gate(dev, "qei1_gate", "pclk2", + clk_base + REG_CLK_APBCLK2, 13); + hws[QEI2_GATE] = ma35d1_clk_gate(dev, "qei2_gate", "pclk1", + clk_base + REG_CLK_APBCLK2, 14); + + hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(dev, "adc_div", hws[PCLK0], + &ma35d1_lock, 0, + clk_base + REG_CLK_CLKDIV4, + 4, 17, 0x1ffff); + hws[ADC_GATE] = ma35d1_clk_gate(dev, "adc_gate", "adc_div", + clk_base + REG_CLK_APBCLK2, 24); + + hws[EADC_DIV] = ma35d1_clk_divider_table(dev, "eadc_div", "pclk2", + clk_base + REG_CLK_CLKDIV4, + 0, 4, eadc_div_table); + hws[EADC_GATE] = ma35d1_clk_gate(dev, "eadc_gate", "eadc_div", + clk_base + REG_CLK_APBCLK2, 25); + + return devm_of_clk_add_hw_provider(dev, + of_clk_hw_onecell_get, + ma35d1_hw_data); +} + +static const struct of_device_id ma35d1_clk_of_match[] = { + { .compatible = "nuvoton,ma35d1-clk" }, + { } +}; +MODULE_DEVICE_TABLE(of, ma35d1_clk_of_match); + +static struct platform_driver ma35d1_clk_driver = { + .probe = ma35d1_clocks_probe, + .driver = { + .name = "ma35d1-clk", + .of_match_table = ma35d1_clk_of_match, + }, +}; + +static int __init ma35d1_clocks_init(void) +{ + return platform_driver_register(&ma35d1_clk_driver); +} + +postcore_initcall(ma35d1_clocks_init); + +MODULE_AUTHOR("Chi-Fang Li <cfli0@nuvoton.com>"); +MODULE_DESCRIPTION("NUVOTON MA35D1 Clock Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h new file mode 100644 index 000000000000..3adee440f60a --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li <cfli0@nuvoton.com> + */ + +#ifndef __DRV_CLK_NUVOTON_MA35D1_H +#define __DRV_CLK_NUVOTON_MA35D1_H + +struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, + struct clk_hw *parent_hw, void __iomem *base); + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + struct clk_hw *parent_hw, spinlock_t *lock, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit); + +#endif /* __DRV_CLK_NUVOTON_MA35D1_H */ diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index d532f3c6f670..2656d3d3ae40 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -51,4 +51,10 @@ config PINCTRL_STM32MP157 depends on OF && HAS_IOMEM default MACH_STM32MP157 select PINCTRL_STM32 + +config PINCTRL_STM32MP257 + bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25 + depends on OF && HAS_IOMEM + default MACH_STM32MP25 + select PINCTRL_STM32 endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 619629ee9944..7b17464d8de1 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o +obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index e0c31c4c8bca..5e5de92ddd58 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -24,6 +24,9 @@ #define STM32MP_PKG_AB BIT(1) #define STM32MP_PKG_AC BIT(2) #define STM32MP_PKG_AD BIT(3) +#define STM32MP_PKG_AI BIT(8) +#define STM32MP_PKG_AK BIT(10) +#define STM32MP_PKG_AL BIT(11) struct stm32_desc_function { const char *name; diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c new file mode 100644 index 000000000000..73f091cd827e --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c @@ -0,0 +1,2581 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32mp257_pins[] = { + STM32_PIN_PKG( + PINCTRL_PIN(0, "PA0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "UART8_CTS"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "UART5_TX"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(8, "TIM3_ETR"), + STM32_FUNCTION(9, "TIM5_CH2"), + STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(1, "PA1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(3, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_SD_A"), + STM32_FUNCTION(6, "USART1_RTS"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(8, "TIM4_CH2"), + STM32_FUNCTION(9, "I2C4_SDA"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(12, "LCD_R3"), + STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(15, "ETH3_PHY_INTN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(2, "PA2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "LPTIM2_IN1"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "I3C1_SDA"), + STM32_FUNCTION(11, "I2C1_SDA"), + STM32_FUNCTION(12, "LCD_B0"), + STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(15, "ETH3_RGMII_RX_CTL ETH3_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(3, "PA3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "I3C1_SCL"), + STM32_FUNCTION(10, "I2C7_SMBA"), + STM32_FUNCTION(11, "I2C1_SCL"), + STM32_FUNCTION(12, "LCD_B1"), + STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(15, "ETH3_RGMII_TX_CTL ETH3_RMII_TX_EN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(4, "PA4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(7, "USART2_TX"), + STM32_FUNCTION(8, "FDCAN2_TX"), + STM32_FUNCTION(9, "TIM2_CH1"), + STM32_FUNCTION(11, "LCD_R1"), + STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"), + STM32_FUNCTION(15, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(5, "PA5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(4, "SPI4_MOSI"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "SAI2_SD_B"), + STM32_FUNCTION(7, "USART2_RTS"), + STM32_FUNCTION(8, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM2_CH4"), + STM32_FUNCTION(11, "LCD_G0"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(15, "ETH3_RGMII_RX_CLK ETH3_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(6, "PA6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(4, "SPI4_SCK"), + STM32_FUNCTION(5, "SAI2_FS_B"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(9, "TIM2_ETR"), + STM32_FUNCTION(11, "LCD_G4"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD0 ETH3_RMII_TXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(7, "PA7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(3, "AUDIOCLK"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "TIM4_ETR"), + STM32_FUNCTION(9, "I2C2_SMBA"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(11, "LCD_B5"), + STM32_FUNCTION(12, "I2C3_SMBA"), + STM32_FUNCTION(13, "I2C4_SMBA"), + STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD1 ETH3_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(8, "PA8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(2, "LPTIM2_CH2"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "USART2_RX"), + STM32_FUNCTION(10, "I2C5_SCL"), + STM32_FUNCTION(13, "LCD_B2"), + STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(9, "PA9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(4, "SPI4_NSS"), + STM32_FUNCTION(5, "SAI2_SCK_B"), + STM32_FUNCTION(7, "USART2_CTS"), + STM32_FUNCTION(8, "LPTIM5_ETR"), + STM32_FUNCTION(9, "TIM2_CH3"), + STM32_FUNCTION(11, "ETH1_MDC"), + STM32_FUNCTION(13, "LCD_G7"), + STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD0 ETH3_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(10, "PA10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(4, "SPI4_MISO"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(7, "USART2_RX"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(9, "TIM2_CH2"), + STM32_FUNCTION(11, "ETH1_MDIO"), + STM32_FUNCTION(13, "LCD_R6"), + STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD1 ETH3_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(11, "PA11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "SPI8_SCK"), + STM32_FUNCTION(3, "LPTIM2_CH1"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(6, "MDF1_SDI4"), + STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(12, "PA12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(3, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_FS_A"), + STM32_FUNCTION(8, "TIM4_CH1"), + STM32_FUNCTION(9, "I2C4_SCL"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(11, "ETH1_PHY_INTN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(13, "PA13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(2, "SPI8_RDY"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "LPTIM2_ETR"), + STM32_FUNCTION(6, "MDF1_CKI3"), + STM32_FUNCTION(7, "USART2_CTS"), + STM32_FUNCTION(10, "I2C7_SMBA"), + STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(14, "PA14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(2, "SPI8_NSS"), + STM32_FUNCTION(3, "LPTIM2_CH2"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(6, "MDF1_CCK1"), + STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(15, "PA15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "USART2_RX"), + STM32_FUNCTION(10, "I2C7_SDA"), + STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(16, "PB0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(8, "TIM16_CH1"), + STM32_FUNCTION(9, "TIM20_CH4N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(17, "PB1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "TIM16_CH1N"), + STM32_FUNCTION(9, "TIM20_CH3N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO1"), + STM32_FUNCTION(13, "FMC_NCE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(18, "PB2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(6, "MDF1_CKI3"), + STM32_FUNCTION(7, "TIM17_BKIN"), + STM32_FUNCTION(8, "TIM16_BKIN"), + STM32_FUNCTION(9, "TIM20_CH2N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(19, "PB3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI3"), + STM32_FUNCTION(9, "TIM20_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO3"), + STM32_FUNCTION(13, "FMC_NCE3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(20, "PB4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(4, "UART4_CTS"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(6, "MDF1_SDI4"), + STM32_FUNCTION(7, "TIM14_CH1"), + STM32_FUNCTION(9, "TIM20_CH2"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO4"), + STM32_FUNCTION(14, "I3C2_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(21, "PB5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(4, "UART4_RTS"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(6, "MDF1_CKI4"), + STM32_FUNCTION(9, "TIM20_CH1"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO5"), + STM32_FUNCTION(13, "FMC_AD8 FMC_D8"), + STM32_FUNCTION(14, "I3C2_SCL"), + STM32_FUNCTION(15, "SDMMC3_D123DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(22, "PB6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "UART4_RX"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(9, "TIM20_CH1N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO6"), + STM32_FUNCTION(13, "FMC_AD9 FMC_D9"), + STM32_FUNCTION(15, "SDMMC3_D0DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(23, "PB7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(4, "UART4_TX"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(9, "TIM20_ETR"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO7"), + STM32_FUNCTION(13, "FMC_AD10 FMC_D10"), + STM32_FUNCTION(15, "SDMMC3_CDIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(24, "PB8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(8, "TIM17_CH1"), + STM32_FUNCTION(9, "TIM20_CH4"), + STM32_FUNCTION(11, "OCTOSPIM_P2_NCS1"), + STM32_FUNCTION(13, "FMC_AD12 FMC_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(25, "PB9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(2, "SPI3_RDY"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM20_BKIN"), + STM32_FUNCTION(10, "TIM10_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P2_DQS"), + STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(13, "FMC_AD13 FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(26, "PB10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(8, "TIM17_CH1N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_CLK"), + STM32_FUNCTION(13, "FMC_AD15 FMC_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(27, "PB11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "I2S3_MCK"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM20_BKIN2"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(11, "OCTOSPIM_P2_NCLK"), + STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(13, "FMC_AD14 FMC_D14"), + STM32_FUNCTION(14, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(28, "PB12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(6, "UART8_CTS"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(10, "DSI_TE"), + STM32_FUNCTION(11, "SDMMC3_D2"), + STM32_FUNCTION(12, "FMC_NWAIT"), + STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(29, "PB13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(6, "UART8_RX"), + STM32_FUNCTION(11, "SDMMC3_CK"), + STM32_FUNCTION(12, "FMC_AD5 FMC_D5"), + STM32_FUNCTION(13, "FMC_AD0 FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(30, "PB14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(10, "TIM4_CH2"), + STM32_FUNCTION(11, "SDMMC3_D0"), + STM32_FUNCTION(12, "FMC_AD7 FMC_D7"), + STM32_FUNCTION(13, "FMC_AD2 FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(31, "PB15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(4, "UART8_RTS"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(6, "UART5_RX"), + STM32_FUNCTION(8, "TIM3_CH2"), + STM32_FUNCTION(9, "TIM5_CH1"), + STM32_FUNCTION(11, "ETH1_PPS_OUT"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(32, "PC0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(4, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_MCLK_B"), + STM32_FUNCTION(6, "USART6_TX"), + STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(12, "ETH1_MII_TX_CLK"), + STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"), + STM32_FUNCTION(14, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(33, "PC1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(7, "USART2_TX"), + STM32_FUNCTION(10, "I2C7_SCL"), + STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(34, "PC2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(2, "SPI8_MOSI"), + STM32_FUNCTION(3, "LPTIM2_IN1"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(6, "MDF1_SDI3"), + STM32_FUNCTION(7, "USART2_RTS"), + STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(35, "PC3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(7, "USART6_RTS"), + STM32_FUNCTION(8, "FDCAN2_TX"), + STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(14, "LCD_G6"), + STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(36, "PC4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_FS_B"), + STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"), + STM32_FUNCTION(13, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(37, "PC5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(3, "SPDIFRX1_IN1"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(10, "I2C4_SDA"), + STM32_FUNCTION(11, "ETH2_MDIO"), + STM32_FUNCTION(12, "ETH1_MII_COL"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(14, "ETH1_PPS_OUT"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(38, "PC6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(3, "SPDIFRX1_IN0"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(10, "I2C4_SCL"), + STM32_FUNCTION(11, "ETH2_MDC"), + STM32_FUNCTION(12, "ETH1_MII_CRS"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(14, "ETH1_PHY_INTN"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(39, "PC7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_SD_B"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"), + STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(14, "LCD_B4"), + STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(40, "PC8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(4, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_SCK_B"), + STM32_FUNCTION(7, "USART6_CTS"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"), + STM32_FUNCTION(12, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(41, "PC9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(10, "USBH_HS_OVRCUR"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(12, "USB3DR_OVRCUR"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "LCD_G2"), + STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(42, "PC10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(10, "USBH_HS_VBUSEN"), + STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(12, "USB3DR_VBUSEN"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(43, "PC11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(5, "SAI2_MCLK_A"), + STM32_FUNCTION(6, "UART5_RTS"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "TIM3_CH1"), + STM32_FUNCTION(9, "TIM5_ETR"), + STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "LCD_R2"), + STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(44, "PC12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(4, "I3C3_SCL"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"), + STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(14, "LCD_G1"), + STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(45, "PC13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(48, "PD0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(4, "SAI1_D2"), + STM32_FUNCTION(6, "SAI4_FS_A"), + STM32_FUNCTION(7, "UART7_RX"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_CLK"), + STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(49, "PD1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SAI1_CK2"), + STM32_FUNCTION(6, "SAI4_SD_A"), + STM32_FUNCTION(7, "UART7_RTS"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(10, "FDCAN3_RX"), + STM32_FUNCTION(11, "OCTOSPIM_P1_NCLK"), + STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(13, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(50, "PD2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(4, "SAI1_CK1"), + STM32_FUNCTION(6, "SAI4_SCK_A"), + STM32_FUNCTION(7, "UART7_CTS"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(10, "FDCAN3_TX"), + STM32_FUNCTION(11, "OCTOSPIM_P1_DQS"), + STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(51, "PD3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(2, "SAI1_MCLK_A"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(4, "SAI1_D1"), + STM32_FUNCTION(6, "SAI4_MCLK_A"), + STM32_FUNCTION(7, "UART7_TX"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "OCTOSPIM_P1_NCS1"), + STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(52, "PD4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "SPI4_MISO"), + STM32_FUNCTION(3, "HDP3"), + STM32_FUNCTION(4, "SAI1_D3"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(10, "TIM4_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO0"), + STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(53, "PD5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "SPI4_NSS"), + STM32_FUNCTION(3, "HDP4"), + STM32_FUNCTION(4, "SAI1_D4"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(10, "TIM4_CH2"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO1"), + STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(54, "PD6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "SPI4_MOSI"), + STM32_FUNCTION(3, "HDP5"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(10, "TIM4_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO2"), + STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(55, "PD7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "SPI4_SCK"), + STM32_FUNCTION(3, "SPI1_RDY"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(10, "TIM4_CH4"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO3"), + STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(56, "PD8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "SPI4_RDY"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(4, "SAI1_FS_A"), + STM32_FUNCTION(5, "UART4_CTS"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(10, "TIM4_ETR"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO4"), + STM32_FUNCTION(12, "SDMMC1_D7"), + STM32_FUNCTION(13, "SDMMC1_D123DIR"), + STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(57, "PD9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(4, "SAI1_SD_A"), + STM32_FUNCTION(5, "UART4_RTS"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO5"), + STM32_FUNCTION(12, "SDMMC1_D6"), + STM32_FUNCTION(13, "SDMMC1_D0DIR"), + STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(58, "PD10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(4, "SAI1_SCK_A"), + STM32_FUNCTION(5, "UART4_RX"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "I2C4_SDA"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO6"), + STM32_FUNCTION(12, "SDMMC1_D5"), + STM32_FUNCTION(13, "SDMMC1_CDIR"), + STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(59, "PD11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SAI1_MCLK_A"), + STM32_FUNCTION(5, "UART4_TX"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(7, "I2C4_SCL"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO7"), + STM32_FUNCTION(12, "SDMMC1_D4"), + STM32_FUNCTION(13, "SDMMC1_CKIN"), + STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(60, "PD12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(2, "SPI7_MISO"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN2"), + STM32_FUNCTION(6, "UART8_RTS"), + STM32_FUNCTION(10, "TIM4_ETR"), + STM32_FUNCTION(11, "SDMMC3_CMD"), + STM32_FUNCTION(12, "FMC_AD6 FMC_D6"), + STM32_FUNCTION(13, "FMC_AD1 FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(61, "PD13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(10, "TIM4_CH4"), + STM32_FUNCTION(11, "SDMMC3_D1"), + STM32_FUNCTION(12, "FMC_AD11 FMC_D11"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(62, "PD14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "I2C7_SDA"), + STM32_FUNCTION(12, "FMC_AD4 FMC_D4"), + STM32_FUNCTION(13, "SDMMC3_D3"), + STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(63, "PD15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(2, "SPI1_RDY"), + STM32_FUNCTION(6, "DSI_TE"), + STM32_FUNCTION(7, "I2C5_SDA"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "TIM5_ETR"), + STM32_FUNCTION(11, "I2C7_SCL"), + STM32_FUNCTION(12, "FMC_AD3 FMC_D3"), + STM32_FUNCTION(13, "SDMMC3_CKIN"), + STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(64, "PE0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "LPTIM2_CH1"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPI3_RDY"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(11, "SDMMC1_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(65, "PE1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "LPTIM2_CH2"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(4, "I2S3_MCK"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(11, "SDMMC1_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(66, "PE2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(11, "SDMMC1_CMD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(67, "PE3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SPI1_RDY"), + STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "SDMMC1_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(68, "PE4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "LPTIM2_IN1"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(11, "SDMMC1_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(69, "PE5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "LPTIM2_IN2"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(11, "SDMMC1_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(70, "PE6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(2, "SPI4_RDY"), + STM32_FUNCTION(5, "SPDIFRX1_IN2"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(12, "FMC_AD1 FMC_D1"), + STM32_FUNCTION(13, "SDMMC2_D6"), + STM32_FUNCTION(14, "SDMMC2_D0DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(71, "PE7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(4, "SAI4_D4"), + STM32_FUNCTION(5, "SPDIFRX1_IN3"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(11, "TIM14_CH1"), + STM32_FUNCTION(12, "FMC_AD2 FMC_D2"), + STM32_FUNCTION(13, "SDMMC2_D7"), + STM32_FUNCTION(14, "SDMMC2_D123DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(72, "PE8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "SPI4_MOSI"), + STM32_FUNCTION(4, "SAI4_CK1"), + STM32_FUNCTION(5, "SAI4_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(12, "FMC_A17 FMC_ALE"), + STM32_FUNCTION(13, "SDMMC2_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(73, "PE9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "SPI4_MISO"), + STM32_FUNCTION(4, "SAI4_D2"), + STM32_FUNCTION(5, "SAI4_FS_A"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(12, "FMC_AD0 FMC_D0"), + STM32_FUNCTION(13, "SDMMC2_D5"), + STM32_FUNCTION(14, "SDMMC2_CDIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(74, "PE10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "SPI4_SCK"), + STM32_FUNCTION(4, "SAI4_D1"), + STM32_FUNCTION(5, "SAI4_SD_A"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(11, "FMC_NE3"), + STM32_FUNCTION(12, "FMC_NCE2"), + STM32_FUNCTION(13, "SDMMC2_D4"), + STM32_FUNCTION(14, "SDMMC2_CKIN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(75, "PE11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(4, "SAI4_D3"), + STM32_FUNCTION(5, "SAI1_FS_A"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(12, "FMC_A16 FMC_CLE"), + STM32_FUNCTION(13, "SDMMC2_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(76, "PE12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "SPI4_NSS"), + STM32_FUNCTION(4, "SAI4_CK2"), + STM32_FUNCTION(5, "SAI4_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(11, "FMC_NE2"), + STM32_FUNCTION(12, "FMC_NCE1"), + STM32_FUNCTION(13, "SDMMC2_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(77, "PE13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(5, "SAI1_SD_A"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(12, "FMC_RNB"), + STM32_FUNCTION(13, "SDMMC2_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(78, "PE14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI1_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(12, "FMC_NWE"), + STM32_FUNCTION(13, "SDMMC2_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(79, "PE15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(5, "SAI1_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(12, "FMC_NOE"), + STM32_FUNCTION(13, "SDMMC2_CMD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(80, "PF0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM12_CH2"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "ETH1_MDC"), + STM32_FUNCTION(12, "ETH2_MII_CRS"), + STM32_FUNCTION(14, "I3C2_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(81, "PF1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(2, "SPI8_MISO"), + STM32_FUNCTION(3, "LPTIM2_IN2"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(6, "MDF1_CKI4"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(82, "PF2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(3, "SPI3_RDY"), + STM32_FUNCTION(7, "I2C4_SMBA"), + STM32_FUNCTION(9, "TIM12_CH1"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "ETH1_MDIO"), + STM32_FUNCTION(12, "ETH2_MII_COL"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(14, "I3C2_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(83, "PF3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(4, "UART8_RX"), + STM32_FUNCTION(5, "SAI2_SCK_B"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(8, "TIM3_CH4"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(84, "PF4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(3, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_SCK_A"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(8, "TIM4_CH4"), + STM32_FUNCTION(9, "ETH1_MDC"), + STM32_FUNCTION(10, "ETH2_CLK"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(12, "ETH1_PPS_OUT"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(85, "PF5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(3, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_MCLK_A"), + STM32_FUNCTION(7, "USART6_TX"), + STM32_FUNCTION(8, "TIM4_CH3"), + STM32_FUNCTION(9, "ETH1_MDIO"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(12, "ETH1_PHY_INTN"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(86, "PF6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(4, "SAI3_MCLK_B"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(8, "TIM12_CH1"), + STM32_FUNCTION(10, "I2C3_SMBA"), + STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(87, "PF7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(3, "SPDIFRX1_IN1"), + STM32_FUNCTION(4, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_SD_A"), + STM32_FUNCTION(8, "TIM2_ETR"), + STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"), + STM32_FUNCTION(12, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(14, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(88, "PF8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(4, "SAI3_SCK_B"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(8, "TIM12_CH2"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH2_MII_RX_ER"), + STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(14, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(89, "PF9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(4, "SAI3_SD_B"), + STM32_FUNCTION(5, "SAI2_SD_A"), + STM32_FUNCTION(6, "MDF1_SDI5"), + STM32_FUNCTION(7, "UART8_RTS"), + STM32_FUNCTION(8, "TIM2_CH2"), + STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(12, "ETH2_MDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(90, "PF10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(3, "SPI3_RDY"), + STM32_FUNCTION(5, "SAI2_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(7, "UART8_TX"), + STM32_FUNCTION(8, "TIM2_CH3"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(91, "PF11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "SPDIFRX1_IN0"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(7, "UART8_RX"), + STM32_FUNCTION(8, "TIM2_CH4"), + STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(92, "PF12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(9, "TIM5_CH1"), + STM32_FUNCTION(14, "LCD_CLK"), + STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(93, "PF13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(3, "AUDIOCLK"), + STM32_FUNCTION(4, "USART6_TX"), + STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(8, "FDCAN3_TX"), + STM32_FUNCTION(9, "TIM3_CH3"), + STM32_FUNCTION(14, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(94, "PF14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(4, "USART6_RX"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "FDCAN3_RX"), + STM32_FUNCTION(9, "TIM3_CH4"), + STM32_FUNCTION(14, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(95, "PF15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(4, "USART6_CTS"), + STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(8, "TIM2_CH2"), + STM32_FUNCTION(9, "TIM3_ETR"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(96, "PG0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(4, "I3C3_SDA"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"), + STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(14, "LCD_G5"), + STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(97, "PG1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "I3C3_SCL"), + STM32_FUNCTION(5, "SAI2_SD_A"), + STM32_FUNCTION(6, "UART5_CTS"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(9, "TIM5_CH4"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "ETH2_MII_RX_ER"), + STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "LCD_VSYNC"), + STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(98, "PG2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "I3C3_SDA"), + STM32_FUNCTION(5, "SAI2_FS_A"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(9, "TIM5_CH3"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(11, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(12, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(99, "PG3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(4, "UART8_TX"), + STM32_FUNCTION(5, "SAI2_FS_B"), + STM32_FUNCTION(8, "TIM3_CH3"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(10, "ETH2_CLK"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(100, "PG4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SAI3_FS_B"), + STM32_FUNCTION(8, "LPTIM4_IN1"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(12, "ETH2_MDC"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(101, "PG5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "HDP3"), + STM32_FUNCTION(4, "USART6_RTS"), + STM32_FUNCTION(8, "TIM2_CH3"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(102, "PG6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "HDP4"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(4, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(8, "TIM2_CH4"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(103, "PG7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "HDP5"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM5_ETR"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(104, "PG8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "SPI1_RDY"), + STM32_FUNCTION(5, "USART6_CK"), + STM32_FUNCTION(6, "UART5_RTS"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(9, "TIM5_CH3"), + STM32_FUNCTION(14, "LCD_G2"), + STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(105, "PG9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(6, "UART5_TX"), + STM32_FUNCTION(9, "TIM5_CH4"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(106, "PG10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(1, "TRACED8"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(6, "UART5_RX"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(14, "LCD_G4"), + STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(107, "PG11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(1, "TRACED9"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(14, "LCD_G5"), + STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(108, "PG12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(1, "TRACED10"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(14, "LCD_G6"), + STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(109, "PG13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(1, "TRACED11"), + STM32_FUNCTION(2, "HDP3"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(10, "I2C1_SCL"), + STM32_FUNCTION(11, "I3C1_SCL"), + STM32_FUNCTION(14, "LCD_G7"), + STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(110, "PG14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(1, "TRACED12"), + STM32_FUNCTION(2, "HDP4"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(6, "MDF1_CKI5"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(14, "LCD_B1"), + STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(111, "PG15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(1, "TRACED13"), + STM32_FUNCTION(2, "HDP5"), + STM32_FUNCTION(4, "LPTIM1_CH2"), + STM32_FUNCTION(6, "MDF1_SDI5"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(14, "LCD_B2"), + STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(114, "PH2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(2, "LPTIM2_CH1"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(4, "SPDIFRX1_IN3"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "I3C3_SDA"), + STM32_FUNCTION(8, "TIM16_CH1"), + STM32_FUNCTION(9, "I2C5_SDA"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(15, "ETH3_RGMII_GTX_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(115, "PH3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "UART7_RX"), + STM32_FUNCTION(8, "TIM17_CH1N"), + STM32_FUNCTION(10, "TIM5_CH3"), + STM32_FUNCTION(11, "I2C7_SCL"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(116, "PH4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(7, "UART7_TX"), + STM32_FUNCTION(8, "TIM17_BKIN"), + STM32_FUNCTION(10, "TIM5_CH2"), + STM32_FUNCTION(11, "LCD_R0"), + STM32_FUNCTION(12, "USB3DR_OVRCUR"), + STM32_FUNCTION(13, "USBH_HS_OVRCUR"), + STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"), + STM32_FUNCTION(15, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(117, "PH5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "SAI2_FS_A"), + STM32_FUNCTION(7, "UART8_CTS"), + STM32_FUNCTION(8, "TIM2_CH1"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(11, "LCD_G1"), + STM32_FUNCTION(12, "USB3DR_VBUSEN"), + STM32_FUNCTION(13, "USBH_HS_VBUSEN"), + STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(118, "PH6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(2, "LPTIM2_IN2"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(6, "I3C3_SCL"), + STM32_FUNCTION(8, "TIM16_CH1N"), + STM32_FUNCTION(9, "I2C5_SCL"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "I2C1_SMBA"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(119, "PH7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(5, "UART4_TX"), + STM32_FUNCTION(7, "UART7_RTS"), + STM32_FUNCTION(8, "TIM17_CH1"), + STM32_FUNCTION(10, "TIM5_CH4"), + STM32_FUNCTION(11, "I2C7_SDA"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(120, "PH8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN3"), + STM32_FUNCTION(5, "UART4_RX"), + STM32_FUNCTION(7, "UART7_CTS"), + STM32_FUNCTION(10, "TIM5_CH1"), + STM32_FUNCTION(11, "I2C3_SMBA"), + STM32_FUNCTION(12, "I2C5_SMBA"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(121, "PH9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(4, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_MCLK_A"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(11, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(122, "PH10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_SCK_A"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(10, "ETH2_MDC"), + STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(123, "PH11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_FS_A"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(10, "ETH2_MDIO"), + STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(124, "PH12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(125, "PH13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(128, "PI0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(1, "TRACED14"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(4, "LPTIM1_IN1"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(129, "PI1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(1, "TRACED15"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(10, "I2C1_SDA"), + STM32_FUNCTION(11, "I3C1_SDA"), + STM32_FUNCTION(14, "LCD_B4"), + STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(130, "PI2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "LPTIM1_ETR"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(14, "LCD_B5"), + STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(131, "PI3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "LPTIM1_IN2"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(132, "PI4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "LPTIM1_CH1"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(133, "PI5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(6, "UART5_CTS"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(9, "TIM5_CH2"), + STM32_FUNCTION(14, "LCD_DE"), + STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(134, "PI6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(8, "TIM2_ETR"), + STM32_FUNCTION(9, "TIM3_CH1"), + STM32_FUNCTION(14, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(135, "PI7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(8, "TIM2_CH1"), + STM32_FUNCTION(9, "TIM3_CH2"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(136, "PI8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(137, "PI9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(2, "SPI7_MOSI"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(5, "FDCAN2_TX"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM16_BKIN"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(13, "DSI_TE"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(138, "PI10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(2, "SAI1_SCK_A"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPDIFRX1_IN0"), + STM32_FUNCTION(5, "FDCAN2_RX"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(9, "TIM4_CH1"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(13, "FMC_AD12 FMC_D12"), + STM32_FUNCTION(14, "DSI_TE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(139, "PI11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(6, "UART8_TX"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(10, "TIM4_CH3"), + STM32_FUNCTION(11, "SDMMC3_D3"), + STM32_FUNCTION(12, "FMC_AD15 FMC_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(140, "PI12"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(3, "SPI4_NSS"), + STM32_FUNCTION(8, "FDCAN3_RX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(14, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(141, "PI13"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(3, "SPI4_MOSI"), + STM32_FUNCTION(5, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(14, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(142, "PI14"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(8, "TIM20_CH3"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(13, "FMC_AD10 FMC_D10"), + STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(143, "PI15"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(4, "UART4_RX"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(8, "TIM20_BKIN2"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "SDMMC3_CDIR"), + STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(144, "PJ0"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(6, "SAI4_D2"), + STM32_FUNCTION(7, "USART6_CTS"), + STM32_FUNCTION(10, "USBH_HS_VBUSEN"), + STM32_FUNCTION(12, "ETH2_PTP_AUX_TS"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(14, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(145, "PJ1"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(10, "I2C1_SCL"), + STM32_FUNCTION(11, "I3C1_SCL"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(146, "PJ2"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(10, "USBH_HS_OVRCUR"), + STM32_FUNCTION(13, "FMC_A14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(147, "PJ3"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(4, "SAI2_FS_A"), + STM32_FUNCTION(6, "SAI4_D1"), + STM32_FUNCTION(7, "USART6_RTS"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(148, "PJ4"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(4, "SAI2_FS_B"), + STM32_FUNCTION(6, "MDF1_CCK1"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(10, "I2C2_SMBA"), + STM32_FUNCTION(11, "I2C5_SMBA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(149, "PJ5"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SAI2_SCK_B"), + STM32_FUNCTION(6, "SAI4_CK1"), + STM32_FUNCTION(7, "USART6_TX"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(150, "PJ6"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ6"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(5, "SAI4_SD_A"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(8, "TIM20_CH1N"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(151, "PJ7"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ7"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "SAI4_D3"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(10, "I2C1_SMBA"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(152, "PJ8"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ8"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(6, "SAI4_CK2"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(153, "PJ9"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ9"), + STM32_FUNCTION(3, "SPI4_RDY"), + STM32_FUNCTION(8, "TIM12_CH1"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(154, "PJ10"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ10"), + STM32_FUNCTION(8, "TIM12_CH2"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(10, "I2C1_SDA"), + STM32_FUNCTION(11, "I3C1_SDA"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(155, "PJ11"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ11"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "SAI2_SCK_A"), + STM32_FUNCTION(6, "SAI4_D4"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(156, "PJ12"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(4, "SAI2_SD_A"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "I3C2_SCL"), + STM32_FUNCTION(13, "FMC_A15"), + STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(157, "PJ13"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(4, "SAI2_MCLK_A"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "I3C2_SDA"), + STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(158, "PJ14"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(3, "SPI4_SCK"), + STM32_FUNCTION(8, "FDCAN3_TX"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(159, "PJ15"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(3, "SPI4_MISO"), + STM32_FUNCTION(5, "FDCAN2_TX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(14, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(160, "PK0"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK0"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN2"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(8, "TIM20_ETR"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(11, "SDMMC3_D123DIR"), + STM32_FUNCTION(13, "FMC_AD11 FMC_D11"), + STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(161, "PK1"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK1"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(8, "TIM20_BKIN"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "SDMMC3_D0DIR"), + STM32_FUNCTION(13, "FMC_AD13 FMC_D13"), + STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(162, "PK2"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK2"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI4_SCK_A"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(8, "TIM20_CH2"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(13, "FMC_NCE3"), + STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(163, "PK3"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(8, "TIM20_CH3N"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(13, "FMC_AD8 FMC_D8"), + STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(15, "FMC_NCE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(164, "PK4"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(4, "UART4_TX"), + STM32_FUNCTION(5, "SAI4_FS_A"), + STM32_FUNCTION(8, "TIM20_CH1"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(11, "SDMMC3_CKIN"), + STM32_FUNCTION(13, "FMC_AD9 FMC_D9"), + STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(165, "PK5"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(8, "TIM20_CH4N"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(11, "I2C5_SCL"), + STM32_FUNCTION(13, "FMC_AD5 FMC_D5"), + STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(166, "PK6"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(5, "SAI4_MCLK_A"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "TIM20_CH2N"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(12, "FMC_AD14 FMC_D14"), + STM32_FUNCTION(13, "FMC_AD7 FMC_D7"), + STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(167, "PK7"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(8, "TIM20_CH4"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(11, "I2C5_SDA"), + STM32_FUNCTION(12, "FMC_NCE4"), + STM32_FUNCTION(13, "FMC_AD6 FMC_D6"), + STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static const struct stm32_desc_pin stm32mp257_z_pins[] = { + STM32_PIN_PKG( + PINCTRL_PIN(400, "PZ0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ0"), + STM32_FUNCTION(3, "LPTIM3_IN1"), + STM32_FUNCTION(4, "SPI8_MOSI"), + STM32_FUNCTION(5, "TIM8_CH1"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM5_OUT"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(401, "PZ1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ1"), + STM32_FUNCTION(3, "LPTIM3_CH1"), + STM32_FUNCTION(4, "SPI8_MISO"), + STM32_FUNCTION(5, "TIM8_CH2"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM5_ETR"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(10, "I2C8_SMBA"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(402, "PZ2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ2"), + STM32_FUNCTION(3, "LPTIM3_CH1"), + STM32_FUNCTION(4, "SPI8_SCK"), + STM32_FUNCTION(6, "ADF1_CCK0"), + STM32_FUNCTION(7, "LPUART1_RTS"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(403, "PZ3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ3"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(3, "LPTIM3_ETR"), + STM32_FUNCTION(4, "SPI8_NSS"), + STM32_FUNCTION(5, "MDF1_SDI5"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_CTS"), + STM32_FUNCTION(8, "LPTIM4_IN1"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(404, "PZ4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ4"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(3, "MCO2"), + STM32_FUNCTION(4, "SPI8_RDY"), + STM32_FUNCTION(5, "MDF1_CCK1"), + STM32_FUNCTION(6, "ADF1_CCK1"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM4_CH1"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(405, "PZ5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ5"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "LPTIM3_ETR"), + STM32_FUNCTION(4, "SPI8_SCK"), + STM32_FUNCTION(6, "ADF1_CCK0"), + STM32_FUNCTION(7, "LPUART1_RTS"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(406, "PZ6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ6"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(4, "SPI8_NSS"), + STM32_FUNCTION(5, "TIM8_CH3"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_CTS"), + STM32_FUNCTION(8, "LPTIM5_OUT"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(407, "PZ7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ7"), + STM32_FUNCTION(4, "SPI8_MOSI"), + STM32_FUNCTION(5, "MDF1_CCK1"), + STM32_FUNCTION(6, "ADF1_CCK1"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(408, "PZ8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ8"), + STM32_FUNCTION(3, "LPTIM3_IN1"), + STM32_FUNCTION(4, "SPI8_MISO"), + STM32_FUNCTION(5, "MDF1_SDI5"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM4_CH1"), + STM32_FUNCTION(9, "I2C8_SMBA"), + STM32_FUNCTION(10, "LPTIM5_ETR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(409, "PZ9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ9"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(4, "SPI8_RDY"), + STM32_FUNCTION(5, "MDF1_CKI5"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32mp257_match_data = { + .pins = stm32mp257_pins, + .npins = ARRAY_SIZE(stm32mp257_pins), +}; + +static struct stm32_pinctrl_match_data stm32mp257_z_match_data = { + .pins = stm32mp257_z_pins, + .npins = ARRAY_SIZE(stm32mp257_z_pins), +}; + +static const struct of_device_id stm32mp257_pctrl_match[] = { + { + .compatible = "st,stm32mp257-pinctrl", + .data = &stm32mp257_match_data, + }, + { + .compatible = "st,stm32mp257-z-pinctrl", + .data = &stm32mp257_z_match_data, + }, + { } +}; + +static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume) +}; + +static struct platform_driver stm32mp257_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32mp257-pinctrl", + .of_match_table = stm32mp257_pctrl_match, + .pm = &stm32_pinctrl_dev_pm_ops, + }, +}; + +static int __init stm32mp257_pinctrl_init(void) +{ + return platform_driver_register(&stm32mp257_pinctrl_driver); +} +arch_initcall(stm32mp257_pinctrl_init); diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a850e9f486dd..48845dc8fa85 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -313,7 +313,7 @@ config ST_SLIM_REMOTEPROC config STM32_RPROC tristate "STM32 remoteproc support" - depends on ARCH_STM32 + depends on ARCH_STM32 || COMPILE_TEST depends on REMOTEPROC select MAILBOX help diff --git a/drivers/remoteproc/stm32_rproc.c b/drivers/remoteproc/stm32_rproc.c index 8746cbb1f168..e432febf4337 100644 --- a/drivers/remoteproc/stm32_rproc.c +++ b/drivers/remoteproc/stm32_rproc.c @@ -118,10 +118,10 @@ static int stm32_rproc_mem_alloc(struct rproc *rproc, struct device *dev = rproc->dev.parent; void *va; - dev_dbg(dev, "map memory: %pa+%x\n", &mem->dma, mem->len); + dev_dbg(dev, "map memory: %pad+%zx\n", &mem->dma, mem->len); va = ioremap_wc(mem->dma, mem->len); if (IS_ERR_OR_NULL(va)) { - dev_err(dev, "Unable to map memory region: %pa+%x\n", + dev_err(dev, "Unable to map memory region: %pad+0x%zx\n", &mem->dma, mem->len); return -ENOMEM; } @@ -627,7 +627,7 @@ stm32_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz) ddata->rsc_va = devm_ioremap_wc(dev, rsc_pa, RSC_TBL_SIZE); if (IS_ERR_OR_NULL(ddata->rsc_va)) { - dev_err(dev, "Unable to map memory region: %pa+%zx\n", + dev_err(dev, "Unable to map memory region: %pa+%x\n", &rsc_pa, RSC_TBL_SIZE); ddata->rsc_va = NULL; return ERR_PTR(-ENOMEM); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6aa8f243b30c..d9ac540c00ab 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,6 +143,13 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. +config RESET_NUVOTON_MA35D1 + bool "Nuvoton MA35D1 Reset Driver" + depends on ARCH_MA35 || COMPILE_TEST + default ARCH_MA35 + help + This enables the reset controller driver for Nuvoton MA35D1 SoC. + config RESET_OXNAS bool diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 7fec5af6c964..411b45ba0da7 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o +obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c new file mode 100644 index 000000000000..54e53863c98a --- /dev/null +++ b/drivers/reset/reset-ma35d1.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li <cfli0@nuvoton.com> + */ + +#include <linux/bits.h> +#include <linux/container_of.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/reset-controller.h> +#include <linux/spinlock.h> +#include <dt-bindings/reset/nuvoton,ma35d1-reset.h> + +struct ma35d1_reset_data { + struct reset_controller_dev rcdev; + struct notifier_block restart_handler; + void __iomem *base; + /* protect registers against concurrent read-modify-write */ + spinlock_t lock; +}; + +static const struct { + u32 reg_ofs; + u32 bit; +} ma35d1_reset_map[] = { + [MA35D1_RESET_CHIP] = {0x20, 0}, + [MA35D1_RESET_CA35CR0] = {0x20, 1}, + [MA35D1_RESET_CA35CR1] = {0x20, 2}, + [MA35D1_RESET_CM4] = {0x20, 3}, + [MA35D1_RESET_PDMA0] = {0x20, 4}, + [MA35D1_RESET_PDMA1] = {0x20, 5}, + [MA35D1_RESET_PDMA2] = {0x20, 6}, + [MA35D1_RESET_PDMA3] = {0x20, 7}, + [MA35D1_RESET_DISP] = {0x20, 9}, + [MA35D1_RESET_VCAP0] = {0x20, 10}, + [MA35D1_RESET_VCAP1] = {0x20, 11}, + [MA35D1_RESET_GFX] = {0x20, 12}, + [MA35D1_RESET_VDEC] = {0x20, 13}, + [MA35D1_RESET_WHC0] = {0x20, 14}, + [MA35D1_RESET_WHC1] = {0x20, 15}, + [MA35D1_RESET_GMAC0] = {0x20, 16}, + [MA35D1_RESET_GMAC1] = {0x20, 17}, + [MA35D1_RESET_HWSEM] = {0x20, 18}, + [MA35D1_RESET_EBI] = {0x20, 19}, + [MA35D1_RESET_HSUSBH0] = {0x20, 20}, + [MA35D1_RESET_HSUSBH1] = {0x20, 21}, + [MA35D1_RESET_HSUSBD] = {0x20, 22}, + [MA35D1_RESET_USBHL] = {0x20, 23}, + [MA35D1_RESET_SDH0] = {0x20, 24}, + [MA35D1_RESET_SDH1] = {0x20, 25}, + [MA35D1_RESET_NAND] = {0x20, 26}, + [MA35D1_RESET_GPIO] = {0x20, 27}, + [MA35D1_RESET_MCTLP] = {0x20, 28}, + [MA35D1_RESET_MCTLC] = {0x20, 29}, + [MA35D1_RESET_DDRPUB] = {0x20, 30}, + [MA35D1_RESET_TMR0] = {0x24, 2}, + [MA35D1_RESET_TMR1] = {0x24, 3}, + [MA35D1_RESET_TMR2] = {0x24, 4}, + [MA35D1_RESET_TMR3] = {0x24, 5}, + [MA35D1_RESET_I2C0] = {0x24, 8}, + [MA35D1_RESET_I2C1] = {0x24, 9}, + [MA35D1_RESET_I2C2] = {0x24, 10}, + [MA35D1_RESET_I2C3] = {0x24, 11}, + [MA35D1_RESET_QSPI0] = {0x24, 12}, + [MA35D1_RESET_SPI0] = {0x24, 13}, + [MA35D1_RESET_SPI1] = {0x24, 14}, + [MA35D1_RESET_SPI2] = {0x24, 15}, + [MA35D1_RESET_UART0] = {0x24, 16}, + [MA35D1_RESET_UART1] = {0x24, 17}, + [MA35D1_RESET_UART2] = {0x24, 18}, + [MA35D1_RESET_UART3] = {0x24, 19}, + [MA35D1_RESET_UART4] = {0x24, 20}, + [MA35D1_RESET_UART5] = {0x24, 21}, + [MA35D1_RESET_UART6] = {0x24, 22}, + [MA35D1_RESET_UART7] = {0x24, 23}, + [MA35D1_RESET_CANFD0] = {0x24, 24}, + [MA35D1_RESET_CANFD1] = {0x24, 25}, + [MA35D1_RESET_EADC0] = {0x24, 28}, + [MA35D1_RESET_I2S0] = {0x24, 29}, + [MA35D1_RESET_SC0] = {0x28, 0}, + [MA35D1_RESET_SC1] = {0x28, 1}, + [MA35D1_RESET_QSPI1] = {0x28, 4}, + [MA35D1_RESET_SPI3] = {0x28, 6}, + [MA35D1_RESET_EPWM0] = {0x28, 16}, + [MA35D1_RESET_EPWM1] = {0x28, 17}, + [MA35D1_RESET_QEI0] = {0x28, 22}, + [MA35D1_RESET_QEI1] = {0x28, 23}, + [MA35D1_RESET_ECAP0] = {0x28, 26}, + [MA35D1_RESET_ECAP1] = {0x28, 27}, + [MA35D1_RESET_CANFD2] = {0x28, 28}, + [MA35D1_RESET_ADC0] = {0x28, 31}, + [MA35D1_RESET_TMR4] = {0x2C, 0}, + [MA35D1_RESET_TMR5] = {0x2C, 1}, + [MA35D1_RESET_TMR6] = {0x2C, 2}, + [MA35D1_RESET_TMR7] = {0x2C, 3}, + [MA35D1_RESET_TMR8] = {0x2C, 4}, + [MA35D1_RESET_TMR9] = {0x2C, 5}, + [MA35D1_RESET_TMR10] = {0x2C, 6}, + [MA35D1_RESET_TMR11] = {0x2C, 7}, + [MA35D1_RESET_UART8] = {0x2C, 8}, + [MA35D1_RESET_UART9] = {0x2C, 9}, + [MA35D1_RESET_UART10] = {0x2C, 10}, + [MA35D1_RESET_UART11] = {0x2C, 11}, + [MA35D1_RESET_UART12] = {0x2C, 12}, + [MA35D1_RESET_UART13] = {0x2C, 13}, + [MA35D1_RESET_UART14] = {0x2C, 14}, + [MA35D1_RESET_UART15] = {0x2C, 15}, + [MA35D1_RESET_UART16] = {0x2C, 16}, + [MA35D1_RESET_I2S1] = {0x2C, 17}, + [MA35D1_RESET_I2C4] = {0x2C, 18}, + [MA35D1_RESET_I2C5] = {0x2C, 19}, + [MA35D1_RESET_EPWM2] = {0x2C, 20}, + [MA35D1_RESET_ECAP2] = {0x2C, 21}, + [MA35D1_RESET_QEI2] = {0x2C, 22}, + [MA35D1_RESET_CANFD3] = {0x2C, 23}, + [MA35D1_RESET_KPI] = {0x2C, 24}, + [MA35D1_RESET_GIC] = {0x2C, 28}, + [MA35D1_RESET_SSMCC] = {0x2C, 30}, + [MA35D1_RESET_SSPCC] = {0x2C, 31} +}; + +static int ma35d1_restart_handler(struct notifier_block *this, unsigned long mode, void *cmd) +{ + struct ma35d1_reset_data *data = + container_of(this, struct ma35d1_reset_data, restart_handler); + u32 id = MA35D1_RESET_CHIP; + + writel_relaxed(BIT(ma35d1_reset_map[id].bit), + data->base + ma35d1_reset_map[id].reg_ofs); + return 0; +} + +static int ma35d1_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) +{ + struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev); + unsigned long flags; + u32 reg; + + if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map))) + return -EINVAL; + + spin_lock_irqsave(&data->lock, flags); + reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); + if (assert) + reg |= BIT(ma35d1_reset_map[id].bit); + else + reg &= ~(BIT(ma35d1_reset_map[id].bit)); + writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, true); +} + +static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, false); +} + +static int ma35d1_reset_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev); + u32 reg; + + if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map))) + return -EINVAL; + + reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); + return !!(reg & BIT(ma35d1_reset_map[id].bit)); +} + +static const struct reset_control_ops ma35d1_reset_ops = { + .assert = ma35d1_reset_assert, + .deassert = ma35d1_reset_deassert, + .status = ma35d1_reset_status, +}; + +static const struct of_device_id ma35d1_reset_dt_ids[] = { + { .compatible = "nuvoton,ma35d1-reset" }, + { }, +}; + +static int ma35d1_reset_probe(struct platform_device *pdev) +{ + struct ma35d1_reset_data *reset_data; + struct device *dev = &pdev->dev; + int err; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Device tree node not found\n"); + return -EINVAL; + } + + reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reset_data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reset_data->base)) + return PTR_ERR(reset_data->base); + + reset_data->rcdev.owner = THIS_MODULE; + reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT; + reset_data->rcdev.ops = &ma35d1_reset_ops; + reset_data->rcdev.of_node = dev->of_node; + reset_data->restart_handler.notifier_call = ma35d1_restart_handler; + reset_data->restart_handler.priority = 192; + spin_lock_init(&reset_data->lock); + + err = register_restart_handler(&reset_data->restart_handler); + if (err) + dev_warn(&pdev->dev, "failed to register restart handler\n"); + + return devm_reset_controller_register(dev, &reset_data->rcdev); +} + +static struct platform_driver ma35d1_reset_driver = { + .probe = ma35d1_reset_probe, + .driver = { + .name = "ma35d1-reset", + .of_match_table = ma35d1_reset_dt_ids, + }, +}; + +builtin_platform_driver(ma35d1_reset_driver); diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h new file mode 100644 index 000000000000..ba2d70f776a6 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + */ + +#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H +#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H + +/* external and internal oscillator clocks */ +#define HXT 0 +#define HXT_GATE 1 +#define LXT 2 +#define LXT_GATE 3 +#define HIRC 4 +#define HIRC_GATE 5 +#define LIRC 6 +#define LIRC_GATE 7 +/* PLLs */ +#define CAPLL 8 +#define SYSPLL 9 +#define DDRPLL 10 +#define APLL 11 +#define EPLL 12 +#define VPLL 13 +/* EPLL divider */ +#define EPLL_DIV2 14 +#define EPLL_DIV4 15 +#define EPLL_DIV8 16 +/* CPU clock, system clock, AXI, HCLK and PCLK */ +#define CA35CLK_MUX 17 +#define AXICLK_DIV2 18 +#define AXICLK_DIV4 19 +#define AXICLK_MUX 20 +#define SYSCLK0_MUX 21 +#define SYSCLK1_MUX 22 +#define SYSCLK1_DIV2 23 +#define HCLK0 24 +#define HCLK1 25 +#define HCLK2 26 +#define PCLK0 27 +#define PCLK1 28 +#define PCLK2 29 +#define HCLK3 30 +#define PCLK3 31 +#define PCLK4 32 +/* AXI and AHB peripheral clocks */ +#define USBPHY0 33 +#define USBPHY1 34 +#define DDR0_GATE 35 +#define DDR6_GATE 36 +#define CAN0_MUX 37 +#define CAN0_DIV 38 +#define CAN0_GATE 39 +#define CAN1_MUX 40 +#define CAN1_DIV 41 +#define CAN1_GATE 42 +#define CAN2_MUX 43 +#define CAN2_DIV 44 +#define CAN2_GATE 45 +#define CAN3_MUX 46 +#define CAN3_DIV 47 +#define CAN3_GATE 48 +#define SDH0_MUX 49 +#define SDH0_GATE 50 +#define SDH1_MUX 51 +#define SDH1_GATE 52 +#define NAND_GATE 53 +#define USBD_GATE 54 +#define USBH_GATE 55 +#define HUSBH0_GATE 56 +#define HUSBH1_GATE 57 +#define GFX_MUX 58 +#define GFX_GATE 59 +#define VC8K_GATE 60 +#define DCU_MUX 61 +#define DCU_GATE 62 +#define DCUP_DIV 63 +#define EMAC0_GATE 64 +#define EMAC1_GATE 65 +#define CCAP0_MUX 66 +#define CCAP0_DIV 67 +#define CCAP0_GATE 68 +#define CCAP1_MUX 69 +#define CCAP1_DIV 70 +#define CCAP1_GATE 71 +#define PDMA0_GATE 72 +#define PDMA1_GATE 73 +#define PDMA2_GATE 74 +#define PDMA3_GATE 75 +#define WH0_GATE 76 +#define WH1_GATE 77 +#define HWS_GATE 78 +#define EBI_GATE 79 +#define SRAM0_GATE 80 +#define SRAM1_GATE 81 +#define ROM_GATE 82 +#define TRA_GATE 83 +#define DBG_MUX 84 +#define DBG_GATE 85 +#define CKO_MUX 86 +#define CKO_DIV 87 +#define CKO_GATE 88 +#define GTMR_GATE 89 +#define GPA_GATE 90 +#define GPB_GATE 91 +#define GPC_GATE 92 +#define GPD_GATE 93 +#define GPE_GATE 94 +#define GPF_GATE 95 +#define GPG_GATE 96 +#define GPH_GATE 97 +#define GPI_GATE 98 +#define GPJ_GATE 99 +#define GPK_GATE 100 +#define GPL_GATE 101 +#define GPM_GATE 102 +#define GPN_GATE 103 +/* APB peripheral clocks */ +#define TMR0_MUX 104 +#define TMR0_GATE 105 +#define TMR1_MUX 106 +#define TMR1_GATE 107 +#define TMR2_MUX 108 +#define TMR2_GATE 109 +#define TMR3_MUX 110 +#define TMR3_GATE 111 +#define TMR4_MUX 112 +#define TMR4_GATE 113 +#define TMR5_MUX 114 +#define TMR5_GATE 115 +#define TMR6_MUX 116 +#define TMR6_GATE 117 +#define TMR7_MUX 118 +#define TMR7_GATE 119 +#define TMR8_MUX 120 +#define TMR8_GATE 121 +#define TMR9_MUX 122 +#define TMR9_GATE 123 +#define TMR10_MUX 124 +#define TMR10_GATE 125 +#define TMR11_MUX 126 +#define TMR11_GATE 127 +#define UART0_MUX 128 +#define UART0_DIV 129 +#define UART0_GATE 130 +#define UART1_MUX 131 +#define UART1_DIV 132 +#define UART1_GATE 133 +#define UART2_MUX 134 +#define UART2_DIV 135 +#define UART2_GATE 136 +#define UART3_MUX 137 +#define UART3_DIV 138 +#define UART3_GATE 139 +#define UART4_MUX 140 +#define UART4_DIV 141 +#define UART4_GATE 142 +#define UART5_MUX 143 +#define UART5_DIV 144 +#define UART5_GATE 145 +#define UART6_MUX 146 +#define UART6_DIV 147 +#define UART6_GATE 148 +#define UART7_MUX 149 +#define UART7_DIV 150 +#define UART7_GATE 151 +#define UART8_MUX 152 +#define UART8_DIV 153 +#define UART8_GATE 154 +#define UART9_MUX 155 +#define UART9_DIV 156 +#define UART9_GATE 157 +#define UART10_MUX 158 +#define UART10_DIV 159 +#define UART10_GATE 160 +#define UART11_MUX 161 +#define UART11_DIV 162 +#define UART11_GATE 163 +#define UART12_MUX 164 +#define UART12_DIV 165 +#define UART12_GATE 166 +#define UART13_MUX 167 +#define UART13_DIV 168 +#define UART13_GATE 169 +#define UART14_MUX 170 +#define UART14_DIV 171 +#define UART14_GATE 172 +#define UART15_MUX 173 +#define UART15_DIV 174 +#define UART15_GATE 175 +#define UART16_MUX 176 +#define UART16_DIV 177 +#define UART16_GATE 178 +#define RTC_GATE 179 +#define DDR_GATE 180 +#define KPI_MUX 181 +#define KPI_DIV 182 +#define KPI_GATE 183 +#define I2C0_GATE 184 +#define I2C1_GATE 185 +#define I2C2_GATE 186 +#define I2C3_GATE 187 +#define I2C4_GATE 188 +#define I2C5_GATE 189 +#define QSPI0_MUX 190 +#define QSPI0_GATE 191 +#define QSPI1_MUX 192 +#define QSPI1_GATE 193 +#define SMC0_MUX 194 +#define SMC0_DIV 195 +#define SMC0_GATE 196 +#define SMC1_MUX 197 +#define SMC1_DIV 198 +#define SMC1_GATE 199 +#define WDT0_MUX 200 +#define WDT0_GATE 201 +#define WDT1_MUX 202 +#define WDT1_GATE 203 +#define WDT2_MUX 204 +#define WDT2_GATE 205 +#define WWDT0_MUX 206 +#define WWDT1_MUX 207 +#define WWDT2_MUX 208 +#define EPWM0_GATE 209 +#define EPWM1_GATE 210 +#define EPWM2_GATE 211 +#define I2S0_MUX 212 +#define I2S0_GATE 213 +#define I2S1_MUX 214 +#define I2S1_GATE 215 +#define SSMCC_GATE 216 +#define SSPCC_GATE 217 +#define SPI0_MUX 218 +#define SPI0_GATE 219 +#define SPI1_MUX 220 +#define SPI1_GATE 221 +#define SPI2_MUX 222 +#define SPI2_GATE 223 +#define SPI3_MUX 224 +#define SPI3_GATE 225 +#define ECAP0_GATE 226 +#define ECAP1_GATE 227 +#define ECAP2_GATE 228 +#define QEI0_GATE 229 +#define QEI1_GATE 230 +#define QEI2_GATE 231 +#define ADC_DIV 232 +#define ADC_GATE 233 +#define EADC_DIV 234 +#define EADC_GATE 235 +#define CLK_MAX_IDX 236 + +#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4d..28ad0235086a 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -37,6 +37,9 @@ #define STM32MP_PKG_AB 0x2 #define STM32MP_PKG_AC 0x4 #define STM32MP_PKG_AD 0x8 +#define STM32MP_PKG_AI 0x100 +#define STM32MP_PKG_AK 0x400 +#define STM32MP_PKG_AL 0x800 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ diff --git a/include/dt-bindings/reset/nuvoton,ma35d1-reset.h b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h new file mode 100644 index 000000000000..2e99ee0d68c5 --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Nuvoton Technologies. + * Author: Chi-Fen Li <cfli0@nuvoton.com> + * + * Device Tree binding constants for MA35D1 reset controller. + */ + +#ifndef __DT_BINDINGS_RESET_MA35D1_H +#define __DT_BINDINGS_RESET_MA35D1_H + +#define MA35D1_RESET_CHIP 0 +#define MA35D1_RESET_CA35CR0 1 +#define MA35D1_RESET_CA35CR1 2 +#define MA35D1_RESET_CM4 3 +#define MA35D1_RESET_PDMA0 4 +#define MA35D1_RESET_PDMA1 5 +#define MA35D1_RESET_PDMA2 6 +#define MA35D1_RESET_PDMA3 7 +#define MA35D1_RESET_DISP 8 +#define MA35D1_RESET_VCAP0 9 +#define MA35D1_RESET_VCAP1 10 +#define MA35D1_RESET_GFX 11 +#define MA35D1_RESET_VDEC 12 +#define MA35D1_RESET_WHC0 13 +#define MA35D1_RESET_WHC1 14 +#define MA35D1_RESET_GMAC0 15 +#define MA35D1_RESET_GMAC1 16 +#define MA35D1_RESET_HWSEM 17 +#define MA35D1_RESET_EBI 18 +#define MA35D1_RESET_HSUSBH0 19 +#define MA35D1_RESET_HSUSBH1 20 +#define MA35D1_RESET_HSUSBD 21 +#define MA35D1_RESET_USBHL 22 +#define MA35D1_RESET_SDH0 23 +#define MA35D1_RESET_SDH1 24 +#define MA35D1_RESET_NAND 25 +#define MA35D1_RESET_GPIO 26 +#define MA35D1_RESET_MCTLP 27 +#define MA35D1_RESET_MCTLC 28 +#define MA35D1_RESET_DDRPUB 29 +#define MA35D1_RESET_TMR0 30 +#define MA35D1_RESET_TMR1 31 +#define MA35D1_RESET_TMR2 32 +#define MA35D1_RESET_TMR3 33 +#define MA35D1_RESET_I2C0 34 +#define MA35D1_RESET_I2C1 35 +#define MA35D1_RESET_I2C2 36 +#define MA35D1_RESET_I2C3 37 +#define MA35D1_RESET_QSPI0 38 +#define MA35D1_RESET_SPI0 39 +#define MA35D1_RESET_SPI1 40 +#define MA35D1_RESET_SPI2 41 +#define MA35D1_RESET_UART0 42 +#define MA35D1_RESET_UART1 43 +#define MA35D1_RESET_UART2 44 +#define MA35D1_RESET_UART3 45 +#define MA35D1_RESET_UART4 46 +#define MA35D1_RESET_UART5 47 +#define MA35D1_RESET_UART6 48 +#define MA35D1_RESET_UART7 49 +#define MA35D1_RESET_CANFD0 50 +#define MA35D1_RESET_CANFD1 51 +#define MA35D1_RESET_EADC0 52 +#define MA35D1_RESET_I2S0 53 +#define MA35D1_RESET_SC0 54 +#define MA35D1_RESET_SC1 55 +#define MA35D1_RESET_QSPI1 56 +#define MA35D1_RESET_SPI3 57 +#define MA35D1_RESET_EPWM0 58 +#define MA35D1_RESET_EPWM1 59 +#define MA35D1_RESET_QEI0 60 +#define MA35D1_RESET_QEI1 61 +#define MA35D1_RESET_ECAP0 62 +#define MA35D1_RESET_ECAP1 63 +#define MA35D1_RESET_CANFD2 64 +#define MA35D1_RESET_ADC0 65 +#define MA35D1_RESET_TMR4 66 +#define MA35D1_RESET_TMR5 67 +#define MA35D1_RESET_TMR6 68 +#define MA35D1_RESET_TMR7 69 +#define MA35D1_RESET_TMR8 70 +#define MA35D1_RESET_TMR9 71 +#define MA35D1_RESET_TMR10 72 +#define MA35D1_RESET_TMR11 73 +#define MA35D1_RESET_UART8 74 +#define MA35D1_RESET_UART9 75 +#define MA35D1_RESET_UART10 76 +#define MA35D1_RESET_UART11 77 +#define MA35D1_RESET_UART12 78 +#define MA35D1_RESET_UART13 79 +#define MA35D1_RESET_UART14 80 +#define MA35D1_RESET_UART15 81 +#define MA35D1_RESET_UART16 82 +#define MA35D1_RESET_I2S1 83 +#define MA35D1_RESET_I2C4 84 +#define MA35D1_RESET_I2C5 85 +#define MA35D1_RESET_EPWM2 86 +#define MA35D1_RESET_ECAP2 87 +#define MA35D1_RESET_QEI2 88 +#define MA35D1_RESET_CANFD3 89 +#define MA35D1_RESET_KPI 90 +#define MA35D1_RESET_GIC 91 +#define MA35D1_RESET_SSMCC 92 +#define MA35D1_RESET_SSPCC 93 +#define MA35D1_RESET_COUNT 94 + +#endif |