diff options
185 files changed, 14757 insertions, 5897 deletions
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt index 4b87ea1194e3..704be9306c9f 100644 --- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt +++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt @@ -95,7 +95,6 @@ GPMC chip-select settings properties for child nodes. All are optional. - gpmc,burst-wrap Enables wrap bursting - gpmc,burst-read Enables read page/burst mode - gpmc,burst-write Enables write page/burst mode -- gpmc,device-nand Device is NAND - gpmc,device-width Total width of device(s) connected to a GPMC chip-select in bytes. The GPMC supports 8-bit and 16-bit devices and so this property must be diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt new file mode 100644 index 000000000000..bea5b73a7390 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt @@ -0,0 +1,66 @@ +* DMA40 DMA Controller + +Required properties: +- compatible: "stericsson,dma40" +- reg: Address range of the DMAC registers +- reg-names: Names of the above areas to use during resource look-up +- interrupt: Should contain the DMAC interrupt number +- #dma-cells: must be <3> +- memcpy-channels: Channels to be used for memcpy + +Optional properties: +- dma-channels: Number of channels supported by hardware - if not present + the driver will attempt to obtain the information from H/W +- disabled-channels: Channels which can not be used + +Example: + + dma: dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", "stericsson,dma40"; + reg = <0x801C0000 0x1000 0x40010000 0x800>; + reg-names = "base", "lcpa"; + interrupt-parent = <&intc>; + interrupts = <0 25 0x4>; + + #dma-cells = <2>; + memcpy-channels = <56 57 58 59 60>; + disabled-channels = <12>; + dma-channels = <8>; + }; + +Clients +Required properties: +- dmas: Comma separated list of dma channel requests +- dma-names: Names of the aforementioned requested channels + +Each dmas request consists of 4 cells: + 1. A phandle pointing to the DMA controller + 2. Device Type + 3. The DMA request line number (only when 'use fixed channel' is set) + 4. A 32bit mask specifying; mode, direction and endianess [NB: This list will grow] + 0x00000001: Mode: + Logical channel when unset + Physical channel when set + 0x00000002: Direction: + Memory to Device when unset + Device to Memory when set + 0x00000004: Endianess: + Little endian when unset + Big endian when set + 0x00000008: Use fixed channel: + Use automatic channel selection when unset + Use DMA request line number when set + +Example: + + uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 0x4>; + + dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ + <&dma 13 0 0x0>; /* Logical - MemToDev */ + dma-names = "rx", "rx"; + + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt index f1e5dfecf55d..5375625e8cd2 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt @@ -39,46 +39,3 @@ Example: #gpio-cells = <4>; gpio-controller; }; - - -Samsung S3C24XX GPIO Controller - -Required properties: -- compatible: Compatible property value should be "samsung,s3c24xx-gpio". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes - should be the following with values derived from the SoC user manual. - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [mux function] - [flags and pull up/down] - - Values for gpio specifier: - - Pin number: depending on the controller a number from 0 up to 15. - - Mux function: Depending on the SoC and the gpio bank the gpio can be set - as input, output or a special function - - Flags and Pull Up/Down: the values to use differ for the individual SoCs - example S3C2416/S3C2450: - 0 - Pull Up/Down Disabled. - 1 - Pull Down Enabled. - 2 - Pull Up Enabled. - Bit 16 (0x00010000) - Input is active low. - Consult the user manual for the correct values of Mux and Pull Up/Down. - -- gpio-controller: Specifies that the node is a gpio controller. -- #address-cells: should be 1. -- #size-cells: should be 1. - -Example: - - gpa: gpio-controller@56000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "samsung,s3c24xx-gpio"; - reg = <0x56000000 0x10>; - #gpio-cells = <3>; - gpio-controller; - }; diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt new file mode 100644 index 000000000000..46d76a004246 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt @@ -0,0 +1,52 @@ +* Renesas R-Car GPIO Controller + +Required Properties: + + - compatible: should be one of the following. + - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. + - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. + - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. + - "renesas,gpio-rcar": for generic R-Car GPIO controller. + + - reg: Base address and length of each memory resource used by the GPIO + controller hardware module. + + - interrupt-parent: phandle of the parent interrupt controller. + - interrupts: Interrupt specifier for the controllers interrupt. + + - gpio-controller: Marks the device node as a gpio controller. + - #gpio-cells: Should be 2. The first cell is the GPIO number and the second + cell is used to specify optional parameters as bit flags. Only the GPIO + active low flag (bit 0) is currently supported. + - gpio-ranges: Range of pins managed by the GPIO controller as a 4-cells + tuple using the following syntax. + + <[phandle of the pin controller node] + 0 + [index of the first pin] + [number of pins]> + +Please refer to gpio.txt in this directory for details of the common GPIO +bindings used by client devices. + +Example: R8A7779 (R-Car H1) GPIO controller nodes + + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc40000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 141 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + }; + ... + gpio6: gpio@ffc46000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc46000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 147 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 9>; + }; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 6a983c1d87cd..df338cb5059c 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -29,6 +29,13 @@ Optional properties: "bch4" 4-bit BCH ecc code "bch8" 8-bit BCH ecc code + - ti,nand-xfer-type: A string setting the data transfer type. One of: + + "prefetch-polled" Prefetch polled mode (default) + "polled" Polled mode, without prefetch + "prefetch-dma" Prefetch enabled sDMA mode + "prefetch-irq" Prefetch enabled irq mode + - elm_id: Specifies elm device node. This is required to support BCH error correction using ELM module. @@ -55,6 +62,7 @@ Example for an AM33xx board: reg = <0 0 0>; /* CS0, offset 0 */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "polled"; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index e15cfc4bb39e..72e9cd1e89b7 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -7,6 +7,10 @@ on-chip controllers onto these pads. Required Properties: - compatible: should be one of the following. + - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, + - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, + - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, + - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. @@ -116,6 +120,10 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a - compatible: identifies the type of the external wakeup interrupt controller The possible values are: + - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller + found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, + - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller + found on Samsung S3C2412 and S3C2413 SoCs, - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller found on Samsung S3C64xx SoCs, - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt index 93e2b0f048e6..eb2327b2bdb3 100644 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt @@ -5,9 +5,20 @@ Required properties: - reg: physical base address of the controller and length of memory mapped region. - interrupts: IRQ line for the timer. +- either clocks+clock-names or clock-frequency properties + +Optional properties: +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names : should contain "timer" and "pclk" entries, matching entries + in the clocks property. - clock-frequency: The frequency in HZ of the timer. - clock-freq: For backwards compatibility with picoxcell +If using the clock specifiers, the pclk clock is optional, as not all +systems may use one. + + Example: timer1: timer@ffc09000 { @@ -23,3 +34,11 @@ Example: clock-frequency = <200000000>; reg = <0xffd00000 0x1000>; }; + + timer3: timer@ffe00000 { + compatible = "snps,dw-apb-timer-osc"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>, <&timer_pclk>; + clock-names = "timer", "pclk"; + }; diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 60bd2150a3e6..55f51af08bc7 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -47,3 +47,85 @@ usb1: gadget@fffa4000 { interrupts = <10 4>; atmel,vbus-gpio = <&pioC 5 0>; }; + +Atmel High-Speed USB device controller + +Required properties: + - compatible: Should be "atmel,at91sam9rl-udc" + - reg: Address and length of the register set for the device + - interrupts: Should contain usba interrupt + - ep childnode: To specify the number of endpoints and their properties. + +Optional properties: + - atmel,vbus-gpio: If present, specifies a gpio that needs to be + activated for the bus to be powered. + +Required child node properties: + - name: Name of the endpoint. + - reg: Num of the endpoint. + - atmel,fifo-size: Size of the fifo. + - atmel,nb-banks: Number of banks. + - atmel,can-dma: Boolean to specify if the endpoint support DMA. + - atmel,can-isoc: Boolean to specify if the endpoint support ISOC. + +usb2: gadget@fff78000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00600000 0x80000 + 0xfff78000 0x400>; + interrupts = <27 4 0>; + atmel,vbus-gpio = <&pioB 19 0>; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; +}; diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt new file mode 100644 index 000000000000..330d6ec15401 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ux500-usb.txt @@ -0,0 +1,50 @@ +Ux500 MUSB + +Required properties: + - compatible : Should be "stericsson,db8500-musb" + - reg : Offset and length of registers + - interrupts : Interrupt; mode, number and trigger + - dr_mode : Dual-role; either host mode "host", peripheral mode "peripheral" + or both "otg" + +Optional properties: + - dmas : A list of dma channels; + dma-controller, event-line, fixed-channel, flags + - dma-names : An ordered list of channel names affiliated to the above + +Example: + +usb_per5@a03e0000 { + compatible = "stericsson,db8500-musb", "mentor,musb"; + reg = <0xa03e0000 0x10000>; + interrupts = <0 23 0x4>; + interrupt-names = "mc"; + + dr_mode = "otg"; + + dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ + <&dma 38 0 0x0>, /* Logical - MemToDev */ + <&dma 37 0 0x2>, /* Logical - DevToMem */ + <&dma 37 0 0x0>, /* Logical - MemToDev */ + <&dma 36 0 0x2>, /* Logical - DevToMem */ + <&dma 36 0 0x0>, /* Logical - MemToDev */ + <&dma 19 0 0x2>, /* Logical - DevToMem */ + <&dma 19 0 0x0>, /* Logical - MemToDev */ + <&dma 18 0 0x2>, /* Logical - DevToMem */ + <&dma 18 0 0x0>, /* Logical - MemToDev */ + <&dma 17 0 0x2>, /* Logical - DevToMem */ + <&dma 17 0 0x0>, /* Logical - MemToDev */ + <&dma 16 0 0x2>, /* Logical - DevToMem */ + <&dma 16 0 0x0>, /* Logical - MemToDev */ + <&dma 39 0 0x2>, /* Logical - DevToMem */ + <&dma 39 0 0x0>; /* Logical - MemToDev */ + + dma-names = "iep_1_9", "oep_1_9", + "iep_2_10", "oep_2_10", + "iep_3_11", "oep_3_11", + "iep_4_12", "oep_4_12", + "iep_5_13", "oep_5_13", + "iep_6_14", "oep_6_14", + "iep_7_15", "oep_7_15", + "iep_8", "oep_8"; +}; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49d993cee512..4dff801c22eb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -645,7 +645,7 @@ config ARCH_SHMOBILE select MULTI_IRQ_HANDLER select NEED_MACH_MEMORY_H select NO_IOPORT - select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ help @@ -2054,53 +2054,6 @@ menu "CPU Power Management" if ARCH_HAS_CPUFREQ source "drivers/cpufreq/Kconfig" - -config CPU_FREQ_S3C - bool - help - Internal configuration node for common cpufreq on Samsung SoC - -config CPU_FREQ_S3C24XX - bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" - depends on ARCH_S3C24XX && CPU_FREQ - select CPU_FREQ_S3C - help - This enables the CPUfreq driver for the Samsung S3C24XX family - of CPUs. - - For details, take a look at <file:Documentation/cpu-freq>. - - If in doubt, say N. - -config CPU_FREQ_S3C24XX_PLL - bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" - depends on CPU_FREQ_S3C24XX - help - Compile in support for changing the PLL frequency from the - S3C24XX series CPUfreq driver. The PLL takes time to settle - after a frequency change, so by default it is not enabled. - - This also means that the PLL tables for the selected CPU(s) will - be built which may increase the size of the kernel image. - -config CPU_FREQ_S3C24XX_DEBUG - bool "Debug CPUfreq Samsung driver core" - depends on CPU_FREQ_S3C24XX - help - Enable s3c_freq_dbg for the Samsung S3C CPUfreq core - -config CPU_FREQ_S3C24XX_IODEBUG - bool "Debug CPUfreq Samsung driver IO timing" - depends on CPU_FREQ_S3C24XX - help - Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core - -config CPU_FREQ_S3C24XX_DEBUGFS - bool "Export debugfs for CPUFreq" - depends on CPU_FREQ_S3C24XX && DEBUG_FS - help - Export status information via debugfs. - endif source "drivers/cpuidle/Kconfig" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f0895c581a89..56ffdde091fa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ hrefprev60.dtb \ hrefv60plus.dtb \ ccu9540.dtb +dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts index 29b9f15e7599..54cb5cf8604a 100644 --- a/arch/arm/boot/dts/aks-cdu.dts +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -9,7 +9,7 @@ /dts-v1/; -/include/ "ge863-pro3.dtsi" +#include "ge863-pro3.dtsi" / { chosen { @@ -46,7 +46,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 15 0>; + atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -90,23 +90,23 @@ compatible = "gpio-leds"; red { - gpios = <&pioC 10 0>; + gpios = <&pioC 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; }; green { - gpios = <&pioA 5 1>; + gpios = <&pioA 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; yellow { - gpios = <&pioB 20 1>; + gpios = <&pioB 20 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; blue { - gpios = <&pioB 21 1>; + gpios = <&pioB 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; }; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 5160210f74da..3a1de9eb5111 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { model = "Somfy Animeo IP"; @@ -123,7 +123,7 @@ usb0: ohci@00500000 { num-ports = <2>; - atmel,vbus-gpio = <&pioB 15 1>; + atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; status = "okay"; }; }; @@ -133,23 +133,23 @@ power_green { label = "power_green"; - gpios = <&pioC 17 0>; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; power_red { label = "power_red"; - gpios = <&pioA 2 0>; + gpios = <&pioA 2 GPIO_ACTIVE_HIGH>; }; tx_green { label = "tx_green"; - gpios = <&pioC 19 0>; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; }; tx_red { label = "tx_red"; - gpios = <&pioC 18 0>; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; }; }; @@ -160,21 +160,21 @@ keyswitch_in { label = "keyswitch_in"; - gpios = <&pioB 1 0>; + gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; linux,code = <28>; gpio-key,wakeup; }; error_in { label = "error_in"; - gpios = <&pioB 2 0>; + gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; linux,code = <29>; gpio-key,wakeup; }; btn { label = "btn"; - gpios = <&pioC 23 0>; + gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; linux,code = <31>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index c7aebba4e8e7..5ede7678f298 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g25.dtsi" +#include "at91sam9g25.dtsi" / { model = "Acme Systems Aria G25"; @@ -156,7 +156,7 @@ /* little green LED in middle of Aria G25 module */ aria_led { label = "aria_led"; - gpios = <&pioB 8 0>; /* PB8 */ + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */ linux,default-trigger = "heartbeat"; }; @@ -164,7 +164,7 @@ onewire@0 { compatible = "w1-gpio"; - gpios = <&pioA 21 1>; + gpios = <&pioA 21 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_w1_0>; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 5d3ed5aafc69..4aad0d9f5462 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -10,7 +10,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91RM9200 family SoC"; @@ -77,25 +80,29 @@ st: timer@fffffd00 { compatible = "atmel,at91rm9200-st"; reg = <0xfffffd00 0x100>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@fffa0000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffa0000 0x100>; - interrupts = <17 4 0 18 4 0 19 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@fffa4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffa4000 0x100>; - interrupts = <20 4 0 21 4 0 22 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 + 21 IRQ_TYPE_LEVEL_HIGH 0 + 22 IRQ_TYPE_LEVEL_HIGH 0>; }; i2c0: i2c@fffb8000 { compatible = "atmel,at91rm9200-i2c"; reg = <0xfffb8000 0x4000>; - interrupts = <12 4 6>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_twi>; #address-cells = <1>; @@ -106,7 +113,7 @@ mmc0: mmc@fffb4000 { compatible = "atmel,hsmci"; reg = <0xfffb4000 0x4000>; - interrupts = <10 4 0>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -115,7 +122,7 @@ ssc0: ssc@fffd0000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffd0000 0x4000>; - interrupts = <14 4 5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disable"; @@ -124,7 +131,7 @@ ssc1: ssc@fffd4000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffd4000 0x4000>; - interrupts = <15 4 5>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disable"; @@ -133,7 +140,7 @@ ssc2: ssc@fffd8000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffd8000 0x4000>; - interrupts = <16 4 5>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; status = "disable"; @@ -142,7 +149,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at91rm9200-emac", "cdns,emac"; reg = <0xfffbc000 0x4000>; - interrupts = <24 4 3>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; @@ -167,234 +174,234 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <0 30 0x1 0x0 /* PA30 periph A */ - 0 31 0x1 0x1>; /* PA31 periph with pullup */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <0 17 0x1 0x0 /* PA17 periph A */ - 0 18 0x1 0x0>; /* PA18 periph A */ + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ }; pinctrl_uart0_rts: uart0_rts-0 { atmel,pins = - <0 20 0x1 0x0>; /* PA20 periph A */ + <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ }; pinctrl_uart0_cts: uart0_cts-0 { atmel,pins = - <0 21 0x1 0x0>; /* PA21 periph A */ + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <1 20 0x1 0x1 /* PB20 periph A with pullup */ - 1 21 0x1 0x0>; /* PB21 periph A */ + <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ }; pinctrl_uart1_rts: uart1_rts-0 { atmel,pins = - <1 24 0x1 0x0>; /* PB24 periph A */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ }; pinctrl_uart1_cts: uart1_cts-0 { atmel,pins = - <1 26 0x1 0x0>; /* PB26 periph A */ + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ }; pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { atmel,pins = - <1 19 0x1 0x0 /* PB19 periph A */ - 1 25 0x1 0x0>; /* PB25 periph A */ + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ + AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ }; pinctrl_uart1_dcd: uart1_dcd-0 { atmel,pins = - <1 23 0x1 0x0>; /* PB23 periph A */ + <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ }; pinctrl_uart1_ri: uart1_ri-0 { atmel,pins = - <1 18 0x1 0x0>; /* PB18 periph A */ + <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ }; }; uart2 { pinctrl_uart2: uart2-0 { atmel,pins = - <0 22 0x1 0x0 /* PA22 periph A */ - 0 23 0x1 0x1>; /* PA23 periph A with pullup */ + <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ }; pinctrl_uart2_rts: uart2_rts-0 { atmel,pins = - <0 30 0x2 0x0>; /* PA30 periph B */ + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ }; pinctrl_uart2_cts: uart2_cts-0 { atmel,pins = - <0 31 0x2 0x0>; /* PA31 periph B */ + <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ }; }; uart3 { pinctrl_uart3: uart3-0 { atmel,pins = - <0 5 0x2 0x1 /* PA5 periph B with pullup */ - 0 6 0x2 0x0>; /* PA6 periph B */ + <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ + AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */ }; pinctrl_uart3_rts: uart3_rts-0 { atmel,pins = - <1 0 0x2 0x0>; /* PB0 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ }; pinctrl_uart3_cts: uart3_cts-0 { atmel,pins = - <1 1 0x2 0x0>; /* PB1 periph B */ + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */ - 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */ + <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ + AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <0 7 0x1 0x0 /* PA7 periph A */ - 0 8 0x1 0x0 /* PA8 periph A */ - 0 9 0x1 0x0 /* PA9 periph A */ - 0 10 0x1 0x0 /* PA10 periph A */ - 0 11 0x1 0x0 /* PA11 periph A */ - 0 12 0x1 0x0 /* PA12 periph A */ - 0 13 0x1 0x0 /* PA13 periph A */ - 0 14 0x1 0x0 /* PA14 periph A */ - 0 15 0x1 0x0 /* PA15 periph A */ - 0 16 0x1 0x0>; /* PA16 periph A */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <1 12 0x2 0x0 /* PB12 periph B */ - 1 13 0x2 0x0 /* PB13 periph B */ - 1 14 0x2 0x0 /* PB14 periph B */ - 1 15 0x2 0x0 /* PB15 periph B */ - 1 16 0x2 0x0 /* PB16 periph B */ - 1 17 0x2 0x0 /* PB17 periph B */ - 1 18 0x2 0x0 /* PB18 periph B */ - 1 19 0x2 0x0>; /* PB19 periph B */ + <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ + AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ + AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ + AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ + AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ + AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ + AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = - <0 27 0x1 0x0>; /* PA27 periph A */ + <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = - <0 28 0x1 0x1 /* PA28 periph A with pullup */ - 0 29 0x1 0x1>; /* PA29 periph A with pullup */ + <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <1 3 0x2 0x1 /* PB3 periph B with pullup */ - 1 4 0x2 0x1 /* PB4 periph B with pullup */ - 1 5 0x2 0x1>; /* PB5 periph B with pullup */ + <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ + AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = - <0 8 0x2 0x1 /* PA8 periph B with pullup */ - 0 9 0x2 0x1>; /* PA9 periph B with pullup */ + <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ + AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = - <0 10 0x2 0x1 /* PA10 periph B with pullup */ - 0 11 0x2 0x1 /* PA11 periph B with pullup */ - 0 12 0x2 0x1>; /* PA12 periph B with pullup */ + <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A */ - 1 1 0x1 0x0 /* PB1 periph A */ - 1 2 0x1 0x0>; /* PB2 periph A */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <1 3 0x1 0x0 /* PB3 periph A */ - 1 4 0x1 0x0 /* PB4 periph A */ - 1 5 0x1 0x0>; /* PB5 periph A */ + <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = - <1 6 0x1 0x0 /* PB6 periph A */ - 1 7 0x1 0x0 /* PB7 periph A */ - 1 8 0x1 0x0>; /* PB8 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = - <1 9 0x1 0x0 /* PB9 periph A */ - 1 10 0x1 0x0 /* PB10 periph A */ - 1 11 0x1 0x0>; /* PB11 periph A */ + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; }; ssc2 { pinctrl_ssc2_tx: ssc2_tx-0 { atmel,pins = - <1 12 0x1 0x0 /* PB12 periph A */ - 1 13 0x1 0x0 /* PB13 periph A */ - 1 14 0x1 0x0>; /* PB14 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ }; pinctrl_ssc2_rx: ssc2_rx-0 { atmel,pins = - <1 15 0x1 0x0 /* PB15 periph A */ - 1 16 0x1 0x0 /* PB16 periph A */ - 1 17 0x1 0x0>; /* PB17 periph A */ + <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ }; }; twi { pinctrl_twi: twi-0 { atmel,pins = - <0 25 0x1 0x2 /* PA25 periph A with multi drive */ - 0 26 0x1 0x2>; /* PA26 periph A with multi drive */ + <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ }; pinctrl_twi_gpio: twi_gpio-0 { atmel,pins = - <0 25 0x0 0x2 /* PA25 GPIO with multi drive */ - 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */ + <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ + AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ }; }; pioA: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -404,7 +411,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -414,7 +421,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -424,7 +431,7 @@ pioD: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <5 4 1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -435,7 +442,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -444,7 +451,7 @@ usart0: serial@fffc0000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc0000 0x200>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -455,7 +462,7 @@ usart1: serial@fffc4000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc4000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -466,7 +473,7 @@ usart2: serial@fffc8000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc8000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -477,7 +484,7 @@ usart3: serial@fffcc000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffcc000 0x200>; - interrupts = <23 4 5>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -488,7 +495,7 @@ usb1: gadget@fffb0000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfffb0000 0x4000>; - interrupts = <11 4 2>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; @@ -503,9 +510,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; nand-ecc-mode = "soft"; - gpios = <&pioC 2 0 + gpios = <&pioC 2 GPIO_ACTIVE_HIGH 0 - &pioB 1 0 + &pioB 1 GPIO_ACTIVE_HIGH >; status = "disabled"; }; @@ -513,15 +520,15 @@ usb0: ohci@00300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; - interrupts = <23 4 2>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 25 0 /* sda */ - &pioA 26 0 /* scl */ + gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ + &pioA 26 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e586d85f8e23..14058125d123 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91rm9200.dtsi" +#include "at91rm9200.dtsi" / { model = "Atmel AT91RM9200 evaluation kit"; @@ -50,7 +50,7 @@ }; usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 0>; + atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -66,19 +66,19 @@ ds2 { label = "green"; - gpios = <&pioB 0 0x1>; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; ds4 { label = "yellow"; - gpios = <&pioB 1 0x1>; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; ds6 { label = "red"; - gpios = <&pioB 2 0x1>; + gpios = <&pioB 2 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 84c4bef2d726..a776f50f1243 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -8,7 +8,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9260 family SoC"; @@ -84,19 +87,23 @@ pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@fffa0000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffa0000 0x100>; - interrupts = <17 4 0 18 4 0 19 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 + 18 IRQ_TYPE_LEVEL_HIGH 0 + 19 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@fffdc000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffdc000 0x100>; - interrupts = <26 4 0 27 4 0 28 4 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 + 27 IRQ_TYPE_LEVEL_HIGH 0 + 28 IRQ_TYPE_LEVEL_HIGH 0>; }; pinctrl@fffff400 { @@ -116,234 +123,234 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <1 14 0x1 0x0 /* PB14 periph A */ - 1 15 0x1 0x1>; /* PB15 periph with pullup */ + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <1 4 0x1 0x0 /* PB4 periph A */ - 1 5 0x1 0x0>; /* PB5 periph A */ + <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <1 26 0x1 0x0>; /* PB26 periph A */ + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <1 27 0x1 0x0>; /* PB27 periph A */ + <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ }; pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { atmel,pins = - <1 24 0x1 0x0 /* PB24 periph A */ - 1 22 0x1 0x0>; /* PB22 periph A */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ }; pinctrl_usart0_dcd: usart0_dcd-0 { atmel,pins = - <1 23 0x1 0x0>; /* PB23 periph A */ + <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ }; pinctrl_usart0_ri: usart0_ri-0 { atmel,pins = - <1 25 0x1 0x0>; /* PB25 periph A */ + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <1 6 0x1 0x1 /* PB6 periph A with pullup */ - 1 7 0x1 0x0>; /* PB7 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <1 28 0x1 0x0>; /* PB28 periph A */ + <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <1 29 0x1 0x0>; /* PB29 periph A */ + <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <1 8 0x1 0x1 /* PB8 periph A with pullup */ - 1 9 0x1 0x0>; /* PB9 periph A */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <0 4 0x1 0x0>; /* PA4 periph A */ + <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <0 5 0x1 0x0>; /* PA5 periph A */ + <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <1 10 0x1 0x1 /* PB10 periph A with pullup */ - 1 11 0x1 0x0>; /* PB11 periph A */ + <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <2 8 0x2 0x0>; /* PC8 periph B */ + <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <2 10 0x2 0x0>; /* PC10 periph B */ + <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <0 31 0x2 0x1 /* PA31 periph B with pullup */ - 0 30 0x2 0x0>; /* PA30 periph B */ + <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ + AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <1 12 0x1 0x1 /* PB12 periph A with pullup */ - 1 13 0x1 0x0>; /* PB13 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */ - 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <0 12 0x1 0x0 /* PA12 periph A */ - 0 13 0x1 0x0 /* PA13 periph A */ - 0 14 0x1 0x0 /* PA14 periph A */ - 0 15 0x1 0x0 /* PA15 periph A */ - 0 16 0x1 0x0 /* PA16 periph A */ - 0 17 0x1 0x0 /* PA17 periph A */ - 0 18 0x1 0x0 /* PA18 periph A */ - 0 19 0x1 0x0 /* PA19 periph A */ - 0 20 0x1 0x0 /* PA20 periph A */ - 0 21 0x1 0x0>; /* PA21 periph A */ + <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <0 22 0x2 0x0 /* PA22 periph B */ - 0 23 0x2 0x0 /* PA23 periph B */ - 0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0 /* PA26 periph B */ - 0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ + AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { atmel,pins = - <0 10 0x2 0x0 /* PA10 periph B */ - 0 11 0x2 0x0 /* PA11 periph B */ - 0 22 0x2 0x0 /* PA22 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0 /* PA26 periph B */ - 0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ + AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = - <0 8 0x1 0x0>; /* PA8 periph A */ + <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = - <0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 6 0x1 0x1>; /* PA6 periph A with pullup */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 9 0x1 0x1 /* PA9 periph A with pullup */ - 0 10 0x1 0x1 /* PA10 periph A with pullup */ - 0 11 0x1 0x1>; /* PA11 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = - <0 1 0x2 0x1 /* PA1 periph B with pullup */ - 0 0 0x2 0x1>; /* PA0 periph B with pullup */ + <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ + AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = - <0 5 0x2 0x1 /* PA5 periph B with pullup */ - 0 4 0x2 0x1 /* PA4 periph B with pullup */ - 0 3 0x2 0x1>; /* PA3 periph B with pullup */ + <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <1 16 0x1 0x0 /* PB16 periph A */ - 1 17 0x1 0x0 /* PB17 periph A */ - 1 18 0x1 0x0>; /* PB18 periph A */ + <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <1 19 0x1 0x0 /* PB19 periph A */ - 1 20 0x1 0x0 /* PB20 periph A */ - 1 21 0x1 0x0>; /* PB21 periph A */ + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */ - 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */ - 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */ + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */ - 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */ - 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ }; }; pioA: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -353,7 +360,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -363,7 +370,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -374,7 +381,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -383,7 +390,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -394,7 +401,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -405,7 +412,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -416,7 +423,7 @@ usart3: serial@fffd0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd0000 0x200>; - interrupts = <23 4 5>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -427,7 +434,7 @@ uart0: serial@fffd4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd4000 0x200>; - interrupts = <24 4 5>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -438,7 +445,7 @@ uart1: serial@fffd8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd8000 0x200>; - interrupts = <25 4 5>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -449,7 +456,7 @@ macb0: ethernet@fffc4000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffc4000 0x100>; - interrupts = <21 4 3>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; status = "disabled"; @@ -458,14 +465,14 @@ usb1: gadget@fffa4000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfffa4000 0x4000>; - interrupts = <10 4 2>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; i2c0: i2c@fffac000 { compatible = "atmel,at91sam9260-i2c"; reg = <0xfffac000 0x100>; - interrupts = <11 4 6>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -474,7 +481,7 @@ mmc0: mmc@fffa8000 { compatible = "atmel,hsmci"; reg = <0xfffa8000 0x600>; - interrupts = <9 4 0>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -483,7 +490,7 @@ ssc0: ssc@fffbc000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfffbc000 0x4000>; - interrupts = <14 4 5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -494,7 +501,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffc8000 0x200>; - interrupts = <12 4 3>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -505,7 +512,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffcc000 0x200>; - interrupts = <13 4 3>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -514,7 +521,7 @@ adc0: adc@fffe0000 { compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; - interrupts = <5 4 0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xf>; atmel,adc-vref = <3300>; @@ -567,8 +574,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 13 0 - &pioC 14 0 + gpios = <&pioC 13 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -577,15 +584,15 @@ usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; - interrupts = <20 4 2>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 23 0 /* sda */ - &pioA 24 0 /* scl */ + gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ + &pioA 24 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 94b58ab2cc08..d9cf51a01b60 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -6,7 +6,10 @@ * Licensed under GPLv2 only. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9263 family SoC"; @@ -72,13 +75,13 @@ pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; - interrupts = <19 4 0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; }; rstc@fffffd00 { @@ -110,221 +113,221 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <2 30 0x1 0x0 /* PC30 periph A */ - 2 31 0x1 0x1>; /* PC31 periph with pullup */ + <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */ + AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <0 26 0x1 0x1 /* PA26 periph A with pullup */ - 0 27 0x1 0x0>; /* PA27 periph A */ + <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <0 28 0x1 0x0>; /* PA28 periph A */ + <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <0 29 0x1 0x0>; /* PA29 periph A */ + <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <3 0 0x1 0x1 /* PD0 periph A with pullup */ - 3 1 0x1 0x0>; /* PD1 periph A */ + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <3 7 0x2 0x0>; /* PD7 periph B */ + <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <3 8 0x2 0x0>; /* PD8 periph B */ + <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <3 2 0x1 0x1 /* PD2 periph A with pullup */ - 3 3 0x1 0x0>; /* PD3 periph A */ + <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <3 5 0x2 0x0>; /* PD5 periph B */ + <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <4 6 0x2 0x0>; /* PD6 periph B */ + <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/ - 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */ + <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/ + AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <2 25 0x2 0x0 /* PC25 periph B */ - 4 21 0x1 0x0 /* PE21 periph A */ - 4 23 0x1 0x0 /* PE23 periph A */ - 4 24 0x1 0x0 /* PE24 periph A */ - 4 25 0x1 0x0 /* PE25 periph A */ - 4 26 0x1 0x0 /* PE26 periph A */ - 4 27 0x1 0x0 /* PE27 periph A */ - 4 28 0x1 0x0 /* PE28 periph A */ - 4 29 0x1 0x0 /* PE29 periph A */ - 4 30 0x1 0x0>; /* PE30 periph A */ + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ + AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ + AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ + AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ + AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ + AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ + AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ + AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ + AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ + AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <2 20 0x2 0x0 /* PC20 periph B */ - 2 21 0x2 0x0 /* PC21 periph B */ - 2 22 0x2 0x0 /* PC22 periph B */ - 2 23 0x2 0x0 /* PC23 periph B */ - 2 24 0x2 0x0 /* PC24 periph B */ - 2 25 0x2 0x0 /* PC25 periph B */ - 2 27 0x2 0x0 /* PC27 periph B */ - 4 22 0x2 0x0>; /* PE22 periph B */ + <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */ + AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */ + AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */ }; }; mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = - <0 12 0x1 0x0>; /* PA12 periph A */ + <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */ }; pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { atmel,pins = - <0 1 0x1 0x1 /* PA1 periph A with pullup */ - 0 0 0x1 0x1>; /* PA0 periph A with pullup */ + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 3 0x1 0x1 /* PA3 periph A with pullup */ - 0 4 0x1 0x1 /* PA4 periph A with pullup */ - 0 5 0x1 0x1>; /* PA5 periph A with pullup */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ }; pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { atmel,pins = - <0 16 0x1 0x1 /* PA16 periph A with pullup */ - 0 17 0x1 0x1>; /* PA17 periph A with pullup */ + <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */ }; pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { atmel,pins = - <0 18 0x1 0x1 /* PA18 periph A with pullup */ - 0 19 0x1 0x1 /* PA19 periph A with pullup */ - 0 20 0x1 0x1>; /* PA20 periph A with pullup */ + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_clk: mmc1_clk-0 { atmel,pins = - <0 6 0x1 0x0>; /* PA6 periph A */ + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ }; pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 { atmel,pins = - <0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 8 0x1 0x1>; /* PA8 periph A with pullup */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = - <0 9 0x1 0x1 /* PA9 periph A with pullup */ - 0 10 0x1 0x1 /* PA10 periph A with pullup */ - 0 11 0x1 0x1>; /* PA11 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ }; pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 { atmel,pins = - <0 21 0x1 0x1 /* PA21 periph A with pullup */ - 0 22 0x1 0x1>; /* PA22 periph A with pullup */ + <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */ }; pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 { atmel,pins = - <0 23 0x1 0x1 /* PA23 periph A with pullup */ - 0 24 0x1 0x1 /* PA24 periph A with pullup */ - 0 25 0x1 0x1>; /* PA25 periph A with pullup */ + <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */ + AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <1 0 0x2 0x0 /* PB0 periph B */ - 1 1 0x2 0x0 /* PB1 periph B */ - 1 2 0x2 0x0>; /* PB2 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */ + AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */ + AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <1 3 0x2 0x0 /* PB3 periph B */ - 1 4 0x2 0x0 /* PB4 periph B */ - 1 5 0x2 0x0>; /* PB5 periph B */ + <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */ + AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = - <1 6 0x1 0x0 /* PB6 periph A */ - 1 7 0x1 0x0 /* PB7 periph A */ - 1 8 0x1 0x0>; /* PB8 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = - <1 9 0x1 0x0 /* PB9 periph A */ - 1 10 0x1 0x0 /* PB10 periph A */ - 1 11 0x1 0x0>; /* PB11 periph A */ + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 0 0x2 0x0 /* PA0 periph B SPI0_MISO pin */ - 0 1 0x2 0x0 /* PA1 periph B SPI0_MOSI pin */ - 0 2 0x2 0x0>; /* PA2 periph B SPI0_SPCK pin */ + <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */ + AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */ + AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <1 12 0x1 0x0 /* PB12 periph A SPI1_MISO pin */ - 1 13 0x1 0x0 /* PB13 periph A SPI1_MOSI pin */ - 1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */ }; }; pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -334,7 +337,7 @@ pioB: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -344,7 +347,7 @@ pioC: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -354,7 +357,7 @@ pioD: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -364,7 +367,7 @@ pioE: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -375,7 +378,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -384,7 +387,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -395,7 +398,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -406,7 +409,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; - interrupts = <9 4 5>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -417,7 +420,7 @@ ssc0: ssc@fff98000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfff98000 0x4000>; - interrupts = <16 4 5>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -426,7 +429,7 @@ ssc1: ssc@fff9c000 { compatible = "atmel,at91rm9200-ssc"; reg = <0xfff9c000 0x4000>; - interrupts = <17 4 5>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; @@ -435,7 +438,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffbc000 0x100>; - interrupts = <21 4 3>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; status = "disabled"; @@ -444,14 +447,14 @@ usb1: gadget@fff78000 { compatible = "atmel,at91rm9200-udc"; reg = <0xfff78000 0x4000>; - interrupts = <24 4 2>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; i2c0: i2c@fff88000 { compatible = "atmel,at91sam9263-i2c"; reg = <0xfff88000 0x100>; - interrupts = <13 4 6>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -460,7 +463,7 @@ mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; - interrupts = <10 4 0>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -469,7 +472,7 @@ mmc1: mmc@fff84000 { compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; - interrupts = <11 4 0>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -486,7 +489,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffa4000 0x200>; - interrupts = <14 4 3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -497,7 +500,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xfffa8000 0x200>; - interrupts = <15 4 3>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -515,8 +518,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioA 22 0 - &pioD 15 0 + gpios = <&pioA 22 GPIO_ACTIVE_HIGH + &pioD 15 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -525,15 +528,15 @@ usb0: ohci@00a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; - interrupts = <29 4 2>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioB 4 0 /* sda */ - &pioB 5 0 /* scl */ + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 3b82d91e7fcc..eff1afb81304 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91sam9263.dtsi" +#include "at91sam9263.dtsi" / { model = "Atmel at91sam9263ek"; @@ -51,7 +51,7 @@ }; usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioA 25 0>; + atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -65,8 +65,8 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioE 18 0>; - wp-gpios = <&pioE 19 0>; + cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; }; }; @@ -74,8 +74,8 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <5 18 0x0 0x5 /* PE18 gpio CD pin pull up and deglitch */ - 5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */ + <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PE18 gpio CD pin pull up and deglitch */ + AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PE19 gpio WP pin pull up */ }; }; }; @@ -141,8 +141,8 @@ usb0: ohci@00a00000 { num-ports = <2>; status = "okay"; - atmel,vbus-gpio = <&pioA 24 0 - &pioA 21 0 + atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH + &pioA 21 GPIO_ACTIVE_HIGH >; }; }; @@ -152,13 +152,13 @@ d3 { label = "d3"; - gpios = <&pioB 7 0>; + gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; d2 { label = "d2"; - gpios = <&pioC 29 1>; + gpios = <&pioC 29 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; }; @@ -168,14 +168,14 @@ left_click { label = "left_click"; - gpios = <&pioC 5 1>; + gpios = <&pioC 5 GPIO_ACTIVE_LOW>; linux,code = <272>; gpio-key,wakeup; }; right_click { label = "right_click"; - gpios = <&pioC 4 1>; + gpios = <&pioC 4 GPIO_ACTIVE_LOW>; linux,code = <273>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index 28467fd6bf96..cfd7044616d7 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9G15 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts index 5427b2dba87e..26b0444b0f96 100644 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ b/arch/arm/boot/dts/at91sam9g15ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g15.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9g15.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G15-EK"; diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 75ce6e760016..b8e79466014f 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { model = "Atmel AT91SAM9G20 family SoC"; diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts index e5324bf9d529..bbfd753112c9 100644 --- a/arch/arm/boot/dts/at91sam9g20ek.dts +++ b/arch/arm/boot/dts/at91sam9g20ek.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20ek_common.dtsi" +#include "at91sam9g20ek_common.dtsi" / { model = "Atmel at91sam9g20ek"; @@ -17,13 +17,13 @@ ds1 { label = "ds1"; - gpios = <&pioA 9 0>; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds5 { label = "ds5"; - gpios = <&pioA 6 1>; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts index 66467b113126..bdb799bad179 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts +++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20ek_common.dtsi" +#include "at91sam9g20ek_common.dtsi" / { model = "Atmel at91sam9g20ek 2 mmc"; @@ -23,7 +23,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioC 2 0>; + cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; }; }; @@ -31,7 +31,7 @@ mmc0_slot0 { pinctrl_board_mmc0_slot0: mmc0_slot0-board { atmel,pins = - <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */ + <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC2 gpio CD pin pull up and deglitch */ }; }; }; @@ -43,13 +43,13 @@ ds1 { label = "ds1"; - gpios = <&pioB 9 0>; + gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds5 { label = "ds5"; - gpios = <&pioB 8 1>; + gpios = <&pioB 8 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 6a92c5baef8c..c7ffc32918f9 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -5,7 +5,7 @@ * * Licensed under GPLv2. */ -/include/ "at91sam9g20.dtsi" +#include "at91sam9g20.dtsi" / { @@ -34,10 +34,17 @@ board { pinctrl_pck0_as_mck: pck0_as_mck { atmel,pins = - <2 1 0x2 0x0>; /* PC1 periph B */ + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ }; }; + + mmc0_slot1 { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */ + }; + }; }; dbgu: serial@fffff200 { @@ -65,7 +72,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -79,16 +86,7 @@ slot@1 { reg = <1>; bus-width = <4>; - cd-gpios = <&pioC 9 0>; - }; - }; - - pinctrl@fffff400 { - mmc0_slot1 { - pinctrl_board_mmc0_slot1: mmc0_slot1-board { - atmel,pins = - <2 9 0x0 0x5>; /* PC9 gpio CD pin pull up and deglitch */ - }; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; }; }; @@ -180,14 +178,14 @@ btn3 { label = "Button 3"; - gpios = <&pioA 30 1>; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; gpio-key,wakeup; }; btn4 { label = "Button 4"; - gpios = <&pioA 31 1>; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <0x104>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 5fd32df03f25..b4ec6fe53fc7 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9G25 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index a1c511fecdc1..1e4c49c584d3 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g25.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G25-EK"; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index d6fa8af50724..bebf9f55614b 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9G35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts index 6f58ab8d21f5..641a9bf89ed1 100644 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ b/arch/arm/boot/dts/at91sam9g35ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g35.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9g35.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G35-EK"; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index bf18a735c37d..f0091af6c285 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -9,7 +9,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9G45 family SoC"; @@ -83,7 +86,7 @@ pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; @@ -95,19 +98,19 @@ tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; - interrupts = <18 4 0>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@fffd4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffd4000 0x100>; - interrupts = <18 4 0>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; }; dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <21 4 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -130,221 +133,221 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <1 12 0x1 0x0 /* PB12 periph A */ - 1 13 0x1 0x0>; /* PB13 periph A */ + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <1 19 0x1 0x1 /* PB19 periph A with pullup */ - 1 18 0x1 0x0>; /* PB18 periph A */ + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <1 17 0x2 0x0>; /* PB17 periph B */ + <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <1 15 0x2 0x0>; /* PB15 periph B */ + <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */ }; }; uart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <1 4 0x1 0x1 /* PB4 periph A with pullup */ - 1 5 0x1 0x0>; /* PB5 periph A */ + <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <3 16 0x1 0x0>; /* PD16 periph A */ + <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <3 17 0x1 0x0>; /* PD17 periph A */ + <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <1 6 0x1 0x1 /* PB6 periph A with pullup */ - 1 7 0x1 0x0>; /* PB7 periph A */ + <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <2 9 0x2 0x0>; /* PC9 periph B */ + <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <2 11 0x2 0x0>; /* PC11 periph B */ + <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <1 8 0x1 0x1 /* PB9 periph A with pullup */ - 1 9 0x1 0x0>; /* PB8 periph A */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <0 23 0x2 0x0>; /* PA23 periph B */ + <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <0 24 0x2 0x0>; /* PA24 periph B */ + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/ - 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ }; }; macb { pinctrl_macb_rmii: macb_rmii-0 { atmel,pins = - <0 10 0x1 0x0 /* PA10 periph A */ - 0 11 0x1 0x0 /* PA11 periph A */ - 0 12 0x1 0x0 /* PA12 periph A */ - 0 13 0x1 0x0 /* PA13 periph A */ - 0 14 0x1 0x0 /* PA14 periph A */ - 0 15 0x1 0x0 /* PA15 periph A */ - 0 16 0x1 0x0 /* PA16 periph A */ - 0 17 0x1 0x0 /* PA17 periph A */ - 0 18 0x1 0x0 /* PA18 periph A */ - 0 19 0x1 0x0>; /* PA19 periph A */ + <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */ }; pinctrl_macb_rmii_mii: macb_rmii_mii-0 { atmel,pins = - <0 6 0x2 0x0 /* PA6 periph B */ - 0 7 0x2 0x0 /* PA7 periph B */ - 0 8 0x2 0x0 /* PA8 periph B */ - 0 9 0x2 0x0 /* PA9 periph B */ - 0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0 /* PA29 periph B */ - 0 30 0x2 0x0>; /* PA30 periph B */ + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */ + AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */ + AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */ + AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */ + AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */ + AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ }; }; mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 0 0x1 0x0 /* PA0 periph A */ - 0 1 0x1 0x1 /* PA1 periph A with pullup */ - 0 2 0x1 0x1>; /* PA2 periph A with pullup */ + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 3 0x1 0x1 /* PA3 periph A with pullup */ - 0 4 0x1 0x1 /* PA4 periph A with pullup */ - 0 5 0x1 0x1>; /* PA5 periph A with pullup */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */ }; pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { atmel,pins = - <0 6 0x1 0x1 /* PA6 periph A with pullup */ - 0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 8 0x1 0x1 /* PA8 periph A with pullup */ - 0 9 0x1 0x1>; /* PA9 periph A with pullup */ + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 31 0x1 0x0 /* PA31 periph A */ - 0 22 0x1 0x1 /* PA22 periph A with pullup */ - 0 23 0x1 0x1>; /* PA23 periph A with pullup */ + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = - <0 24 0x1 0x1 /* PA24 periph A with pullup */ - 0 25 0x1 0x1 /* PA25 periph A with pullup */ - 0 26 0x1 0x1>; /* PA26 periph A with pullup */ + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */ }; pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 { atmel,pins = - <0 27 0x1 0x1 /* PA27 periph A with pullup */ - 0 28 0x1 0x1 /* PA28 periph A with pullup */ - 0 29 0x1 0x1 /* PA29 periph A with pullup */ - 0 20 0x1 0x1>; /* PA30 periph A with pullup */ + <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <3 0 0x1 0x0 /* PD0 periph A */ - 3 1 0x1 0x0 /* PD1 periph A */ - 3 2 0x1 0x0>; /* PD2 periph A */ + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */ + AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <3 3 0x1 0x0 /* PD3 periph A */ - 3 4 0x1 0x0 /* PD4 periph A */ - 3 5 0x1 0x0>; /* PD5 periph A */ + <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */ + AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */ + AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx-0 { atmel,pins = - <3 10 0x1 0x0 /* PD10 periph A */ - 3 11 0x1 0x0 /* PD11 periph A */ - 3 12 0x1 0x0>; /* PD12 periph A */ + <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */ }; pinctrl_ssc1_rx: ssc1_rx-0 { atmel,pins = - <3 13 0x1 0x0 /* PD13 periph A */ - 3 14 0x1 0x0 /* PD14 periph A */ - 3 15 0x1 0x0>; /* PD15 periph A */ + <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */ + AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */ + AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */ - 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */ - 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */ - 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */ - 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */ + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */ }; }; pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -354,7 +357,7 @@ pioB: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -364,7 +367,7 @@ pioC: gpio@fffff600 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <4 4 1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -374,7 +377,7 @@ pioD: gpio@fffff800 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <5 4 1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -384,7 +387,7 @@ pioE: gpio@fffffa00 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <5 4 1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -395,7 +398,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -404,7 +407,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -415,7 +418,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -426,7 +429,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; - interrupts = <9 4 5>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -437,7 +440,7 @@ usart3: serial@fff98000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff98000 0x200>; - interrupts = <10 4 5>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; pinctrl-names = "default"; @@ -448,7 +451,7 @@ macb0: ethernet@fffbc000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xfffbc000 0x100>; - interrupts = <25 4 3>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; status = "disabled"; @@ -457,7 +460,7 @@ i2c0: i2c@fff84000 { compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff84000 0x100>; - interrupts = <12 4 6>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -466,7 +469,7 @@ i2c1: i2c@fff88000 { compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff88000 0x100>; - interrupts = <13 4 6>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -475,7 +478,7 @@ ssc0: ssc@fff9c000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xfff9c000 0x4000>; - interrupts = <16 4 5>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -484,7 +487,7 @@ ssc1: ssc@fffa0000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xfffa0000 0x4000>; - interrupts = <17 4 5>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; @@ -493,7 +496,7 @@ adc0: adc@fffb0000 { compatible = "atmel,at91sam9260-adc"; reg = <0xfffb0000 0x100>; - interrupts = <20 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; @@ -533,7 +536,7 @@ mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; - interrupts = <11 4 0>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 0>; dma-names = "rxtx"; #address-cells = <1>; @@ -544,7 +547,7 @@ mmc1: mmc@fffd0000 { compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; - interrupts = <29 4 0>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 13>; dma-names = "rxtx"; #address-cells = <1>; @@ -592,8 +595,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioC 8 0 - &pioC 14 0 + gpios = <&pioC 8 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -602,22 +605,22 @@ usb0: ohci@00700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; usb1: ehci@00800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 20 0 /* sda */ - &pioA 21 0 /* scl */ + gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ + &pioA 21 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 51d9251b5bbe..89c50d108d44 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g45.dtsi" +#include "at91sam9g45.dtsi" / { model = "Atmel AT91SAM9M10G45-EK"; @@ -68,7 +68,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 10 0>; + cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; }; }; @@ -81,8 +81,8 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 11 0>; - wp-gpios = <&pioD 29 0>; + cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; }; }; @@ -90,15 +90,15 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */ + <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */ }; }; mmc1 { pinctrl_board_mmc1: mmc1-board { atmel,pins = - <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */ - 3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */ + <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */ + AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ }; }; }; @@ -139,8 +139,8 @@ usb0: ohci@00700000 { status = "okay"; num-ports = <2>; - atmel,vbus-gpio = <&pioD 1 1 - &pioD 3 1>; + atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW + &pioD 3 GPIO_ACTIVE_LOW>; }; usb1: ehci@00800000 { @@ -153,19 +153,19 @@ d8 { label = "d8"; - gpios = <&pioD 30 0>; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; d6 { label = "d6"; - gpios = <&pioD 0 1>; + gpios = <&pioD 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; d7 { label = "d7"; - gpios = <&pioD 31 1>; + gpios = <&pioD 31 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; }; @@ -175,45 +175,45 @@ left_click { label = "left_click"; - gpios = <&pioB 6 1>; + gpios = <&pioB 6 GPIO_ACTIVE_LOW>; linux,code = <272>; gpio-key,wakeup; }; right_click { label = "right_click"; - gpios = <&pioB 7 1>; + gpios = <&pioB 7 GPIO_ACTIVE_LOW>; linux,code = <273>; gpio-key,wakeup; }; left { label = "Joystick Left"; - gpios = <&pioB 14 1>; + gpios = <&pioB 14 GPIO_ACTIVE_LOW>; linux,code = <105>; }; right { label = "Joystick Right"; - gpios = <&pioB 15 1>; + gpios = <&pioB 15 GPIO_ACTIVE_LOW>; linux,code = <106>; }; up { label = "Joystick Up"; - gpios = <&pioB 16 1>; + gpios = <&pioB 16 GPIO_ACTIVE_LOW>; linux,code = <103>; }; down { label = "Joystick Down"; - gpios = <&pioB 17 1>; + gpios = <&pioB 17 GPIO_ACTIVE_LOW>; linux,code = <108>; }; enter { label = "Joystick Press"; - gpios = <&pioB 18 1>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; linux,code = <28>; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 8d25f889928e..d864f7a9d2e0 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -7,7 +7,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9N12 SoC"; @@ -78,7 +81,7 @@ pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; shdwc@fffffe10 { @@ -89,7 +92,7 @@ mmc0: mmc@f0008000 { compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; - interrupts = <12 4 0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 0>; dma-names = "rxtx"; #address-cells = <1>; @@ -100,19 +103,19 @@ tcb0: timer@f8008000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <20 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -134,159 +137,159 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <0 9 0x1 0x0 /* PA9 periph A */ - 0 10 0x1 0x1>; /* PA10 periph with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <0 1 0x1 0x1 /* PA1 periph A with pullup */ - 0 0 0x1 0x0>; /* PA0 periph A */ + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <0 2 0x1 0x0>; /* PA2 periph A */ + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <0 3 0x1 0x0>; /* PA3 periph A */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <0 6 0x1 0x1 /* PA6 periph A with pullup */ - 0 5 0x1 0x0>; /* PA5 periph A */ + <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <0 8 0x1 0x1 /* PA8 periph A with pullup */ - 0 7 0x1 0x0>; /* PA7 periph A */ + <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ }; pinctrl_usart2_rts: usart2_rts-0 { atmel,pins = - <1 0 0x2 0x0>; /* PB0 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ }; pinctrl_usart2_cts: usart2_cts-0 { atmel,pins = - <1 1 0x2 0x0>; /* PB1 periph B */ + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <2 23 0x2 0x1 /* PC23 periph B with pullup */ - 2 22 0x2 0x0>; /* PC22 periph B */ + <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ + AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <2 24 0x2 0x0>; /* PC24 periph B */ + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <2 25 0x2 0x0>; /* PC25 periph B */ + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <2 9 0x3 0x1 /* PC9 periph C with pullup */ - 2 8 0x3 0x0>; /* PC8 periph C */ + <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ + AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <2 16 0x3 0x1 /* PC17 periph C with pullup */ - 2 17 0x3 0x0>; /* PC16 periph C */ + <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ + AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/ - 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */ + <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ + AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ }; }; mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 17 0x1 0x0 /* PA17 periph A */ - 0 16 0x1 0x1 /* PA16 periph A with pullup */ - 0 15 0x1 0x1>; /* PA15 periph A with pullup */ + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 18 0x1 0x1 /* PA18 periph A with pullup */ - 0 19 0x1 0x1 /* PA19 periph A with pullup */ - 0 20 0x1 0x1>; /* PA20 periph A with pullup */ + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { atmel,pins = - <0 11 0x2 0x1 /* PA11 periph B with pullup */ - 0 12 0x2 0x1 /* PA12 periph B with pullup */ - 0 13 0x2 0x1 /* PA13 periph B with pullup */ - 0 14 0x2 0x1>; /* PA14 periph B with pullup */ + <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ + AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ + AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0>; /* PA26 periph B */ + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ - 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ - 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ + <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ - 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ - 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ }; }; pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -296,7 +299,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -306,7 +309,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -316,7 +319,7 @@ pioD: gpio@fffffa00 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -327,7 +330,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -336,7 +339,7 @@ ssc0: ssc@f0010000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -345,7 +348,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x4000>; - interrupts = <5 4 5>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -354,7 +357,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x4000>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -363,7 +366,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x4000>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -372,7 +375,7 @@ usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x4000>; - interrupts = <8 4 5>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; status = "disabled"; @@ -381,7 +384,7 @@ i2c0: i2c@f8010000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma 1 13>, <&dma 1 14>; dma-names = "tx", "rx"; @@ -393,7 +396,7 @@ i2c1: i2c@f8014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; - interrupts = <10 4 6>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma 1 15>, <&dma 1 16>; dma-names = "tx", "rx"; @@ -407,7 +410,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0000000 0x100>; - interrupts = <13 4 3>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -418,7 +421,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0004000 0x100>; - interrupts = <14 4 3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -439,8 +442,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 0 - &pioD 4 0 + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -449,15 +452,15 @@ usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 30 0 /* sda */ - &pioA 31 0 /* scl */ + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index d30e48bd1e9d..2e67cd5e47eb 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9n12.dtsi" +#include "at91sam9n12.dtsi" / { model = "Atmel AT91SAM9N12-EK"; @@ -55,7 +55,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioA 7 0>; + cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; }; }; @@ -63,7 +63,7 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <0 7 0x0 0x5>; /* PA7 gpio CD pin pull up and deglitch */ + <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */ }; }; }; @@ -95,19 +95,19 @@ d8 { label = "d8"; - gpios = <&pioB 4 1>; + gpios = <&pioB 4 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; d9 { label = "d6"; - gpios = <&pioB 5 1>; + gpios = <&pioB 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; d10 { label = "d7"; - gpios = <&pioB 6 0>; + gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -117,7 +117,7 @@ enter { label = "Enter"; - gpios = <&pioB 4 1>; + gpios = <&pioB 4 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 9ac2bc2b4f07..49e94aba938f 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9X25 SoC"; @@ -26,16 +26,16 @@ macb1 { pinctrl_macb1_rmii: macb1_rmii-0 { atmel,pins = - <2 16 0x2 0x0 /* PC16 periph B */ - 2 18 0x2 0x0 /* PC18 periph B */ - 2 19 0x2 0x0 /* PC19 periph B */ - 2 20 0x2 0x0 /* PC20 periph B */ - 2 21 0x2 0x0 /* PC21 periph B */ - 2 27 0x2 0x0 /* PC27 periph B */ - 2 28 0x2 0x0 /* PC28 periph B */ - 2 29 0x2 0x0 /* PC29 periph B */ - 2 30 0x2 0x0 /* PC30 periph B */ - 2 31 0x2 0x0>; /* PC31 periph B */ + <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ + AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ + AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ + AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ + AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ + AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ + AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts index 315250b4995e..494864836e83 100644 --- a/arch/arm/boot/dts/at91sam9x25ek.dts +++ b/arch/arm/boot/dts/at91sam9x25ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9x25.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9x25.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9X25-EK"; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index ba67d83d17ac..1a3d525a1f5d 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ -/include/ "at91sam9x5.dtsi" +#include "at91sam9x5.dtsi" / { model = "Atmel AT91SAM9X35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts index 6ad19a0d5424..343d32818ca3 100644 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ b/arch/arm/boot/dts/at91sam9x35ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9x35.dtsi" -/include/ "at91sam9x5ek.dtsi" +#include "at91sam9x35.dtsi" +#include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9X35-EK"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 1145ac330fb7..af91599488e9 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -9,7 +9,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel AT91SAM9x5 family SoC"; @@ -85,32 +88,32 @@ pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; tcb0: timer@f8008000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; - interrupts = <17 4 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; }; dma0: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; - interrupts = <20 4 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; dma1: dma-controller@ffffee00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffee00 0x200>; - interrupts = <21 4 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -124,297 +127,297 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <0 9 0x1 0x0 /* PA9 periph A */ - 0 10 0x1 0x1>; /* PA10 periph A with pullup */ + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <0 0 0x1 0x1 /* PA0 periph A with pullup */ - 0 1 0x1 0x0>; /* PA1 periph A */ + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ }; pinctrl_usart0_rts: usart0_rts-0 { atmel,pins = - <0 2 0x1 0x0>; /* PA2 periph A */ + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ }; pinctrl_usart0_cts: usart0_cts-0 { atmel,pins = - <0 3 0x1 0x0>; /* PA3 periph A */ + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ }; pinctrl_usart0_sck: usart0_sck-0 { atmel,pins = - <0 4 0x1 0x0>; /* PA4 periph A */ + <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <0 5 0x1 0x1 /* PA5 periph A with pullup */ - 0 6 0x1 0x0>; /* PA6 periph A */ + <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ }; pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <2 27 0x3 0x0>; /* PC27 periph C */ + <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <2 28 0x3 0x0>; /* PC28 periph C */ + <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ }; pinctrl_usart1_sck: usart1_sck-0 { atmel,pins = - <2 28 0x3 0x0>; /* PC29 periph C */ + <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <0 7 0x1 0x1 /* PA7 periph A with pullup */ - 0 8 0x1 0x0>; /* PA8 periph A */ + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ }; pinctrl_uart2_rts: uart2_rts-0 { atmel,pins = - <1 0 0x2 0x0>; /* PB0 periph B */ + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ }; pinctrl_uart2_cts: uart2_cts-0 { atmel,pins = - <1 1 0x2 0x0>; /* PB1 periph B */ + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ }; pinctrl_usart2_sck: usart2_sck-0 { atmel,pins = - <1 2 0x2 0x0>; /* PB2 periph B */ + <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <2 22 0x2 0x1 /* PC22 periph B with pullup */ - 2 23 0x2 0x0>; /* PC23 periph B */ + <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <2 24 0x2 0x0>; /* PC24 periph B */ + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <2 25 0x2 0x0>; /* PC25 periph B */ + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ }; pinctrl_usart3_sck: usart3_sck-0 { atmel,pins = - <2 26 0x2 0x0>; /* PC26 periph B */ + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <2 8 0x3 0x0 /* PC8 periph C */ - 2 9 0x3 0x1>; /* PC9 periph C with pullup */ + <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ + AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <2 16 0x3 0x0 /* PC16 periph C */ - 2 17 0x3 0x1>; /* PC17 periph C with pullup */ + <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ + AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ }; }; nand { pinctrl_nand: nand-0 { atmel,pins = - <3 0 0x1 0x0 /* PD0 periph A Read Enable */ - 3 1 0x1 0x0 /* PD1 periph A Write Enable */ - 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ - 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ - 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ - 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ - 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ - 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ - 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ - 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ - 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ - 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ - 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ - 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ + AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ + AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ + AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ + AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ + AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ + AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ + AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ + AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ + AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ }; pinctrl_nand_16bits: nand_16bits-0 { atmel,pins = - <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ - 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ - 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ - 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ - 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ - 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ - 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ - 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ + <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ + AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ + AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ + AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ + AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ + AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ + AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ + AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ }; }; macb0 { pinctrl_macb0_rmii: macb0_rmii-0 { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A */ - 1 1 0x1 0x0 /* PB1 periph A */ - 1 2 0x1 0x0 /* PB2 periph A */ - 1 3 0x1 0x0 /* PB3 periph A */ - 1 4 0x1 0x0 /* PB4 periph A */ - 1 5 0x1 0x0 /* PB5 periph A */ - 1 6 0x1 0x0 /* PB6 periph A */ - 1 7 0x1 0x0 /* PB7 periph A */ - 1 9 0x1 0x0 /* PB9 periph A */ - 1 10 0x1 0x0>; /* PB10 periph A */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ }; pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { atmel,pins = - <1 8 0x1 0x0 /* PB8 periph A */ - 1 11 0x1 0x0 /* PB11 periph A */ - 1 12 0x1 0x0 /* PB12 periph A */ - 1 13 0x1 0x0 /* PB13 periph A */ - 1 14 0x1 0x0 /* PB14 periph A */ - 1 15 0x1 0x0 /* PB15 periph A */ - 1 16 0x1 0x0 /* PB16 periph A */ - 1 17 0x1 0x0>; /* PB17 periph A */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ }; }; mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 17 0x1 0x0 /* PA17 periph A */ - 0 16 0x1 0x1 /* PA16 periph A with pullup */ - 0 15 0x1 0x1>; /* PA15 periph A with pullup */ + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ }; pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { atmel,pins = - <0 18 0x1 0x1 /* PA18 periph A with pullup */ - 0 19 0x1 0x1 /* PA19 periph A with pullup */ - 0 20 0x1 0x1>; /* PA20 periph A with pullup */ + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ }; }; mmc1 { pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { atmel,pins = - <0 13 0x2 0x0 /* PA13 periph B */ - 0 12 0x2 0x1 /* PA12 periph B with pullup */ - 0 11 0x2 0x1>; /* PA11 periph B with pullup */ + <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ }; pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { atmel,pins = - <0 2 0x2 0x1 /* PA2 periph B with pullup */ - 0 3 0x2 0x1 /* PA3 periph B with pullup */ - 0 4 0x2 0x1>; /* PA4 periph B with pullup */ + <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = - <0 24 0x2 0x0 /* PA24 periph B */ - 0 25 0x2 0x0 /* PA25 periph B */ - 0 26 0x2 0x0>; /* PA26 periph B */ + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ }; pinctrl_ssc0_rx: ssc0_rx-0 { atmel,pins = - <0 27 0x2 0x0 /* PA27 periph B */ - 0 28 0x2 0x0 /* PA28 periph B */ - 0 29 0x2 0x0>; /* PA29 periph B */ + <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ }; }; spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ - 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ - 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ + <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ - 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ - 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ }; }; i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = - <0 30 0x1 0x0 /* PA30 periph A I2C0 data */ - 0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ }; }; i2c1 { pinctrl_i2c1: i2c1-0 { atmel,pins = - <2 0 0x3 0x0 /* PC0 periph C I2C1 data */ - 2 1 0x3 0x0>; /* PC1 periph C I2C1 clock */ + <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ + AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ }; }; i2c2 { pinctrl_i2c2: i2c2-0 { atmel,pins = - <1 4 0x2 0x0 /* PB4 periph B I2C2 data */ - 1 5 0x2 0x0>; /* PB5 periph B I2C2 clock */ + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ }; }; i2c_gpio0 { pinctrl_i2c_gpio0: i2c_gpio0-0 { atmel,pins = - <0 30 0x0 0x2 /* PA30 gpio multidrive I2C0 data */ - 0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */ + <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ + AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ }; }; i2c_gpio1 { pinctrl_i2c_gpio1: i2c_gpio1-0 { atmel,pins = - <2 0 0x0 0x2 /* PC0 gpio multidrive I2C1 data */ - 2 1 0x0 0x2>; /* PC1 gpio multidrive I2C1 clock */ + <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ + AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ }; }; i2c_gpio2 { pinctrl_i2c_gpio2: i2c_gpio2-0 { atmel,pins = - <1 4 0x0 0x2 /* PB4 gpio multidrive I2C2 data */ - 1 5 0x0 0x2>; /* PB5 gpio multidrive I2C2 clock */ + <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ + AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ }; }; pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -424,7 +427,7 @@ pioB: gpio@fffff600 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff600 0x200>; - interrupts = <2 4 1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; #gpio-lines = <19>; @@ -435,7 +438,7 @@ pioC: gpio@fffff800 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff800 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; interrupt-controller; @@ -445,7 +448,7 @@ pioD: gpio@fffffa00 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffffa00 0x200>; - interrupts = <3 4 1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; #gpio-cells = <2>; gpio-controller; #gpio-lines = <22>; @@ -457,7 +460,7 @@ ssc0: ssc@f0010000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -466,7 +469,7 @@ mmc0: mmc@f0008000 { compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; - interrupts = <12 4 0>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 1 0>; dma-names = "rxtx"; #address-cells = <1>; @@ -477,7 +480,7 @@ mmc1: mmc@f000c000 { compatible = "atmel,hsmci"; reg = <0xf000c000 0x600>; - interrupts = <26 4 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 1 0>; dma-names = "rxtx"; #address-cells = <1>; @@ -488,7 +491,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -497,7 +500,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x200>; - interrupts = <5 4 5>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -506,7 +509,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x200>; - interrupts = <6 4 5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -515,7 +518,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x200>; - interrupts = <7 4 5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -524,7 +527,7 @@ macb0: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; - interrupts = <24 4 3>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; status = "disabled"; @@ -533,14 +536,14 @@ macb1: ethernet@f8030000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf8030000 0x100>; - interrupts = <27 4 3>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; status = "disabled"; }; i2c0: i2c@f8010000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma0 1 7>, <&dma0 1 8>; dma-names = "tx", "rx"; @@ -554,7 +557,7 @@ i2c1: i2c@f8014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; - interrupts = <10 4 6>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma1 1 5>, <&dma1 1 6>; dma-names = "tx", "rx"; @@ -568,7 +571,7 @@ i2c2: i2c@f8018000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8018000 0x100>; - interrupts = <11 4 6>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma0 1 9>, <&dma0 1 10>; dma-names = "tx", "rx"; @@ -582,7 +585,7 @@ adc0: adc@f804c000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf804c000 0x100>; - interrupts = <19 4 0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; atmel,adc-use-external; atmel,adc-channels-used = <0xffff>; atmel,adc-vref = <3300>; @@ -625,7 +628,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0000000 0x100>; - interrupts = <13 4 3>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -636,7 +639,7 @@ #size-cells = <0>; compatible = "atmel,at91rm9200-spi"; reg = <0xf0004000 0x100>; - interrupts = <14 4 3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -645,7 +648,7 @@ rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x40>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; }; @@ -664,8 +667,8 @@ atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - gpios = <&pioD 5 0 - &pioD 4 0 + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH 0 >; status = "disabled"; @@ -674,22 +677,22 @@ usb0: ohci@00600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; usb1: ehci@00700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; - interrupts = <22 4 2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; }; i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 30 0 /* sda */ - &pioA 31 0 /* scl */ + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; @@ -703,8 +706,8 @@ i2c@1 { compatible = "i2c-gpio"; - gpios = <&pioC 0 0 /* sda */ - &pioC 1 0 /* scl */ + gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ + &pioC 1 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; @@ -718,8 +721,8 @@ i2c@2 { compatible = "i2c-gpio"; - gpios = <&pioB 4 0 /* sda */ - &pioB 5 0 /* scl */ + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 347a74a857f6..4a5ee5cc115a 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -28,7 +28,7 @@ pinctrl@fffff400 { 1wire_cm { pinctrl_1wire_cm: 1wire_cm-0 { - atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */ + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */ }; }; }; @@ -75,19 +75,19 @@ pb18 { label = "pb18"; - gpios = <&pioB 18 1>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; pd21 { label = "pd21"; - gpios = <&pioD 21 0>; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; }; }; 1wire_cm { compatible = "w1-gpio"; - gpios = <&pioB 18 0>; + gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; linux,open-drain; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_1wire_cm>; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 1fa48d2bfd80..19c8ebb303f4 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -6,7 +6,7 @@ * * Licensed under GPLv2 or later. */ -/include/ "at91sam9x5cm.dtsi" +#include "at91sam9x5cm.dtsi" / { model = "Atmel AT91SAM9X5-EK"; @@ -27,7 +27,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 15 0>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; }; }; @@ -40,7 +40,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 14 0>; + cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; }; }; @@ -60,14 +60,14 @@ mmc0 { pinctrl_board_mmc0: mmc0-board { atmel,pins = - <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */ + <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ }; }; mmc1 { pinctrl_board_mmc1: mmc1-board { atmel,pins = - <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */ + <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */ }; }; }; @@ -86,8 +86,8 @@ usb0: ohci@00600000 { status = "okay"; num-ports = <2>; - atmel,vbus-gpio = <&pioD 19 1 - &pioD 20 1 + atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW >; }; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 1ea9d34460a4..143b6d25bc80 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { model = "Ethernut 5"; @@ -40,7 +40,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -52,7 +52,7 @@ status = "okay"; gpios = <0 - &pioC 14 0 + &pioC 14 GPIO_ACTIVE_HIGH 0 >; diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts index 96e50f569433..4d829685fdfb 100644 --- a/arch/arm/boot/dts/evk-pro3.dts +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -9,7 +9,7 @@ /dts-v1/; -/include/ "ge863-pro3.dtsi" +#include "ge863-pro3.dtsi" / { model = "Telit EVK-PRO3 for Telit GE863-PRO3"; @@ -31,7 +31,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -50,4 +50,4 @@ status = "okay"; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi index 17136fc7a516..230099bb31c8 100644 --- a/arch/arm/boot/dts/ge863-pro3.dtsi +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ -/include/ "at91sam9260.dtsi" +#include "at91sam9260.dtsi" / { clocks { diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts index b4dc3ed9a3ec..02df1914a47c 100644 --- a/arch/arm/boot/dts/kizbox.dts +++ b/arch/arm/boot/dts/kizbox.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20.dtsi" +#include "at91sam9g20.dtsi" / { @@ -94,26 +94,26 @@ led1g { label = "led1:green"; - gpios = <&pioB 0 1>; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; led1r { label = "led1:red"; - gpios = <&pioB 1 1>; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; led2g { label = "led2:green"; - gpios = <&pioB 2 1>; + gpios = <&pioB 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; }; led2r { label = "led2:red"; - gpios = <&pioB 3 1>; + gpios = <&pioB 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; }; @@ -125,16 +125,16 @@ reset { label = "reset"; - gpios = <&pioB 30 1>; + gpios = <&pioB 30 GPIO_ACTIVE_LOW>; linux,code = <0x100>; gpio-key,wakeup; }; mode { label = "mode"; - gpios = <&pioB 31 1>; + gpios = <&pioB 31 GPIO_ACTIVE_LOW>; linux,code = <0x101>; gpio-key,wakeup; }; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index 317300875f34..ccf9ea242f72 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91rm9200.dtsi" +#include "at91rm9200.dtsi" / { model = "Phontech MPA 1600"; @@ -62,7 +62,7 @@ monitor_mute { label = "Monitor mute"; - gpios = <&pioC 1 1>; + gpios = <&pioC 1 GPIO_ACTIVE_LOW>; linux,code = <113>; }; }; diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 144ae43453c4..6076d016b479 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -105,7 +105,6 @@ nand-bus-width = <8>; ti,nand-ecc-opt = "sw"; - gpmc,device-nand; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <36>; gpmc,cs-wr-off-ns = <36>; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 387fedb58988..33ffabe9c4c8 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g45.dtsi" +#include "at91sam9g45.dtsi" / { model = "Ronetix pm9g45"; @@ -42,15 +42,15 @@ board { pinctrl_board_nand: nand0-board { atmel,pins = - <3 3 0x0 0x1 /* PD3 gpio RDY pin pull_up*/ - 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */ + <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD3 gpio RDY pin pull_up*/ + AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ }; }; mmc { pinctrl_board_mmc: mmc0-board { atmel,pins = - <3 6 0x0 0x5>; /* PD6 gpio CD pin pull_up and deglitch */ + <AT91_PIOD 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD6 gpio CD pin pull_up and deglitch */ }; }; }; @@ -64,7 +64,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 6 0>; + cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>; }; }; @@ -81,8 +81,8 @@ nand-on-flash-bbt; pinctrl-0 = <&pinctrl_board_nand>; - gpios = <&pioD 3 0 - &pioC 14 0 + gpios = <&pioD 3 GPIO_ACTIVE_HIGH + &pioC 14 GPIO_ACTIVE_HIGH 0 >; @@ -134,13 +134,13 @@ led0 { label = "led0"; - gpios = <&pioD 0 1>; + gpios = <&pioD 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "nand-disk"; }; led1 { label = "led1"; - gpios = <&pioD 31 0>; + gpios = <&pioD 31 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -152,13 +152,13 @@ right { label = "SW4"; - gpios = <&pioE 7 1>; + gpios = <&pioE 7 GPIO_ACTIVE_LOW>; linux,code = <106>; }; up { label = "SW3"; - gpios = <&pioE 8 1>; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; linux,code = <103>; }; }; diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi new file mode 100644 index 000000000000..527e3193817f --- /dev/null +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -0,0 +1,173 @@ +/* + * Samsung S3C2416 pinctrl settings + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&pinctrl_0 { + /* + * Pin banks + */ + + gpa: gpa { + gpio-controller; + #gpio-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc: gpc { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd: gpd { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe: gpe { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf: gpf { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg: gpg { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph: gph { + gpio-controller; + #gpio-cells = <2>; + }; + + gpj: gpj { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk: gpk { + gpio-controller; + #gpio-cells = <2>; + }; + + gpl: gpl { + gpio-controller; + #gpio-cells = <2>; + }; + + gpm: gpm { + gpio-controller; + #gpio-cells = <2>; + }; + + /* + * Pin groups + */ + + uart0_data: uart0-data { + samsung,pins = "gph-0", "gph-1"; + samsung,pin-function = <2>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gph-8", "gph-9"; + samsung,pin-function = <2>; + }; + + uart1_data: uart1-data { + samsung,pins = "gph-2", "gph-3"; + samsung,pin-function = <2>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gph-10", "gph-11"; + samsung,pin-function = <2>; + }; + + uart2_data: uart2-data { + samsung,pins = "gph-4", "gph-5"; + samsung,pin-function = <2>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gph-6", "gph-7"; + samsung,pin-function = <2>; + }; + + uart3_data: uart3-data { + samsung,pins = "gph-6", "gph-7"; + samsung,pin-function = <2>; + }; + + extuart_clk: extuart-clk { + samsung,pins = "gph-12"; + samsung,pin-function = <2>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpe-14", "gpe-15"; + samsung,pin-function = <2>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpe-11", "gpe-12", "gpe-13"; + samsung,pin-function = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpe-5"; + samsung,pin-function = <2>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpe-6"; + samsung,pin-function = <2>; + }; + + sd0_bus1: sd0-bus1 { + samsung,pins = "gpe-7"; + samsung,pin-function = <2>; + }; + + sd0_bus4: sd0-bus4 { + samsung,pins = "gpe-8", "gpe-9", "gpe-10"; + samsung,pin-function = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpl-8"; + samsung,pin-function = <2>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpl-9"; + samsung,pin-function = <2>; + }; + + sd1_bus1: sd1-bus1 { + samsung,pins = "gpl-0"; + samsung,pin-function = <2>; + }; + + sd1_bus4: sd1-bus4 { + samsung,pins = "gpl-1", "gpl-2", "gpl-3"; + samsung,pin-function = <2>; + }; +}; diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts new file mode 100644 index 000000000000..ad1dd09c10eb --- /dev/null +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -0,0 +1,72 @@ +/* + * SAMSUNG SMDK2416 board device tree source + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "s3c2416.dtsi" + +/ { + model = "SMDK2416"; + compatible = "samsung,s3c2416"; + + memory { + reg = <0x30000000 0x4000000>; + }; + + serial@50000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_data>, <&uart0_fctl>; + }; + + serial@50004000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_data>, <&uart1_fctl>; + }; + + serial@50008000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + }; + + serial@5000C000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_data>; + }; + + watchdog@53000000 { + status = "okay"; + }; + + rtc@57000000 { + status = "okay"; + }; + + sdhci@4AC00000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, + <&sd0_bus1>, <&sd0_bus4>; + bus-width = <4>; + cd-gpios = <&gpf 1 0>; + cd-inverted; + status = "okay"; + }; + + sdhci@4A800000 { + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, + <&sd1_bus1>, <&sd1_bus4>; + bus-width = <4>; + broken-cd; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi new file mode 100644 index 000000000000..6809324934a3 --- /dev/null +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -0,0 +1,79 @@ +/* + * Samsung's S3C2416 SoC device tree source + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "s3c24xx.dtsi" +/include/ "s3c2416-pinctrl.dtsi" + +/ { + model = "Samsung S3C2416 SoC"; + compatible = "samsung,s3c2416"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ejs"; + }; + }; + + interrupt-controller@4a000000 { + compatible = "samsung,s3c2416-irq"; + }; + + pinctrl@56000000 { + compatible = "samsung,s3c2416-pinctrl"; + }; + + serial@50000000 { + compatible = "samsung,s3c2440-uart"; + }; + + serial@50004000 { + compatible = "samsung,s3c2440-uart"; + }; + + serial@50008000 { + compatible = "samsung,s3c2440-uart"; + }; + + serial@5000C000 { + compatible = "samsung,s3c2440-uart"; + reg = <0x5000C000 0x4000>; + interrupts = <1 18 24 4>, <1 18 25 4>; + status = "disabled"; + }; + + sdhci@4AC00000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x4AC00000 0x100>; + interrupts = <0 0 21 3>; + status = "disabled"; + }; + + sdhci@4A800000 { + compatible = "samsung,s3c6410-sdhci"; + reg = <0x4A800000 0x100>; + interrupts = <0 0 20 3>; + status = "disabled"; + }; + + watchdog@53000000 { + interrupts = <1 9 27 3>; + }; + + rtc@57000000 { + compatible = "samsung,s3c2416-rtc"; + }; + + i2c@54000000 { + compatible = "samsung,s3c2440-i2c"; + }; +}; diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi new file mode 100644 index 000000000000..cab46ff5fb4d --- /dev/null +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -0,0 +1,92 @@ +/* + * Samsung's S3C24XX family device tree source + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,s3c24xx"; + interrupt-parent = <&intc>; + + aliases { + pinctrl0 = &pinctrl_0; + }; + + intc:interrupt-controller@4a000000 { + compatible = "samsung,s3c2410-irq"; + reg = <0x4a000000 0x100>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + pinctrl_0: pinctrl@56000000 { + reg = <0x56000000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,s3c2410-wakeup-eint"; + interrupts = <0 0 0 3>, + <0 0 1 3>, + <0 0 2 3>, + <0 0 3 3>, + <0 0 4 4>, + <0 0 5 4>; + }; + }; + + timer@51000000 { + compatible = "samsung,s3c2410-pwm"; + reg = <0x51000000 0x1000>; + interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; + #pwm-cells = <4>; + }; + + serial@50000000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50000000 0x4000>; + interrupts = <1 28 0 4>, <1 28 1 4>; + status = "disabled"; + }; + + serial@50004000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50004000 0x4000>; + interrupts = <1 23 3 4>, <1 23 4 4>; + status = "disabled"; + }; + + serial@50008000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50008000 0x4000>; + interrupts = <1 15 6 4>, <1 15 7 4>; + status = "disabled"; + }; + + watchdog@53000000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x53000000 0x100>; + interrupts = <0 0 9 3>; + status = "disabled"; + }; + + rtc@57000000 { + compatible = "samsung,s3c2410-rtc"; + reg = <0x57000000 0x100>; + interrupts = <0 0 30 3>, <0 0 8 3>; + status = "disabled"; + }; + + i2c@54000000 { + compatible = "samsung,s3c2410-i2c"; + reg = <0x54000000 0x100>; + interrupts = <0 0 27 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5000e0d42849..d5922935523f 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -8,7 +8,10 @@ * Licensed under GPLv2 or later. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Atmel SAMA5D3 family SoC"; @@ -59,7 +62,7 @@ mmc0: mmc@f0000000 { compatible = "atmel,hsmci"; reg = <0xf0000000 0x600>; - interrupts = <21 4 0>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 2 0>; dma-names = "rxtx"; pinctrl-names = "default"; @@ -74,7 +77,7 @@ #size-cells = <0>; compatible = "atmel,at91sam9x5-spi"; reg = <0xf0004000 0x100>; - interrupts = <24 4 3>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; status = "disabled"; @@ -83,7 +86,7 @@ ssc0: ssc@f0008000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0008000 0x4000>; - interrupts = <38 4 4>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; @@ -92,7 +95,7 @@ can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; - interrupts = <40 4 3>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; status = "disabled"; @@ -101,13 +104,13 @@ tcb0: timer@f0010000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; - interrupts = <26 4 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; }; i2c0: i2c@f0014000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf0014000 0x4000>; - interrupts = <18 4 6>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma0 2 7>, <&dma0 2 8>; dma-names = "tx", "rx"; @@ -121,7 +124,7 @@ i2c1: i2c@f0018000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf0018000 0x4000>; - interrupts = <19 4 6>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma0 2 9>, <&dma0 2 10>; dma-names = "tx", "rx"; @@ -135,7 +138,7 @@ usart0: serial@f001c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -144,7 +147,7 @@ usart1: serial@f0020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; - interrupts = <13 4 5>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -153,7 +156,7 @@ macb0: ethernet@f0028000 { compatible = "cdns,pc302-gem", "cdns,gem"; reg = <0xf0028000 0x100>; - interrupts = <34 4 3>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; status = "disabled"; @@ -162,14 +165,14 @@ isi: isi@f0034000 { compatible = "atmel,at91sam9g45-isi"; reg = <0xf0034000 0x4000>; - interrupts = <37 4 5>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; status = "disabled"; }; mmc1: mmc@f8000000 { compatible = "atmel,hsmci"; reg = <0xf8000000 0x600>; - interrupts = <22 4 0>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 2 0>; dma-names = "rxtx"; pinctrl-names = "default"; @@ -182,7 +185,7 @@ mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; - interrupts = <23 4 0>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 2 1>; dma-names = "rxtx"; pinctrl-names = "default"; @@ -197,7 +200,7 @@ #size-cells = <0>; compatible = "atmel,at91sam9x5-spi"; reg = <0xf8008000 0x100>; - interrupts = <25 4 3>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; @@ -206,7 +209,7 @@ ssc1: ssc@f800c000 { compatible = "atmel,at91sam9g45-ssc"; reg = <0xf800c000 0x4000>; - interrupts = <39 4 4>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; @@ -215,7 +218,7 @@ can1: can@f8010000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf8010000 0x300>; - interrupts = <41 4 3>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; }; @@ -223,13 +226,13 @@ tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8014000 0x100>; - interrupts = <27 4 0>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; }; adc0: adc@f8018000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf8018000 0x100>; - interrupts = <29 4 5>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = < &pinctrl_adc0_adtrg @@ -283,7 +286,7 @@ tsadcc: tsadcc@f8018000 { compatible = "atmel,at91sam9x5-tsadcc"; reg = <0xf8018000 0x4000>; - interrupts = <29 4 5>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; atmel,tsadcc_clock = <300000>; atmel,filtering_average = <0x03>; atmel,pendet_debounce = <0x08>; @@ -295,7 +298,7 @@ i2c2: i2c@f801c000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf801c000 0x4000>; - interrupts = <20 4 6>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; dmas = <&dma1 2 11>, <&dma1 2 12>; dma-names = "tx", "rx"; @@ -307,7 +310,7 @@ usart2: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; - interrupts = <14 4 5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -316,7 +319,7 @@ usart3: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; - interrupts = <15 4 5>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; status = "disabled"; @@ -325,7 +328,7 @@ macb1: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; - interrupts = <35 4 3>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; status = "disabled"; @@ -334,7 +337,7 @@ sha@f8034000 { compatible = "atmel,sam9g46-sha"; reg = <0xf8034000 0x100>; - interrupts = <42 4 0>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; }; aes@f8038000 { @@ -346,20 +349,20 @@ tdes@f803c000 { compatible = "atmel,sam9g46-tdes"; reg = <0xf803c000 0x100>; - interrupts = <44 4 0>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; }; dma0: dma-controller@ffffe600 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffe600 0x200>; - interrupts = <30 4 0>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; dma1: dma-controller@ffffe800 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffe800 0x200>; - interrupts = <31 4 0>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; }; @@ -371,7 +374,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; - interrupts = <2 4 7>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; status = "disabled"; @@ -403,202 +406,202 @@ adc0 { pinctrl_adc0_adtrg: adc0_adtrg { atmel,pins = - <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ + <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ }; pinctrl_adc0_ad0: adc0_ad0 { atmel,pins = - <3 20 0x1 0x0>; /* PD20 periph A AD0 */ + <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ }; pinctrl_adc0_ad1: adc0_ad1 { atmel,pins = - <3 21 0x1 0x0>; /* PD21 periph A AD1 */ + <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ }; pinctrl_adc0_ad2: adc0_ad2 { atmel,pins = - <3 22 0x1 0x0>; /* PD22 periph A AD2 */ + <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ }; pinctrl_adc0_ad3: adc0_ad3 { atmel,pins = - <3 23 0x1 0x0>; /* PD23 periph A AD3 */ + <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ }; pinctrl_adc0_ad4: adc0_ad4 { atmel,pins = - <3 24 0x1 0x0>; /* PD24 periph A AD4 */ + <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ }; pinctrl_adc0_ad5: adc0_ad5 { atmel,pins = - <3 25 0x1 0x0>; /* PD25 periph A AD5 */ + <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ }; pinctrl_adc0_ad6: adc0_ad6 { atmel,pins = - <3 26 0x1 0x0>; /* PD26 periph A AD6 */ + <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ }; pinctrl_adc0_ad7: adc0_ad7 { atmel,pins = - <3 27 0x1 0x0>; /* PD27 periph A AD7 */ + <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ }; pinctrl_adc0_ad8: adc0_ad8 { atmel,pins = - <3 28 0x1 0x0>; /* PD28 periph A AD8 */ + <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ }; pinctrl_adc0_ad9: adc0_ad9 { atmel,pins = - <3 29 0x1 0x0>; /* PD29 periph A AD9 */ + <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ }; pinctrl_adc0_ad10: adc0_ad10 { atmel,pins = - <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ + <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ }; pinctrl_adc0_ad11: adc0_ad11 { atmel,pins = - <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ + <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ }; }; can0 { pinctrl_can0_rx_tx: can0_rx_tx { atmel,pins = - <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ - 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ + AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ }; }; can1 { pinctrl_can1_rx_tx: can1_rx_tx { atmel,pins = - <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ - 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ }; }; dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - <1 30 0x1 0x0 /* PB30 periph A */ - 1 31 0x1 0x1>; /* PB31 periph A with pullup */ + <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ + AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ }; }; i2c0 { pinctrl_i2c0: i2c0-0 { atmel,pins = - <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ - 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ }; }; i2c1 { pinctrl_i2c1: i2c1-0 { atmel,pins = - <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ - 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ }; }; isi { pinctrl_isi: isi-0 { atmel,pins = - <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ - 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ - 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ - 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ - 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ - 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ - 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ - 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ - 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ - 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ - 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ - 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ - 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ + <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ + AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ + AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ + AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ + AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ + AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ + AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ + AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ + AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ + AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ + AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ + AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ + AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ }; pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { atmel,pins = - <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ + <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ }; }; lcd { pinctrl_lcd: lcd-0 { atmel,pins = - <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ - 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ - 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ - 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ - 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ - 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ - 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ - 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ - 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ - 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ - 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ - 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ - 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ - 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ - 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ - 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ - 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ - 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ - 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ - 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ - 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ - 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ - 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ - 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ - 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ - 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ - 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ - 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ - 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ - 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ + AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ + AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ + AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ + AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ + AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ + AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ }; }; macb0 { pinctrl_macb0_data_rgmii: macb0_data_rgmii { atmel,pins = - <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ - 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ - 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ - 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ - 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ - 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ - 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ - 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ }; pinctrl_macb0_data_gmii: macb0_data_gmii { atmel,pins = - <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ - 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ - 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ - 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ - 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ - 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ - 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ - 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ + <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ + AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ + AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ + AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ + AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ + AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ + AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ + AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ }; pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { atmel,pins = - <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ - 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ - 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ - 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ - 1 16 0x1 0x0 /* PB16 periph A GMDC */ - 1 17 0x1 0x0 /* PB17 periph A GMDIO */ - 1 18 0x1 0x0>; /* PB18 periph A G125CK */ + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ }; pinctrl_macb0_signal_gmii: macb0_signal_gmii { atmel,pins = - <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ - 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ - 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ - 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ - 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ - 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ - 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ - 1 16 0x1 0x0 /* PB16 periph A GMDC */ - 1 17 0x1 0x0 /* PB17 periph A GMDIO */ - 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ }; }; @@ -606,252 +609,251 @@ macb1 { pinctrl_macb1_rmii: macb1_rmii-0 { atmel,pins = - <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ - 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ - 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ - 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ - 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ - 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ - 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ - 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ - 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ - 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ }; }; mmc0 { pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { atmel,pins = - <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ - 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ - 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ + <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ + AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ }; pinctrl_mmc0_dat1_3: mmc0_dat1_3 { atmel,pins = - <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ - 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ - 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ + <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ + AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ }; pinctrl_mmc0_dat4_7: mmc0_dat4_7 { atmel,pins = - <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ - 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ - 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ - 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ + <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ + AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ + AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ + AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ }; }; mmc1 { pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { atmel,pins = - <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ - 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ - 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ + AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ }; pinctrl_mmc1_dat1_3: mmc1_dat1_3 { atmel,pins = - <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ - 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ - 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ + <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ }; }; mmc2 { pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { atmel,pins = - <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ - 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ - 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ }; pinctrl_mmc2_dat1_3: mmc2_dat1_3 { atmel,pins = - <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ - 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ - 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ }; }; nand0 { pinctrl_nand0_ale_cle: nand0_ale_cle-0 { atmel,pins = - <4 21 0x1 0x1 /* PE21 periph A with pullup */ - 4 22 0x1 0x1>; /* PE22 periph A with pullup */ + <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ + AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ }; }; - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 4 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - }; - spi0 { pinctrl_spi0: spi0-0 { atmel,pins = - <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ - 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ - 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ - 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ + <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ }; }; spi1 { pinctrl_spi1: spi1-0 { atmel,pins = - <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ - 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ - 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ - 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ + <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ }; }; ssc0 { pinctrl_ssc0_tx: ssc0_tx { atmel,pins = - <2 16 0x1 0x0 /* PC16 periph A TK0 */ - 2 17 0x1 0x0 /* PC17 periph A TF0 */ - 2 18 0x1 0x0>; /* PC18 periph A TD0 */ + <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ }; pinctrl_ssc0_rx: ssc0_rx { atmel,pins = - <2 19 0x1 0x0 /* PC19 periph A RK0 */ - 2 20 0x1 0x0 /* PC20 periph A RF0 */ - 2 21 0x1 0x0>; /* PC21 periph A RD0 */ + <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ }; }; ssc1 { pinctrl_ssc1_tx: ssc1_tx { atmel,pins = - <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ - 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ - 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ + <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ + AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ + AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ }; pinctrl_ssc1_rx: ssc1_rx { atmel,pins = - <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ - 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ - 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ + <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ + AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ + AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ - 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ - 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ }; }; usart0 { pinctrl_usart0: usart0-0 { atmel,pins = - <3 17 0x1 0x0 /* PD17 periph A */ - 3 18 0x1 0x1>; /* PD18 periph A with pullup */ + <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ + AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ }; pinctrl_usart0_rts_cts: usart0_rts_cts-0 { atmel,pins = - <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ - 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ + <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ + AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ }; }; usart1 { pinctrl_usart1: usart1-0 { atmel,pins = - <1 28 0x1 0x0 /* PB28 periph A */ - 1 29 0x1 0x1>; /* PB29 periph A with pullup */ + <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ + AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ }; pinctrl_usart1_rts_cts: usart1_rts_cts-0 { atmel,pins = - <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ - 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ + AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ }; }; usart2 { pinctrl_usart2: usart2-0 { atmel,pins = - <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ - 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ + <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ + AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ }; pinctrl_usart2_rts_cts: usart2_rts_cts-0 { atmel,pins = - <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ - 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ + <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ + AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ }; }; usart3 { pinctrl_usart3: usart3-0 { atmel,pins = - <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ - 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ + <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ + AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ }; pinctrl_usart3_rts_cts: usart3_rts_cts-0 { atmel,pins = - <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ - 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ + <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ + AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ }; }; + + + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmc: pmc@fffffc00 { @@ -867,7 +869,7 @@ pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; - interrupts = <3 4 5>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; }; watchdog@fffffe40 { @@ -879,7 +881,7 @@ rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; - interrupts = <1 4 7>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; }; @@ -889,7 +891,7 @@ compatible = "atmel,at91sam9rl-udc"; reg = <0x00500000 0x100000 0xf8030000 0x4000>; - interrupts = <33 4 2>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; ep0 { @@ -1001,14 +1003,14 @@ usb1: ohci@00600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; - interrupts = <32 4 2>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; usb2: ehci@00700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; - interrupts = <32 4 2>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; status = "disabled"; }; @@ -1024,7 +1026,7 @@ 0xffffc000 0x00000070 /* NFC HSMC regs */ 0x00200000 0x00100000 /* NFC SRAM banks */ >; - interrupts = <5 4 6>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; atmel,nand-addr-offset = <21>; atmel,nand-cmd-offset = <22>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index fa5d216f1db7..027bac7510b6 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" -/include/ "sama5d3xdm.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D31-EK"; @@ -41,7 +41,7 @@ leds { d3 { label = "d3"; - gpios = <&pioE 24 0>; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts index c38c9433d7a5..99bd0c8e0471 100644 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ b/arch/arm/boot/dts/sama5d33ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" -/include/ "sama5d3xdm.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D33-EK"; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 6bebfcdcb1d1..fb8ee11cf282 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -7,8 +7,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" -/include/ "sama5d3xdm.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D34-EK"; @@ -51,7 +51,7 @@ leds { d3 { label = "d3"; - gpios = <&pioE 24 0>; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index a488fc4e9777..509a53d9cc7b 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -7,7 +7,7 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "sama5d3xmb.dtsi" +#include "sama5d3xmb.dtsi" / { model = "Atmel SAMA5D35-EK"; @@ -48,7 +48,7 @@ pb_user1 { label = "pb_user1"; - gpios = <&pioE 27 0>; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index b336e7787cb3..1f8050813a54 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -6,7 +6,7 @@ * * Licensed under GPLv2 or later. */ -/include/ "sama5d3.dtsi" +#include "sama5d3.dtsi" / { compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; @@ -89,7 +89,7 @@ d2 { label = "d2"; - gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ }; }; }; diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 4b8830eb2060..1c296d6b2f2a 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi @@ -33,7 +33,7 @@ board { pinctrl_qt1070_irq: qt1070_irq { atmel,pins = - <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */ }; }; }; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 661d7ca9c309..8a9e05d8a4b8 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -6,7 +6,7 @@ * * Licensed under GPLv2 or later. */ -/include/ "sama5d3xcm.dtsi" +#include "sama5d3xcm.dtsi" / { compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; @@ -20,7 +20,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 17 0>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; }; }; @@ -62,7 +62,7 @@ slot@0 { reg = <0>; bus-width = <4>; - cd-gpios = <&pioD 18 0>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; }; }; @@ -87,32 +87,32 @@ board { pinctrl_mmc0_cd: mmc0_cd { atmel,pins = - <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ + <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */ }; pinctrl_mmc1_cd: mmc1_cd { atmel,pins = - <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ + <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */ }; pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { atmel,pins = - <3 30 0x2 0x0>; /* PD30 periph B */ + <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */ }; pinctrl_isi_reset: isi_reset-0 { atmel,pins = - <4 24 0x0 0x0>; /* PE24 gpio */ + <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */ }; pinctrl_isi_power: isi_power-0 { atmel,pins = - <4 29 0x0 0x0>; /* PE29 gpio */ + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */ }; pinctrl_usba_vbus: usba_vbus { atmel,pins = - <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ + <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */ }; }; }; @@ -127,7 +127,7 @@ }; usb0: gadget@00500000 { - atmel,vbus-gpio = <&pioD 29 0>; + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; @@ -135,9 +135,9 @@ usb1: ohci@00600000 { num-ports = <3>; - atmel,vbus-gpio = <&pioD 25 0 - &pioD 26 1 - &pioD 27 1 + atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH + &pioD 26 GPIO_ACTIVE_LOW + &pioD 27 GPIO_ACTIVE_LOW >; status = "okay"; }; diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts index 367a16dcd5ef..dabe232216b4 100644 --- a/arch/arm/boot/dts/tny_a9260.dts +++ b/arch/arm/boot/dts/tny_a9260.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9260.dtsi" -/include/ "tny_a9260_common.dtsi" +#include "at91sam9260.dtsi" +#include "tny_a9260_common.dtsi" / { model = "Calao TNY A9260"; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index dee9c571306b..0751a6a979a8 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91sam9263.dtsi" +#include "at91sam9263.dtsi" / { model = "Calao TNY A9263"; @@ -38,7 +38,7 @@ }; usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 0>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts index e1ab64c72dba..8456d70bb42b 100644 --- a/arch/arm/boot/dts/tny_a9g20.dts +++ b/arch/arm/boot/dts/tny_a9g20.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2. */ /dts-v1/; -/include/ "at91sam9g20.dtsi" -/include/ "tny_a9260_common.dtsi" +#include "at91sam9g20.dtsi" +#include "tny_a9260_common.dtsi" / { model = "Calao TNY A9G20"; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index 296216058c11..a604107eb474 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9260.dtsi" -/include/ "usb_a9260_common.dtsi" +#include "at91sam9260.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9260"; diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi index e70d229baef5..285977682cf3 100644 --- a/arch/arm/boot/dts/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/usb_a9260_common.dtsi @@ -30,7 +30,7 @@ }; usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 0>; + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; @@ -93,7 +93,7 @@ user_led { label = "user_led"; - gpios = <&pioB 21 1>; + gpios = <&pioB 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; }; @@ -105,7 +105,7 @@ user_pb { label = "user_pb"; - gpios = <&pioB 10 1>; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 6fe05ccb6203..f8ec36cb036b 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -6,7 +6,7 @@ * Licensed under GPLv2 only */ /dts-v1/; -/include/ "at91sam9263.dtsi" +#include "at91sam9263.dtsi" / { model = "Calao USB A9263"; @@ -43,7 +43,7 @@ }; usb1: gadget@fff78000 { - atmel,vbus-gpio = <&pioB 11 0>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -107,7 +107,7 @@ user_led { label = "user_led"; - gpios = <&pioB 21 0>; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -119,7 +119,7 @@ user_pb { label = "user_pb"; - gpios = <&pioB 10 1>; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi index ad3eca17c436..5b0ffc1a0b24 100644 --- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi +++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi @@ -28,39 +28,39 @@ user_led1 { label = "user_led1"; - gpios = <&pioB 20 1>; + gpios = <&pioB 20 GPIO_ACTIVE_LOW>; }; /* * led already used by mother board but active as high * user_led2 { * label = "user_led2"; -* gpios = <&pioB 21 1>; +* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; * }; */ user_led3 { label = "user_led3"; - gpios = <&pioB 22 1>; + gpios = <&pioB 22 GPIO_ACTIVE_LOW>; }; user_led4 { label = "user_led4"; - gpios = <&pioB 23 1>; + gpios = <&pioB 23 GPIO_ACTIVE_LOW>; }; red { label = "red"; - gpios = <&pioB 24 1>; + gpios = <&pioB 24 GPIO_ACTIVE_LOW>; }; orange { label = "orange"; - gpios = <&pioB 30 1>; + gpios = <&pioB 30 GPIO_ACTIVE_LOW>; }; green { label = "green"; - gpios = <&pioB 31 1>; + gpios = <&pioB 31 GPIO_ACTIVE_LOW>; }; }; @@ -71,25 +71,25 @@ user_pb1 { label = "user_pb1"; - gpios = <&pioB 25 1>; + gpios = <&pioB 25 GPIO_ACTIVE_LOW>; linux,code = <0x100>; }; user_pb2 { label = "user_pb2"; - gpios = <&pioB 13 1>; + gpios = <&pioB 13 GPIO_ACTIVE_LOW>; linux,code = <0x101>; }; user_pb3 { label = "user_pb3"; - gpios = <&pioA 26 1>; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <0x102>; }; user_pb4 { label = "user_pb4"; - gpios = <&pioC 9 1>; + gpios = <&pioC 9 GPIO_ACTIVE_LOW>; linux,code = <0x103>; }; }; diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts index 2dacb16ce4ae..c979c06cf697 100644 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ b/arch/arm/boot/dts/usb_a9g20.dts @@ -6,8 +6,8 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -/include/ "at91sam9g20.dtsi" -/include/ "usb_a9260_common.dtsi" +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9G20"; diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 047f2a415309..a8800d361805 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -42,6 +39,9 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set @@ -51,7 +51,8 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set CONFIG_IPV6_SIT_6RD=y -# CONFIG_WIRELESS is not set +CONFIG_CFG80211=y +CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_ATMEL_PWM=y CONFIG_ATMEL_TCLIB=y -CONFIG_EEPROM_93CX6=m CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y @@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_MACB=y # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_FARADAY is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MARVELL is not set @@ -92,7 +91,23 @@ CONFIG_MACB=y # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_DAVICOM_PHY=y CONFIG_MICREL_PHY=y -# CONFIG_WLAN is not set +CONFIG_RTL8187=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTLWIFI=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8192CU=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m CONFIG_INPUT_POLLDEV=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 @@ -112,13 +127,11 @@ CONFIG_I2C=y CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_ATMEL=y -CONFIG_PINCTRL_AT91=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_SSB=m CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set @@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y CONFIG_FONT_ACORN_8x8=y CONFIG_FONT_MINI_4x6=y CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_ACM=y @@ -146,14 +156,9 @@ CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_FTDI_SIO=y CONFIG_USB_SERIAL_PL2303=y CONFIG_USB_GADGET=y -CONFIG_USB_AT91=m -CONFIG_USB_ATMEL_USBA=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_MULTI=m -CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_AT91=y +CONFIG_USB_ATMEL_USBA=y +CONFIG_USB_G_SERIAL=y CONFIG_MMC=y CONFIG_MMC_ATMELMCI=y CONFIG_NEW_LEDS=y @@ -168,16 +173,18 @@ CONFIG_RTC_DRV_AT91RM9200=y CONFIG_RTC_DRV_AT91SAM9=y CONFIG_DMADEVICES=y # CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y +CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y CONFIG_STRIP_ASM_SYMS=y CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set @@ -192,7 +199,7 @@ CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC_ITU_T=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y CONFIG_CRC7=m CONFIG_AVERAGE=y diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index 4ae57a34a582..8b099349c4b1 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -1,10 +1,12 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +CONFIG_USER_NS=y CONFIG_BLK_DEV_INITRD=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y @@ -35,49 +37,37 @@ CONFIG_AT91_TIMER_HZ=100 # CONFIG_ARM_THUMB is not set CONFIG_PCCARD=y CONFIG_AT91_CF=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y CONFIG_AEABI=y -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y +# CONFIG_COMPACTION is not set CONFIG_ZBOOT_ROM_TEXT=0x10000000 CONFIG_ZBOOT_ROM_BSS=0x20040000 CONFIG_KEXEC=y +CONFIG_AUTO_ZRELADDR=y CONFIG_FPE_NWFPE=y CONFIG_BINFMT_MISC=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_XFRM_USER=m CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -CONFIG_NET_IPIP=m -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_BT=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_AFS_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y @@ -94,55 +84,21 @@ CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y -CONFIG_TUN=m +CONFIG_MII=y CONFIG_ARM_AT91_ETHER=y -CONFIG_PHYLIB=y CONFIG_DAVICOM_PHY=y CONFIG_SMSC_PHY=y CONFIG_MICREL_PHY=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=m -CONFIG_PPP_ASYNC=y -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_LEGACY_PTY_COUNT=32 +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_HW_RANDOM=y @@ -151,38 +107,8 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_ATMEL=y -CONFIG_SPI_BITBANG=y CONFIG_GPIO_SYSFS=y -CONFIG_HWMON=m -CONFIG_SENSORS_ADM1021=m -CONFIG_SENSORS_ADM1025=m -CONFIG_SENSORS_ADM1026=m -CONFIG_SENSORS_ADM1029=m -CONFIG_SENSORS_ADM1031=m -CONFIG_SENSORS_ADM9240=m -CONFIG_SENSORS_DS1621=m -CONFIG_SENSORS_GL518SM=m -CONFIG_SENSORS_GL520SM=m -CONFIG_SENSORS_IT87=m -CONFIG_SENSORS_LM63=m -CONFIG_SENSORS_LM73=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM77=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM80=m -CONFIG_SENSORS_LM83=m -CONFIG_SENSORS_LM85=m -CONFIG_SENSORS_LM87=m -CONFIG_SENSORS_LM90=m -CONFIG_SENSORS_LM92=m -CONFIG_SENSORS_MAX1619=m -CONFIG_SENSORS_PCF8591=m -CONFIG_SENSORS_SMSC47B397=m -CONFIG_SENSORS_W83781D=m -CONFIG_SENSORS_W83791D=m -CONFIG_SENSORS_W83792D=m -CONFIG_SENSORS_W83793=m -CONFIG_SENSORS_W83L785TS=m +# CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_AT91RM9200_WATCHDOG=y @@ -194,43 +120,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_DISPLAY_SUPPORT=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y -CONFIG_FONT_MINI_4x6=y CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_CONSOLE=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_FTDI_SIO=y -CONFIG_USB_SERIAL_KEYSPAN=y -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_MCT_U232=y -CONFIG_USB_SERIAL_PL2303=y CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_AT91=y +CONFIG_USB_G_SERIAL=y CONFIG_MMC=y CONFIG_MMC_ATMELMCI=y CONFIG_NEW_LEDS=y @@ -240,84 +137,27 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y -# CONFIG_RTC_HCTOSYS is not set -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_AT91RM9200=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_REISERFS_FS=y +CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_CRAMFS=y -CONFIG_MINIX_FS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_CIFS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAC_PARTITION=y CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m +CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y CONFIG_CRYPTO_PCBC=y CONFIG_CRYPTO_SHA1=y +CONFIG_XZ_DEC_ARMTHUMB=y diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig index 892e8287ed73..f50c404f0d3f 100644 --- a/arch/arm/configs/at91sam9g20_defconfig +++ b/arch/arm/configs/at91sam9260_9g20_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -11,7 +10,15 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_AT91=y -CONFIG_ARCH_AT91SAM9G20=y +CONFIG_ARCH_AT91SAM9260=y +CONFIG_MACH_AT91SAM9260EK=y +CONFIG_MACH_CAM60=y +CONFIG_MACH_SAM9_L9260=y +CONFIG_MACH_AFEB9260=y +CONFIG_MACH_USB_A9260=y +CONFIG_MACH_QIL_A9260=y +CONFIG_MACH_CPU9260=y +CONFIG_MACH_FLEXIBITY=y CONFIG_MACH_AT91SAM9G20EK=y CONFIG_MACH_AT91SAM9G20EK_2MMC=y CONFIG_MACH_CPU9G20=y @@ -20,10 +27,10 @@ CONFIG_MACH_PORTUXG20=y CONFIG_MACH_STAMP9G20=y CONFIG_MACH_PCONTROL_G20=y CONFIG_MACH_GSIA18S=y -CONFIG_MACH_USB_A9G20=y CONFIG_MACH_SNAPPER_9260=y CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_SLOW_CLOCK=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y CONFIG_LEDS=y @@ -33,12 +40,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" +CONFIG_AUTO_ZRELADDR=y CONFIG_FPE_NWFPE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set @@ -46,8 +55,11 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_DATAFLASH=y @@ -56,6 +68,8 @@ CONFIG_MTD_NAND_ATMEL=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_AT25=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y @@ -63,23 +77,36 @@ CONFIG_SCSI_MULTI_LUN=y CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_MACB=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_SMSC_PHY=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set -CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIO is not set CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_ATMEL=y CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SEQUENCER=y @@ -94,12 +121,11 @@ CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m +CONFIG_USB_AT91=y +CONFIG_USB_G_SERIAL=y CONFIG_MMC=y -CONFIG_MMC_ATMELMCI=m +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_SPI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y @@ -109,15 +135,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_RV3029C2=y CONFIG_RTC_DRV_AT91SAM9=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y +CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_CRAMFS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y @@ -125,3 +148,9 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y # CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_LL=y +CONFIG_AT91_DEBUG_LL_DBGU0=y +CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig deleted file mode 100644 index 05618eb694f8..000000000000 --- a/arch/arm/configs/at91sam9260_defconfig +++ /dev/null @@ -1,91 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_AT91=y -CONFIG_ARCH_AT91SAM9260=y -CONFIG_ARCH_AT91SAM9260_SAM9XE=y -CONFIG_MACH_AT91SAM9260EK=y -CONFIG_MACH_CAM60=y -CONFIG_MACH_SAM9_L9260=y -CONFIG_MACH_AFEB9260=y -CONFIG_MACH_USB_A9260=y -CONFIG_MACH_QIL_A9260=y -CONFIG_MACH_CPU9260=y -CONFIG_MACH_FLEXIBITY=y -CONFIG_MACH_SNAPPER_9260=y -CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y -# CONFIG_ARM_THUMB is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_MACB=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_AT91SAM9X_WATCHDOG=y -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DEBUG=y -CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AT91SAM9=y -CONFIG_EXT2_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_CRAMFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig index c87beb973b37..9d35cd81c611 100644 --- a/arch/arm/configs/at91sam9261_defconfig +++ b/arch/arm/configs/at91sam9261_9g10_defconfig @@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9261=y CONFIG_MACH_AT91SAM9261EK=y +CONFIG_MACH_AT91SAM9G10EK=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y @@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_CFG80211=y -CONFIG_LIB80211=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y @@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_MISC_DEVICES=y CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_SSC=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y CONFIG_DM9000=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set CONFIG_USB_ZD1201=m CONFIG_RTL8187=m CONFIG_LIBERTAS=m @@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y CONFIG_SND_USB_AUDIO=m # CONFIG_USB_HID is not set CONFIG_USB=y -CONFIG_USB_DEVICEFS=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m +CONFIG_USB_AT91=y +CONFIG_USB_G_SERIAL=y CONFIG_MMC=y CONFIG_MMC_ATMELMCI=m CONFIG_NEW_LEDS=y @@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -CONFIG_FTRACE=y CONFIG_CRC_CCITT=m diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig index 36fed66bd4b5..9d72ab684829 100644 --- a/arch/arm/configs/at91sam9263_defconfig +++ b/arch/arm/configs/at91sam9263_defconfig @@ -1,6 +1,4 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_KERNEL_LZMA=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y @@ -48,9 +46,11 @@ CONFIG_IP_PIMSM_V2=y # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set CONFIG_IPV6=y +# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y @@ -65,7 +65,6 @@ CONFIG_MTD_UBI_GLUEBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_MISC_DEVICES=y CONFIG_ATMEL_PWM=y CONFIG_ATMEL_TCLIB=y CONFIG_SCSI=y @@ -73,23 +72,18 @@ CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y CONFIG_NETDEVICES=y CONFIG_MII=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MACB=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_USB_ZD1201=m +CONFIG_SMSC_PHY=y +# CONFIG_WLAN is not set CONFIG_INPUT_POLLDEV=m -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 +# CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_HW_RANDOM=y @@ -98,6 +92,7 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_ATMEL=y +CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y @@ -107,9 +102,9 @@ CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_ATMEL_LCDC=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y @@ -124,16 +119,12 @@ CONFIG_SND_ATMEL_AC97C=y # CONFIG_SND_SPI is not set CONFIG_SND_USB_AUDIO=m CONFIG_USB=y -CONFIG_USB_DEVICEFS=y CONFIG_USB_MON=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m +CONFIG_USB_ATMEL_USBA=y +CONFIG_USB_G_SERIAL=y CONFIG_MMC=y CONFIG_SDIO_UART=m CONFIG_MMC_ATMELMCI=m @@ -145,22 +136,18 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_AT91SAM9=y -CONFIG_EXT2_FS=y -CONFIG_FUSE_FS=m +CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_CRAMFS=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y -CONFIG_FTRACE=y +CONFIG_NLS_UTF8=y CONFIG_DEBUG_USER=y CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig index 18964cdacd68..08166cd4e7d6 100644 --- a/arch/arm/configs/at91sam9g45_defconfig +++ b/arch/arm/configs/at91sam9g45_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_SLOW_CLOCK=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -CONFIG_LEDS=y -CONFIG_LEDS_CPU=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -36,6 +33,9 @@ CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set @@ -45,9 +45,6 @@ CONFIG_IPV6=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set CONFIG_IPV6_SIT_6RD=y -CONFIG_CFG80211=y -CONFIG_LIB80211=y -CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_MISC_DEVICES=y CONFIG_ATMEL_PWM=y CONFIG_ATMEL_TCLIB=y +CONFIG_ATMEL_SSC=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y @@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_MACB=y CONFIG_DAVICOM_PHY=y -CONFIG_LIBERTAS_THINFIRM=m -CONFIG_LIBERTAS_THINFIRM_USB=m -CONFIG_AT76C50X_USB=m -CONFIG_USB_ZD1201=m -CONFIG_RTL8187=m -CONFIG_ATH_COMMON=m -CONFIG_ATH9K=m -CONFIG_CARL9170=m -CONFIG_B43=m -CONFIG_B43_PHY_N=y -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_SPI=m -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT53XX=y -CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RTL8192CU=m -CONFIG_WL1251=m -CONFIG_WL1251_SDIO=m -CONFIG_WL12XX_MENU=m -CONFIG_WL12XX=m -CONFIG_WL12XX_SDIO=m -CONFIG_ZD1211RW=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_INPUT_POLLDEV=m -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 +# CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_QT1070=m -CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_QT1070=y +CONFIG_KEYBOARD_QT2160=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y # CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_ATMEL=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_ATMEL=y -CONFIG_FB_UDL=m CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_ATMEL_LCDC=y +CONFIG_BACKLIGHT_ATMEL_PWM=y # CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SEQUENCER=y @@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y # CONFIG_SND_ARM is not set CONFIG_SND_ATMEL_AC97C=y # CONFIG_SND_SPI is not set -CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB is not set # CONFIG_USB_HID is not set CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_USB_ATMEL_USBA=m -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m -CONFIG_USB_ETH=m -CONFIG_USB_ETH_EEM=y -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_G_MULTI=m +CONFIG_USB_ATMEL_USBA=y +CONFIG_USB_G_MULTI=y CONFIG_USB_G_MULTI_CDC=y CONFIG_MMC=y # CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_SDIO_UART=m CONFIG_MMC_ATMELMCI=y -CONFIG_LEDS_ATMEL_PWM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_GPIO=y @@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y CONFIG_AT_HDMAC=y CONFIG_DMATEST=m # CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y +CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y @@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_USER_API_HASH=m diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 9940f7b4e438..d74edbad18fc 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -26,7 +26,8 @@ CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP1=y CONFIG_OMAP_RESET_CLOCKS=y # CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MBOX_FWK=y +CONFIG_MAILBOX=y +CONFIG_OMAP1_MBOX=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_DM_TIMER=y CONFIG_ARCH_OMAP730=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 4d0dc3c16063..f6e78f83c3c3 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -26,7 +26,9 @@ CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_KEXEC=y CONFIG_AUTO_ZRELADDR=y CONFIG_VFP=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -39,6 +41,9 @@ CONFIG_UNIX=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set @@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=4 @@ -95,7 +102,19 @@ CONFIG_MACB=y # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_MICREL_PHY=y -# CONFIG_WLAN is not set +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_RTL8187=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set @@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y CONFIG_USB_GADGET=y -CONFIG_USB_AT91=y -CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_ATMEL_USBA=y +CONFIG_USB_G_SERIAL=y CONFIG_MMC=y # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_ATMELMCI=y @@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=y CONFIG_AT91_ADC=y -CONFIG_EXT2_FS=y +CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y CONFIG_STRIP_ASM_SYMS=y CONFIG_DEBUG_FS=y # CONFIG_SCHED_DEBUG is not set diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 6c24985515a2..1a2abd8ed407 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt @@ -14,15 +14,11 @@ config ARCH_AT91RM9200 select SOC_AT91RM9200 config ARCH_AT91SAM9260 - bool "AT91SAM9260 or AT91SAM9XE" + bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" select SOC_AT91SAM9260 config ARCH_AT91SAM9261 - bool "AT91SAM9261" - select SOC_AT91SAM9261 - -config ARCH_AT91SAM9G10 - bool "AT91SAM9G10" + bool "AT91SAM9261 or AT91SAM9G10" select SOC_AT91SAM9261 config ARCH_AT91SAM9263 @@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL bool "AT91SAM9RL" select SOC_AT91SAM9RL -config ARCH_AT91SAM9G20 - bool "AT91SAM9G20" - select SOC_AT91SAM9260 - config ARCH_AT91SAM9G45 bool "AT91SAM9G45" select SOC_AT91SAM9G45 @@ -50,6 +42,14 @@ config ARCH_AT91X40 endchoice +config ARCH_AT91SAM9G20 + bool + select ARCH_AT91SAM9260 + +config ARCH_AT91SAM9G10 + bool + select ARCH_AT91SAM9261 + # ---------------------------------------------------------- if ARCH_AT91RM9200 @@ -207,76 +207,6 @@ config MACH_FLEXIBITY Select this if you are using Flexibity Connect board <http://www.flexibity.com> -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9261 - -comment "AT91SAM9261 Board Type" - -config MACH_AT91SAM9261EK - bool "Atmel AT91SAM9261-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. - <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9G10 - -comment "AT91SAM9G10 Board Type" - -config MACH_AT91SAM9G10EK - bool "Atmel AT91SAM9G10-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. - <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9263 - -comment "AT91SAM9263 Board Type" - -config MACH_AT91SAM9263EK - bool "Atmel AT91SAM9263-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. - <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> - -config MACH_USB_A9263 - bool "CALAO USB-A9263" - help - Select this if you are using a Calao Systems USB-A9263. - <http://www.calao-systems.com> - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9RL - -comment "AT91SAM9RL Board Type" - -config MACH_AT91SAM9RLEK - bool "Atmel AT91SAM9RL-EK Evaluation Kit" - help - Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9G20 - comment "AT91SAM9G20 Board Type" config MACH_AT91SAM9G20EK @@ -341,17 +271,70 @@ config MACH_USB_A9G20 Select this if you are using a Calao Systems USB-A9G20. <http://www.calao-systems.com> +config MACH_SNAPPER_9260 + bool "Bluewater Systems Snapper 9260/9G20 module" + help + Select this if you are using the Bluewater Systems Snapper 9260 or + Snapper 9G20 modules. + <http://www.bluewatersys.com/> endif -if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) -comment "AT91SAM9260/AT91SAM9G20 boards" +# ---------------------------------------------------------- + +if ARCH_AT91SAM9261 + +comment "AT91SAM9261 Board Type" + +config MACH_AT91SAM9261EK + bool "Atmel AT91SAM9261-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. + <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> + +comment "AT91SAM9G10 Board Type" + +config MACH_AT91SAM9G10EK + bool "Atmel AT91SAM9G10-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. + <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9263 + +comment "AT91SAM9263 Board Type" + +config MACH_AT91SAM9263EK + bool "Atmel AT91SAM9263-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. + <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> + +config MACH_USB_A9263 + bool "CALAO USB-A9263" + help + Select this if you are using a Calao Systems USB-A9263. + <http://www.calao-systems.com> + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9RL + +comment "AT91SAM9RL Board Type" + +config MACH_AT91SAM9RLEK + bool "Atmel AT91SAM9RL-EK Evaluation Kit" + help + Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. -config MACH_SNAPPER_9260 - bool "Bluewater Systems Snapper 9260/9G20 module" - help - Select this if you are using the Bluewater Systems Snapper 9260 or - Snapper 9G20 modules. - <http://www.bluewatersys.com/> endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 788562dccb43..f4a5f7998bd7 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -27,10 +27,8 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261_devices.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index b446645c7727..d3437624ca4e 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {} */ static struct at73c213_board_info at73c213_data = { .ssc_id = 1, -#if defined(CONFIG_MACH_AT91SAM9261EK) - .shortname = "AT91SAM9261-EK external DAC", -#else - .shortname = "AT91SAM9G10-EK external DAC", -#endif + .shortname = "AT91SAM9261/9G10-EK external DAC", }; #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) @@ -412,9 +408,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .default_monspecs = &at91fb_default_stn_monspecs, .atmel_lcdfb_power_control = at91_lcdc_stn_power_control, .guard_time = 1, -#if defined(CONFIG_MACH_AT91SAM9G10EK) - .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, -#endif }; #else @@ -468,9 +461,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .default_monspecs = &at91fb_default_tft_monspecs, .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, .guard_time = 1, -#if defined(CONFIG_MACH_AT91SAM9G10EK) - .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, -#endif }; #endif @@ -574,6 +564,10 @@ static void __init ek_board_init(void) /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); at91_add_device_serial(); + + if (cpu_is_at91sam9g10()) + ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; + /* USB Host */ at91_add_device_usbh(&ek_usbh_data); /* USB Device */ @@ -606,11 +600,17 @@ static void __init ek_board_init(void) at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); } -#if defined(CONFIG_MACH_AT91SAM9261EK) MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") -#else + /* Maintainer: Atmel */ + .init_time = at91sam926x_pit_init, + .map_io = at91_map_io, + .handle_irq = at91_aic_handle_irq, + .init_early = ek_init_early, + .init_irq = at91_init_irq_default, + .init_machine = ek_board_init, +MACHINE_END + MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") -#endif /* Maintainer: Atmel */ .init_time = at91sam926x_pit_init, .map_io = at91_map_io, diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 222d58c0ae76..3889b6cd211e 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -19,10 +19,6 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o # Power Management obj-$(CONFIG_PM) += pm.o sleep.o -# DSP -obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o -mailbox_mach-objs := mailbox.o - i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 55a9d6777683..f2d19af051eb 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -203,9 +203,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o -obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o -mailbox_mach-objs := mailbox.o - iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o obj-y += $(iommu-m) $(iommu-y) diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index c33adea0247c..fc20a61f6b2a 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = { .cs_rd_off = 36, .cs_wr_off = 36, + .we_on = 6, + .oe_on = 6, + .adv_on = 6, .adv_rd_off = 24, .adv_wr_off = 36, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 4269fc145698..73762accd128 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -20,6 +20,7 @@ #include <linux/pinctrl/machine.h> #include <linux/platform_data/omap4-keypad.h> #include <linux/platform_data/omap_ocp2scp.h> +#include <linux/platform_data/mailbox-omap.h> #include <linux/usb/omap_control_usb.h> #include <asm/mach-types.h> @@ -327,25 +328,31 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data return 0; } -#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) +#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE) static inline void __init omap_init_mbox(void) { struct omap_hwmod *oh; struct platform_device *pdev; + struct omap_mbox_pdata *pdata; oh = omap_hwmod_lookup("mailbox"); if (!oh) { pr_err("%s: unable to find hwmod\n", __func__); return; } + if (!oh->dev_attr) { + pr_err("%s: hwmod doesn't have valid attrs\n", __func__); + return; + } - pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0); + pdata = (struct omap_mbox_pdata *)oh->dev_attr; + pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata)); WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", __func__, PTR_ERR(pdev)); } #else static inline void omap_init_mbox(void) { } -#endif /* CONFIG_OMAP_MBOX_FWK */ +#endif /* CONFIG_OMAP2PLUS_MBOX */ static inline void omap_init_sti(void) {} diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index d9c27195caf0..662c7fd633cc 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = { .resource = gpmc_nand_resource, }; -static int omap2_nand_gpmc_retime( - struct omap_nand_platform_data *gpmc_nand_data, - struct gpmc_timings *gpmc_t) -{ - struct gpmc_timings t; - int err; - - memset(&t, 0, sizeof(t)); - t.sync_clk = gpmc_t->sync_clk; - t.cs_on = gpmc_t->cs_on; - t.adv_on = gpmc_t->adv_on; - - /* Read */ - t.adv_rd_off = gpmc_t->adv_rd_off; - t.oe_on = t.adv_on; - t.access = gpmc_t->access; - t.oe_off = gpmc_t->oe_off; - t.cs_rd_off = gpmc_t->cs_rd_off; - t.rd_cycle = gpmc_t->rd_cycle; - - /* Write */ - t.adv_wr_off = gpmc_t->adv_wr_off; - t.we_on = t.oe_on; - if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; - t.wr_access = gpmc_t->wr_access; - } - t.we_off = gpmc_t->we_off; - t.cs_wr_off = gpmc_t->cs_wr_off; - t.wr_cycle = gpmc_t->wr_cycle; - - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); - if (err) - return err; - - return 0; -} - static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ @@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); if (gpmc_t) { - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); if (err < 0) { dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; @@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, if (gpmc_nand_data->of_node) { gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); } else { - s.device_nand = true; - /* Enable RD PIN Monitoring Reg */ if (gpmc_nand_data->dev_ready) { s.wait_on_read = true; @@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, } } + s.device_nand = true; + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) s.device_width = GPMC_DEVWIDTH_16BIT; else diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 6c4da1254f53..1c7969e965d7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -30,6 +30,7 @@ #include <linux/of_mtd.h> #include <linux/of_device.h> #include <linux/mtd/nand.h> +#include <linux/pm_runtime.h> #include <linux/platform_data/mtd-nand-omap2.h> @@ -155,6 +156,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); /* Define chip-selects as reserved by default until probe completes */ static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); +static unsigned int gpmc_cs_num = GPMC_CS_NUM; static unsigned int gpmc_nr_waitpins; static struct device *gpmc_dev; static int gpmc_irq; @@ -521,8 +523,10 @@ static int gpmc_cs_remap(int cs, u32 base) int ret; u32 old_base, size; - if (cs > GPMC_CS_NUM) + if (cs > gpmc_cs_num) { + pr_err("%s: requested chip-select is disabled\n", __func__); return -ENODEV; + } gpmc_cs_get_memconf(cs, &old_base, &size); if (base == old_base) return 0; @@ -545,9 +549,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) struct resource *res = &gpmc_cs_mem[cs]; int r = -1; - if (cs > GPMC_CS_NUM) + if (cs > gpmc_cs_num) { + pr_err("%s: requested chip-select is disabled\n", __func__); return -ENODEV; - + } size = gpmc_mem_align(size); if (size > (1 << GPMC_SECTION_SHIFT)) return -ENOMEM; @@ -582,7 +587,7 @@ EXPORT_SYMBOL(gpmc_cs_request); void gpmc_cs_free(int cs) { spin_lock(&gpmc_mem_lock); - if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { + if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); BUG(); spin_unlock(&gpmc_mem_lock); @@ -777,7 +782,7 @@ static void gpmc_mem_exit(void) { int cs; - for (cs = 0; cs < GPMC_CS_NUM; cs++) { + for (cs = 0; cs < gpmc_cs_num; cs++) { if (!gpmc_cs_mem_enabled(cs)) continue; gpmc_cs_delete_mem(cs); @@ -798,7 +803,7 @@ static void gpmc_mem_init(void) gpmc_mem_root.end = GPMC_MEM_END; /* Reserve all regions that has been set up by bootloader */ - for (cs = 0; cs < GPMC_CS_NUM; cs++) { + for (cs = 0; cs < gpmc_cs_num; cs++) { u32 base, size; if (!gpmc_cs_mem_enabled(cs)) @@ -1245,7 +1250,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); - p->device_nand = of_property_read_bool(np, "gpmc,device-nand"); of_property_read_u32(np, "gpmc,device-width", &p->device_width); of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); @@ -1345,6 +1349,13 @@ static const char * const nand_ecc_opts[] = { [OMAP_ECC_BCH8_CODE_HW] = "bch8", }; +static const char * const nand_xfer_types[] = { + [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", + [NAND_OMAP_POLLED] = "polled", + [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", + [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", +}; + static int gpmc_probe_nand_child(struct platform_device *pdev, struct device_node *child) { @@ -1374,6 +1385,13 @@ static int gpmc_probe_nand_child(struct platform_device *pdev, break; } + if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) + for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++) + if (!strcasecmp(s, nand_xfer_types[val])) { + gpmc_nand_data->xfer_type = val; + break; + } + val = of_get_nand_bus_width(child); if (val == 16) gpmc_nand_data->devsize = NAND_BUSWIDTH_16; @@ -1513,6 +1531,20 @@ static int gpmc_probe_dt(struct platform_device *pdev) if (!of_id) return 0; + ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", + &gpmc_cs_num); + if (ret < 0) { + pr_err("%s: number of chip-selects not defined\n", __func__); + return ret; + } else if (gpmc_cs_num < 1) { + pr_err("%s: all chip-selects are disabled\n", __func__); + return -EINVAL; + } else if (gpmc_cs_num > GPMC_CS_NUM) { + pr_err("%s: number of supported chip-selects cannot be > %d\n", + __func__, GPMC_CS_NUM); + return -EINVAL; + } + ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", &gpmc_nr_waitpins); if (ret < 0) { @@ -1577,7 +1609,8 @@ static int gpmc_probe(struct platform_device *pdev) return PTR_ERR(gpmc_l3_clk); } - clk_prepare_enable(gpmc_l3_clk); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); gpmc_dev = &pdev->dev; @@ -1610,12 +1643,14 @@ static int gpmc_probe(struct platform_device *pdev) /* Now the GPMC is initialised, unreserve the chip-selects */ gpmc_cs_map = 0; - if (!pdev->dev.of_node) + if (!pdev->dev.of_node) { + gpmc_cs_num = GPMC_CS_NUM; gpmc_nr_waitpins = GPMC_NR_WAITPINS; + } rc = gpmc_probe_dt(pdev); if (rc < 0) { - clk_disable_unprepare(gpmc_l3_clk); + pm_runtime_put_sync(&pdev->dev); clk_put(gpmc_l3_clk); dev_err(gpmc_dev, "failed to probe DT parameters\n"); return rc; @@ -1628,10 +1663,30 @@ static int gpmc_remove(struct platform_device *pdev) { gpmc_free_irq(); gpmc_mem_exit(); + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); gpmc_dev = NULL; return 0; } +#ifdef CONFIG_PM_SLEEP +static int gpmc_suspend(struct device *dev) +{ + omap3_gpmc_save_context(); + pm_runtime_put_sync(dev); + return 0; +} + +static int gpmc_resume(struct device *dev) +{ + pm_runtime_get_sync(dev); + omap3_gpmc_restore_context(); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); + static struct platform_driver gpmc_driver = { .probe = gpmc_probe, .remove = gpmc_remove, @@ -1639,6 +1694,7 @@ static struct platform_driver gpmc_driver = { .name = DEVICE_NAME, .owner = THIS_MODULE, .of_match_table = of_match_ptr(gpmc_dt_ids), + .pm = &gpmc_pm_ops, }, }; @@ -1701,7 +1757,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev) return IRQ_HANDLED; } -#ifdef CONFIG_ARCH_OMAP3 static struct omap3_gpmc_regs gpmc_context; void omap3_gpmc_save_context(void) @@ -1715,7 +1770,7 @@ void omap3_gpmc_save_context(void) gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); - for (i = 0; i < GPMC_CS_NUM; i++) { + for (i = 0; i < gpmc_cs_num; i++) { gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); if (gpmc_context.cs_context[i].is_valid) { gpmc_context.cs_context[i].config1 = @@ -1747,7 +1802,7 @@ void omap3_gpmc_restore_context(void) gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); - for (i = 0; i < GPMC_CS_NUM; i++) { + for (i = 0; i < gpmc_cs_num; i++) { if (gpmc_context.cs_context[i].is_valid) { gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, gpmc_context.cs_context[i].config1); @@ -1766,4 +1821,3 @@ void omap3_gpmc_restore_context(void) } } } -#endif /* CONFIG_ARCH_OMAP3 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 5137cc84b504..d8b9d60f854f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -16,6 +16,7 @@ #include <linux/i2c-omap.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/omap-dma.h> +#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "omap_hwmod.h" @@ -166,6 +167,18 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { }; /* mailbox */ +static struct omap_mbox_dev_info omap2420_mailbox_info[] = { + { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 }, + { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 }, +}; + +static struct omap_mbox_pdata omap2420_mailbox_attrs = { + .num_users = 4, + .num_fifos = 6, + .info_cnt = ARRAY_SIZE(omap2420_mailbox_info), + .info = omap2420_mailbox_info, +}; + static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, { .name = "iva", .irq = 34 + OMAP_INTC_START, }, @@ -186,6 +199,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, + .dev_attr = &omap2420_mailbox_attrs, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4ce999ee3ee9..5b9083461dc5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -17,6 +17,7 @@ #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/omap-dma.h> +#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "omap_hwmod.h" @@ -170,6 +171,17 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { }; /* mailbox */ +static struct omap_mbox_dev_info omap2430_mailbox_info[] = { + { .name = "dsp", .tx_id = 0, .rx_id = 1 }, +}; + +static struct omap_mbox_pdata omap2430_mailbox_attrs = { + .num_users = 4, + .num_fifos = 6, + .info_cnt = ARRAY_SIZE(omap2430_mailbox_info), + .info = omap2430_mailbox_info, +}; + static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { { .irq = 26 + OMAP_INTC_START, }, { .irq = -1 }, @@ -189,6 +201,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, + .dev_attr = &omap2430_mailbox_attrs, }; /* mcspi3 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 31c7126eb3bb..8e4cbc99ce28 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -25,6 +25,7 @@ #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/platform_data/iommu-omap.h> +#include <linux/platform_data/mailbox-omap.h> #include <plat/dmtimer.h> #include "am35xx.h" @@ -1505,6 +1506,17 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { .sysc = &omap3xxx_mailbox_sysc, }; +static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = { + { .name = "dsp", .tx_id = 0, .rx_id = 1 }, +}; + +static struct omap_mbox_pdata omap3xxx_mailbox_attrs = { + .num_users = 2, + .num_fifos = 2, + .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info), + .info = omap3xxx_mailbox_info, +}; + static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { { .irq = 26 + OMAP_INTC_START, }, { .irq = -1 }, @@ -1524,6 +1536,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, }, }, + .dev_attr = &omap3xxx_mailbox_attrs, }; /* diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig index 13bae78b215a..b1022f4315f7 100644 --- a/arch/arm/mach-picoxcell/Kconfig +++ b/arch/arm/mach-picoxcell/Kconfig @@ -4,7 +4,6 @@ config ARCH_PICOXCELL select ARM_PATCH_PHYS_VIRT select ARM_VIC select CPU_V6K - select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select HAVE_TCM diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index 70b441ad1d18..7cde0424d33c 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -15,7 +15,6 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/dw_apb_timer.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -88,7 +87,6 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .map_io = picoxcell_map_io, .nr_irqs = NR_IRQS_LEGACY, .init_irq = irqchip_init, - .init_time = dw_apb_timer_init, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, .restart = picoxcell_wdt_restart, diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index f2f7088bfd22..7ef71198fc11 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -28,7 +28,7 @@ config CPU_S3C2410 select CPU_ARM920T select CPU_LLSERIAL_S3C2410 select S3C2410_CLOCK - select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX + select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ select S3C2410_PM if PM select SAMSUNG_HRT help @@ -204,27 +204,38 @@ config S3C24XX_GPIO_EXTRA128 Add an extra 128 gpio numbers to the available GPIO pool. This is available for boards that need extra gpios for external devices. +config S3C24XX_PLL + bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" + depends on ARM_S3C24XX + help + Compile in support for changing the PLL frequency from the + S3C24XX series CPUfreq driver. The PLL takes time to settle + after a frequency change, so by default it is not enabled. + + This also means that the PLL tables for the selected CPU(s) will + be built which may increase the size of the kernel image. + # cpu frequency items common between s3c2410 and s3c2440/s3c2442 config S3C2410_IOTIMING bool - depends on CPU_FREQ_S3C24XX + depends on ARM_S3C24XX_CPUFREQ help Internal node to select io timing code that is common to the s3c2410 and s3c2440/s3c2442 cpu frequency support. config S3C2410_CPUFREQ_UTILS - bool - depends on CPU_FREQ_S3C24XX - help - Internal node to select timing code that is common to the s3c2410 - and s3c2440/s3c244 cpu frequency support. + bool + depends on ARM_S3C24XX_CPUFREQ + help + Internal node to select timing code that is common to the s3c2410 + and s3c2440/s3c244 cpu frequency support. # cpu frequency support common to s3c2412, s3c2413 and s3c2442 config S3C2412_IOTIMING bool - depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) + depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443) help Intel node to select io timing code that is common to the s3c2412 and the s3c2443. @@ -233,16 +244,9 @@ config S3C2412_IOTIMING if CPU_S3C2410 -config S3C2410_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2410 - config S3C2410_PLL bool - depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL default y help Select the PLL table for the S3C2410 @@ -278,7 +282,7 @@ config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select ISA select MACH_BAST_IDE - select S3C2410_IOTIMING if S3C2410_CPUFREQ + select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ select S3C24XX_DCLK select S3C24XX_SIMTEC_NOR select S3C24XX_SIMTEC_PM if PM @@ -385,14 +389,6 @@ config CPU_S3C2412_ONLY !CPU_S3C2442 && !CPU_S3C2443 default y -config S3C2412_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX - default y - select S3C2412_IOTIMING - help - CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. - config S3C2412_DMA bool help @@ -490,18 +486,22 @@ config MACH_SMDK2416 help Say Y here if you are using an SMDK2416 +config MACH_S3C2416_DT + bool "Samsung S3C2416 machine using devicetree" + select CLKSRC_OF + select USE_OF + select PINCTRL + select PINCTRL_S3C24XX + help + Machine support for Samsung S3C2416 machines with device tree enabled. + Select this if a fdt blob is available for the S3C2416 SoC based board. + Note: This is under development and not all peripherals can be supported + with this machine file. + endif # CPU_S3C2416 if CPU_S3C2440 -config S3C2440_CPUFREQ - bool "S3C2440/S3C2442 CPU Frequency scaling support" - depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) - default y - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. - config S3C2440_DMA bool help @@ -521,15 +521,15 @@ config S3C2440_XTAL_16934400 config S3C2440_PLL_12000000 bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 - default y if CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000 + default y if S3C24XX_PLL help PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. config S3C2440_PLL_16934400 bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 - default y if CPU_FREQ_S3C24XX_PLL + depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400 + default y if S3C24XX_PLL help PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. @@ -583,7 +583,7 @@ config MACH_NEXCODER_2440 config MACH_OSIRIS bool "Simtec IM2440D20 (OSIRIS) module" - select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_12000000 select S3C24XX_DCLK select S3C24XX_GPIO_EXTRA128 @@ -655,7 +655,7 @@ config MACH_RX1950 bool "HP iPAQ rx1950" select I2C select PM_H1940 if PM - select S3C2410_IOTIMING if S3C2440_CPUFREQ + select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ select S3C2440_XTAL_16934400 select S3C24XX_DCLK select S3C24XX_PWM diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 6f46ecfc8396..7f54e5b954ca 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -17,13 +17,11 @@ obj- := obj-y += common.o obj-$(CONFIG_CPU_S3C2410) += s3c2410.o -obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o -obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o @@ -34,7 +32,6 @@ obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o -obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o @@ -59,9 +56,6 @@ obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o -obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o -obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o - # # machine support # following is ordered alphabetically by option text. @@ -85,6 +79,7 @@ obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o +obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h index 548ced42cbb7..548ced42cbb7 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.h +++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c index 663436d9db01..bd064c05c473 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c @@ -31,7 +31,7 @@ #include <plat/cpu-freq-core.h> #include <plat/clock.h> -#include "s3c2412.h" +#include <mach/s3c2412.h> #define print_ns(x) ((x) / 10), ((x) % 10) diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c new file mode 100644 index 000000000000..f50454a34f72 --- /dev/null +++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c @@ -0,0 +1,91 @@ +/* + * Samsung's S3C2416 flattened device tree enabled machine + * + * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> + * + * based on mach-exynos/mach-exynos4-dt.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clocksource.h> +#include <linux/irqchip.h> +#include <linux/of_platform.h> +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <mach/map.h> + +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/regs-serial.h> + +#include "common.h" + +/* + * The following lookup table is used to override device names when devices + * are registered from device tree. This is temporarily added to enable + * device tree support addition for the S3C2416 architecture. + * + * For drivers that require platform data to be provided from the machine + * file, a platform data pointer can also be supplied along with the + * devices names. Usually, the platform data elements that cannot be parsed + * from the device tree by the drivers (example: function pointers) are + * supplied. But it should be noted that this is a temporary mechanism and + * at some point, the drivers should be capable of parsing all the platform + * data from the device tree. + */ +static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART, + "s3c2440-uart.0", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000, + "s3c2440-uart.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000, + "s3c2440-uart.2", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000, + "s3c2440-uart.3", NULL), + OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0, + "s3c-sdhci.0", NULL), + OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1, + "s3c-sdhci.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC, + "s3c2440-i2c.0", NULL), + {}, +}; + +static void __init s3c2416_dt_map_io(void) +{ + s3c24xx_init_io(NULL, 0); + s3c24xx_init_clocks(12000000); +} + +static void __init s3c2416_dt_machine_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + s3c2416_auxdata_lookup, NULL); + + s3c_pm_init(); +} + +static char const *s3c2416_dt_compat[] __initdata = { + "samsung,s3c2416", + "samsung,s3c2450", + NULL +}; + +DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)") + /* Maintainer: Heiko Stuebner <heiko@sntech.de> */ + .dt_compat = s3c2416_dt_compat, + .map_io = s3c2416_dt_map_io, + .init_irq = irqchip_init, + .init_machine = s3c2416_dt_machine_init, + .init_time = clocksource_of_init, + .restart = s3c2416_restart, +MACHINE_END diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 1a517e2fe449..06da4d36bc7c 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -37,6 +37,7 @@ config ARCH_R8A7740 config ARCH_R8A7778 bool "R-Car M1 (R8A77780)" + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V7 select SH_CLK_CPG select ARM_GIC diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 45f78cadec1d..297bf5eec5ab 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -1026,10 +1026,8 @@ out: /* TouchScreen */ #ifdef CONFIG_AP4EVB_QHD -# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 # define GPIO_TSC_PORT 123 #else /* WVGA */ -# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 # define GPIO_TSC_PORT 40 #endif @@ -1037,22 +1035,12 @@ out: #define IRQ7 evt2irq(0x02e0) /* IRQ7A */ static int ts_get_pendown_state(void) { - int val; - - gpio_free(GPIO_TSC_IRQ); - - gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); - - val = gpio_get_value(GPIO_TSC_PORT); - - gpio_request(GPIO_TSC_IRQ, NULL); - - return !val; + return !gpio_get_value(GPIO_TSC_PORT); } static int ts_init(void) { - gpio_request(GPIO_TSC_IRQ, NULL); + gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); return 0; } @@ -1086,11 +1074,42 @@ static struct i2c_board_info i2c1_devices[] = { static const struct pinctrl_map ap4evb_pinctrl_map[] = { + /* CEU */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_clk_0", "ceu"), + /* FSIA (AK4643) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_data_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_data_out", "fsia"), + /* FSIB (HDMI) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", + "fsib_mclk_in", "fsib"), + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", + "hdmi", "hdmi"), + /* KEYSC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", + "keysc_in04_0", "keysc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372", + "keysc_out5", "keysc"), +#ifndef CONFIG_AP4EVB_QHD + /* LCDC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_data18", "lcd"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_sync", "lcd"), +#endif /* MMCIF */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", "mmc0_data8_0", "mmc0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", "mmc0_ctrl_0", "mmc0"), + /* SCIFA0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", + "scifa0_data", "scifa0"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_data4", "sdhi0"), @@ -1105,6 +1124,26 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = { "sdhi1_data4", "sdhi1"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", "sdhi1_ctrl", "sdhi1"), + /* SMSC911X */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "bsc_cs5a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "intc_irq6_0", "intc"), + /* TSC2007 */ +#ifdef CONFIG_AP4EVB_QHD + PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", + "intc_irq28_0", "intc"), +#else /* WVGA */ + PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372", + "intc_irq7_0", "intc"), +#endif + /* USBHS1 */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", + "usb1_vbus", "usb1"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", + "usb1_otg_id_0", "usb1"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372", + "usb1_otg_ctrl_0", "usb1"), }; #define GPIO_PORT9CR IOMEM(0xE6051009) @@ -1137,36 +1176,16 @@ static void __init ap4evb_init(void) ARRAY_SIZE(ap4evb_pinctrl_map)); sh7372_pinmux_init(); - /* enable SCIFA0 */ - gpio_request(GPIO_FN_SCIFA0_TXD, NULL); - gpio_request(GPIO_FN_SCIFA0_RXD, NULL); - - /* enable SMSC911X */ - gpio_request(GPIO_FN_CS5A, NULL); - gpio_request(GPIO_FN_IRQ6_39, NULL); - /* enable Debug switch (S6) */ gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL); gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL); gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); - /* USB enable */ - gpio_request(GPIO_FN_VBUS0_1, NULL); - gpio_request(GPIO_FN_IDIN_1_18, NULL); - gpio_request(GPIO_FN_PWEN_1_115, NULL); - gpio_request(GPIO_FN_OVCN_1_114, NULL); - gpio_request(GPIO_FN_EXTLP_1, NULL); - gpio_request(GPIO_FN_OVCN2_1, NULL); - /* setup USB phy */ __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */ - /* enable FSI2 port A (ak4643) */ - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAISLD, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); + /* FSI2 port A (ak4643) */ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ gpio_request(9, NULL); @@ -1177,8 +1196,7 @@ static void __init ap4evb_init(void) /* card detect pin for MMC slot (CN7) */ gpio_request_one(41, GPIOF_IN, NULL); - /* setup FSI2 port B (HDMI) */ - gpio_request(GPIO_FN_FSIBCK, NULL); + /* FSI2 port B (HDMI) */ __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ /* set SPU2 clock to 119.6 MHz */ @@ -1208,18 +1226,6 @@ static void __init ap4evb_init(void) * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON. */ - /* enable KEYSC */ - gpio_request(GPIO_FN_KEYOUT0, NULL); - gpio_request(GPIO_FN_KEYOUT1, NULL); - gpio_request(GPIO_FN_KEYOUT2, NULL); - gpio_request(GPIO_FN_KEYOUT3, NULL); - gpio_request(GPIO_FN_KEYOUT4, NULL); - gpio_request(GPIO_FN_KEYIN0_136, NULL); - gpio_request(GPIO_FN_KEYIN1_135, NULL); - gpio_request(GPIO_FN_KEYIN2_134, NULL); - gpio_request(GPIO_FN_KEYIN3_133, NULL); - gpio_request(GPIO_FN_KEYIN4, NULL); - /* enable TouchScreen */ irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); @@ -1241,28 +1247,6 @@ static void __init ap4evb_init(void) * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF. */ - - gpio_request(GPIO_FN_LCDD17, NULL); - gpio_request(GPIO_FN_LCDD16, NULL); - gpio_request(GPIO_FN_LCDD15, NULL); - gpio_request(GPIO_FN_LCDD14, NULL); - gpio_request(GPIO_FN_LCDD13, NULL); - gpio_request(GPIO_FN_LCDD12, NULL); - gpio_request(GPIO_FN_LCDD11, NULL); - gpio_request(GPIO_FN_LCDD10, NULL); - gpio_request(GPIO_FN_LCDD9, NULL); - gpio_request(GPIO_FN_LCDD8, NULL); - gpio_request(GPIO_FN_LCDD7, NULL); - gpio_request(GPIO_FN_LCDD6, NULL); - gpio_request(GPIO_FN_LCDD5, NULL); - gpio_request(GPIO_FN_LCDD4, NULL); - gpio_request(GPIO_FN_LCDD3, NULL); - gpio_request(GPIO_FN_LCDD2, NULL); - gpio_request(GPIO_FN_LCDD1, NULL); - gpio_request(GPIO_FN_LCDD0, NULL); - gpio_request(GPIO_FN_LCDDISP, NULL); - gpio_request(GPIO_FN_LCDDCK, NULL); - gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ @@ -1288,8 +1272,6 @@ static void __init ap4evb_init(void) */ /* MIPI-CSI stuff */ - gpio_request(GPIO_FN_VIO_CKO, NULL); - clk = clk_get(NULL, "vck1_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 13000000)); @@ -1299,10 +1281,6 @@ static void __init ap4evb_init(void) sh7372_add_standard_devices(); - /* HDMI */ - gpio_request(GPIO_FN_HDMI_HPD, NULL); - gpio_request(GPIO_FN_HDMI_CEC, NULL); - /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ #define SRCR4 IOMEM(0xe61580bc) srcr4 = __raw_readl(SRCR4); diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index b85b2882dbd0..44a621505eeb 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = { static struct fixed_voltage_config vcc_sdhi0_info = { .supply_name = "SDHI0 Vcc", .microvolts = 3300000, - .gpio = GPIO_PORT75, + .gpio = 75, .enable_high = 1, .init_data = &vcc_sdhi0_init_data, }; @@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = { }; static struct gpio vccq_sdhi0_gpios[] = { - {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, + {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, }; static struct gpio_regulator_state vccq_sdhi0_states[] = { @@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = { static struct gpio_regulator_config vccq_sdhi0_info = { .supply_name = "vqmmc", - .enable_gpio = GPIO_PORT74, + .enable_gpio = 74, .enable_high = 1, .enabled_at_boot = 0, @@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = { static struct fixed_voltage_config vcc_sdhi1_info = { .supply_name = "SDHI1 Vcc", .microvolts = 3300000, - .gpio = GPIO_PORT16, + .gpio = 16, .enable_high = 1, .init_data = &vcc_sdhi1_init_data, }; @@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, - .cd_gpio = GPIO_PORT167, + .cd_gpio = 167, }; static struct resource sdhi0_resources[] = { @@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = { MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, /* Port72 cannot generate IRQs, will be used in polling mode. */ - .cd_gpio = GPIO_PORT72, + .cd_gpio = 72, }; static struct resource sdhi1_resources[] = { @@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = { }; static const struct pinctrl_map eva_pinctrl_map[] = { + /* CEU0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_data_0_7", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_clk_0", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_sync", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_field", "ceu0"), + /* FSIA */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_mclk_out", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_data_in_1", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_data_out_0", "fsia"), + /* FSIB */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740", + "fsib_mclk_in", "fsib"), + /* GETHER */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_mii", "gether"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_int", "gether"), + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740", + "hdmi", "hdmi"), /* LCD0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", "lcd0_data24_0", "lcd0"), @@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { "mmc0_data8_1", "mmc0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", "mmc0_ctrl_1", "mmc0"), + /* SCIFA1 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", + "scifa1_data", "scifa1"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", "sdhi0_data4", "sdhi0"), @@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = { "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", "sdhi0_wp", "sdhi0"), + /* ST1232 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", + "intc_irq10", "intc"), + /* USBHS */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", + "intc_irq7_1", "intc"), }; static void __init eva_clock_init(void) @@ -1119,40 +1157,14 @@ static void __init eva_init(void) r8a7740_pinmux_init(); r8a7740_meram_workaround(); - /* SCIFA1 */ - gpio_request(GPIO_FN_SCIFA1_RXD, NULL); - gpio_request(GPIO_FN_SCIFA1_TXD, NULL); - /* LCDC0 */ - gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ /* Touchscreen */ - gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ + gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ /* GETHER */ - gpio_request(GPIO_FN_ET_CRS, NULL); - gpio_request(GPIO_FN_ET_MDC, NULL); - gpio_request(GPIO_FN_ET_MDIO, NULL); - gpio_request(GPIO_FN_ET_TX_ER, NULL); - gpio_request(GPIO_FN_ET_RX_ER, NULL); - gpio_request(GPIO_FN_ET_ERXD0, NULL); - gpio_request(GPIO_FN_ET_ERXD1, NULL); - gpio_request(GPIO_FN_ET_ERXD2, NULL); - gpio_request(GPIO_FN_ET_ERXD3, NULL); - gpio_request(GPIO_FN_ET_TX_CLK, NULL); - gpio_request(GPIO_FN_ET_TX_EN, NULL); - gpio_request(GPIO_FN_ET_ETXD0, NULL); - gpio_request(GPIO_FN_ET_ETXD1, NULL); - gpio_request(GPIO_FN_ET_ETXD2, NULL); - gpio_request(GPIO_FN_ET_ETXD3, NULL); - gpio_request(GPIO_FN_ET_PHY_INT, NULL); - gpio_request(GPIO_FN_ET_COL, NULL); - gpio_request(GPIO_FN_ET_RX_DV, NULL); - gpio_request(GPIO_FN_ET_RX_CLK, NULL); - gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ /* USB */ @@ -1163,34 +1175,17 @@ static void __init eva_init(void) } else { /* USB Func */ /* - * A1 chip has 2 IRQ7 pin and it was controled by MSEL register. - * OTOH, usbhs interrupt needs its value (HI/LOW) to decide - * USB connection/disconnection (usbhsf_get_vbus()). - * This means we needs to select GPIO_FN_IRQ7_PORT209 first, - * and select GPIO 209 here + * The USBHS interrupt handlers needs to read the IRQ pin value + * (HI/LOW) to diffentiate USB connection and disconnection + * events (usbhsf_get_vbus()). We thus need to select both the + * intc_irq7_1 pin group and GPIO 209 here. */ - gpio_request(GPIO_FN_IRQ7_PORT209, NULL); gpio_request_one(209, GPIOF_IN, NULL); platform_device_register(&usbhsf_device); usb = &usbhsf_device; } - /* CEU0 */ - gpio_request(GPIO_FN_VIO0_D7, NULL); - gpio_request(GPIO_FN_VIO0_D6, NULL); - gpio_request(GPIO_FN_VIO0_D5, NULL); - gpio_request(GPIO_FN_VIO0_D4, NULL); - gpio_request(GPIO_FN_VIO0_D3, NULL); - gpio_request(GPIO_FN_VIO0_D2, NULL); - gpio_request(GPIO_FN_VIO0_D1, NULL); - gpio_request(GPIO_FN_VIO0_D0, NULL); - gpio_request(GPIO_FN_VIO0_CLK, NULL); - gpio_request(GPIO_FN_VIO0_HD, NULL); - gpio_request(GPIO_FN_VIO0_VD, NULL); - gpio_request(GPIO_FN_VIO0_FIELD, NULL); - gpio_request(GPIO_FN_VIO_CKO, NULL); - /* CON1/CON15 Camera */ gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ @@ -1198,24 +1193,11 @@ static void __init eva_init(void) gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ /* FSI-WM8978 */ - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAOMC, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); - gpio_request(7, NULL); gpio_request(8, NULL); gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ - /* FSI-HDMI */ - gpio_request(GPIO_FN_FSIBCK, NULL); - - /* HDMI */ - gpio_request(GPIO_FN_HDMI_HPD, NULL); - gpio_request(GPIO_FN_HDMI_CEC, NULL); - /* * CAUTION * diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 38e5e50fb318..dac4365c5158 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/pinctrl/machine.h> #include <linux/platform_device.h> #include <linux/smsc911x.h> #include <mach/common.h> @@ -37,6 +38,14 @@ static struct resource smsc911x_resources[] = { DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ }; +static const struct pinctrl_map bockw_pinctrl_map[] = { + /* SCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_data_a", "scif0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_ctrl", "scif0"), +}; + #define IRQ0MR 0x30 static void __init bockw_init(void) { @@ -46,6 +55,10 @@ static void __init bockw_init(void) r8a7778_init_irq_extpin(1); r8a7778_add_standard_devices(); + pinctrl_register_mappings(bockw_pinctrl_map, + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); + fpga = ioremap_nocache(0x18200000, SZ_1M); if (fpga) { /* diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c index 70d992c540ae..b373e9ced573 100644 --- a/arch/arm/mach-shmobile/board-bonito.c +++ b/arch/arm/mach-shmobile/board-bonito.c @@ -331,12 +331,6 @@ static struct platform_device smsc_device = { }; /* - * core board devices - */ -static struct platform_device *bonito_core_devices[] __initdata = { -}; - -/* * base board devices */ static struct platform_device *bonito_base_devices[] __initdata = { @@ -375,12 +369,37 @@ static void __init bonito_map_io(void) #define VCCQ1CR IOMEM(0xE6058140) #define VCCQ1LCDCR IOMEM(0xE6058186) +/* + * HACK: The FPGA mappings should be associated with the FPGA device, but we + * don't have one at the moment. Associate them with the PFC device to make + * sure they will be applied. + */ +static const struct pinctrl_map fpga_pinctrl_map[] = { + /* FPGA */ + PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", + "bsc_cs5a_0", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", + "bsc_cs5b", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", + "bsc_cs6a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740", + "intc_irq10", "intc"), +}; + +static const struct pinctrl_map scifa5_pinctrl_map[] = { + /* SCIFA5 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740", + "scifa5_data_2", "scifa5"), +}; + static void __init bonito_init(void) { u16 val; regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + pinctrl_register_mappings(fpga_pinctrl_map, + ARRAY_SIZE(fpga_pinctrl_map)); r8a7740_pinmux_init(); bonito_fpga_init(); @@ -397,9 +416,6 @@ static void __init bonito_init(void) r8a7740_add_standard_devices(); - platform_add_devices(bonito_core_devices, - ARRAY_SIZE(bonito_core_devices)); - /* * base board settings */ @@ -409,14 +425,6 @@ static void __init bonito_init(void) u16 bsw3; u16 bsw4; - /* - * FPGA - */ - gpio_request(GPIO_FN_CS5B, NULL); - gpio_request(GPIO_FN_CS6A, NULL); - gpio_request(GPIO_FN_CS5A_PORT105, NULL); - gpio_request(GPIO_FN_IRQ10, NULL); - val = bonito_fpga_read(BVERR); pr_info("bonito version: cpu %02x, base %02x\n", ((val >> 8) & 0xFF), @@ -432,8 +440,8 @@ static void __init bonito_init(void) if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */ BIT_OFF(bsw3, 9) && /* S39.6 = ON */ BIT_OFF(bsw4, 4)) { /* S43.1 = ON */ - gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL); - gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL); + pinctrl_register_mappings(scifa5_pinctrl_map, + ARRAY_SIZE(scifa5_pinctrl_map)); } /* @@ -443,7 +451,6 @@ static void __init bonito_init(void) BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ pinctrl_register_mappings(lcdc0_pinctrl_map, ARRAY_SIZE(lcdc0_pinctrl_map)); - gpio_request(GPIO_FN_LCDC0_SELECT, NULL); gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index aefa50d385b7..44055fe8a45c 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -79,7 +79,6 @@ static void __init kzm_init(void) sh73a0_pinmux_init(); /* enable SD */ - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index e6b775a10aad..1fdf05cb6da1 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -663,13 +663,13 @@ static unsigned long pin_pullup_conf[] = { static const struct pinctrl_map kzm_pinctrl_map[] = { /* FSIA (AK4648) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_mclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_data_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_data_out", "fsia"), /* I2C3 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", @@ -788,9 +788,6 @@ static void __init kzm_init(void) /* Touchscreen */ gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ - /* enable SD */ - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index f587187a8603..6114edd0a977 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -21,15 +21,30 @@ #include <linux/interrupt.h> #include <linux/irqchip.h> #include <linux/kernel.h> +#include <linux/pinctrl/machine.h> #include <linux/platform_device.h> #include <mach/common.h> #include <mach/r8a7790.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", + "scif0_data", "scif0"), + /* SCIF1 (CN20: DEBUG SERIAL1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", + "scif1_data", "scif1"), +}; + static void __init lager_add_standard_devices(void) { r8a7790_clock_init(); + + pinctrl_register_mappings(lager_pinctrl_map, + ARRAY_SIZE(lager_pinctrl_map)); + r8a7790_pinmux_init(); + r8a7790_add_standard_devices(); } diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index fa3407da682a..85f51a849a50 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = { }; static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* ADXL34X */ + PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372", + "intc_irq21", "intc"), + /* CEU */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_data_0_7", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_clk_0", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_sync", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_field", "ceu"), + /* FLCTL */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_data", "flctl"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_ce0", "flctl"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_ctrl", "flctl"), + /* FSIA (AK4643) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_data_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_data_out", "fsia"), + /* FSIB (HDMI) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", + "fsib_mclk_in", "fsib"), + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", + "hdmi", "hdmi"), + /* LCDC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_data24", "lcd"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_sync", "lcd"), + /* SCIFA0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", + "scifa0_data", "scifa0"), + /* SCIFA2 (GT-720F GPS module) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372", + "scifa2_data", "scifa2"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_data4", "sdhi0"), @@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_wp", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "intc_irq26_1", "intc"), /* SDHI1 */ #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", @@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { "sdhi2_data4", "sdhi2"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", "sdhi2_ctrl", "sdhi2"), + /* SMSC911X */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "bsc_cs5a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "intc_irq6_0", "intc"), + /* ST1232 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372", + "intc_irq7_0", "intc"), + /* TCA6416 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372", + "intc_irq9_0", "intc"), + /* USBHS0 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", + "usb0_vbus", "usb0"), + /* USBHS1 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", + "usb1_vbus", "usb1"), + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", + "usb1_otg_id_0", "usb1"), }; #define GPIO_PORT9CR IOMEM(0xE6051009) @@ -1377,61 +1441,18 @@ static void __init mackerel_init(void) ARRAY_SIZE(mackerel_pinctrl_map)); sh7372_pinmux_init(); - /* enable SCIFA0 */ - gpio_request(GPIO_FN_SCIFA0_TXD, NULL); - gpio_request(GPIO_FN_SCIFA0_RXD, NULL); - - /* enable SMSC911X */ - gpio_request(GPIO_FN_CS5A, NULL); - gpio_request(GPIO_FN_IRQ6_39, NULL); - - /* LCDC */ - gpio_request(GPIO_FN_LCDD23, NULL); - gpio_request(GPIO_FN_LCDD22, NULL); - gpio_request(GPIO_FN_LCDD21, NULL); - gpio_request(GPIO_FN_LCDD20, NULL); - gpio_request(GPIO_FN_LCDD19, NULL); - gpio_request(GPIO_FN_LCDD18, NULL); - gpio_request(GPIO_FN_LCDD17, NULL); - gpio_request(GPIO_FN_LCDD16, NULL); - gpio_request(GPIO_FN_LCDD15, NULL); - gpio_request(GPIO_FN_LCDD14, NULL); - gpio_request(GPIO_FN_LCDD13, NULL); - gpio_request(GPIO_FN_LCDD12, NULL); - gpio_request(GPIO_FN_LCDD11, NULL); - gpio_request(GPIO_FN_LCDD10, NULL); - gpio_request(GPIO_FN_LCDD9, NULL); - gpio_request(GPIO_FN_LCDD8, NULL); - gpio_request(GPIO_FN_LCDD7, NULL); - gpio_request(GPIO_FN_LCDD6, NULL); - gpio_request(GPIO_FN_LCDD5, NULL); - gpio_request(GPIO_FN_LCDD4, NULL); - gpio_request(GPIO_FN_LCDD3, NULL); - gpio_request(GPIO_FN_LCDD2, NULL); - gpio_request(GPIO_FN_LCDD1, NULL); - gpio_request(GPIO_FN_LCDD0, NULL); - gpio_request(GPIO_FN_LCDDISP, NULL); - gpio_request(GPIO_FN_LCDDCK, NULL); - /* backlight, off by default */ gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ /* USBHS0 */ - gpio_request(GPIO_FN_VBUS0_0, NULL); gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */ /* USBHS1 */ - gpio_request(GPIO_FN_VBUS0_1, NULL); gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */ - gpio_request(GPIO_FN_IDIN_1_113, NULL); - /* enable FSI2 port A (ak4643) */ - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAISLD, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); + /* FSI2 port A (ak4643) */ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ gpio_request(9, NULL); @@ -1441,8 +1462,7 @@ static void __init mackerel_init(void) intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ - /* setup FSI2 port B (HDMI) */ - gpio_request(GPIO_FN_FSIBCK, NULL); + /* FSI2 port B (HDMI) */ __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ /* set SPU2 clock to 119.6 MHz */ @@ -1452,68 +1472,15 @@ static void __init mackerel_init(void) clk_put(clk); } - /* enable Keypad */ - gpio_request(GPIO_FN_IRQ9_42, NULL); + /* Keypad */ irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); - /* enable Touchscreen */ - gpio_request(GPIO_FN_IRQ7_40, NULL); + /* Touchscreen */ irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); - /* enable Accelerometer */ - gpio_request(GPIO_FN_IRQ21, NULL); + /* Accelerometer */ irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); - /* SDHI0 PORT172 card-detect IRQ26 */ - gpio_request(GPIO_FN_IRQ26_172, NULL); - - /* FLCTL */ - gpio_request(GPIO_FN_D0_NAF0, NULL); - gpio_request(GPIO_FN_D1_NAF1, NULL); - gpio_request(GPIO_FN_D2_NAF2, NULL); - gpio_request(GPIO_FN_D3_NAF3, NULL); - gpio_request(GPIO_FN_D4_NAF4, NULL); - gpio_request(GPIO_FN_D5_NAF5, NULL); - gpio_request(GPIO_FN_D6_NAF6, NULL); - gpio_request(GPIO_FN_D7_NAF7, NULL); - gpio_request(GPIO_FN_D8_NAF8, NULL); - gpio_request(GPIO_FN_D9_NAF9, NULL); - gpio_request(GPIO_FN_D10_NAF10, NULL); - gpio_request(GPIO_FN_D11_NAF11, NULL); - gpio_request(GPIO_FN_D12_NAF12, NULL); - gpio_request(GPIO_FN_D13_NAF13, NULL); - gpio_request(GPIO_FN_D14_NAF14, NULL); - gpio_request(GPIO_FN_D15_NAF15, NULL); - gpio_request(GPIO_FN_FCE0, NULL); - gpio_request(GPIO_FN_WE0_FWE, NULL); - gpio_request(GPIO_FN_FRB, NULL); - gpio_request(GPIO_FN_A4_FOE, NULL); - gpio_request(GPIO_FN_A5_FCDE, NULL); - gpio_request(GPIO_FN_RD_FSC, NULL); - - /* enable GPS module (GT-720F) */ - gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); - gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); - - /* CEU */ - gpio_request(GPIO_FN_VIO_CLK, NULL); - gpio_request(GPIO_FN_VIO_VD, NULL); - gpio_request(GPIO_FN_VIO_HD, NULL); - gpio_request(GPIO_FN_VIO_FIELD, NULL); - gpio_request(GPIO_FN_VIO_CKO, NULL); - gpio_request(GPIO_FN_VIO_D7, NULL); - gpio_request(GPIO_FN_VIO_D6, NULL); - gpio_request(GPIO_FN_VIO_D5, NULL); - gpio_request(GPIO_FN_VIO_D4, NULL); - gpio_request(GPIO_FN_VIO_D3, NULL); - gpio_request(GPIO_FN_VIO_D2, NULL); - gpio_request(GPIO_FN_VIO_D1, NULL); - gpio_request(GPIO_FN_VIO_D0, NULL); - - /* HDMI */ - gpio_request(GPIO_FN_HDMI_HPD, NULL); - gpio_request(GPIO_FN_HDMI_CEC, NULL); - /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ srcr4 = __raw_readl(SRCR4); __raw_writel(srcr4 | (1 << 13), SRCR4); diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index b9594e911ce7..9112faef923b 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -28,6 +28,7 @@ #include <linux/leds.h> #include <linux/dma-mapping.h> #include <linux/pinctrl/machine.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/smsc911x.h> @@ -173,15 +174,15 @@ static struct platform_device usb_phy_device = { static struct gpio_led marzen_leds[] = { { .name = "led2", - .gpio = 157, + .gpio = RCAR_GP_PIN(4, 29), .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led3", - .gpio = 158, + .gpio = RCAR_GP_PIN(4, 30), .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led4", - .gpio = 159, + .gpio = RCAR_GP_PIN(4, 31), .default_state = LEDS_GPIO_DEFSTATE_ON, }, }; diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index b2074e2acb15..d241bfd6926d 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -16,4 +16,9 @@ #define IRQPIN_BASE 2000 #define irq_pin(nr) ((nr) + IRQPIN_BASE) +/* GPIO IRQ */ +#define _GPIO_IRQ_BASE 2500 +#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) +#define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y) + #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index abdc4d4efa28..9c9a66ccaf6f 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -28,494 +28,6 @@ #define MD_CK1 (1 << 1) #define MD_CK0 (1 << 0) -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, - - GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, - GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, - - GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, - - /* IRQ */ - GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, - GPIO_FN_IRQ1, - GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, - GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, - GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, - GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, - GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, - GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, - GPIO_FN_IRQ8, - GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, - GPIO_FN_IRQ10, - GPIO_FN_IRQ11, - GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, - GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, - GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, - GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, - GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, - GPIO_FN_IRQ17, - GPIO_FN_IRQ18, - GPIO_FN_IRQ19, - GPIO_FN_IRQ20, - GPIO_FN_IRQ21, - GPIO_FN_IRQ22, - GPIO_FN_IRQ23, - GPIO_FN_IRQ24, - GPIO_FN_IRQ25, - GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, - GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, - GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, - GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, - GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, - GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, - - /* Function */ - - /* DBGT */ - GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, - GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, - GPIO_FN_DBGMD21, - - /* FSI-A */ - GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ - GPIO_FN_FSIAISLD_PORT5, - GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ - GPIO_FN_FSIASPDIF_PORT18, - GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, - GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, - GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, - GPIO_FN_FSIACK, GPIO_FN_FSIAILR, - GPIO_FN_FSIAIBT, - - /* FSI-B */ - GPIO_FN_FSIBCK, - - /* FMSI */ - GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ - GPIO_FN_FMSISLD_PORT6, - GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, - GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, - GPIO_FN_FMSICK, GPIO_FN_FMSOILR, - GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, - GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, - GPIO_FN_FMSOCK, - - /* SCIFA0 */ - GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, - GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_TXD, - - /* SCIFA1 */ - GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, - GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, - GPIO_FN_SCIFA1_RTS, - - /* SCIFA2 */ - GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ - GPIO_FN_SCIFA2_SCK_PORT199, - GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, - GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, - - /* SCIFA3 */ - GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ - GPIO_FN_SCIFA3_SCK_PORT116, - GPIO_FN_SCIFA3_CTS_PORT117, - GPIO_FN_SCIFA3_RXD_PORT174, - GPIO_FN_SCIFA3_TXD_PORT175, - - GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ - GPIO_FN_SCIFA3_SCK_PORT158, - GPIO_FN_SCIFA3_CTS_PORT162, - GPIO_FN_SCIFA3_RXD_PORT159, - GPIO_FN_SCIFA3_TXD_PORT160, - - /* SCIFA4 */ - GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ - GPIO_FN_SCIFA4_TXD_PORT13, - - GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ - GPIO_FN_SCIFA4_TXD_PORT203, - - GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ - GPIO_FN_SCIFA4_TXD_PORT93, - - GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ - GPIO_FN_SCIFA4_SCK_PORT205, - - /* SCIFA5 */ - GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ - GPIO_FN_SCIFA5_RXD_PORT10, - - GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ - GPIO_FN_SCIFA5_TXD_PORT208, - - GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ - GPIO_FN_SCIFA5_RXD_PORT92, - - GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ - GPIO_FN_SCIFA5_SCK_PORT206, - - /* SCIFA6 */ - GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, - - /* SCIFA7 */ - GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, - - /* SCIFAB */ - GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ - GPIO_FN_SCIFB_RXD_PORT191, - GPIO_FN_SCIFB_TXD_PORT192, - GPIO_FN_SCIFB_RTS_PORT186, - GPIO_FN_SCIFB_CTS_PORT187, - - GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ - GPIO_FN_SCIFB_RXD_PORT3, - GPIO_FN_SCIFB_TXD_PORT4, - GPIO_FN_SCIFB_RTS_PORT172, - GPIO_FN_SCIFB_CTS_PORT173, - - /* LCD0 */ - GPIO_FN_LCDC0_SELECT, - - /* LCD1 */ - GPIO_FN_LCDC1_SELECT, - - /* RSPI */ - GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, - GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, - GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, - GPIO_FN_RSPI_CK_A, - - /* VIO CKO */ - GPIO_FN_VIO_CKO1, - GPIO_FN_VIO_CKO2, - GPIO_FN_VIO_CKO_1, - GPIO_FN_VIO_CKO, - - /* VIO0 */ - GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, - GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, - GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, - GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, - GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, - GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, - - GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ - GPIO_FN_VIO0_D14_PORT25, - GPIO_FN_VIO0_D15_PORT24, - - GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ - GPIO_FN_VIO0_D14_PORT95, - GPIO_FN_VIO0_D15_PORT96, - - /* VIO1 */ - GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, - GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, - GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, - GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, - - /* TPU0 */ - GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, - GPIO_FN_TPU0TO3, - GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ - GPIO_FN_TPU0TO2_PORT202, - - /* SSP1 0 */ - GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, - GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, - GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, - GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, - - /* SSP1 1 */ - GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, - GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, - GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, - - GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ - GPIO_FN_STP1_IPEN_PORT187, - - GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ - GPIO_FN_STP1_IPEN_PORT193, - - /* SIM */ - GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, - GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ - GPIO_FN_SIM_D_PORT199, - - /* MSIOF2 */ - GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, - GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_MSIOF2_RSCK, - - /* KEYSC */ - GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, - GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, - GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, - GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, - GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, - - GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ - GPIO_FN_KEYIN1_PORT44, - GPIO_FN_KEYIN2_PORT45, - GPIO_FN_KEYIN3_PORT46, - - GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ - GPIO_FN_KEYIN1_PORT57, - GPIO_FN_KEYIN2_PORT56, - GPIO_FN_KEYIN3_PORT55, - - /* VOU */ - GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, - GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, - GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, - GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, - GPIO_FN_DV_CLK, - GPIO_FN_DV_VSYNC, - GPIO_FN_DV_HSYNC, - - /* MEMC */ - GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, - GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, - GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, - GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, - GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, - GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, - GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, - - GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ - GPIO_FN_MEMC_ADV, - GPIO_FN_MEMC_WAIT, - GPIO_FN_MEMC_BUSCLK, - - GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ - GPIO_FN_MEMC_DREQ0, - GPIO_FN_MEMC_DREQ1, - GPIO_FN_MEMC_A0, - - /* MSIOF0 */ - GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, - GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, - GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, - - /* MSIOF1 */ - GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, - - GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, - GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, - GPIO_FN_MSIOF1_TSYNC_PORT120, - GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ - - GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, - GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, - GPIO_FN_MSIOF1_RXD_PORT75, - GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN_GPO0, GPIO_FN_GPI0, - GPIO_FN_GPO1, GPIO_FN_GPI1, - - /* USB0 */ - GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, - - /* USB1 */ - GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, - - /* BBIF1 */ - GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, - GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, - - /* BBIF2 */ - GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ - GPIO_FN_BBIF2_RXD2_PORT60, - GPIO_FN_BBIF2_TSYNC2_PORT6, - GPIO_FN_BBIF2_TSCK2_PORT59, - - GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ - GPIO_FN_BBIF2_TXD2_PORT183, - GPIO_FN_BBIF2_TSCK2_PORT89, - GPIO_FN_BBIF2_TSYNC2_PORT184, - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, - GPIO_FN_CS5B, GPIO_FN_CS6A, - GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ - GPIO_FN_CS5A_PORT19, - GPIO_FN_IOIS16, /* ? */ - - GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, - GPIO_FN_A4_FOE, /* share with FLCTL */ - GPIO_FN_A5_FCDE, /* share with FLCTL */ - GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, - GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, - GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, - GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, - GPIO_FN_A26, - - GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ - GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ - GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ - GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ - GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ - GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ - GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ - GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ - - GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, - GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, - GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, - GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, - - GPIO_FN_WE0_FWE, /* share with FLCTL */ - GPIO_FN_WE1, - GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ - GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ - GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, - GPIO_FN_RD_FSC, /* share with FLCTL */ - GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ - GPIO_FN_WAIT_PORT90, - - GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ - - /* IRDA */ - GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, - - /* ATAPI */ - GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, - GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, - GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, - GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, - GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, - GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, - GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, - GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, - GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, - GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, - - /* RMII */ - GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, - GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, - GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, - GPIO_FN_RMII_REF50CK, /* for RMII */ - GPIO_FN_RMII_REF125CK, /* for GMII */ - - /* GEther */ - GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, - GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, - GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ - GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ - GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, - GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, - GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, - GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, - GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ - GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ - GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, - GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, - GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, - GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, - - /* DMA0 */ - GPIO_FN_DREQ0, GPIO_FN_DACK0, - - /* DMA1 */ - GPIO_FN_DREQ1, GPIO_FN_DACK1, - - /* SYSC */ - GPIO_FN_RESETOUTS, - GPIO_FN_RESETP_PULLUP, - GPIO_FN_RESETP_PLAIN, - - /* HDMI */ - GPIO_FN_HDMI_HPD, - GPIO_FN_HDMI_CEC, - - /* SDENC */ - GPIO_FN_SDENC_CPG, - GPIO_FN_SDENC_DV_CLKI, - - /* IRREM */ - GPIO_FN_IROUT, - - /* DEBUG */ - GPIO_FN_EDEBGREQ_PULLDOWN, - GPIO_FN_EDEBGREQ_PULLUP, - - GPIO_FN_TRACEAUD_FROM_VIO, - GPIO_FN_TRACEAUD_FROM_LCDC0, - GPIO_FN_TRACEAUD_FROM_MEMC, -}; - /* DMA slave IDs */ enum { SHDMA_SLAVE_INVALID, diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 951149e6bcca..68053fc4d9dc 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -28,5 +28,6 @@ extern void r8a7778_init_irq(void); extern void r8a7778_init_irq_dt(void); extern void r8a7778_clock_init(void); extern void r8a7778_init_irq_extpin(int irlm); +extern void r8a7778_pinmux_init(void); #endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index fd7cba024c39..e882717ca97f 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -15,397 +15,6 @@ #include <linux/pm_domain.h> #include <mach/pm-rmobile.h> -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, - - GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, - GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, - - GPIO_PORT190, - - /* IRQ */ - GPIO_FN_IRQ0_6, /* PORT 6 */ - GPIO_FN_IRQ0_162, /* PORT 162 */ - GPIO_FN_IRQ1, /* PORT 12 */ - GPIO_FN_IRQ2_4, /* PORT 4 */ - GPIO_FN_IRQ2_5, /* PORT 5 */ - GPIO_FN_IRQ3_8, /* PORT 8 */ - GPIO_FN_IRQ3_16, /* PORT 16 */ - GPIO_FN_IRQ4_17, /* PORT 17 */ - GPIO_FN_IRQ4_163, /* PORT 163 */ - GPIO_FN_IRQ5, /* PORT 18 */ - GPIO_FN_IRQ6_39, /* PORT 39 */ - GPIO_FN_IRQ6_164, /* PORT 164 */ - GPIO_FN_IRQ7_40, /* PORT 40 */ - GPIO_FN_IRQ7_167, /* PORT 167 */ - GPIO_FN_IRQ8_41, /* PORT 41 */ - GPIO_FN_IRQ8_168, /* PORT 168 */ - GPIO_FN_IRQ9_42, /* PORT 42 */ - GPIO_FN_IRQ9_169, /* PORT 169 */ - GPIO_FN_IRQ10, /* PORT 65 */ - GPIO_FN_IRQ11, /* PORT 67 */ - GPIO_FN_IRQ12_80, /* PORT 80 */ - GPIO_FN_IRQ12_137, /* PORT 137 */ - GPIO_FN_IRQ13_81, /* PORT 81 */ - GPIO_FN_IRQ13_145, /* PORT 145 */ - GPIO_FN_IRQ14_82, /* PORT 82 */ - GPIO_FN_IRQ14_146, /* PORT 146 */ - GPIO_FN_IRQ15_83, /* PORT 83 */ - GPIO_FN_IRQ15_147, /* PORT 147 */ - GPIO_FN_IRQ16_84, /* PORT 84 */ - GPIO_FN_IRQ16_170, /* PORT 170 */ - GPIO_FN_IRQ17, /* PORT 85 */ - GPIO_FN_IRQ18, /* PORT 86 */ - GPIO_FN_IRQ19, /* PORT 87 */ - GPIO_FN_IRQ20, /* PORT 92 */ - GPIO_FN_IRQ21, /* PORT 93 */ - GPIO_FN_IRQ22, /* PORT 94 */ - GPIO_FN_IRQ23, /* PORT 95 */ - GPIO_FN_IRQ24, /* PORT 112 */ - GPIO_FN_IRQ25, /* PORT 119 */ - GPIO_FN_IRQ26_121, /* PORT 121 */ - GPIO_FN_IRQ26_172, /* PORT 172 */ - GPIO_FN_IRQ27_122, /* PORT 122 */ - GPIO_FN_IRQ27_180, /* PORT 180 */ - GPIO_FN_IRQ28_123, /* PORT 123 */ - GPIO_FN_IRQ28_181, /* PORT 181 */ - GPIO_FN_IRQ29_129, /* PORT 129 */ - GPIO_FN_IRQ29_182, /* PORT 182 */ - GPIO_FN_IRQ30_130, /* PORT 130 */ - GPIO_FN_IRQ30_183, /* PORT 183 */ - GPIO_FN_IRQ31_138, /* PORT 138 */ - GPIO_FN_IRQ31_184, /* PORT 184 */ - - /* - * MSIOF0 (PORT 36, 37, 38, 39 - * 40, 41, 42, 43, 44, 45) - */ - GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_TSCK, - GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_MCK0, - GPIO_FN_MSIOF0_MCK1, GPIO_FN_MSIOF0_SS1, - GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TXD, - - /* - * MSIOF1 (PORT 39, 40, 41, 42, 43, 44 - * 84, 85, 86, 87, 88, 89, 90, 91, 92, 93) - */ - GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40, - GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89, - GPIO_FN_MSIOF1_TXD_41, GPIO_FN_MSIOF1_RXD_42, - GPIO_FN_MSIOF1_TXD_90, GPIO_FN_MSIOF1_RXD_91, - GPIO_FN_MSIOF1_SS1_43, GPIO_FN_MSIOF1_SS2_44, - GPIO_FN_MSIOF1_SS1_92, GPIO_FN_MSIOF1_SS2_93, - GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, - - /* - * MSIOF2 (PORT 134, 135, 136, 137, 138, 139 - * 148, 149, 150, 151) - */ - GPIO_FN_MSIOF2_RSCK, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_MCK1, - GPIO_FN_MSIOF2_SS1, GPIO_FN_MSIOF2_SS2, - GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TXD, - - /* MSIOF3 (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ - GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_TXD, - GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, - GPIO_FN_BBIF1_FLOW, GPIO_FN_BB_RX_FLOW_N, - - /* MSIOF4 (PORT 0, 1, 2, 3) */ - GPIO_FN_BBIF2_TSCK1, GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_BBIF2_TXD1, GPIO_FN_BBIF2_RXD, - - /* FSI (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */ - GPIO_FN_FSIACK, GPIO_FN_FSIBCK, - GPIO_FN_FSIAILR, GPIO_FN_FSIAIBT, - GPIO_FN_FSIAISLD, GPIO_FN_FSIAOMC, - GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, - GPIO_FN_FSIAOSLD, GPIO_FN_FSIASPDIF_11, - GPIO_FN_FSIASPDIF_15, - - /* FMSI (PORT 12, 13, 14, 15, 16, 17, 18, 65) */ - GPIO_FN_FMSOCK, GPIO_FN_FMSOOLR, - GPIO_FN_FMSIOLR, GPIO_FN_FMSOOBT, - GPIO_FN_FMSIOBT, GPIO_FN_FMSOSLD, - GPIO_FN_FMSOILR, GPIO_FN_FMSIILR, - GPIO_FN_FMSOIBT, GPIO_FN_FMSIIBT, - GPIO_FN_FMSISLD, GPIO_FN_FMSICK, - - /* SCIFA0 (PORT 152, 153, 156, 157, 158) */ - GPIO_FN_SCIFA0_TXD, GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_RTS, - GPIO_FN_SCIFA0_CTS, - - /* SCIFA1 (PORT 154, 155, 159, 160, 161) */ - GPIO_FN_SCIFA1_TXD, GPIO_FN_SCIFA1_RXD, - GPIO_FN_SCIFA1_SCK, GPIO_FN_SCIFA1_RTS, - GPIO_FN_SCIFA1_CTS, - - /* SCIFA2 (PORT 94, 95, 96, 97, 98) */ - GPIO_FN_SCIFA2_CTS1, GPIO_FN_SCIFA2_RTS1, - GPIO_FN_SCIFA2_TXD1, GPIO_FN_SCIFA2_RXD1, - GPIO_FN_SCIFA2_SCK1, - - /* SCIFA3 (PORT 43, 44, - 140, 141, 142, 143, 144) */ - GPIO_FN_SCIFA3_CTS_43, GPIO_FN_SCIFA3_CTS_140, - GPIO_FN_SCIFA3_RTS_44, GPIO_FN_SCIFA3_RTS_141, - GPIO_FN_SCIFA3_SCK, GPIO_FN_SCIFA3_TXD, - GPIO_FN_SCIFA3_RXD, - - /* SCIFA4 (PORT 5, 6) */ - GPIO_FN_SCIFA4_RXD, GPIO_FN_SCIFA4_TXD, - - /* SCIFA5 (PORT 8, 12) */ - GPIO_FN_SCIFA5_RXD, GPIO_FN_SCIFA5_TXD, - - /* SCIFB (PORT 162, 163, 164, 165, 166) */ - GPIO_FN_SCIFB_SCK, GPIO_FN_SCIFB_RTS, - GPIO_FN_SCIFB_CTS, GPIO_FN_SCIFB_TXD, - GPIO_FN_SCIFB_RXD, - - /* - * CEU (PORT 16, 17, - * 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, - * 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, - * 120) - */ - GPIO_FN_VIO_HD, GPIO_FN_VIO_CKO1, GPIO_FN_VIO_CKO2, - GPIO_FN_VIO_VD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, - GPIO_FN_VIO_CKO, - GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, - GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, - GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, - GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, - GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, - GPIO_FN_VIO_D15, - - /* USB0 (PORT 113, 114, 115, 116, 117, 167) */ - GPIO_FN_IDIN_0, GPIO_FN_EXTLP_0, - GPIO_FN_OVCN2_0, GPIO_FN_PWEN_0, - GPIO_FN_OVCN_0, GPIO_FN_VBUS0_0, - - /* USB1 (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */ - GPIO_FN_IDIN_1_18, GPIO_FN_IDIN_1_113, - GPIO_FN_PWEN_1_115, GPIO_FN_PWEN_1_138, - GPIO_FN_OVCN_1_114, GPIO_FN_OVCN_1_162, - GPIO_FN_EXTLP_1, GPIO_FN_OVCN2_1, - GPIO_FN_VBUS0_1, - - /* GPIO (PORT 41, 42, 43, 44) */ - GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPO0, GPIO_FN_GPO1, - - /* - * BSC (PORT 19, - * 20, 21, 22, 25, 26, 27, 28, 29, - * 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, - * 40, 41, 42, 43, 44, 45, - * 62, 63, 64, 65, 66, 67, - * 71, 72, 74, 75) - */ - GPIO_FN_BS, GPIO_FN_WE1, - GPIO_FN_CKO, GPIO_FN_WAIT, GPIO_FN_RDWR, - - GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, - GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, - GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, - GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, - GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, - GPIO_FN_A26, - - GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, - GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_CS6A, - - /* - * BSC/FLCTL (PORT 23, 24, - * 46, 47, 48, 49, - * 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, - * 60, 61, 69, 70) - */ - GPIO_FN_RD_FSC, GPIO_FN_WE0_FWE, - GPIO_FN_A4_FOE, GPIO_FN_A5_FCDE, - GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2, - GPIO_FN_D3_NAF3, GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, - GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, GPIO_FN_D8_NAF8, - GPIO_FN_D9_NAF9, GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, - GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, - GPIO_FN_D15_NAF15, - - /* SPU2 (PORT 65) */ - GPIO_FN_VINT_I, - - /* FLCTL (PORT 66, 68, 73) */ - GPIO_FN_FCE1, GPIO_FN_FCE0, GPIO_FN_FRB, - - /* HSI (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ - GPIO_FN_GP_RX_FLAG, GPIO_FN_GP_RX_DATA, GPIO_FN_GP_TX_READY, - GPIO_FN_GP_RX_WAKE, GPIO_FN_MP_TX_FLAG, GPIO_FN_MP_TX_DATA, - GPIO_FN_MP_RX_READY, GPIO_FN_MP_TX_WAKE, - - /* - * MFI (PORT 76, 77, 78, 79, - * 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, - * 90, 91, 92, 93, 94, 95, 96, 97, 98, 99) - */ - GPIO_FN_MFIv6, /* see MSEL4CR 6 */ - GPIO_FN_MFIv4, /* see MSEL4CR 6 */ - - GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_BUSCLK_MEMC_A0, - GPIO_FN_MEMC_CS1_MEMC_A1, GPIO_FN_MEMC_ADV_MEMC_DREQ0, - GPIO_FN_MEMC_WAIT_MEMC_DREQ1, GPIO_FN_MEMC_NOE, - GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_INT, - - GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, - GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, - GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, - GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, - GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, - GPIO_FN_MEMC_AD15, - - /* SIM (PORT 94, 95, 98) */ - GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, GPIO_FN_SIM_D, - - /* TPU (PORT 93, 99, 112, 160, 161) */ - GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, - GPIO_FN_TPU0TO2_93, GPIO_FN_TPU0TO2_99, - GPIO_FN_TPU0TO3, - - /* I2C2 (PORT 110, 111) */ - GPIO_FN_I2C_SCL2, GPIO_FN_I2C_SDA2, - - /* I2C3(1) (PORT 114, 115) */ - GPIO_FN_I2C_SCL3, GPIO_FN_I2C_SDA3, - - /* I2C3(2) (PORT 137, 145) */ - GPIO_FN_I2C_SCL3S, GPIO_FN_I2C_SDA3S, - - /* I2C4(2) (PORT 116, 117) */ - GPIO_FN_I2C_SCL4, GPIO_FN_I2C_SDA4, - - /* I2C4(2) (PORT 146, 147) */ - GPIO_FN_I2C_SCL4S, GPIO_FN_I2C_SDA4S, - - /* - * KEYSC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, - * 130, 131, 132, 133, 134, 135, 136) - */ - GPIO_FN_KEYOUT0, GPIO_FN_KEYIN0_121, GPIO_FN_KEYIN0_136, - GPIO_FN_KEYOUT1, GPIO_FN_KEYIN1_122, GPIO_FN_KEYIN1_135, - GPIO_FN_KEYOUT2, GPIO_FN_KEYIN2_123, GPIO_FN_KEYIN2_134, - GPIO_FN_KEYOUT3, GPIO_FN_KEYIN3_124, GPIO_FN_KEYIN3_133, - GPIO_FN_KEYOUT4, GPIO_FN_KEYIN4, - GPIO_FN_KEYOUT5, GPIO_FN_KEYIN5, - GPIO_FN_KEYOUT6, GPIO_FN_KEYIN6, - GPIO_FN_KEYOUT7, GPIO_FN_KEYIN7, - - /* - * LCDC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, - * 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, - * 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, - * 150, 151) - */ - GPIO_FN_LCDC0_SELECT, /* LCDC 0 */ - GPIO_FN_LCDC1_SELECT, /* LCDC 1 */ - GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDVSYN, - GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDRD, - GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDLCLK, - GPIO_FN_LCDDON, - - GPIO_FN_LCDD0, GPIO_FN_LCDD1, GPIO_FN_LCDD2, GPIO_FN_LCDD3, - GPIO_FN_LCDD4, GPIO_FN_LCDD5, GPIO_FN_LCDD6, GPIO_FN_LCDD7, - GPIO_FN_LCDD8, GPIO_FN_LCDD9, GPIO_FN_LCDD10, GPIO_FN_LCDD11, - GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15, - GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19, - GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23, - - /* IRDA (PORT 139, 140, 141, 142) */ - GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, - GPIO_FN_IROUT_139, GPIO_FN_IROUT_140, - - /* TSIF1 (PORT 156, 157, 158, 159) */ - GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */ - GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */ - GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */ - GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */ - - GPIO_FN_TS_SPSYNC1, GPIO_FN_TS_SDAT1, - GPIO_FN_TS_SDEN1, GPIO_FN_TS_SCK1, - - /* TSIF2 (PORT 137, 145, 146, 147) */ - GPIO_FN_TS_SPSYNC2, GPIO_FN_TS_SDAT2, - GPIO_FN_TS_SDEN2, GPIO_FN_TS_SCK2, - - /* HDMI (PORT 169, 170) */ - GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, - - /* SDENC see MSEL4CR 19 */ - GPIO_FN_SDENC_CPG, - GPIO_FN_SDENC_DV_CLKI, -}; - /* DMA slave IDs */ enum { SHDMA_SLAVE_INVALID, diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 326a4ab0bd5f..3a6b6fe7b6c0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -70,29 +70,15 @@ void __init r8a7740_map_io(void) } /* PFC */ -static struct resource r8a7740_pfc_resources[] = { - [0] = { - .start = 0xe6050000, - .end = 0xe6057fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xe605800c, - .end = 0xe605802b, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device r8a7740_pfc_device = { - .name = "pfc-r8a7740", - .id = -1, - .resource = r8a7740_pfc_resources, - .num_resources = ARRAY_SIZE(r8a7740_pfc_resources), +static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6050000, 0x8000), + DEFINE_RES_MEM(0xe605800c, 0x0020), }; void __init r8a7740_pinmux_init(void) { - platform_device_register(&r8a7740_pfc_device); + platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); } static struct renesas_intc_irqpin_config irqpin0_platform_data = { diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 30b4a336308f..1f36ecc322a3 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -24,6 +24,7 @@ #include <linux/irqchip/arm-gic.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <linux/platform_device.h> #include <linux/irqchip.h> @@ -94,6 +95,52 @@ static struct resource ether_resources[] = { &sh_tmu##idx##_platform_data, \ sizeof(sh_tmu##idx##_platform_data)) +/* PFC/GPIO */ +static struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xfffc0000, 0x118), +}; + +#define R8A7778_GPIO(idx) \ +static struct resource r8a7778_gpio##idx##_resources[] = { \ + DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ + DEFINE_RES_IRQ(gic_iid(0x87)), \ +}; \ + \ +static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ + .gpio_base = 32 * (idx), \ + .irq_base = GPIO_IRQ_BASE(idx), \ + .number_of_pins = 32, \ + .pctl_name = "pfc-r8a7778", \ +} + +R8A7778_GPIO(0); +R8A7778_GPIO(1); +R8A7778_GPIO(2); +R8A7778_GPIO(3); +R8A7778_GPIO(4); + +#define r8a7778_register_gpio(idx) \ + platform_device_register_resndata( \ + &platform_bus, "gpio_rcar", idx, \ + r8a7778_gpio##idx##_resources, \ + ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ + &r8a7778_gpio##idx##_platform_data, \ + sizeof(r8a7778_gpio##idx##_platform_data)) + +void __init r8a7778_pinmux_init(void) +{ + platform_device_register_simple( + "pfc-r8a7778", -1, + pfc_resources, + ARRAY_SIZE(pfc_resources)); + + r8a7778_register_gpio(0); + r8a7778_register_gpio(1); + r8a7778_register_gpio(2); + r8a7778_register_gpio(3); + r8a7778_register_gpio(4); +} + void __init r8a7778_add_standard_devices(void) { int i; diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index b0b394842ea5..dbb13f289e79 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -65,11 +65,7 @@ void __init r8a7779_map_io(void) } static struct resource r8a7779_pfc_resources[] = { - [0] = { - .start = 0xfffc0000, - .end = 0xfffc023b, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(0xfffc0000, 0x023c), }; static struct platform_device r8a7779_pfc_device = { @@ -81,15 +77,8 @@ static struct platform_device r8a7779_pfc_device = { #define R8A7779_GPIO(idx, npins) \ static struct resource r8a7779_gpio##idx##_resources[] = { \ - [0] = { \ - .start = 0xffc40000 + 0x1000 * (idx), \ - .end = 0xffc4002b + 0x1000 * (idx), \ - .flags = IORESOURCE_MEM, \ - }, \ - [1] = { \ - .start = gic_iid(0xad + (idx)), \ - .flags = IORESOURCE_IRQ, \ - } \ + DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ + DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ }; \ \ static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 49de2d56f86d..b461d93431ed 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -23,6 +23,7 @@ #include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/serial_sci.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-irqc.h> #include <mach/common.h> #include <mach/irqs.h> @@ -31,13 +32,46 @@ static const struct resource pfc_resources[] = { DEFINE_RES_MEM(0xe6060000, 0x250), - DEFINE_RES_MEM(0xe6050000, 0x5050), }; +#define R8A7790_GPIO(idx) \ +static struct resource r8a7790_gpio##idx##_resources[] = { \ + DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ + DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ +}; \ + \ +static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \ + .gpio_base = 32 * (idx), \ + .irq_base = 0, \ + .number_of_pins = 32, \ + .pctl_name = "pfc-r8a7790", \ + .has_both_edge_trigger = 1, \ +}; \ + +R8A7790_GPIO(0); +R8A7790_GPIO(1); +R8A7790_GPIO(2); +R8A7790_GPIO(3); +R8A7790_GPIO(4); +R8A7790_GPIO(5); + +#define r8a7790_register_gpio(idx) \ + platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ + r8a7790_gpio##idx##_resources, \ + ARRAY_SIZE(r8a7790_gpio##idx##_resources), \ + &r8a7790_gpio##idx##_platform_data, \ + sizeof(r8a7790_gpio##idx##_platform_data)) + void __init r8a7790_pinmux_init(void) { platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, ARRAY_SIZE(pfc_resources)); + r8a7790_register_gpio(0); + r8a7790_register_gpio(1); + r8a7790_register_gpio(2); + r8a7790_register_gpio(3); + r8a7790_register_gpio(4); + r8a7790_register_gpio(5); } #define SCIF_COMMON(scif_type, baseaddr, irq) \ diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 566e804d4036..a279fb315069 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -7,7 +7,6 @@ config ARCH_SOCFPGA select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 - select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select GPIO_PL061 if GPIOLIB diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 46a051359f02..8ea11b472b91 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -14,7 +14,6 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <linux/dw_apb_timer.h> #include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of_address.h> @@ -120,7 +119,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .smp = smp_ops(socfpga_smp_ops), .map_io = socfpga_map_io, .init_irq = socfpga_init_irq, - .init_time = dw_apb_timer_init, .init_machine = socfpga_cyclone5_init, .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index aba9e5692958..bfe443daf4b0 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -21,28 +21,14 @@ static struct stedma40_chan_cfg msp0_dma_rx = { .high_priority = true, - .dir = STEDMA40_PERIPH_TO_MEM, - - .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0, }; static struct stedma40_chan_cfg msp0_dma_tx = { .high_priority = true, - .dir = STEDMA40_MEM_TO_PERIPH, - - .src_dev_type = STEDMA40_DEV_DST_MEMORY, - .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0, }; struct msp_i2s_platform_data msp0_platform_data = { @@ -53,28 +39,14 @@ struct msp_i2s_platform_data msp0_platform_data = { static struct stedma40_chan_cfg msp1_dma_rx = { .high_priority = true, - .dir = STEDMA40_PERIPH_TO_MEM, - - .src_dev_type = DB8500_DMA_DEV30_MSP3_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV30_MSP3, }; static struct stedma40_chan_cfg msp1_dma_tx = { .high_priority = true, - .dir = STEDMA40_MEM_TO_PERIPH, - - .src_dev_type = STEDMA40_DEV_DST_MEMORY, - .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - - /* data_width is set during configuration */ + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV30_MSP1, }; struct msp_i2s_platform_data msp1_platform_data = { @@ -85,32 +57,16 @@ struct msp_i2s_platform_data msp1_platform_data = { static struct stedma40_chan_cfg msp2_dma_rx = { .high_priority = true, - .dir = STEDMA40_PERIPH_TO_MEM, - - .src_dev_type = DB8500_DMA_DEV14_MSP2_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - - /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */ - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - - /* data_width is set during configuration */ + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV14_MSP2, }; static struct stedma40_chan_cfg msp2_dma_tx = { .high_priority = true, - .dir = STEDMA40_MEM_TO_PERIPH, - - .src_dev_type = STEDMA40_DEV_DST_MEMORY, - .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX, - - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, - + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV14_MSP2, .use_fixed_channel = true, .phy_channel = 1, - - /* data_width is set during configuration */ }; static struct platform_device *db8500_add_msp_i2s(struct device *parent, diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 0ef38775a0c1..e6891d1933fa 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -34,20 +34,14 @@ #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV29_SD_MM0, }; static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV29_SD_MM0, }; #endif @@ -87,20 +81,14 @@ void mop500_sdi_tc35892_init(struct device *parent) #ifdef CONFIG_STE_DMA40 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV32_SD_MM1, }; static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV32_SD_MM1, }; #endif @@ -124,20 +112,14 @@ struct mmci_platform_data mop500_sdi1_data = { #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV28_SD_MM2, }; static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV28_SD_MM2, }; #endif @@ -162,20 +144,14 @@ struct mmci_platform_data mop500_sdi2_data = { #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV42_SD_MM4, }; static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV42_SD_MM4, }; #endif diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 78389de94dde..2d70e2b45660 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -424,36 +424,21 @@ void mop500_snowball_ethernet_clock_enable(void) static struct cryp_platform_data u8500_cryp1_platform_data = { .mem_to_engine = { - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV48_CAC1, .mode = STEDMA40_MODE_LOGICAL, - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, }, .engine_to_mem = { - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV48_CAC1_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV48_CAC1, .mode = STEDMA40_MODE_LOGICAL, - .src_info.psize = STEDMA40_PSIZE_LOG_4, - .dst_info.psize = STEDMA40_PSIZE_LOG_4, } }; static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV50_HAC1_TX, .mode = STEDMA40_MODE_LOGICAL, - .src_info.psize = STEDMA40_PSIZE_LOG_16, - .dst_info.psize = STEDMA40_PSIZE_LOG_16, }; static struct hash_platform_data u8500_hash1_platform_data = { @@ -470,20 +455,14 @@ static struct platform_device *mop500_platform_devs[] __initdata = { #ifdef CONFIG_STE_DMA40 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV8_SSP0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV8_SSP0, }; static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV8_SSP0, }; #endif @@ -511,56 +490,38 @@ static void __init mop500_spi_init(struct device *parent) #ifdef CONFIG_STE_DMA40 static struct stedma40_chan_cfg uart0_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV13_UART0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV13_UART0, }; static struct stedma40_chan_cfg uart0_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV13_UART0_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV13_UART0, }; static struct stedma40_chan_cfg uart1_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV12_UART1_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV12_UART1, }; static struct stedma40_chan_cfg uart1_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV12_UART1_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV12_UART1, }; static struct stedma40_chan_cfg uart2_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB8500_DMA_DEV11_UART2_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV11_UART2, }; static struct stedma40_chan_cfg uart2_dma_cfg_tx = { .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB8500_DMA_DEV11_UART2_TX, - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV11_UART2, }; #endif @@ -676,6 +637,8 @@ static void __init snowball_init_machine(void) mop500_snowball_ethernet_clock_enable(); + u8500_cryp1_hash1_init(parent); + /* This board has full regulator constraints */ regulator_has_full_constraints(); } diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 49514b825034..6f0bfcb08907 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat; extern struct amba_pl011_data uart1_plat; extern struct amba_pl011_data uart2_plat; extern struct pl022_ssp_controller ssp0_plat; +extern struct stedma40_platform_data dma40_plat_data; extern void mop500_sdi_init(struct device *parent); extern void snowball_sdi_init(struct device *parent); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 46cca52890bc..f63847dabe7d 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -162,26 +162,15 @@ static void __init db8500_add_gpios(struct device *parent) dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); } -static int usb_db8500_rx_dma_cfg[] = { - DB8500_DMA_DEV38_USB_OTG_IEP_1_9, - DB8500_DMA_DEV37_USB_OTG_IEP_2_10, - DB8500_DMA_DEV36_USB_OTG_IEP_3_11, - DB8500_DMA_DEV19_USB_OTG_IEP_4_12, - DB8500_DMA_DEV18_USB_OTG_IEP_5_13, - DB8500_DMA_DEV17_USB_OTG_IEP_6_14, - DB8500_DMA_DEV16_USB_OTG_IEP_7_15, - DB8500_DMA_DEV39_USB_OTG_IEP_8 -}; - -static int usb_db8500_tx_dma_cfg[] = { - DB8500_DMA_DEV38_USB_OTG_OEP_1_9, - DB8500_DMA_DEV37_USB_OTG_OEP_2_10, - DB8500_DMA_DEV36_USB_OTG_OEP_3_11, - DB8500_DMA_DEV19_USB_OTG_OEP_4_12, - DB8500_DMA_DEV18_USB_OTG_OEP_5_13, - DB8500_DMA_DEV17_USB_OTG_OEP_6_14, - DB8500_DMA_DEV16_USB_OTG_OEP_7_15, - DB8500_DMA_DEV39_USB_OTG_OEP_8 +static int usb_db8500_dma_cfg[] = { + DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9, + DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10, + DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11, + DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12, + DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13, + DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14, + DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15, + DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 }; static const char *db8500_read_soc_id(void) @@ -215,7 +204,7 @@ struct device * __init u8500_init_devices(void) db8500_add_rtc(parent); db8500_add_gpios(parent); - db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); + db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg); for (i = 0; i < ARRAY_SIZE(platform_devs); i++) platform_devs[i]->dev.parent = parent; @@ -226,34 +215,13 @@ struct device * __init u8500_init_devices(void) } #ifdef CONFIG_MACH_UX500_DT - -/* TODO: Once all pieces are DT:ed, remove completely. */ -static struct device * __init u8500_of_init_devices(void) -{ - struct device *parent = db8500_soc_device_init(); - - db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); - - u8500_dma40_device.dev.parent = parent; - - /* - * Devices to be DT:ed: - * u8500_dma40_device = todo - * db8500_pmu_device = done - * db8500_prcmu_device = done - */ - platform_device_register(&u8500_dma40_device); - - return parent; -} - static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { /* Requires call-back bindings. */ OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), /* Requires DMA bindings. */ - OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), - OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), - OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), + OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL), + OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), + OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), @@ -289,6 +257,8 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { "ux500-msp-i2s.2", &msp2_platform_data), OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, "ux500-msp-i2s.3", &msp3_platform_data), + /* Requires clock name bindings and channel address lookup table. */ + OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL), {}, }; @@ -302,7 +272,7 @@ static const struct of_device_id u8500_local_bus_nodes[] = { static void __init u8500_init_machine(void) { - struct device *parent = NULL; + struct device *parent = db8500_soc_device_init(); /* Pinmaps must be in place before devices register */ if (of_machine_is_compatible("st-ericsson,mop500")) @@ -315,9 +285,6 @@ static void __init u8500_init_machine(void) else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} /* TODO: Add pinmaps for ccu9540 board. */ - /* TODO: Export SoC, USB, cpu-freq and DMA40 */ - parent = u8500_of_init_devices(); - /* automatically probe child nodes of db8500 device */ of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); } diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 1cf94ce0feec..e21ffd8c1412 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -42,128 +42,7 @@ static struct resource dma40_resources[] = { } }; -/* Default configuration for physcial memcpy */ -struct stedma40_chan_cfg dma40_memcpy_conf_phy = { - .mode = STEDMA40_MODE_PHYSICAL, - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_PHY_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_PHY_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; -/* Default configuration for logical memcpy */ -struct stedma40_chan_cfg dma40_memcpy_conf_log = { - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* - * Mapping between destination event lines and physical device address. - * The event line is tied to a device and therefore the address is constant. - * When the address comes from a primecell it will be configured in runtime - * and we set the address to -1 as a placeholder. - */ -static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { - /* MUSB - these will be runtime-reconfigured */ - [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1, - [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1, - [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1, - [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1, - [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1, - [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1, - [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1, - [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1, - /* PrimeCells - run-time configured */ - [DB8500_DMA_DEV0_SPI0_TX] = -1, - [DB8500_DMA_DEV1_SD_MMC0_TX] = -1, - [DB8500_DMA_DEV2_SD_MMC1_TX] = -1, - [DB8500_DMA_DEV3_SD_MMC2_TX] = -1, - [DB8500_DMA_DEV8_SSP0_TX] = -1, - [DB8500_DMA_DEV9_SSP1_TX] = -1, - [DB8500_DMA_DEV11_UART2_TX] = -1, - [DB8500_DMA_DEV12_UART1_TX] = -1, - [DB8500_DMA_DEV13_UART0_TX] = -1, - [DB8500_DMA_DEV28_SD_MM2_TX] = -1, - [DB8500_DMA_DEV29_SD_MM0_TX] = -1, - [DB8500_DMA_DEV32_SD_MM1_TX] = -1, - [DB8500_DMA_DEV33_SPI2_TX] = -1, - [DB8500_DMA_DEV35_SPI1_TX] = -1, - [DB8500_DMA_DEV40_SPI3_TX] = -1, - [DB8500_DMA_DEV41_SD_MM3_TX] = -1, - [DB8500_DMA_DEV42_SD_MM4_TX] = -1, - [DB8500_DMA_DEV43_SD_MM5_TX] = -1, - [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET, - [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET, -}; - -/* Mapping between source event lines and physical device address */ -static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { - /* MUSB - these will be runtime-reconfigured */ - [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1, - [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1, - [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1, - [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1, - [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1, - [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1, - [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1, - [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1, - /* PrimeCells */ - [DB8500_DMA_DEV0_SPI0_RX] = -1, - [DB8500_DMA_DEV1_SD_MMC0_RX] = -1, - [DB8500_DMA_DEV2_SD_MMC1_RX] = -1, - [DB8500_DMA_DEV3_SD_MMC2_RX] = -1, - [DB8500_DMA_DEV8_SSP0_RX] = -1, - [DB8500_DMA_DEV9_SSP1_RX] = -1, - [DB8500_DMA_DEV11_UART2_RX] = -1, - [DB8500_DMA_DEV12_UART1_RX] = -1, - [DB8500_DMA_DEV13_UART0_RX] = -1, - [DB8500_DMA_DEV28_SD_MM2_RX] = -1, - [DB8500_DMA_DEV29_SD_MM0_RX] = -1, - [DB8500_DMA_DEV32_SD_MM1_RX] = -1, - [DB8500_DMA_DEV33_SPI2_RX] = -1, - [DB8500_DMA_DEV35_SPI1_RX] = -1, - [DB8500_DMA_DEV40_SPI3_RX] = -1, - [DB8500_DMA_DEV41_SD_MM3_RX] = -1, - [DB8500_DMA_DEV42_SD_MM4_RX] = -1, - [DB8500_DMA_DEV43_SD_MM5_RX] = -1, - [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, - [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET, -}; - -/* Reserved event lines for memcpy only */ -static int dma40_memcpy_event[] = { - DB8500_DMA_MEMCPY_TX_0, - DB8500_DMA_MEMCPY_TX_1, - DB8500_DMA_MEMCPY_TX_2, - DB8500_DMA_MEMCPY_TX_3, - DB8500_DMA_MEMCPY_TX_4, - DB8500_DMA_MEMCPY_TX_5, -}; - -static struct stedma40_platform_data dma40_plat_data = { - .dev_len = DB8500_DMA_NR_DEV, - .dev_rx = dma40_rx_map, - .dev_tx = dma40_tx_map, - .memcpy = dma40_memcpy_event, - .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), - .memcpy_conf_phy = &dma40_memcpy_conf_phy, - .memcpy_conf_log = &dma40_memcpy_conf_log, +struct stedma40_platform_data dma40_plat_data = { .disabled_channels = {-1}, }; diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h index a616419bea76..0296ae5b0fd9 100644 --- a/arch/arm/mach-ux500/ste-dma40-db8500.h +++ b/arch/arm/mach-ux500/ste-dma40-db8500.h @@ -12,133 +12,74 @@ #define DB8500_DMA_NR_DEV 64 -enum dma_src_dev_type { - DB8500_DMA_DEV0_SPI0_RX = 0, - DB8500_DMA_DEV1_SD_MMC0_RX = 1, - DB8500_DMA_DEV2_SD_MMC1_RX = 2, - DB8500_DMA_DEV3_SD_MMC2_RX = 3, - DB8500_DMA_DEV4_I2C1_RX = 4, - DB8500_DMA_DEV5_I2C3_RX = 5, - DB8500_DMA_DEV6_I2C2_RX = 6, - DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */ - DB8500_DMA_DEV8_SSP0_RX = 8, - DB8500_DMA_DEV9_SSP1_RX = 9, - DB8500_DMA_DEV10_MCDE_RX = 10, - DB8500_DMA_DEV11_UART2_RX = 11, - DB8500_DMA_DEV12_UART1_RX = 12, - DB8500_DMA_DEV13_UART0_RX = 13, - DB8500_DMA_DEV14_MSP2_RX = 14, - DB8500_DMA_DEV15_I2C0_RX = 15, - DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16, - DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17, - DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18, - DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19, - DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20, - DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21, - DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22, - DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23, - DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24, - DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25, - DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26, - DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27, - DB8500_DMA_DEV28_SD_MM2_RX = 28, - DB8500_DMA_DEV29_SD_MM0_RX = 29, - DB8500_DMA_DEV30_MSP1_RX = 30, +/* + * Unless otherwise specified, all channels numbers are used for + * TX & RX, and can be used for either source or destination + * channels. + */ +enum dma_dev_type { + DB8500_DMA_DEV0_SPI0 = 0, + DB8500_DMA_DEV1_SD_MMC0 = 1, + DB8500_DMA_DEV2_SD_MMC1 = 2, + DB8500_DMA_DEV3_SD_MMC2 = 3, + DB8500_DMA_DEV4_I2C1 = 4, + DB8500_DMA_DEV5_I2C3 = 5, + DB8500_DMA_DEV6_I2C2 = 6, + DB8500_DMA_DEV7_I2C4 = 7, /* Only on V1 and later */ + DB8500_DMA_DEV8_SSP0 = 8, + DB8500_DMA_DEV9_SSP1 = 9, + DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */ + DB8500_DMA_DEV11_UART2 = 11, + DB8500_DMA_DEV12_UART1 = 12, + DB8500_DMA_DEV13_UART0 = 13, + DB8500_DMA_DEV14_MSP2 = 14, + DB8500_DMA_DEV15_I2C0 = 15, + DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16, + DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17, + DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18, + DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19, + DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20, + DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21, + DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22, + DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23, + DB8500_DMA_DEV24_SXA0 = 24, + DB8500_DMA_DEV25_SXA1 = 25, + DB8500_DMA_DEV26_SXA2 = 26, + DB8500_DMA_DEV27_SXA3 = 27, + DB8500_DMA_DEV28_SD_MM2 = 28, + DB8500_DMA_DEV29_SD_MM0 = 29, + DB8500_DMA_DEV30_MSP1 = 30, /* On DB8500v2, MSP3 RX replaces MSP1 RX */ - DB8500_DMA_DEV30_MSP3_RX = 30, - DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31, - DB8500_DMA_DEV32_SD_MM1_RX = 32, - DB8500_DMA_DEV33_SPI2_RX = 33, - DB8500_DMA_DEV34_I2C3_RX2 = 34, - DB8500_DMA_DEV35_SPI1_RX = 35, - DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36, - DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37, - DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38, - DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39, - DB8500_DMA_DEV40_SPI3_RX = 40, - DB8500_DMA_DEV41_SD_MM3_RX = 41, - DB8500_DMA_DEV42_SD_MM4_RX = 42, - DB8500_DMA_DEV43_SD_MM5_RX = 43, - DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44, - DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45, - DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46, - DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47, - DB8500_DMA_DEV48_CAC1_RX = 48, - /* 49, 50 and 51 are not used */ - DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52, - DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53, - DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54, - DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55, - /* 56, 57, 58, 59 and 60 are not used */ - DB8500_DMA_DEV61_CAC0_RX = 61, - /* 62 and 63 are not used */ -}; - -enum dma_dest_dev_type { - DB8500_DMA_DEV0_SPI0_TX = 0, - DB8500_DMA_DEV1_SD_MMC0_TX = 1, - DB8500_DMA_DEV2_SD_MMC1_TX = 2, - DB8500_DMA_DEV3_SD_MMC2_TX = 3, - DB8500_DMA_DEV4_I2C1_TX = 4, - DB8500_DMA_DEV5_I2C3_TX = 5, - DB8500_DMA_DEV6_I2C2_TX = 6, - DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */ - DB8500_DMA_DEV8_SSP0_TX = 8, - DB8500_DMA_DEV9_SSP1_TX = 9, - /* 10 is not used*/ - DB8500_DMA_DEV11_UART2_TX = 11, - DB8500_DMA_DEV12_UART1_TX = 12, - DB8500_DMA_DEV13_UART0_TX = 13, - DB8500_DMA_DEV14_MSP2_TX = 14, - DB8500_DMA_DEV15_I2C0_TX = 15, - DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16, - DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17, - DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18, - DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19, - DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20, - DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21, - DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22, - DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23, - DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24, - DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25, - DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26, - DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27, - DB8500_DMA_DEV28_SD_MM2_TX = 28, - DB8500_DMA_DEV29_SD_MM0_TX = 29, - DB8500_DMA_DEV30_MSP1_TX = 30, - DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31, - DB8500_DMA_DEV32_SD_MM1_TX = 32, - DB8500_DMA_DEV33_SPI2_TX = 33, - DB8500_DMA_DEV34_I2C3_TX2 = 34, - DB8500_DMA_DEV35_SPI1_TX = 35, - DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36, - DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37, - DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38, - DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39, - DB8500_DMA_DEV40_SPI3_TX = 40, - DB8500_DMA_DEV41_SD_MM3_TX = 41, - DB8500_DMA_DEV42_SD_MM4_TX = 42, - DB8500_DMA_DEV43_SD_MM5_TX = 43, - DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44, - DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45, - DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46, - DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47, - DB8500_DMA_DEV48_CAC1_TX = 48, - DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, - DB8500_DMA_DEV50_HAC1_TX = 50, - DB8500_DMA_MEMCPY_TX_0 = 51, - DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52, - DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53, - DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54, - DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55, - DB8500_DMA_MEMCPY_TX_1 = 56, - DB8500_DMA_MEMCPY_TX_2 = 57, - DB8500_DMA_MEMCPY_TX_3 = 58, - DB8500_DMA_MEMCPY_TX_4 = 59, - DB8500_DMA_MEMCPY_TX_5 = 60, - DB8500_DMA_DEV61_CAC0_TX = 61, - DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, - DB8500_DMA_DEV63_HAC0_TX = 63, + DB8500_DMA_DEV30_MSP3 = 30, + DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31, + DB8500_DMA_DEV32_SD_MM1 = 32, + DB8500_DMA_DEV33_SPI2 = 33, + DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34, + DB8500_DMA_DEV35_SPI1 = 35, + DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36, + DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37, + DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38, + DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39, + DB8500_DMA_DEV40_SPI3 = 40, + DB8500_DMA_DEV41_SD_MM3 = 41, + DB8500_DMA_DEV42_SD_MM4 = 42, + DB8500_DMA_DEV43_SD_MM5 = 43, + DB8500_DMA_DEV44_SXA4 = 44, + DB8500_DMA_DEV45_SXA5 = 45, + DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46, + DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47, + DB8500_DMA_DEV48_CAC1 = 48, + DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */ + DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */ + DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */ + DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52, + DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53, + DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54, + DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55, + /* 56 -> 60 are channels reserved for memcpy only */ + DB8500_DMA_DEV61_CAC0 = 61, + DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */ + DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */ }; #endif diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c index 2dfc72f7cd8a..b7bd8d3a5507 100644 --- a/arch/arm/mach-ux500/usb.c +++ b/arch/arm/mach-ux500/usb.c @@ -14,25 +14,15 @@ #define MUSB_DMA40_RX_CH { \ .mode = STEDMA40_MODE_LOGICAL, \ - .dir = STEDMA40_PERIPH_TO_MEM, \ - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \ - .src_info.data_width = STEDMA40_WORD_WIDTH, \ - .dst_info.data_width = STEDMA40_WORD_WIDTH, \ - .src_info.psize = STEDMA40_PSIZE_LOG_16, \ - .dst_info.psize = STEDMA40_PSIZE_LOG_16, \ + .dir = DMA_DEV_TO_MEM, \ } #define MUSB_DMA40_TX_CH { \ .mode = STEDMA40_MODE_LOGICAL, \ - .dir = STEDMA40_MEM_TO_PERIPH, \ - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \ - .src_info.data_width = STEDMA40_WORD_WIDTH, \ - .dst_info.data_width = STEDMA40_WORD_WIDTH, \ - .src_info.psize = STEDMA40_PSIZE_LOG_16, \ - .dst_info.psize = STEDMA40_PSIZE_LOG_16, \ + .dir = DMA_MEM_TO_DEV, \ } -static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS] +static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = { MUSB_DMA40_RX_CH, MUSB_DMA40_RX_CH, @@ -44,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS] MUSB_DMA40_RX_CH }; -static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS] +static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = { MUSB_DMA40_TX_CH, MUSB_DMA40_TX_CH, @@ -56,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS] MUSB_DMA40_TX_CH, }; -static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = { +static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = { &musb_dma_rx_ch[0], &musb_dma_rx_ch[1], &musb_dma_rx_ch[2], @@ -67,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = { &musb_dma_rx_ch[7] }; -static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = { +static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = { &musb_dma_tx_ch[0], &musb_dma_tx_ch[1], &musb_dma_tx_ch[2], @@ -81,23 +71,11 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = { static struct ux500_musb_board_data musb_board_data = { .dma_rx_param_array = ux500_dma_rx_param_array, .dma_tx_param_array = ux500_dma_tx_param_array, - .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS, - .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS, .dma_filter = stedma40_filter, }; -static u64 ux500_musb_dmamask = DMA_BIT_MASK(32); - -static struct musb_hdrc_config musb_hdrc_config = { - .multipoint = true, - .dyn_fifo = true, - .num_eps = 16, - .ram_bits = 16, -}; - static struct musb_hdrc_platform_data musb_platform_data = { .mode = MUSB_OTG, - .config = &musb_hdrc_config, .board_data = &musb_board_data, }; @@ -118,27 +96,26 @@ struct platform_device ux500_musb_device = { .id = 0, .dev = { .platform_data = &musb_platform_data, - .dma_mask = &ux500_musb_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(usb_resources), .resource = usb_resources, }; -static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type) +static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type) { u32 idx; - for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++) - musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx]; + for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++) + musb_dma_rx_ch[idx].dev_type = dev_type[idx]; } -static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type) +static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type) { u32 idx; - for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++) - musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx]; + for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++) + musb_dma_tx_ch[idx].dev_type = dev_type[idx]; } void ux500_add_usb(struct device *parent, resource_size_t base, int irq, diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index ce66eb9be481..f82bae2171eb 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -86,22 +86,6 @@ config OMAP_MUX_WARNINGS to change the pin multiplexing setup. When there are no warnings printed, it's safe to deselect OMAP_MUX for your product. -config OMAP_MBOX_FWK - tristate "Mailbox framework support" - depends on ARCH_OMAP && !ARCH_MULTIPLATFORM - help - Say Y here if you want to use OMAP Mailbox framework support for - DSP, IVA1.0 and IVA2 in OMAP1/2/3. - -config OMAP_MBOX_KFIFO_SIZE - int "Mailbox kfifo default buffer size (bytes)" - depends on OMAP_MBOX_FWK - default 256 - help - Specify the default size of mailbox's kfifo buffers (bytes). - This can also be changed at runtime (via the mbox_kfifo_size - module parameter). - config OMAP_IOMMU_IVA2 bool diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 31199417b56a..0b01b68fd033 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -17,6 +17,3 @@ obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) -# OMAP mailbox framework -obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o - diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h index 95509d8eb140..d7e17150028a 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h @@ -202,7 +202,7 @@ extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS #define s3c_cpufreq_debugfs_call(x) x #else #define s3c_cpufreq_debugfs_call(x) NULL @@ -259,17 +259,17 @@ extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, #define s3c2412_iotiming_set NULL #endif /* CONFIG_S3C2412_IOTIMING */ -#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG #define s3c_freq_dbg(x...) printk(KERN_INFO x) #else #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ +#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */ -#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG +#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG #define s3c_freq_iodbg(x...) printk(KERN_INFO x) #else #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ +#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, int index, size_t table_size, diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h index 80c4a809c721..85517ab962ae 100644 --- a/arch/arm/plat-samsung/include/plat/cpu-freq.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h @@ -126,7 +126,7 @@ struct s3c_cpufreq_board { }; /* Things depending on frequency scaling. */ -#ifdef CONFIG_CPU_FREQ_S3C +#ifdef CONFIG_ARM_S3C_CPUFREQ #define __init_or_cpufreq #else #define __init_or_cpufreq __init @@ -134,7 +134,7 @@ struct s3c_cpufreq_board { /* Board functions */ -#ifdef CONFIG_CPU_FREQ_S3C +#ifdef CONFIG_ARM_S3C_CPUFREQ extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); #else @@ -142,4 +142,4 @@ static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) { return 0; } -#endif /* CONFIG_CPU_FREQ_S3C */ +#endif /* CONFIG_ARM_S3C_CPUFREQ */ diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index f151c6cf27c3..5871933c4e51 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -21,6 +21,8 @@ config DW_APB_TIMER config DW_APB_TIMER_OF bool + select DW_APB_TIMER + select CLKSRC_OF config ARMADA_370_XP_TIMER bool diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index 54f3d119d99c..77398f8c19a0 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -10,7 +10,7 @@ * DBx500-PRCMU Timer * The PRCMU has 5 timers which are available in a always-on * power domain. We use the Timer 4 for our always-on clock - * source on DB8500 and Timer 3 on DB5500. + * source on DB8500. */ #include <linux/clockchips.h> #include <linux/clksrc-dbx500-prcmu.h> @@ -30,15 +30,14 @@ static void __iomem *clksrc_dbx500_timer_base; -static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs) +static cycle_t notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) { + void __iomem *base = clksrc_dbx500_timer_base; u32 count, count2; do { - count = readl(clksrc_dbx500_timer_base + - PRCMU_TIMER_DOWNCOUNT); - count2 = readl(clksrc_dbx500_timer_base + - PRCMU_TIMER_DOWNCOUNT); + count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); + count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); } while (count2 != count); /* Negate because the timer is a decrementing counter */ diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index ab09ed3742ee..cef554432a33 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -20,6 +20,7 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/clk.h> #include <asm/mach/time.h> #include <asm/sched_clock.h> @@ -27,14 +28,37 @@ static void timer_get_base_and_rate(struct device_node *np, void __iomem **base, u32 *rate) { + struct clk *timer_clk; + struct clk *pclk; + *base = of_iomap(np, 0); if (!*base) panic("Unable to map regs for %s", np->name); + /* + * Not all implementations use a periphal clock, so don't panic + * if it's not present + */ + pclk = of_clk_get_by_name(np, "pclk"); + if (!IS_ERR(pclk)) + if (clk_prepare_enable(pclk)) + pr_warn("pclk for %s is present, but could not be activated\n", + np->name); + + timer_clk = of_clk_get_by_name(np, "timer"); + if (IS_ERR(timer_clk)) + goto try_clock_freq; + + if (!clk_prepare_enable(timer_clk)) { + *rate = clk_get_rate(timer_clk); + return; + } + +try_clock_freq: if (of_property_read_u32(np, "clock-freq", rate) && of_property_read_u32(np, "clock-frequency", rate)) - panic("No clock-frequency property for %s", np->name); + panic("No clock nor clock-frequency property for %s", np->name); } static void add_clockevent(struct device_node *event_timer) @@ -57,6 +81,9 @@ static void add_clockevent(struct device_node *event_timer) dw_apb_clockevent_register(ced); } +static void __iomem *sched_io_base; +static u32 sched_rate; + static void add_clocksource(struct device_node *source_timer) { void __iomem *iobase; @@ -71,9 +98,15 @@ static void add_clocksource(struct device_node *source_timer) dw_apb_clocksource_start(cs); dw_apb_clocksource_register(cs); -} -static void __iomem *sched_io_base; + /* + * Fallback to use the clocksource as sched_clock if no separate + * timer is found. sched_io_base then points to the current_value + * register of the clocksource timer. + */ + sched_io_base = iobase + 0x04; + sched_rate = rate; +} static u32 read_sched_clock(void) { @@ -89,39 +122,37 @@ static const struct of_device_id sptimer_ids[] __initconst = { static void init_sched_clock(void) { struct device_node *sched_timer; - u32 rate; sched_timer = of_find_matching_node(NULL, sptimer_ids); - if (!sched_timer) - panic("No RTC for sched clock to use"); + if (sched_timer) { + timer_get_base_and_rate(sched_timer, &sched_io_base, + &sched_rate); + of_node_put(sched_timer); + } - timer_get_base_and_rate(sched_timer, &sched_io_base, &rate); - of_node_put(sched_timer); - - setup_sched_clock(read_sched_clock, 32, rate); + setup_sched_clock(read_sched_clock, 32, sched_rate); } -static const struct of_device_id osctimer_ids[] __initconst = { - { .compatible = "picochip,pc3x2-timer" }, - { .compatible = "snps,dw-apb-timer-osc" }, - {}, -}; - -void __init dw_apb_timer_init(void) +static int num_called; +static void __init dw_apb_timer_init(struct device_node *timer) { - struct device_node *event_timer, *source_timer; - - event_timer = of_find_matching_node(NULL, osctimer_ids); - if (!event_timer) - panic("No timer for clockevent"); - add_clockevent(event_timer); - - source_timer = of_find_matching_node(event_timer, osctimer_ids); - if (!source_timer) - panic("No timer for clocksource"); - add_clocksource(source_timer); - - of_node_put(source_timer); - - init_sched_clock(); + switch (num_called) { + case 0: + pr_debug("%s: found clockevent timer\n", __func__); + add_clockevent(timer); + of_node_put(timer); + break; + case 1: + pr_debug("%s: found clocksource timer\n", __func__); + add_clocksource(timer); + of_node_put(timer); + init_sched_clock(); + break; + default: + break; + } + + num_called++; } +CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init); +CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init); diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 6e57543fe0b9..a92440896868 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -96,6 +96,56 @@ config ARM_OMAP2PLUS_CPUFREQ default ARCH_OMAP2PLUS select CPU_FREQ_TABLE +config ARM_S3C_CPUFREQ + bool + help + Internal configuration node for common cpufreq on Samsung SoC + +config ARM_S3C24XX_CPUFREQ + bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" + depends on ARCH_S3C24XX + select ARM_S3C_CPUFREQ + help + This enables the CPUfreq driver for the Samsung S3C24XX family + of CPUs. + + For details, take a look at <file:Documentation/cpu-freq>. + + If in doubt, say N. + +config ARM_S3C24XX_CPUFREQ_DEBUG + bool "Debug CPUfreq Samsung driver core" + depends on ARM_S3C24XX_CPUFREQ + help + Enable s3c_freq_dbg for the Samsung S3C CPUfreq core + +config ARM_S3C24XX_CPUFREQ_IODEBUG + bool "Debug CPUfreq Samsung driver IO timing" + depends on ARM_S3C24XX_CPUFREQ + help + Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core + +config ARM_S3C24XX_CPUFREQ_DEBUGFS + bool "Export debugfs for CPUFreq" + depends on ARM_S3C24XX_CPUFREQ && DEBUG_FS + help + Export status information via debugfs. + +config ARM_S3C2410_CPUFREQ + bool + depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2410 + select S3C2410_CPUFREQ_UTILS + help + CPU Frequency scaling support for S3C2410 + +config ARM_S3C2412_CPUFREQ + bool + depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2412 + default y + select S3C2412_IOTIMING + help + CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. + config ARM_S3C2416_CPUFREQ bool "S3C2416 CPU Frequency scaling support" depends on CPU_S3C2416 @@ -118,6 +168,14 @@ config ARM_S3C2416_CPUFREQ_VCORESCALE If in doubt, say N. +config ARM_S3C2440_CPUFREQ + bool "S3C2440/S3C2442 CPU Frequency scaling support" + depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2440 || CPU_S3C2442) + select S3C2410_CPUFREQ_UTILS + default y + help + CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. + config ARM_S3C64XX_CPUFREQ bool "Samsung S3C64XX" depends on CPU_S3C6410 diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 315b9231feb1..6ad0b913ca17 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -65,7 +65,12 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_PXA25x) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA27x) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o +obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o +obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o +obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o +obj-$(CONFIG_ARM_S3C2440_CPUFREQ) += s3c2440-cpufreq.o obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/drivers/cpufreq/s3c2410-cpufreq.c index cfa0dd8723ec..cfa0dd8723ec 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c +++ b/drivers/cpufreq/s3c2410-cpufreq.c diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/drivers/cpufreq/s3c2412-cpufreq.c index 8bf0f3a77476..4645b4898996 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c +++ b/drivers/cpufreq/s3c2412-cpufreq.c @@ -25,13 +25,12 @@ #include <asm/mach/map.h> #include <mach/regs-clock.h> +#include <mach/s3c2412.h> #include <plat/cpu.h> #include <plat/clock.h> #include <plat/cpu-freq-core.h> -#include "s3c2412.h" - /* our clock resources. */ static struct clk *xtal; static struct clk *fclk; diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/drivers/cpufreq/s3c2440-cpufreq.c index 72b2cc8a5a85..72b2cc8a5a85 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c +++ b/drivers/cpufreq/s3c2440-cpufreq.c diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/drivers/cpufreq/s3c24xx-cpufreq-debugfs.c index 9b7b4289d66c..9b7b4289d66c 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c +++ b/drivers/cpufreq/s3c24xx-cpufreq-debugfs.c diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/drivers/cpufreq/s3c24xx-cpufreq.c index 3c0e78ede0da..3c0e78ede0da 100644 --- a/arch/arm/mach-s3c24xx/cpufreq.c +++ b/drivers/cpufreq/s3c24xx-cpufreq.c diff --git a/drivers/crypto/ux500/cryp/cryp.h b/drivers/crypto/ux500/cryp/cryp.h index 14cfd05b777a..d1d6606fe56c 100644 --- a/drivers/crypto/ux500/cryp/cryp.h +++ b/drivers/crypto/ux500/cryp/cryp.h @@ -114,6 +114,9 @@ enum cryp_status_id { }; /* Cryp DMA interface */ +#define CRYP_DMA_TX_FIFO 0x08 +#define CRYP_DMA_RX_FIFO 0x10 + enum cryp_dma_req_type { CRYP_DMA_DISABLE_BOTH, CRYP_DMA_ENABLE_IN_DATA, @@ -217,7 +220,8 @@ struct cryp_dma { /** * struct cryp_device_data - structure for a cryp device. - * @base: Pointer to the hardware base address. + * @base: Pointer to virtual base address of the cryp device. + * @phybase: Pointer to physical memory location of the cryp device. * @dev: Pointer to the devices dev structure. * @clk: Pointer to the device's clock control. * @pwr_regulator: Pointer to the device's power control. @@ -232,6 +236,7 @@ struct cryp_dma { */ struct cryp_device_data { struct cryp_register __iomem *base; + phys_addr_t phybase; struct device *dev; struct clk *clk; struct regulator *pwr_regulator; diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c index 32f480622b97..4f8b11af29a6 100644 --- a/drivers/crypto/ux500/cryp/cryp_core.c +++ b/drivers/crypto/ux500/cryp/cryp_core.c @@ -475,6 +475,19 @@ static int cryp_get_device_data(struct cryp_ctx *ctx, static void cryp_dma_setup_channel(struct cryp_device_data *device_data, struct device *dev) { + struct dma_slave_config mem2cryp = { + .direction = DMA_MEM_TO_DEV, + .dst_addr = device_data->phybase + CRYP_DMA_TX_FIFO, + .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, + .dst_maxburst = 4, + }; + struct dma_slave_config cryp2mem = { + .direction = DMA_DEV_TO_MEM, + .src_addr = device_data->phybase + CRYP_DMA_RX_FIFO, + .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, + .src_maxburst = 4, + }; + dma_cap_zero(device_data->dma.mask); dma_cap_set(DMA_SLAVE, device_data->dma.mask); @@ -490,6 +503,9 @@ static void cryp_dma_setup_channel(struct cryp_device_data *device_data, stedma40_filter, device_data->dma.cfg_cryp2mem); + dmaengine_slave_config(device_data->dma.chan_mem2cryp, &mem2cryp); + dmaengine_slave_config(device_data->dma.chan_cryp2mem, &cryp2mem); + init_completion(&device_data->dma.cryp_dma_complete); } @@ -1431,6 +1447,7 @@ static int ux500_cryp_probe(struct platform_device *pdev) goto out_kfree; } + device_data->phybase = res->start; device_data->base = ioremap(res->start, resource_size(res)); if (!device_data->base) { dev_err(dev, "[%s]: ioremap failed!", __func__); @@ -1458,11 +1475,17 @@ static int ux500_cryp_probe(struct platform_device *pdev) goto out_regulator; } + ret = clk_prepare(device_data->clk); + if (ret) { + dev_err(dev, "[%s]: clk_prepare() failed!", __func__); + goto out_clk; + } + /* Enable device power (and clock) */ ret = cryp_enable_power(device_data->dev, device_data, false); if (ret) { dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__); - goto out_clk; + goto out_clk_unprepare; } cryp_error = cryp_check(device_data); @@ -1518,11 +1541,16 @@ static int ux500_cryp_probe(struct platform_device *pdev) goto out_power; } + dev_info(dev, "successfully registered\n"); + return 0; out_power: cryp_disable_power(device_data->dev, device_data, false); +out_clk_unprepare: + clk_unprepare(device_data->clk); + out_clk: clk_put(device_data->clk); @@ -1593,6 +1621,7 @@ static int ux500_cryp_remove(struct platform_device *pdev) dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed", __func__); + clk_unprepare(device_data->clk); clk_put(device_data->clk); regulator_put(device_data->pwr_regulator); diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index cd9351cb24df..be6eb54da40f 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -11,6 +11,7 @@ #include <linux/bitops.h> #define HASH_BLOCK_SIZE 64 +#define HASH_DMA_FIFO 4 #define HASH_DMA_ALIGN_SIZE 4 #define HASH_DMA_PERFORMANCE_MIN_SIZE 1024 #define HASH_BYTES_PER_WORD 4 @@ -347,7 +348,8 @@ struct hash_req_ctx { /** * struct hash_device_data - structure for a hash device. - * @base: Pointer to the hardware base address. + * @base: Pointer to virtual base address of the hash device. + * @phybase: Pointer to physical memory location of the hash device. * @list_node: For inclusion in klist. * @dev: Pointer to the device dev structure. * @ctx_lock: Spinlock for current_ctx. @@ -361,6 +363,7 @@ struct hash_req_ctx { */ struct hash_device_data { struct hash_register __iomem *base; + phys_addr_t phybase; struct klist_node list_node; struct device *dev; struct spinlock ctx_lock; diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index cf5508967539..9ca6fbb5e30d 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -122,6 +122,13 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data, struct device *dev) { struct hash_platform_data *platform_data = dev->platform_data; + struct dma_slave_config conf = { + .direction = DMA_MEM_TO_DEV, + .dst_addr = device_data->phybase + HASH_DMA_FIFO, + .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES, + .dst_maxburst = 16, + }; + dma_cap_zero(device_data->dma.mask); dma_cap_set(DMA_SLAVE, device_data->dma.mask); @@ -131,6 +138,8 @@ static void hash_dma_setup_channel(struct hash_device_data *device_data, platform_data->dma_filter, device_data->dma.cfg_mem2hash); + dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf); + init_completion(&device_data->dma.complete); } @@ -1699,6 +1708,7 @@ static int ux500_hash_probe(struct platform_device *pdev) goto out_kfree; } + device_data->phybase = res->start; device_data->base = ioremap(res->start, resource_size(res)); if (!device_data->base) { dev_err(dev, "[%s] ioremap() failed!", @@ -1726,11 +1736,17 @@ static int ux500_hash_probe(struct platform_device *pdev) goto out_regulator; } + ret = clk_prepare(device_data->clk); + if (ret) { + dev_err(dev, "[%s] clk_prepare() failed!", __func__); + goto out_clk; + } + /* Enable device power (and clock) */ ret = hash_enable_power(device_data, false); if (ret) { dev_err(dev, "[%s]: hash_enable_power() failed!", __func__); - goto out_clk; + goto out_clk_unprepare; } ret = hash_check_hw(device_data); @@ -1756,12 +1772,15 @@ static int ux500_hash_probe(struct platform_device *pdev) goto out_power; } - dev_info(dev, "[%s] successfully probed\n", __func__); + dev_info(dev, "successfully registered\n"); return 0; out_power: hash_disable_power(device_data, false); +out_clk_unprepare: + clk_unprepare(device_data->clk); + out_clk: clk_put(device_data->clk); @@ -1826,6 +1845,7 @@ static int ux500_hash_remove(struct platform_device *pdev) dev_err(dev, "[%s]: hash_disable_power() failed", __func__); + clk_unprepare(device_data->clk); clk_put(device_data->clk); regulator_put(device_data->regulator); diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 71bf4ec300ea..fa4f9a33a74d 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -17,6 +17,8 @@ #include <linux/pm.h> #include <linux/pm_runtime.h> #include <linux/err.h> +#include <linux/of.h> +#include <linux/of_dma.h> #include <linux/amba/bus.h> #include <linux/regulator/consumer.h> #include <linux/platform_data/dma-ste-dma40.h> @@ -45,15 +47,63 @@ #define D40_LCLA_LINK_PER_EVENT_GRP 128 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP +/* Max number of logical channels per physical channel */ +#define D40_MAX_LOG_CHAN_PER_PHY 32 + /* Attempts before giving up to trying to get pages that are aligned */ #define MAX_LCLA_ALLOC_ATTEMPTS 256 /* Bit markings for allocation map */ -#define D40_ALLOC_FREE (1 << 31) -#define D40_ALLOC_PHY (1 << 30) +#define D40_ALLOC_FREE BIT(31) +#define D40_ALLOC_PHY BIT(30) #define D40_ALLOC_LOG_FREE 0 -#define MAX(a, b) (((a) < (b)) ? (b) : (a)) +#define D40_MEMCPY_MAX_CHANS 8 + +/* Reserved event lines for memcpy only. */ +#define DB8500_DMA_MEMCPY_EV_0 51 +#define DB8500_DMA_MEMCPY_EV_1 56 +#define DB8500_DMA_MEMCPY_EV_2 57 +#define DB8500_DMA_MEMCPY_EV_3 58 +#define DB8500_DMA_MEMCPY_EV_4 59 +#define DB8500_DMA_MEMCPY_EV_5 60 + +static int dma40_memcpy_channels[] = { + DB8500_DMA_MEMCPY_EV_0, + DB8500_DMA_MEMCPY_EV_1, + DB8500_DMA_MEMCPY_EV_2, + DB8500_DMA_MEMCPY_EV_3, + DB8500_DMA_MEMCPY_EV_4, + DB8500_DMA_MEMCPY_EV_5, +}; + +/* Default configuration for physcial memcpy */ +struct stedma40_chan_cfg dma40_memcpy_conf_phy = { + .mode = STEDMA40_MODE_PHYSICAL, + .dir = DMA_MEM_TO_MEM, + + .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, + .src_info.psize = STEDMA40_PSIZE_PHY_1, + .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, + + .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, + .dst_info.psize = STEDMA40_PSIZE_PHY_1, + .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, +}; + +/* Default configuration for logical memcpy */ +struct stedma40_chan_cfg dma40_memcpy_conf_log = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_MEM_TO_MEM, + + .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, + .src_info.psize = STEDMA40_PSIZE_LOG_1, + .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, + + .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE, + .dst_info.psize = STEDMA40_PSIZE_LOG_1, + .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, +}; /** * enum 40_command - The different commands and/or statuses. @@ -171,6 +221,9 @@ static u32 d40_backup_regs_chan[] = { D40_CHAN_REG_SDLNK, }; +#define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \ + BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B) + /** * struct d40_interrupt_lookup - lookup table for interrupt handler * @@ -471,6 +524,8 @@ struct d40_gen_dmac { * @phy_start: Physical memory start of the DMA registers. * @phy_size: Size of the DMA register map. * @irq: The IRQ number. + * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem + * transfers). * @num_phy_chans: The number of physical channels. Read from HW. This * is the number of available channels for this driver, not counting "Secure * mode" allocated physical channels. @@ -514,6 +569,7 @@ struct d40_base { phys_addr_t phy_start; resource_size_t phy_size; int irq; + int num_memcpy_chans; int num_phy_chans; int num_log_chans; struct device_dma_parameters dma_parms; @@ -534,7 +590,7 @@ struct d40_base { resource_size_t lcpa_size; struct kmem_cache *desc_slab; u32 reg_val_backup[BACKUP_REGS_SZ]; - u32 reg_val_backup_v4[MAX(BACKUP_REGS_SZ_V4A, BACKUP_REGS_SZ_V4B)]; + u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX]; u32 *reg_val_backup_chan; u16 gcc_pwr_off_mask; bool initialized; @@ -792,7 +848,7 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) * that uses linked lists. */ if (!(chan->phy_chan->use_soft_lli && - chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)) + chan->dma_cfg.dir == DMA_DEV_TO_MEM)) curr_lcla = d40_lcla_alloc_one(chan, desc); first_lcla = curr_lcla; @@ -954,20 +1010,21 @@ static int d40_psize_2_burst_size(bool is_log, int psize) /* * The dma only supports transmitting packages up to - * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of - * dma elements required to send the entire sg list + * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes. + * + * Calculate the total number of dma elements required to send the entire sg list. */ static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) { int dmalen; u32 max_w = max(data_width1, data_width2); u32 min_w = min(data_width1, data_width2); - u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); + u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w); if (seg_max > STEDMA40_MAX_SEG_SIZE) - seg_max -= (1 << max_w); + seg_max -= max_w; - if (!IS_ALIGNED(size, 1 << max_w)) + if (!IS_ALIGNED(size, max_w)) return -EINVAL; if (size <= seg_max) @@ -1257,21 +1314,17 @@ static void __d40_config_set_event(struct d40_chan *d40c, static void d40_config_set_event(struct d40_chan *d40c, enum d40_events event_type) { - /* Enable event line connected to device (or memcpy) */ - if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || - (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { - u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); + u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); + /* Enable event line connected to device (or memcpy) */ + if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) || + (d40c->dma_cfg.dir == DMA_DEV_TO_DEV)) __d40_config_set_event(d40c, event_type, event, D40_CHAN_REG_SSLNK); - } - - if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { - u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); + if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM) __d40_config_set_event(d40c, event_type, event, D40_CHAN_REG_SDLNK); - } } static u32 d40_chan_has_events(struct d40_chan *d40c) @@ -1417,7 +1470,7 @@ static u32 d40_residue(struct d40_chan *d40c) >> D40_SREG_ELEM_PHY_ECNT_POS; } - return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); + return num_elt * d40c->dma_cfg.dst_info.data_width; } static bool d40_tx_is_linked(struct d40_chan *d40c) @@ -1693,7 +1746,7 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data) } /* ACK interrupt */ - writel(1 << idx, base->virtbase + il[row].clr); + writel(BIT(idx), base->virtbase + il[row].clr); spin_lock(&d40c->lock); @@ -1715,8 +1768,6 @@ static int d40_validate_conf(struct d40_chan *d40c, struct stedma40_chan_cfg *conf) { int res = 0; - u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); - u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; if (!conf->dir) { @@ -1724,48 +1775,14 @@ static int d40_validate_conf(struct d40_chan *d40c, res = -EINVAL; } - if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && - d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && - d40c->runtime_addr == 0) { - - chan_err(d40c, "Invalid TX channel address (%d)\n", - conf->dst_dev_type); - res = -EINVAL; - } - - if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && - d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && - d40c->runtime_addr == 0) { - chan_err(d40c, "Invalid RX channel address (%d)\n", - conf->src_dev_type); - res = -EINVAL; - } - - if (conf->dir == STEDMA40_MEM_TO_PERIPH && - dst_event_group == STEDMA40_DEV_DST_MEMORY) { - chan_err(d40c, "Invalid dst\n"); - res = -EINVAL; - } - - if (conf->dir == STEDMA40_PERIPH_TO_MEM && - src_event_group == STEDMA40_DEV_SRC_MEMORY) { - chan_err(d40c, "Invalid src\n"); + if ((is_log && conf->dev_type > d40c->base->num_log_chans) || + (!is_log && conf->dev_type > d40c->base->num_phy_chans) || + (conf->dev_type < 0)) { + chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type); res = -EINVAL; } - if (src_event_group == STEDMA40_DEV_SRC_MEMORY && - dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { - chan_err(d40c, "No event line\n"); - res = -EINVAL; - } - - if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && - (src_event_group != dst_event_group)) { - chan_err(d40c, "Invalid event group\n"); - res = -EINVAL; - } - - if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { + if (conf->dir == DMA_DEV_TO_DEV) { /* * DMAC HW supports it. Will be added to this driver, * in case any dma client requires it. @@ -1775,9 +1792,9 @@ static int d40_validate_conf(struct d40_chan *d40c, } if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * - (1 << conf->src_info.data_width) != + conf->src_info.data_width != d40_psize_2_burst_size(is_log, conf->dst_info.psize) * - (1 << conf->dst_info.data_width)) { + conf->dst_info.data_width) { /* * The DMAC hardware only supports * src (burst x width) == dst (burst x width) @@ -1819,8 +1836,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy, if (phy->allocated_src == D40_ALLOC_FREE) phy->allocated_src = D40_ALLOC_LOG_FREE; - if (!(phy->allocated_src & (1 << log_event_line))) { - phy->allocated_src |= 1 << log_event_line; + if (!(phy->allocated_src & BIT(log_event_line))) { + phy->allocated_src |= BIT(log_event_line); goto found; } else goto not_found; @@ -1831,8 +1848,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy, if (phy->allocated_dst == D40_ALLOC_FREE) phy->allocated_dst = D40_ALLOC_LOG_FREE; - if (!(phy->allocated_dst & (1 << log_event_line))) { - phy->allocated_dst |= 1 << log_event_line; + if (!(phy->allocated_dst & BIT(log_event_line))) { + phy->allocated_dst |= BIT(log_event_line); goto found; } else goto not_found; @@ -1862,11 +1879,11 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, /* Logical channel */ if (is_src) { - phy->allocated_src &= ~(1 << log_event_line); + phy->allocated_src &= ~BIT(log_event_line); if (phy->allocated_src == D40_ALLOC_LOG_FREE) phy->allocated_src = D40_ALLOC_FREE; } else { - phy->allocated_dst &= ~(1 << log_event_line); + phy->allocated_dst &= ~BIT(log_event_line); if (phy->allocated_dst == D40_ALLOC_LOG_FREE) phy->allocated_dst = D40_ALLOC_FREE; } @@ -1882,7 +1899,7 @@ out: static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) { - int dev_type; + int dev_type = d40c->dma_cfg.dev_type; int event_group; int event_line; struct d40_phy_res *phys; @@ -1896,14 +1913,12 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) phys = d40c->base->phy_res; num_phy_chans = d40c->base->num_phy_chans; - if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { - dev_type = d40c->dma_cfg.src_dev_type; + if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) { log_num = 2 * dev_type; is_src = true; - } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || - d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { + } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV || + d40c->dma_cfg.dir == DMA_MEM_TO_MEM) { /* dst event lines are used for logical memcpy */ - dev_type = d40c->dma_cfg.dst_dev_type; log_num = 2 * dev_type + 1; is_src = false; } else @@ -1913,7 +1928,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) event_line = D40_TYPE_TO_EVENT(dev_type); if (!is_log) { - if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { + if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) { /* Find physical half channel */ if (d40c->dma_cfg.use_fixed_channel) { i = d40c->dma_cfg.phy_channel; @@ -2014,14 +2029,23 @@ static int d40_config_memcpy(struct d40_chan *d40c) dma_cap_mask_t cap = d40c->chan.device->cap_mask; if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { - d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; - d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; - d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> - memcpy[d40c->chan.chan_id]; + d40c->dma_cfg = dma40_memcpy_conf_log; + d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id]; + + d40_log_cfg(&d40c->dma_cfg, + &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); } else if (dma_has_cap(DMA_MEMCPY, cap) && dma_has_cap(DMA_SLAVE, cap)) { - d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; + d40c->dma_cfg = dma40_memcpy_conf_phy; + + /* Generate interrrupt at end of transfer or relink. */ + d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS); + + /* Generate interrupt on error. */ + d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS); + d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS); + } else { chan_err(d40c, "No memcpy\n"); return -EINVAL; @@ -2034,7 +2058,7 @@ static int d40_free_dma(struct d40_chan *d40c) { int res = 0; - u32 event; + u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); struct d40_phy_res *phy = d40c->phy_chan; bool is_src; @@ -2052,14 +2076,12 @@ static int d40_free_dma(struct d40_chan *d40c) return -EINVAL; } - if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || - d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { - event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); + if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV || + d40c->dma_cfg.dir == DMA_MEM_TO_MEM) is_src = false; - } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { - event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); + else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) is_src = true; - } else { + else { chan_err(d40c, "Unknown direction\n"); return -EINVAL; } @@ -2100,7 +2122,7 @@ static bool d40_is_paused(struct d40_chan *d40c) unsigned long flags; void __iomem *active_reg; u32 status; - u32 event; + u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); spin_lock_irqsave(&d40c->lock, flags); @@ -2119,12 +2141,10 @@ static bool d40_is_paused(struct d40_chan *d40c) goto _exit; } - if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || - d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { - event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); + if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV || + d40c->dma_cfg.dir == DMA_MEM_TO_MEM) { status = readl(chanbase + D40_CHAN_REG_SDLNK); - } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { - event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); + } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) { status = readl(chanbase + D40_CHAN_REG_SSLNK); } else { chan_err(d40c, "Unknown direction\n"); @@ -2255,24 +2275,6 @@ err: return NULL; } -static dma_addr_t -d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction) -{ - struct stedma40_platform_data *plat = chan->base->plat_data; - struct stedma40_chan_cfg *cfg = &chan->dma_cfg; - dma_addr_t addr = 0; - - if (chan->runtime_addr) - return chan->runtime_addr; - - if (direction == DMA_DEV_TO_MEM) - addr = plat->dev_rx[cfg->src_dev_type]; - else if (direction == DMA_MEM_TO_DEV) - addr = plat->dev_tx[cfg->dst_dev_type]; - - return addr; -} - static struct dma_async_tx_descriptor * d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, struct scatterlist *sg_dst, unsigned int sg_len, @@ -2299,14 +2301,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, if (sg_next(&sg_src[sg_len - 1]) == sg_src) desc->cyclic = true; - if (direction != DMA_TRANS_NONE) { - dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); - - if (direction == DMA_DEV_TO_MEM) - src_dev_addr = dev_addr; - else if (direction == DMA_MEM_TO_DEV) - dst_dev_addr = dev_addr; - } + if (direction == DMA_DEV_TO_MEM) + src_dev_addr = chan->runtime_addr; + else if (direction == DMA_MEM_TO_DEV) + dst_dev_addr = chan->runtime_addr; if (chan_is_logical(chan)) ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, @@ -2366,7 +2364,7 @@ static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) u32 rtreg; u32 event = D40_TYPE_TO_EVENT(dev_type); u32 group = D40_TYPE_TO_GROUP(dev_type); - u32 bit = 1 << event; + u32 bit = BIT(event); u32 prioreg; struct d40_gen_dmac *dmac = &d40c->base->gen_dmac; @@ -2397,13 +2395,57 @@ static void d40_set_prio_realtime(struct d40_chan *d40c) if (d40c->base->rev < 3) return; - if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || - (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) - __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); + if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) || + (d40c->dma_cfg.dir == DMA_DEV_TO_DEV)) + __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true); - if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || - (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) - __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); + if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) || + (d40c->dma_cfg.dir == DMA_DEV_TO_DEV)) + __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false); +} + +#define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1) +#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1) +#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1) +#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1) + +static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct stedma40_chan_cfg cfg; + dma_cap_mask_t cap; + u32 flags; + + memset(&cfg, 0, sizeof(struct stedma40_chan_cfg)); + + dma_cap_zero(cap); + dma_cap_set(DMA_SLAVE, cap); + + cfg.dev_type = dma_spec->args[0]; + flags = dma_spec->args[2]; + + switch (D40_DT_FLAGS_MODE(flags)) { + case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break; + case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break; + } + + switch (D40_DT_FLAGS_DIR(flags)) { + case 0: + cfg.dir = DMA_MEM_TO_DEV; + cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags); + break; + case 1: + cfg.dir = DMA_DEV_TO_MEM; + cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags); + break; + } + + if (D40_DT_FLAGS_FIXED_CHAN(flags)) { + cfg.phy_channel = dma_spec->args[1]; + cfg.use_fixed_channel = true; + } + + return dma_request_channel(cap, stedma40_filter, &cfg); } /* DMA ENGINE functions */ @@ -2435,23 +2477,21 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) } pm_runtime_get_sync(d40c->base->dev); - /* Fill in basic CFG register values */ - d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, - &d40c->dst_def_cfg, chan_is_logical(d40c)); d40_set_prio_realtime(d40c); if (chan_is_logical(d40c)) { - d40_log_cfg(&d40c->dma_cfg, - &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); - - if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) + if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) d40c->lcpa = d40c->base->lcpa_base + - d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; + d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE; else d40c->lcpa = d40c->base->lcpa_base + - d40c->dma_cfg.dst_dev_type * + d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; + + /* Unmask the Global Interrupt Mask. */ + d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); + d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS); } dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", @@ -2641,33 +2681,10 @@ static void d40_terminate_all(struct dma_chan *chan) static int dma40_config_to_halfchannel(struct d40_chan *d40c, struct stedma40_half_channel_info *info, - enum dma_slave_buswidth width, u32 maxburst) { - enum stedma40_periph_data_width addr_width; int psize; - switch (width) { - case DMA_SLAVE_BUSWIDTH_1_BYTE: - addr_width = STEDMA40_BYTE_WIDTH; - break; - case DMA_SLAVE_BUSWIDTH_2_BYTES: - addr_width = STEDMA40_HALFWORD_WIDTH; - break; - case DMA_SLAVE_BUSWIDTH_4_BYTES: - addr_width = STEDMA40_WORD_WIDTH; - break; - case DMA_SLAVE_BUSWIDTH_8_BYTES: - addr_width = STEDMA40_DOUBLEWORD_WIDTH; - break; - default: - dev_err(d40c->base->dev, - "illegal peripheral address width " - "requested (%d)\n", - width); - return -EINVAL; - } - if (chan_is_logical(d40c)) { if (maxburst >= 16) psize = STEDMA40_PSIZE_LOG_16; @@ -2688,7 +2705,6 @@ dma40_config_to_halfchannel(struct d40_chan *d40c, psize = STEDMA40_PSIZE_PHY_1; } - info->data_width = addr_width; info->psize = psize; info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; @@ -2712,21 +2728,14 @@ static int d40_set_runtime_config(struct dma_chan *chan, dst_maxburst = config->dst_maxburst; if (config->direction == DMA_DEV_TO_MEM) { - dma_addr_t dev_addr_rx = - d40c->base->plat_data->dev_rx[cfg->src_dev_type]; - config_addr = config->src_addr; - if (dev_addr_rx) - dev_dbg(d40c->base->dev, - "channel has a pre-wired RX address %08x " - "overriding with %08x\n", - dev_addr_rx, config_addr); - if (cfg->dir != STEDMA40_PERIPH_TO_MEM) + + if (cfg->dir != DMA_DEV_TO_MEM) dev_dbg(d40c->base->dev, "channel was not configured for peripheral " "to memory transfer (%d) overriding\n", cfg->dir); - cfg->dir = STEDMA40_PERIPH_TO_MEM; + cfg->dir = DMA_DEV_TO_MEM; /* Configure the memory side */ if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) @@ -2735,21 +2744,14 @@ static int d40_set_runtime_config(struct dma_chan *chan, dst_maxburst = src_maxburst; } else if (config->direction == DMA_MEM_TO_DEV) { - dma_addr_t dev_addr_tx = - d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; - config_addr = config->dst_addr; - if (dev_addr_tx) - dev_dbg(d40c->base->dev, - "channel has a pre-wired TX address %08x " - "overriding with %08x\n", - dev_addr_tx, config_addr); - if (cfg->dir != STEDMA40_MEM_TO_PERIPH) + + if (cfg->dir != DMA_MEM_TO_DEV) dev_dbg(d40c->base->dev, "channel was not configured for memory " "to peripheral transfer (%d) overriding\n", cfg->dir); - cfg->dir = STEDMA40_MEM_TO_PERIPH; + cfg->dir = DMA_MEM_TO_DEV; /* Configure the memory side */ if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) @@ -2763,6 +2765,11 @@ static int d40_set_runtime_config(struct dma_chan *chan, return -EINVAL; } + if (config_addr <= 0) { + dev_err(d40c->base->dev, "no address supplied\n"); + return -EINVAL; + } + if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { dev_err(d40c->base->dev, "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", @@ -2781,14 +2788,24 @@ static int d40_set_runtime_config(struct dma_chan *chan, src_maxburst = dst_maxburst * dst_addr_width / src_addr_width; } + /* Only valid widths are; 1, 2, 4 and 8. */ + if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED || + src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES || + dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED || + dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES || + ((src_addr_width > 1) && (src_addr_width & 1)) || + ((dst_addr_width > 1) && (dst_addr_width & 1))) + return -EINVAL; + + cfg->src_info.data_width = src_addr_width; + cfg->dst_info.data_width = dst_addr_width; + ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, - src_addr_width, src_maxburst); if (ret) return ret; ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, - dst_addr_width, dst_maxburst); if (ret) return ret; @@ -2797,8 +2814,7 @@ static int d40_set_runtime_config(struct dma_chan *chan, if (chan_is_logical(d40c)) d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); else - d40_phy_cfg(cfg, &d40c->src_def_cfg, - &d40c->dst_def_cfg, false); + d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg); /* These settings will take precedence later */ d40c->runtime_addr = config_addr; @@ -2929,7 +2945,7 @@ static int __init d40_dmaengine_init(struct d40_base *base, } d40_chan_init(base, &base->dma_memcpy, base->log_chans, - base->num_log_chans, base->plat_data->memcpy_len); + base->num_log_chans, base->num_memcpy_chans); dma_cap_zero(base->dma_memcpy.cap_mask); dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); @@ -3123,13 +3139,14 @@ static int __init d40_phy_res_init(struct d40_base *base) static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) { - struct stedma40_platform_data *plat_data; + struct stedma40_platform_data *plat_data = pdev->dev.platform_data; struct clk *clk = NULL; void __iomem *virtbase = NULL; struct resource *res = NULL; struct d40_base *base = NULL; int num_log_chans = 0; int num_phy_chans; + int num_memcpy_chans; int clk_ret = -EINVAL; int i; u32 pid; @@ -3189,8 +3206,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) * DB8540v1 has revision 4 */ rev = AMBA_REV_BITS(pid); - - plat_data = pdev->dev.platform_data; + if (rev < 2) { + d40_err(&pdev->dev, "hardware revision: %d is not supported", rev); + goto failure; + } /* The number of physical channels on this HW */ if (plat_data->num_of_phy_chans) @@ -3198,26 +3217,20 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) else num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; - dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n", - rev, res->start, num_phy_chans); - - if (rev < 2) { - d40_err(&pdev->dev, "hardware revision: %d is not supported", - rev); - goto failure; - } + /* The number of channels used for memcpy */ + if (plat_data->num_of_memcpy_chans) + num_memcpy_chans = plat_data->num_of_memcpy_chans; + else + num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels); - /* Count the number of logical channels in use */ - for (i = 0; i < plat_data->dev_len; i++) - if (plat_data->dev_rx[i] != 0) - num_log_chans++; + num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY; - for (i = 0; i < plat_data->dev_len; i++) - if (plat_data->dev_tx[i] != 0) - num_log_chans++; + dev_info(&pdev->dev, + "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n", + rev, res->start, num_phy_chans, num_log_chans); base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + - (num_phy_chans + num_log_chans + plat_data->memcpy_len) * + (num_phy_chans + num_log_chans + num_memcpy_chans) * sizeof(struct d40_chan), GFP_KERNEL); if (base == NULL) { @@ -3227,6 +3240,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) base->rev = rev; base->clk = clk; + base->num_memcpy_chans = num_memcpy_chans; base->num_phy_chans = num_phy_chans; base->num_log_chans = num_log_chans; base->phy_start = res->start; @@ -3278,17 +3292,11 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) if (!base->lookup_phy_chans) goto failure; - if (num_log_chans + plat_data->memcpy_len) { - /* - * The max number of logical channels are event lines for all - * src devices and dst devices - */ - base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * - sizeof(struct d40_chan *), - GFP_KERNEL); - if (!base->lookup_log_chans) - goto failure; - } + base->lookup_log_chans = kzalloc(num_log_chans * + sizeof(struct d40_chan *), + GFP_KERNEL); + if (!base->lookup_log_chans) + goto failure; base->reg_val_backup_chan = kmalloc(base->num_phy_chans * sizeof(d40_backup_regs_chan), @@ -3472,17 +3480,83 @@ failure: return ret; } +static int __init d40_of_probe(struct platform_device *pdev, + struct device_node *np) +{ + struct stedma40_platform_data *pdata; + int num_phy = 0, num_memcpy = 0, num_disabled = 0; + const const __be32 *list; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct stedma40_platform_data), + GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + /* If absent this value will be obtained from h/w. */ + of_property_read_u32(np, "dma-channels", &num_phy); + if (num_phy > 0) + pdata->num_of_phy_chans = num_phy; + + list = of_get_property(np, "memcpy-channels", &num_memcpy); + num_memcpy /= sizeof(*list); + + if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) { + d40_err(&pdev->dev, + "Invalid number of memcpy channels specified (%d)\n", + num_memcpy); + return -EINVAL; + } + pdata->num_of_memcpy_chans = num_memcpy; + + of_property_read_u32_array(np, "memcpy-channels", + dma40_memcpy_channels, + num_memcpy); + + list = of_get_property(np, "disabled-channels", &num_disabled); + num_disabled /= sizeof(*list); + + if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) { + d40_err(&pdev->dev, + "Invalid number of disabled channels specified (%d)\n", + num_disabled); + return -EINVAL; + } + + of_property_read_u32_array(np, "disabled-channels", + pdata->disabled_channels, + num_disabled); + pdata->disabled_channels[num_disabled] = -1; + + pdev->dev.platform_data = pdata; + + return 0; +} + static int __init d40_probe(struct platform_device *pdev) { + struct stedma40_platform_data *plat_data = pdev->dev.platform_data; + struct device_node *np = pdev->dev.of_node; int err; int ret = -ENOENT; - struct d40_base *base; + struct d40_base *base = NULL; struct resource *res = NULL; int num_reserved_chans; u32 val; - base = d40_hw_detect_init(pdev); + if (!plat_data) { + if (np) { + if(d40_of_probe(pdev, np)) { + ret = -ENOMEM; + goto failure; + } + } else { + d40_err(&pdev->dev, "No pdata or Device Tree provided\n"); + goto failure; + } + } + base = d40_hw_detect_init(pdev); if (!base) goto failure; @@ -3603,6 +3677,13 @@ static int __init d40_probe(struct platform_device *pdev) d40_hw_init(base); + if (np) { + err = of_dma_controller_register(np, d40_xlate, NULL); + if (err && err != -ENODEV) + dev_err(&pdev->dev, + "could not register of_dma_controller\n"); + } + dev_info(base->dev, "initialized\n"); return 0; @@ -3656,11 +3737,17 @@ failure: return ret; } +static const struct of_device_id d40_match[] = { + { .compatible = "stericsson,dma40", }, + {} +}; + static struct platform_driver d40_driver = { .driver = { .owner = THIS_MODULE, .name = D40_NAME, .pm = DMA40_PM_OPS, + .of_match_table = d40_match, }, }; diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c index 7180e0d41722..27b818dee7c7 100644 --- a/drivers/dma/ste_dma40_ll.c +++ b/drivers/dma/ste_dma40_ll.c @@ -10,6 +10,18 @@ #include "ste_dma40_ll.h" +u8 d40_width_to_bits(enum dma_slave_buswidth width) +{ + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE) + return STEDMA40_ESIZE_8_BIT; + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES) + return STEDMA40_ESIZE_16_BIT; + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES) + return STEDMA40_ESIZE_64_BIT; + else + return STEDMA40_ESIZE_32_BIT; +} + /* Sets up proper LCSP1 and LCSP3 register for a logical channel */ void d40_log_cfg(struct stedma40_chan_cfg *cfg, u32 *lcsp1, u32 *lcsp3) @@ -18,106 +30,100 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg, u32 l1 = 0; /* src */ /* src is mem? -> increase address pos */ - if (cfg->dir == STEDMA40_MEM_TO_PERIPH || - cfg->dir == STEDMA40_MEM_TO_MEM) - l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS; + if (cfg->dir == DMA_MEM_TO_DEV || + cfg->dir == DMA_MEM_TO_MEM) + l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS); /* dst is mem? -> increase address pos */ - if (cfg->dir == STEDMA40_PERIPH_TO_MEM || - cfg->dir == STEDMA40_MEM_TO_MEM) - l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS; + if (cfg->dir == DMA_DEV_TO_MEM || + cfg->dir == DMA_MEM_TO_MEM) + l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS); /* src is hw? -> master port 1 */ - if (cfg->dir == STEDMA40_PERIPH_TO_MEM || - cfg->dir == STEDMA40_PERIPH_TO_PERIPH) - l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS; + if (cfg->dir == DMA_DEV_TO_MEM || + cfg->dir == DMA_DEV_TO_DEV) + l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS); /* dst is hw? -> master port 1 */ - if (cfg->dir == STEDMA40_MEM_TO_PERIPH || - cfg->dir == STEDMA40_PERIPH_TO_PERIPH) - l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS; + if (cfg->dir == DMA_MEM_TO_DEV || + cfg->dir == DMA_DEV_TO_DEV) + l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS); - l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS; + l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS); l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS; - l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS; + l3 |= d40_width_to_bits(cfg->dst_info.data_width) + << D40_MEM_LCSP3_DCFG_ESIZE_POS; - l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS; + l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS); l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS; - l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS; + l1 |= d40_width_to_bits(cfg->src_info.data_width) + << D40_MEM_LCSP1_SCFG_ESIZE_POS; *lcsp1 = l1; *lcsp3 = l3; } -/* Sets up SRC and DST CFG register for both logical and physical channels */ -void d40_phy_cfg(struct stedma40_chan_cfg *cfg, - u32 *src_cfg, u32 *dst_cfg, bool is_log) +void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg) { u32 src = 0; u32 dst = 0; - if (!is_log) { - /* Physical channel */ - if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) || - (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { - /* Set master port to 1 */ - src |= 1 << D40_SREG_CFG_MST_POS; - src |= D40_TYPE_TO_EVENT(cfg->src_dev_type); - - if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) - src |= 1 << D40_SREG_CFG_PHY_TM_POS; - else - src |= 3 << D40_SREG_CFG_PHY_TM_POS; - } - if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) || - (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) { - /* Set master port to 1 */ - dst |= 1 << D40_SREG_CFG_MST_POS; - dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type); - - if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) - dst |= 1 << D40_SREG_CFG_PHY_TM_POS; - else - dst |= 3 << D40_SREG_CFG_PHY_TM_POS; - } - /* Interrupt on end of transfer for destination */ - dst |= 1 << D40_SREG_CFG_TIM_POS; - - /* Generate interrupt on error */ - src |= 1 << D40_SREG_CFG_EIM_POS; - dst |= 1 << D40_SREG_CFG_EIM_POS; - - /* PSIZE */ - if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) { - src |= 1 << D40_SREG_CFG_PHY_PEN_POS; - src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS; - } - if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) { - dst |= 1 << D40_SREG_CFG_PHY_PEN_POS; - dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS; - } - - /* Element size */ - src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS; - dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS; - - /* Set the priority bit to high for the physical channel */ - if (cfg->high_priority) { - src |= 1 << D40_SREG_CFG_PRI_POS; - dst |= 1 << D40_SREG_CFG_PRI_POS; - } - - } else { - /* Logical channel */ - dst |= 1 << D40_SREG_CFG_LOG_GIM_POS; - src |= 1 << D40_SREG_CFG_LOG_GIM_POS; + if ((cfg->dir == DMA_DEV_TO_MEM) || + (cfg->dir == DMA_DEV_TO_DEV)) { + /* Set master port to 1 */ + src |= BIT(D40_SREG_CFG_MST_POS); + src |= D40_TYPE_TO_EVENT(cfg->dev_type); + + if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) + src |= BIT(D40_SREG_CFG_PHY_TM_POS); + else + src |= 3 << D40_SREG_CFG_PHY_TM_POS; + } + if ((cfg->dir == DMA_MEM_TO_DEV) || + (cfg->dir == DMA_DEV_TO_DEV)) { + /* Set master port to 1 */ + dst |= BIT(D40_SREG_CFG_MST_POS); + dst |= D40_TYPE_TO_EVENT(cfg->dev_type); + + if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) + dst |= BIT(D40_SREG_CFG_PHY_TM_POS); + else + dst |= 3 << D40_SREG_CFG_PHY_TM_POS; + } + /* Interrupt on end of transfer for destination */ + dst |= BIT(D40_SREG_CFG_TIM_POS); + + /* Generate interrupt on error */ + src |= BIT(D40_SREG_CFG_EIM_POS); + dst |= BIT(D40_SREG_CFG_EIM_POS); + + /* PSIZE */ + if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) { + src |= BIT(D40_SREG_CFG_PHY_PEN_POS); + src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS; + } + if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) { + dst |= BIT(D40_SREG_CFG_PHY_PEN_POS); + dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS; + } + + /* Element size */ + src |= d40_width_to_bits(cfg->src_info.data_width) + << D40_SREG_CFG_ESIZE_POS; + dst |= d40_width_to_bits(cfg->dst_info.data_width) + << D40_SREG_CFG_ESIZE_POS; + + /* Set the priority bit to high for the physical channel */ + if (cfg->high_priority) { + src |= BIT(D40_SREG_CFG_PRI_POS); + dst |= BIT(D40_SREG_CFG_PRI_POS); } if (cfg->src_info.big_endian) - src |= 1 << D40_SREG_CFG_LBE_POS; + src |= BIT(D40_SREG_CFG_LBE_POS); if (cfg->dst_info.big_endian) - dst |= 1 << D40_SREG_CFG_LBE_POS; + dst |= BIT(D40_SREG_CFG_LBE_POS); *src_cfg = src; *dst_cfg = dst; @@ -143,23 +149,22 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli, num_elems = 2 << psize; /* Must be aligned */ - if (!IS_ALIGNED(data, 0x1 << data_width)) + if (!IS_ALIGNED(data, data_width)) return -EINVAL; /* Transfer size can't be smaller than (num_elms * elem_size) */ - if (data_size < num_elems * (0x1 << data_width)) + if (data_size < num_elems * data_width) return -EINVAL; /* The number of elements. IE now many chunks */ - lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS; + lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS; /* * Distance to next element sized entry. * Usually the size of the element unless you want gaps. */ if (addr_inc) - lli->reg_elt |= (0x1 << data_width) << - D40_SREG_ELEM_PHY_EIDX_POS; + lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS; /* Where the data is */ lli->reg_ptr = data; @@ -167,18 +172,20 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli, /* If this scatter list entry is the last one, no next link */ if (next_lli == 0) - lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS; + lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS); else lli->reg_lnk = next_lli; /* Set/clear interrupt generation on this link item.*/ if (term_int) - lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS; + lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS); else - lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS); + lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS); - /* Post link */ - lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS; + /* + * Post link - D40_SREG_LNK_PHY_PRE_POS = 0 + * Relink happens after transfer completion. + */ return 0; } @@ -187,16 +194,16 @@ static int d40_seg_size(int size, int data_width1, int data_width2) { u32 max_w = max(data_width1, data_width2); u32 min_w = min(data_width1, data_width2); - u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); + u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w); if (seg_max > STEDMA40_MAX_SEG_SIZE) - seg_max -= (1 << max_w); + seg_max -= max_w; if (size <= seg_max) return size; if (size <= 2 * seg_max) - return ALIGN(size / 2, 1 << max_w); + return ALIGN(size / 2, max_w); return seg_max; } @@ -362,10 +369,10 @@ static void d40_log_fill_lli(struct d40_log_lli *lli, lli->lcsp13 = reg_cfg; /* The number of elements to transfer */ - lli->lcsp02 = ((data_size >> data_width) << + lli->lcsp02 = ((data_size / data_width) << D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK; - BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE); + BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE); /* 16 LSBs address of the current element */ lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK; diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index fdde8ef77542..1b47312bc574 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h @@ -432,8 +432,7 @@ enum d40_lli_flags { void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, - u32 *dst_cfg, - bool is_log); + u32 *dst_cfg); void d40_log_cfg(struct stedma40_chan_cfg *cfg, u32 *lcsp1, diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index b4ca450947b8..f3327533bfd5 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -49,6 +49,9 @@ struct gpio_rcar_priv { #define POSNEG 0x20 #define EDGLEVEL 0x24 #define FILONOFF 0x28 +#define BOTHEDGE 0x4c + +#define RCAR_MAX_GPIO_PER_BANK 32 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) { @@ -91,7 +94,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d) static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, unsigned int hwirq, bool active_high_rising_edge, - bool level_trigger) + bool level_trigger, + bool both) { unsigned long flags; @@ -108,6 +112,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, /* Configure edge or level trigger in EDGLEVEL */ gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); + /* Select one edge or both edges in BOTHEDGE */ + if (p->config.has_both_edge_trigger) + gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); + /* Select "Interrupt Input Mode" in IOINTSEL */ gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); @@ -127,16 +135,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_LEVEL_HIGH: - gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true); + gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, + false); break; case IRQ_TYPE_LEVEL_LOW: - gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true); + gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, + false); break; case IRQ_TYPE_EDGE_RISING: - gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false); + gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, + false); break; case IRQ_TYPE_EDGE_FALLING: - gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false); + gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, + false); + break; + case IRQ_TYPE_EDGE_BOTH: + if (!p->config.has_both_edge_trigger) + return -EINVAL; + gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, + true); break; default: return -EINVAL; @@ -258,9 +276,39 @@ static struct irq_domain_ops gpio_rcar_irq_domain_ops = { .map = gpio_rcar_irq_domain_map, }; +static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) +{ + struct gpio_rcar_config *pdata = p->pdev->dev.platform_data; +#ifdef CONFIG_OF + struct device_node *np = p->pdev->dev.of_node; + struct of_phandle_args args; + int ret; +#endif + + if (pdata) + p->config = *pdata; +#ifdef CONFIG_OF + else if (np) { + ret = of_parse_phandle_with_args(np, "gpio-ranges", + "#gpio-range-cells", 0, &args); + p->config.number_of_pins = ret == 0 && args.args_count == 3 + ? args.args[2] + : RCAR_MAX_GPIO_PER_BANK; + p->config.gpio_base = -1; + } +#endif + + if (p->config.number_of_pins == 0 || + p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { + dev_warn(&p->pdev->dev, + "Invalid number of gpio lines %u, using %u\n", + p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK); + p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK; + } +} + static int gpio_rcar_probe(struct platform_device *pdev) { - struct gpio_rcar_config *pdata = pdev->dev.platform_data; struct gpio_rcar_priv *p; struct resource *io, *irq; struct gpio_chip *gpio_chip; @@ -275,14 +323,14 @@ static int gpio_rcar_probe(struct platform_device *pdev) goto err0; } - /* deal with driver instance configuration */ - if (pdata) - p->config = *pdata; - p->pdev = pdev; - platform_set_drvdata(pdev, p); spin_lock_init(&p->lock); + /* Get device configuration from DT node or platform data. */ + gpio_rcar_parse_pdata(p); + + platform_set_drvdata(pdev, p); + io = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); @@ -309,6 +357,7 @@ static int gpio_rcar_probe(struct platform_device *pdev) gpio_chip->set = gpio_rcar_set; gpio_chip->to_irq = gpio_rcar_to_irq; gpio_chip->label = name; + gpio_chip->dev = &pdev->dev; gpio_chip->owner = THIS_MODULE; gpio_chip->base = p->config.gpio_base; gpio_chip->ngpio = p->config.number_of_pins; @@ -333,7 +382,7 @@ static int gpio_rcar_probe(struct platform_device *pdev) } if (devm_request_irq(&pdev->dev, irq->start, - gpio_rcar_irq_handler, 0, name, p)) { + gpio_rcar_irq_handler, IRQF_SHARED, name, p)) { dev_err(&pdev->dev, "failed to request IRQ\n"); ret = -ENOENT; goto err1; @@ -355,10 +404,12 @@ static int gpio_rcar_probe(struct platform_device *pdev) p->config.irq_base, ret); } - ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, - gpio_chip->base, gpio_chip->ngpio); - if (ret < 0) - dev_warn(&pdev->dev, "failed to add pin range\n"); + if (p->config.pctl_name) { + ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, + gpio_chip->base, gpio_chip->ngpio); + if (ret < 0) + dev_warn(&pdev->dev, "failed to add pin range\n"); + } return 0; @@ -381,11 +432,23 @@ static int gpio_rcar_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_OF +static const struct of_device_id gpio_rcar_of_table[] = { + { + .compatible = "renesas,gpio-rcar", + }, + { }, +}; + +MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); +#endif + static struct platform_driver gpio_rcar_device_driver = { .probe = gpio_rcar_probe, .remove = gpio_rcar_remove, .driver = { .name = "gpio_rcar", + .of_match_table = of_match_ptr(gpio_rcar_of_table), } }; diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index b22ca7933745..a1392f47bbda 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -933,67 +933,6 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip) s3c_gpiolib_track(chip); } -#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) -static int s3c24xx_gpio_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, u32 *flags) -{ - unsigned int pin; - - if (WARN_ON(gc->of_gpio_n_cells < 3)) - return -EINVAL; - - if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) - return -EINVAL; - - if (gpiospec->args[0] > gc->ngpio) - return -EINVAL; - - pin = gc->base + gpiospec->args[0]; - - if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1]))) - pr_warn("gpio_xlate: failed to set pin function\n"); - if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff)) - pr_warn("gpio_xlate: failed to set pin pull up/down\n"); - - if (flags) - *flags = gpiospec->args[2] >> 16; - - return gpiospec->args[0]; -} - -static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = { - { .compatible = "samsung,s3c24xx-gpio", }, - {} -}; - -static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, - u64 base, u64 offset) -{ - struct gpio_chip *gc = &chip->chip; - u64 address; - - if (!of_have_populated_dt()) - return; - - address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset; - gc->of_node = of_find_matching_node_by_address(NULL, - s3c24xx_gpio_dt_match, address); - if (!gc->of_node) { - pr_info("gpio: device tree node not found for gpio controller" - " with base address %08llx\n", address); - return; - } - gc->of_gpio_n_cells = 3; - gc->of_xlate = s3c24xx_gpio_xlate; -} -#else -static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, - u64 base, u64 offset) -{ - return; -} -#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */ - static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, int nr_chips, void __iomem *base) { @@ -1018,8 +957,6 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, gc->direction_output = samsung_gpiolib_2bit_output; samsung_gpiolib_add(chip); - - s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10); } } @@ -3026,6 +2963,10 @@ static __init int samsung_gpiolib_init(void) */ struct device_node *pctrl_np; static const struct of_device_id exynos_pinctrl_ids[] = { + { .compatible = "samsung,s3c2412-pinctrl", }, + { .compatible = "samsung,s3c2416-pinctrl", }, + { .compatible = "samsung,s3c2440-pinctrl", }, + { .compatible = "samsung,s3c2450-pinctrl", }, { .compatible = "samsung,exynos4210-pinctrl", }, { .compatible = "samsung,exynos4x12-pinctrl", }, { .compatible = "samsung,exynos5250-pinctrl", }, diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 9545c9f03809..c8b5c13bcd05 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -16,4 +16,38 @@ config PL320_MBOX Management Engine, primarily for cpufreq. Say Y here if you want to use the PL320 IPCM support. +config OMAP_MBOX + tristate + help + This option is selected by any OMAP architecture specific mailbox + driver such as CONFIG_OMAP1_MBOX or CONFIG_OMAP2PLUS_MBOX. This + enables the common OMAP mailbox framework code. + +config OMAP1_MBOX + tristate "OMAP1 Mailbox framework support" + depends on ARCH_OMAP1 + select OMAP_MBOX + help + Mailbox implementation for OMAP chips with hardware for + interprocessor communication involving DSP in OMAP1. Say Y here + if you want to use OMAP1 Mailbox framework support. + +config OMAP2PLUS_MBOX + tristate "OMAP2+ Mailbox framework support" + depends on ARCH_OMAP2PLUS + select OMAP_MBOX + help + Mailbox implementation for OMAP family chips with hardware for + interprocessor communication involving DSP, IVA1.0 and IVA2 in + OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you + want to use OMAP2+ Mailbox framework support. + +config OMAP_MBOX_KFIFO_SIZE + int "Mailbox kfifo default buffer size (bytes)" + depends on OMAP2PLUS_MBOX || OMAP1_MBOX + default 256 + help + Specify the default size of mailbox's kfifo buffers (bytes). + This can also be changed at runtime (via the mbox_kfifo_size + module parameter). endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 543ad6a79505..e0facb34084a 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -1 +1,7 @@ obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o + +obj-$(CONFIG_OMAP_MBOX) += omap-mailbox.o +obj-$(CONFIG_OMAP1_MBOX) += mailbox_omap1.o +mailbox_omap1-objs := mailbox-omap1.o +obj-$(CONFIG_OMAP2PLUS_MBOX) += mailbox_omap2.o +mailbox_omap2-objs := mailbox-omap2.o diff --git a/arch/arm/mach-omap1/mailbox.c b/drivers/mailbox/mailbox-omap1.c index efc8f207f6fc..9001b7633f10 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/drivers/mailbox/mailbox-omap1.c @@ -13,7 +13,8 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> -#include <plat/mailbox.h> + +#include "omap-mbox.h" #define MAILBOX_ARM2DSP1 0x00 #define MAILBOX_ARM2DSP1b 0x04 @@ -86,21 +87,21 @@ static int omap1_mbox_fifo_full(struct omap_mbox *mbox) /* irq */ static void -omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) +omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { if (irq == IRQ_RX) enable_irq(mbox->irq); } static void -omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) +omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { if (irq == IRQ_RX) disable_irq(mbox->irq); } static int -omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) +omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { if (irq == IRQ_TX) return 0; @@ -152,6 +153,9 @@ static int omap1_mbox_probe(struct platform_device *pdev) list[0]->irq = platform_get_irq_byname(pdev, "dsp"); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) + return -ENOENT; + mbox_base = ioremap(mem->start, resource_size(mem)); if (!mbox_base) return -ENOMEM; diff --git a/arch/arm/mach-omap2/mailbox.c b/drivers/mailbox/mailbox-omap2.c index 0b080267b7f6..eba380d7b17f 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/drivers/mailbox/mailbox-omap2.c @@ -11,15 +11,15 @@ */ #include <linux/module.h> +#include <linux/slab.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/pm_runtime.h> +#include <linux/platform_data/mailbox-omap.h> -#include <plat/mailbox.h> - -#include "soc.h" +#include "omap-mbox.h" #define MAILBOX_REVISION 0x000 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) @@ -59,11 +59,9 @@ struct omap_mbox2_priv { u32 notfull_bit; u32 ctx[OMAP4_MBOX_NR_REGS]; unsigned long irqdisable; + u32 intr_type; }; -static void omap2_mbox_enable_irq(struct omap_mbox *mbox, - omap_mbox_type_t irq); - static inline unsigned int mbox_read_reg(size_t ofs) { return __raw_readl(mbox_base + ofs); @@ -124,8 +122,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox) } /* Mailbox IRQ handle functions */ -static void omap2_mbox_enable_irq(struct omap_mbox *mbox, - omap_mbox_type_t irq) +static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { struct omap_mbox2_priv *p = mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; @@ -135,20 +132,22 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox, mbox_write_reg(l, p->irqenable); } -static void omap2_mbox_disable_irq(struct omap_mbox *mbox, - omap_mbox_type_t irq) +static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; - if (!cpu_is_omap44xx()) + /* + * Read and update the interrupt configuration register for pre-OMAP4. + * OMAP4 and later SoCs have a dedicated interrupt disabling register. + */ + if (!p->intr_type) bit = mbox_read_reg(p->irqdisable) & ~bit; mbox_write_reg(bit, p->irqdisable); } -static void omap2_mbox_ack_irq(struct omap_mbox *mbox, - omap_mbox_type_t irq) +static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; @@ -159,8 +158,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox, mbox_read_reg(p->irqstatus); } -static int omap2_mbox_is_irq(struct omap_mbox *mbox, - omap_mbox_type_t irq) +static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) { struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; @@ -175,7 +173,8 @@ static void omap2_mbox_save_ctx(struct omap_mbox *mbox) int i; struct omap_mbox2_priv *p = mbox->priv; int nr_regs; - if (cpu_is_omap44xx()) + + if (p->intr_type) nr_regs = OMAP4_MBOX_NR_REGS; else nr_regs = MBOX_NR_REGS; @@ -192,7 +191,8 @@ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox) int i; struct omap_mbox2_priv *p = mbox->priv; int nr_regs; - if (cpu_is_omap44xx()) + + if (p->intr_type) nr_regs = OMAP4_MBOX_NR_REGS; else nr_regs = MBOX_NR_REGS; @@ -220,192 +220,120 @@ static struct omap_mbox_ops omap2_mbox_ops = { .restore_ctx = omap2_mbox_restore_ctx, }; -/* - * MAILBOX 0: ARM -> DSP, - * MAILBOX 1: ARM <- DSP. - * MAILBOX 2: ARM -> IVA, - * MAILBOX 3: ARM <- IVA. - */ - -/* FIXME: the following structs should be filled automatically by the user id */ - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2) -/* DSP */ -static struct omap_mbox2_priv omap2_mbox_dsp_priv = { - .tx_fifo = { - .msg = MAILBOX_MESSAGE(0), - .fifo_stat = MAILBOX_FIFOSTATUS(0), - }, - .rx_fifo = { - .msg = MAILBOX_MESSAGE(1), - .msg_stat = MAILBOX_MSGSTATUS(1), - }, - .irqenable = MAILBOX_IRQENABLE(0), - .irqstatus = MAILBOX_IRQSTATUS(0), - .notfull_bit = MAILBOX_IRQ_NOTFULL(0), - .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), - .irqdisable = MAILBOX_IRQENABLE(0), -}; - -struct omap_mbox mbox_dsp_info = { - .name = "dsp", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_dsp_priv, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP3) -struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; -#endif - -#if defined(CONFIG_SOC_OMAP2420) -/* IVA */ -static struct omap_mbox2_priv omap2_mbox_iva_priv = { - .tx_fifo = { - .msg = MAILBOX_MESSAGE(2), - .fifo_stat = MAILBOX_FIFOSTATUS(2), - }, - .rx_fifo = { - .msg = MAILBOX_MESSAGE(3), - .msg_stat = MAILBOX_MSGSTATUS(3), - }, - .irqenable = MAILBOX_IRQENABLE(3), - .irqstatus = MAILBOX_IRQSTATUS(3), - .notfull_bit = MAILBOX_IRQ_NOTFULL(2), - .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), - .irqdisable = MAILBOX_IRQENABLE(3), -}; - -static struct omap_mbox mbox_iva_info = { - .name = "iva", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_iva_priv, -}; -#endif - -#ifdef CONFIG_ARCH_OMAP2 -struct omap_mbox *omap2_mboxes[] = { - &mbox_dsp_info, -#ifdef CONFIG_SOC_OMAP2420 - &mbox_iva_info, -#endif - NULL -}; -#endif - -#if defined(CONFIG_ARCH_OMAP4) -/* OMAP4 */ -static struct omap_mbox2_priv omap2_mbox_1_priv = { - .tx_fifo = { - .msg = MAILBOX_MESSAGE(0), - .fifo_stat = MAILBOX_FIFOSTATUS(0), - }, - .rx_fifo = { - .msg = MAILBOX_MESSAGE(1), - .msg_stat = MAILBOX_MSGSTATUS(1), - }, - .irqenable = OMAP4_MAILBOX_IRQENABLE(0), - .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0), - .notfull_bit = MAILBOX_IRQ_NOTFULL(0), - .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), - .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0), -}; - -struct omap_mbox mbox_1_info = { - .name = "mailbox-1", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_1_priv, -}; - -static struct omap_mbox2_priv omap2_mbox_2_priv = { - .tx_fifo = { - .msg = MAILBOX_MESSAGE(3), - .fifo_stat = MAILBOX_FIFOSTATUS(3), - }, - .rx_fifo = { - .msg = MAILBOX_MESSAGE(2), - .msg_stat = MAILBOX_MSGSTATUS(2), - }, - .irqenable = OMAP4_MAILBOX_IRQENABLE(0), - .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0), - .notfull_bit = MAILBOX_IRQ_NOTFULL(3), - .newmsg_bit = MAILBOX_IRQ_NEWMSG(2), - .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0), -}; - -struct omap_mbox mbox_2_info = { - .name = "mailbox-2", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_2_priv, -}; - -struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL }; -#endif - static int omap2_mbox_probe(struct platform_device *pdev) { struct resource *mem; int ret; - struct omap_mbox **list; - - if (false) - ; -#if defined(CONFIG_ARCH_OMAP3) - else if (cpu_is_omap34xx()) { - list = omap3_mboxes; + struct omap_mbox **list, *mbox, *mboxblk; + struct omap_mbox2_priv *priv, *privblk; + struct omap_mbox_pdata *pdata = pdev->dev.platform_data; + struct omap_mbox_dev_info *info; + int i; - list[0]->irq = platform_get_irq(pdev, 0); + if (!pdata || !pdata->info_cnt || !pdata->info) { + pr_err("%s: platform not supported\n", __func__); + return -ENODEV; } -#endif -#if defined(CONFIG_ARCH_OMAP2) - else if (cpu_is_omap2430()) { - list = omap2_mboxes; - list[0]->irq = platform_get_irq(pdev, 0); - } else if (cpu_is_omap2420()) { - list = omap2_mboxes; + /* allocate one extra for marking end of list */ + list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL); + if (!list) + return -ENOMEM; - list[0]->irq = platform_get_irq_byname(pdev, "dsp"); - list[1]->irq = platform_get_irq_byname(pdev, "iva"); + mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL); + if (!mboxblk) { + ret = -ENOMEM; + goto free_list; } -#endif -#if defined(CONFIG_ARCH_OMAP4) - else if (cpu_is_omap44xx()) { - list = omap4_mboxes; - list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0); + privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL); + if (!privblk) { + ret = -ENOMEM; + goto free_mboxblk; } -#endif - else { - pr_err("%s: platform not supported\n", __func__); - return -ENODEV; + + info = pdata->info; + for (i = 0; i < pdata->info_cnt; i++, info++, priv++) { + priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id); + priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id); + priv->rx_fifo.msg = MAILBOX_MESSAGE(info->rx_id); + priv->rx_fifo.msg_stat = MAILBOX_MSGSTATUS(info->rx_id); + priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id); + priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id); + if (pdata->intr_type) { + priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id); + priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id); + priv->irqdisable = + OMAP4_MAILBOX_IRQENABLE_CLR(info->usr_id); + } else { + priv->irqenable = MAILBOX_IRQENABLE(info->usr_id); + priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id); + priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id); + } + priv->intr_type = pdata->intr_type; + + mbox->priv = priv; + mbox->name = info->name; + mbox->ops = &omap2_mbox_ops; + mbox->irq = platform_get_irq(pdev, info->irq_id); + if (mbox->irq < 0) { + ret = mbox->irq; + goto free_privblk; + } + list[i] = mbox++; } mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + ret = -ENOENT; + goto free_privblk; + } + mbox_base = ioremap(mem->start, resource_size(mem)); - if (!mbox_base) - return -ENOMEM; + if (!mbox_base) { + ret = -ENOMEM; + goto free_privblk; + } ret = omap_mbox_register(&pdev->dev, list); - if (ret) { - iounmap(mbox_base); - return ret; - } + if (ret) + goto unmap_mbox; + platform_set_drvdata(pdev, list); return 0; + +unmap_mbox: + iounmap(mbox_base); +free_privblk: + kfree(privblk); +free_mboxblk: + kfree(mboxblk); +free_list: + kfree(list); + return ret; } static int omap2_mbox_remove(struct platform_device *pdev) { + struct omap_mbox2_priv *privblk; + struct omap_mbox **list = platform_get_drvdata(pdev); + struct omap_mbox *mboxblk = list[0]; + + privblk = mboxblk->priv; omap_mbox_unregister(); iounmap(mbox_base); + kfree(privblk); + kfree(mboxblk); + kfree(list); + platform_set_drvdata(pdev, NULL); + return 0; } static struct platform_driver omap2_mbox_driver = { - .probe = omap2_mbox_probe, - .remove = omap2_mbox_remove, - .driver = { + .probe = omap2_mbox_probe, + .remove = omap2_mbox_remove, + .driver = { .name = "omap-mailbox", }, }; diff --git a/arch/arm/plat-omap/mailbox.c b/drivers/mailbox/omap-mailbox.c index 42377ef9ea3d..d79a646b9042 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/drivers/mailbox/omap-mailbox.c @@ -31,7 +31,7 @@ #include <linux/notifier.h> #include <linux/module.h> -#include <plat/mailbox.h> +#include "omap-mbox.h" static struct omap_mbox **mboxes; @@ -116,6 +116,40 @@ out: } EXPORT_SYMBOL(omap_mbox_msg_send); +void omap_mbox_save_ctx(struct omap_mbox *mbox) +{ + if (!mbox->ops->save_ctx) { + dev_err(mbox->dev, "%s:\tno save\n", __func__); + return; + } + + mbox->ops->save_ctx(mbox); +} +EXPORT_SYMBOL(omap_mbox_save_ctx); + +void omap_mbox_restore_ctx(struct omap_mbox *mbox) +{ + if (!mbox->ops->restore_ctx) { + dev_err(mbox->dev, "%s:\tno restore\n", __func__); + return; + } + + mbox->ops->restore_ctx(mbox); +} +EXPORT_SYMBOL(omap_mbox_restore_ctx); + +void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) +{ + mbox->ops->enable_irq(mbox, irq); +} +EXPORT_SYMBOL(omap_mbox_enable_irq); + +void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) +{ + mbox->ops->disable_irq(mbox, irq); +} +EXPORT_SYMBOL(omap_mbox_disable_irq); + static void mbox_tx_tasklet(unsigned long tx_data) { struct omap_mbox *mbox = (struct omap_mbox *)tx_data; @@ -261,13 +295,6 @@ static int omap_mbox_startup(struct omap_mbox *mbox) } if (!mbox->use_count++) { - ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, - mbox->name, mbox); - if (unlikely(ret)) { - pr_err("failed to register mailbox interrupt:%d\n", - ret); - goto fail_request_irq; - } mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); if (!mq) { ret = -ENOMEM; @@ -282,17 +309,24 @@ static int omap_mbox_startup(struct omap_mbox *mbox) } mbox->rxq = mq; mq->mbox = mbox; + ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, + mbox->name, mbox); + if (unlikely(ret)) { + pr_err("failed to register mailbox interrupt:%d\n", + ret); + goto fail_request_irq; + } omap_mbox_enable_irq(mbox, IRQ_RX); } mutex_unlock(&mbox_configured_lock); return 0; +fail_request_irq: + mbox_queue_free(mbox->rxq); fail_alloc_rxq: mbox_queue_free(mbox->txq); fail_alloc_txq: - free_irq(mbox->irq, mbox); -fail_request_irq: if (mbox->ops->shutdown) mbox->ops->shutdown(mbox); mbox->use_count--; diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/drivers/mailbox/omap-mbox.h index cc3921e9059c..6cd38fc68599 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/drivers/mailbox/omap-mbox.h @@ -1,20 +1,20 @@ -/* mailbox.h */ +/* + * omap-mbox.h: OMAP mailbox internal definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ -#ifndef MAILBOX_H -#define MAILBOX_H +#ifndef OMAP_MBOX_H +#define OMAP_MBOX_H -#include <linux/spinlock.h> -#include <linux/workqueue.h> -#include <linux/interrupt.h> #include <linux/device.h> +#include <linux/interrupt.h> #include <linux/kfifo.h> - -typedef u32 mbox_msg_t; -struct omap_mbox; - -typedef int __bitwise omap_mbox_irq_t; -#define IRQ_TX ((__force omap_mbox_irq_t) 1) -#define IRQ_RX ((__force omap_mbox_irq_t) 2) +#include <linux/spinlock.h> +#include <linux/workqueue.h> +#include <linux/omap-mailbox.h> typedef int __bitwise omap_mbox_type_t; #define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1) @@ -51,55 +51,17 @@ struct omap_mbox_queue { }; struct omap_mbox { - char *name; + const char *name; unsigned int irq; struct omap_mbox_queue *txq, *rxq; struct omap_mbox_ops *ops; struct device *dev; void *priv; int use_count; - struct blocking_notifier_head notifier; + struct blocking_notifier_head notifier; }; -int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); -void omap_mbox_init_seq(struct omap_mbox *); - -struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb); -void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb); - int omap_mbox_register(struct device *parent, struct omap_mbox **); int omap_mbox_unregister(void); -static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) -{ - if (!mbox->ops->save_ctx) { - dev_err(mbox->dev, "%s:\tno save\n", __func__); - return; - } - - mbox->ops->save_ctx(mbox); -} - -static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox) -{ - if (!mbox->ops->restore_ctx) { - dev_err(mbox->dev, "%s:\tno restore\n", __func__); - return; - } - - mbox->ops->restore_ctx(mbox); -} - -static inline void omap_mbox_enable_irq(struct omap_mbox *mbox, - omap_mbox_irq_t irq) -{ - mbox->ops->enable_irq(mbox, irq); -} - -static inline void omap_mbox_disable_irq(struct omap_mbox *mbox, - omap_mbox_irq_t irq) -{ - mbox->ops->disable_irq(mbox, irq); -} - -#endif /* MAILBOX_H */ +#endif /* OMAP_MBOX_H */ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8f6692438149..526a5d04c216 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -216,6 +216,11 @@ config PINCTRL_EXYNOS5440 select PINMUX select PINCONF +config PINCTRL_S3C24XX + bool "Samsung S3C24XX SoC pinctrl driver" + depends on ARCH_S3C24XX + select PINCTRL_SAMSUNG + config PINCTRL_S3C64XX bool "Samsung S3C64XX SoC pinctrl driver" depends on ARCH_S3C64XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9bdaeb8785ce..f90b645fb601 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o +obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o diff --git a/drivers/pinctrl/pinctrl-s3c24xx.c b/drivers/pinctrl/pinctrl-s3c24xx.c new file mode 100644 index 000000000000..c8b03996cdcb --- /dev/null +++ b/drivers/pinctrl/pinctrl-s3c24xx.c @@ -0,0 +1,652 @@ +/* + * S3C24XX specific support for Samsung pinctrl/gpiolib driver. + * + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the SamsungS3C24XX specific information required by the + * Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/irq.h> +#include <linux/of_irq.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> + +#include <asm/mach/irq.h> + +#include "pinctrl-samsung.h" + +#define NUM_EINT 24 +#define NUM_EINT_IRQ 6 +#define EINT_MAX_PER_GROUP 8 + +#define EINTPEND_REG 0xa8 +#define EINTMASK_REG 0xa4 + +#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP)) +#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88) +#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4) + +#define EINT_LEVEL_LOW 0 +#define EINT_LEVEL_HIGH 1 +#define EINT_EDGE_FALLING 2 +#define EINT_EDGE_RISING 4 +#define EINT_EDGE_BOTH 6 +#define EINT_MASK 0xf + +static struct samsung_pin_bank_type bank_type_1bit = { + .fld_width = { 1, 1, }, + .reg_offset = { 0x00, 0x04, }, +}; + +static struct samsung_pin_bank_type bank_type_2bit = { + .fld_width = { 2, 1, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, }, +}; + +#define PIN_BANK_A(pins, reg, id) \ + { \ + .type = &bank_type_1bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT(pins, reg, id) \ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ + { \ + .type = &bank_type_2bit, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_func = 2, \ + .eint_mask = emask, \ + .eint_offset = eoffs, \ + .name = id \ + } + +/** + * struct s3c24xx_eint_data: EINT common data + * @drvdata: pin controller driver data + * @domains: IRQ domains of particular EINT interrupts + * @parents: mapped parent irqs in the main interrupt controller + */ +struct s3c24xx_eint_data { + struct samsung_pinctrl_drv_data *drvdata; + struct irq_domain *domains[NUM_EINT]; + int parents[NUM_EINT_IRQ]; +}; + +/** + * struct s3c24xx_eint_domain_data: per irq-domain data + * @bank: pin bank related to the domain + * @eint_data: common data + * eint0_3_parent_only: live eints 0-3 only in the main intc + */ +struct s3c24xx_eint_domain_data { + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + bool eint0_3_parent_only; +}; + +static int s3c24xx_eint_get_trigger(unsigned int type) +{ + switch (type) { + case IRQ_TYPE_EDGE_RISING: + return EINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + return EINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + return EINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + return EINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + return EINT_LEVEL_LOW; + break; + default: + return -EINVAL; + } +} + +static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) +{ + /* Edge- and level-triggered interrupts need different handlers */ + if (type & IRQ_TYPE_EDGE_BOTH) + __irq_set_handler_locked(irq, handle_edge_irq); + else + __irq_set_handler_locked(irq, handle_level_irq); +} + +static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, + struct samsung_pin_bank *bank, int pin) +{ + struct samsung_pin_bank_type *bank_type = bank->type; + unsigned long flags; + void __iomem *reg; + u8 shift; + u32 mask; + u32 val; + + /* Make sure that pin is configured as interrupt */ + reg = d->virt_base + bank->pctl_offset; + shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; + mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; + + spin_lock_irqsave(&bank->slock, flags); + + val = readl(reg); + val &= ~(mask << shift); + val |= bank->eint_func << shift; + writel(val, reg); + + spin_unlock_irqrestore(&bank->slock, flags); +} + +static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + int index = bank->eint_offset + data->hwirq; + void __iomem *reg; + int trigger; + u8 shift; + u32 val; + + trigger = s3c24xx_eint_get_trigger(type); + if (trigger < 0) { + dev_err(d->dev, "unsupported external interrupt type\n"); + return -EINVAL; + } + + s3c24xx_eint_set_handler(data->irq, type); + + /* Set up interrupt trigger */ + reg = d->virt_base + EINT_REG(index); + shift = EINT_OFFS(index); + + val = readl(reg); + val &= ~(EINT_MASK << shift); + val |= trigger << shift; + writel(val, reg); + + s3c24xx_eint_set_function(d, bank, data->hwirq); + + return 0; +} + +/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */ + +static void s3c2410_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_ack(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_mask(irq_get_irq_data(parent_irq)); +} + +static void s3c2410_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; + struct s3c24xx_eint_data *eint_data = ddata->eint_data; + int parent_irq = eint_data->parents[data->hwirq]; + struct irq_chip *parent_chip = irq_get_chip(parent_irq); + + parent_chip->irq_unmask(irq_get_irq_data(parent_irq)); +} + +static struct irq_chip s3c2410_eint0_3_chip = { + .name = "s3c2410-eint0_3", + .irq_ack = s3c2410_eint0_3_ack, + .irq_mask = s3c2410_eint0_3_mask, + .irq_unmask = s3c2410_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); +} + +/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */ + +static void s3c2412_eint0_3_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + + unsigned long bitval = 1UL << data->hwirq; + writel(bitval, d->virt_base + EINTPEND_REG); +} + +static void s3c2412_eint0_3_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c2412_eint0_3_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << data->hwirq); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c2412_eint0_3_chip = { + .name = "s3c2412-eint0_3", + .irq_ack = s3c2412_eint0_3_ack, + .irq_mask = s3c2412_eint0_3_mask, + .irq_unmask = s3c2412_eint0_3_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct irq_data *data = irq_desc_get_irq_data(desc); + struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); + unsigned int virq; + + chained_irq_enter(chip, desc); + + /* the first 4 eints have a simple 1 to 1 mapping */ + virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq); + /* Something must be really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + + chained_irq_exit(chip, desc); +} + +/* Handling of all other eints */ + +static void s3c24xx_eint_ack(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + + writel(1UL << index, d->virt_base + EINTPEND_REG); +} + +static void s3c24xx_eint_mask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask |= (1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static void s3c24xx_eint_unmask(struct irq_data *data) +{ + struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; + unsigned char index = bank->eint_offset + data->hwirq; + unsigned long mask; + + mask = readl(d->virt_base + EINTMASK_REG); + mask &= ~(1UL << index); + writel(mask, d->virt_base + EINTMASK_REG); +} + +static struct irq_chip s3c24xx_eint_chip = { + .name = "s3c-eint", + .irq_ack = s3c24xx_eint_ack, + .irq_mask = s3c24xx_eint_mask, + .irq_unmask = s3c24xx_eint_unmask, + .irq_set_type = s3c24xx_eint_type, +}; + +static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, + u32 offset, u32 range) +{ + struct irq_chip *chip = irq_get_chip(irq); + struct s3c24xx_eint_data *data = irq_get_handler_data(irq); + struct samsung_pinctrl_drv_data *d = data->drvdata; + unsigned int pend, mask; + + chained_irq_enter(chip, desc); + + pend = readl(d->virt_base + EINTPEND_REG); + mask = readl(d->virt_base + EINTMASK_REG); + + pend &= ~mask; + pend &= range; + + while (pend) { + unsigned int virq; + + irq = __ffs(pend); + pend &= ~(1 << irq); + virq = irq_linear_revmap(data->domains[irq], irq - offset); + /* Something is really wrong if an unmapped EINT is unmasked */ + BUG_ON(!virq); + + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 0, 0xf0); +} + +static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) +{ + s3c24xx_demux_eint(irq, desc, 8, 0xffff00); +} + +static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c2410_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = { + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c2412_demux_eint0_3, + s3c24xx_demux_eint4_7, + s3c24xx_demux_eint8_23, +}; + +static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + if (hw <= 3) { + if (ddata->eint0_3_parent_only) + irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip, + handle_edge_irq); + } else { + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, + handle_edge_irq); + } + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpf_irq_ops = { + .map = s3c24xx_gpf_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c24xx_eint_domain_data *ddata = h->host_data; + struct samsung_pin_bank *bank = ddata->bank; + + if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) + return -EINVAL; + + irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); + irq_set_chip_data(virq, bank); + set_irq_flags(virq, IRQF_VALID); + return 0; +} + +static const struct irq_domain_ops s3c24xx_gpg_irq_ops = { + .map = s3c24xx_gpg_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static const struct of_device_id s3c24xx_eint_irq_ids[] = { + { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 }, + { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 }, + { } +}; + +static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) +{ + struct device *dev = d->dev; + const struct of_device_id *match; + struct device_node *eint_np = NULL; + struct device_node *np; + struct samsung_pin_bank *bank; + struct s3c24xx_eint_data *eint_data; + const struct irq_domain_ops *ops; + unsigned int i; + bool eint0_3_parent_only; + irq_flow_handler_t *handlers; + + for_each_child_of_node(dev->of_node, np) { + match = of_match_node(s3c24xx_eint_irq_ids, np); + if (match) { + eint_np = np; + eint0_3_parent_only = (bool)match->data; + break; + } + } + if (!eint_np) + return -ENODEV; + + eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL); + if (!eint_data) + return -ENOMEM; + + eint_data->drvdata = d; + + handlers = eint0_3_parent_only ? s3c2410_eint_handlers + : s3c2412_eint_handlers; + for (i = 0; i < NUM_EINT_IRQ; ++i) { + unsigned int irq; + + irq = irq_of_parse_and_map(eint_np, i); + if (!irq) { + dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); + return -ENXIO; + } + + eint_data->parents[i] = irq; + irq_set_chained_handler(irq, handlers[i]); + irq_set_handler_data(irq, eint_data); + } + + bank = d->ctrl->pin_banks; + for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { + struct s3c24xx_eint_domain_data *ddata; + unsigned int mask; + unsigned int irq; + unsigned int pin; + + if (bank->eint_type != EINT_TYPE_WKUP) + continue; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->bank = bank; + ddata->eint_data = eint_data; + ddata->eint0_3_parent_only = eint0_3_parent_only; + + ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops + : &s3c24xx_gpg_irq_ops; + + bank->irq_domain = irq_domain_add_linear(bank->of_node, + bank->nr_pins, ops, ddata); + if (!bank->irq_domain) { + dev_err(dev, "wkup irq domain add failed\n"); + return -ENXIO; + } + + irq = bank->eint_offset; + mask = bank->eint_mask; + for (pin = 0; mask; ++pin, mask >>= 1) { + if (irq > NUM_EINT) + break; + if (!(mask & 1)) + continue; + eint_data->domains[irq] = bank->irq_domain; + ++irq; + } + } + + return 0; +} + +static struct samsung_pin_bank s3c2412_pin_banks[] = { + PIN_BANK_A(23, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x080, "gpj"), +}; + +struct samsung_pin_ctrl s3c2412_pin_ctrl[] = { + { + .pin_banks = s3c2412_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2412-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2416_pin_banks[] = { + PIN_BANK_A(27, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(14, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2416_pin_ctrl[] = { + { + .pin_banks = s3c2416_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2416-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2440_pin_banks[] = { + PIN_BANK_A(25, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(11, 0x070, "gph"), + PIN_BANK_2BIT(13, 0x0d0, "gpj"), +}; + +struct samsung_pin_ctrl s3c2440_pin_ctrl[] = { + { + .pin_banks = s3c2440_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2440-GPIO", + }, +}; + +static struct samsung_pin_bank s3c2450_pin_banks[] = { + PIN_BANK_A(28, 0x000, "gpa"), + PIN_BANK_2BIT(11, 0x010, "gpb"), + PIN_BANK_2BIT(16, 0x020, "gpc"), + PIN_BANK_2BIT(16, 0x030, "gpd"), + PIN_BANK_2BIT(16, 0x040, "gpe"), + PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), + PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), + PIN_BANK_2BIT(15, 0x070, "gph"), + PIN_BANK_2BIT(16, 0x0d0, "gpj"), + PIN_BANK_2BIT(16, 0x0e0, "gpk"), + PIN_BANK_2BIT(15, 0x0f0, "gpl"), + PIN_BANK_2BIT(2, 0x100, "gpm"), +}; + +struct samsung_pin_ctrl s3c2450_pin_ctrl[] = { + { + .pin_banks = s3c2450_pin_banks, + .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), + .eint_wkup_init = s3c24xx_eint_init, + .label = "S3C2450-GPIO", + }, +}; diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c index 63ac22e89678..e67ff1b8042c 100644 --- a/drivers/pinctrl/pinctrl-samsung.c +++ b/drivers/pinctrl/pinctrl-samsung.c @@ -1118,6 +1118,16 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { { .compatible = "samsung,s3c64xx-pinctrl", .data = s3c64xx_pin_ctrl }, #endif +#ifdef CONFIG_PINCTRL_S3C24XX + { .compatible = "samsung,s3c2412-pinctrl", + .data = s3c2412_pin_ctrl }, + { .compatible = "samsung,s3c2416-pinctrl", + .data = s3c2416_pin_ctrl }, + { .compatible = "samsung,s3c2440-pinctrl", + .data = s3c2440_pin_ctrl }, + { .compatible = "samsung,s3c2450-pinctrl", + .data = s3c2450_pin_ctrl }, +#endif {}, }; MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h index 26d3519240c9..79fcc2076c00 100644 --- a/drivers/pinctrl/pinctrl-samsung.h +++ b/drivers/pinctrl/pinctrl-samsung.h @@ -255,5 +255,9 @@ extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2440_pin_ctrl[]; +extern struct samsung_pin_ctrl s3c2450_pin_ctrl[]; #endif /* __PINCTRL_SAMSUNG_H */ diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index f8a2ae413c7f..636a882b406e 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -5,8 +5,6 @@ if ARCH_SHMOBILE || SUPERH config PINCTRL_SH_PFC - # XXX move off the gpio dependency - depends on GPIOLIB select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB select PINMUX select PINCONF @@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740 depends on ARCH_R8A7740 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7778 + def_bool y + depends on ARCH_R8A7778 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7779 def_bool y depends on ARCH_R8A7779 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7790 + def_bool y + depends on ARCH_R8A7790 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 @@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0 def_bool y depends on ARCH_SH73A0 select PINCTRL_SH_PFC + select REGULATOR config PINCTRL_PFC_SH7720 def_bool y diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 211cd8e98a8a..5e0c222c12d7 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -5,7 +5,9 @@ endif obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o +obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index b551336924a5..3b2fd43ff294 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev) spin_lock_init(&pfc->lock); + if (info->ops && info->ops->init) { + ret = info->ops->init(pfc); + if (ret < 0) + return ret; + } + pinctrl_provide_dummies(); /* @@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev) */ ret = sh_pfc_register_pinctrl(pfc); if (unlikely(ret != 0)) - return ret; + goto error; #ifdef CONFIG_GPIO_SH_PFC /* @@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev) dev_info(pfc->dev, "%s support registered\n", info->name); return 0; + +error: + if (info->ops && info->ops->exit) + info->ops->exit(pfc); + return ret; } static int sh_pfc_remove(struct platform_device *pdev) @@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev) #endif sh_pfc_unregister_pinctrl(pfc); + if (pfc->info->ops && pfc->info->ops->exit) + pfc->info->ops->exit(pfc); + platform_set_drvdata(pdev, NULL); return 0; @@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_R8A7740 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7778 + { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7779 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7790 + { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH7203 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, #endif diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 89cb4289d761..f02ba1dde3a0 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -11,6 +11,7 @@ #define __SH_PFC_CORE_H__ #include <linux/compiler.h> +#include <linux/spinlock.h> #include <linux/types.h> #include "sh_pfc.h" @@ -27,6 +28,7 @@ struct sh_pfc_pinctrl; struct sh_pfc { struct device *dev; const struct sh_pfc_soc_info *info; + void *soc_data; spinlock_t lock; unsigned int num_windows; @@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; +extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index bbd87d29bfd0..f6ea47c433b3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -18,10 +18,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> +#include <linux/pinctrl/pinconf-generic.h> + #include <mach/r8a7740.h> #include <mach/irqs.h> +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -30,6 +34,29 @@ PORT_10(fn, pfx##20, sfx), \ PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) +#undef _GPIO_PORT +#define _GPIO_PORT(gpio, sfx) \ + [gpio] = { \ + .name = __stringify(PORT##gpio), \ + .enum_id = PORT##gpio##_DATA, \ + } + +#define IRQC_PIN_MUX(irq, pin) \ +static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_mux[] = { \ + IRQ##irq##_MARK, \ +} + +#define IRQC_PINS_MUX(irq, idx, pin) \ +static const unsigned int intc_irq##irq##_##idx##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_##idx##_mux[] = { \ + IRQ##irq##_PORT##pin##_MARK, \ +} + enum { PINMUX_RESERVED = 0, @@ -43,16 +70,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT211_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT211_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT211_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -261,8 +278,6 @@ enum { SCIFB_CTS_PORT173_MARK, /* LCD0 */ - LCDC0_SELECT_MARK, - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, @@ -285,8 +300,6 @@ enum { LCD0_LCLK_PORT102_MARK, /* LCD1 */ - LCDC1_SELECT_MARK, - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, @@ -577,137 +590,11 @@ enum { PINMUX_MARK_END, }; +#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) + static const pinmux_enum_t pinmux_data[] = { - /* specify valid pin states for each pin in GPIO mode */ - - /* I/O and Pull U/D */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), - PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), - PORT_DATA_IO_PD(6), PORT_DATA_IO(7), - PORT_DATA_IO(8), PORT_DATA_IO(9), - - PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), - PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_IO(18), PORT_DATA_IO_PU(19), - - PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), - PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), - PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), - PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), - - PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), - PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), - PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), - PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), - PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), - - PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), - PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), - PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), - PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), - - PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), - PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), - PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), - PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), - PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), - - PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), - PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), - PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), - - PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), - PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO(84), PORT_DATA_IO_PD(85), - PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), - PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), - - PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), - - PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), - PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), - PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), - PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), - PORT_DATA_IO(108), PORT_DATA_IO(109), - - PORT_DATA_IO(110), PORT_DATA_IO(111), - PORT_DATA_IO(112), PORT_DATA_IO(113), - PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), - PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), - PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), - - PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO(125), - PORT_DATA_IO(126), PORT_DATA_IO(127), - PORT_DATA_IO(128), PORT_DATA_IO(129), - - PORT_DATA_IO(130), PORT_DATA_IO(131), - PORT_DATA_IO(132), PORT_DATA_IO(133), - PORT_DATA_IO(134), PORT_DATA_IO(135), - PORT_DATA_IO(136), PORT_DATA_IO(137), - PORT_DATA_IO(138), PORT_DATA_IO(139), - - PORT_DATA_IO(140), PORT_DATA_IO(141), - PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), - PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), - PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), - PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), - - PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), - PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), - PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), - PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), - PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), - PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), - - PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), - PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), - PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), - PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), - - PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), - PORT_DATA_IO_PU(182), PORT_DATA_IO(183), - PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), - PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), - PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), - - PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), - PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), - PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), - PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), - - PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), - PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), - PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), - PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), - - PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + PINMUX_DATA_GP_ALL(), /* Port0 */ PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), @@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), /* Port58 */ - PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), + PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0), PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), PINMUX_DATA(DV_D0_MARK, PORT58_FN6), @@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), - /* LCDC select */ - PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), - PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), - /* SDENC */ PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), @@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), }; +#define R8A7740_PIN(pin, cfgs) \ + { \ + .name = __stringify(PORT##pin), \ + .enum_id = PORT##pin##_DATA, \ + .configs = cfgs, \ + } + +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD) +#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU) +#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD) +#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO) +#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD) +#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU) +#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD) +#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O) +#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD) + static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), + /* Table 56-1 (I/O and Pull U/D) */ + R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), + R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), + R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5), + R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7), + R8A7740_PIN_IO(8), R8A7740_PIN_IO(9), + R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11), + R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13), + R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15), + R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17), + R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19), + R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21), + R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23), + R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25), + R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27), + R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29), + R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31), + R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33), + R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35), + R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37), + R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39), + R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41), + R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43), + R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45), + R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47), + R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49), + R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51), + R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53), + R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55), + R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57), + R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59), + R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61), + R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63), + R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65), + R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67), + R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69), + R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71), + R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73), + R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75), + R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77), + R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79), + R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81), + R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83), + R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85), + R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87), + R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89), + R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91), + R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93), + R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95), + R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97), + R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99), + R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101), + R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103), + R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105), + R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107), + R8A7740_PIN_IO(108), R8A7740_PIN_IO(109), + R8A7740_PIN_IO(110), R8A7740_PIN_IO(111), + R8A7740_PIN_IO(112), R8A7740_PIN_IO(113), + R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115), + R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117), + R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119), + R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121), + R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123), + R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125), + R8A7740_PIN_IO(126), R8A7740_PIN_IO(127), + R8A7740_PIN_IO(128), R8A7740_PIN_IO(129), + R8A7740_PIN_IO(130), R8A7740_PIN_IO(131), + R8A7740_PIN_IO(132), R8A7740_PIN_IO(133), + R8A7740_PIN_IO(134), R8A7740_PIN_IO(135), + R8A7740_PIN_IO(136), R8A7740_PIN_IO(137), + R8A7740_PIN_IO(138), R8A7740_PIN_IO(139), + R8A7740_PIN_IO(140), R8A7740_PIN_IO(141), + R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143), + R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145), + R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147), + R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149), + R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151), + R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153), + R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155), + R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157), + R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159), + R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161), + R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163), + R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165), + R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167), + R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169), + R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171), + R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173), + R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175), + R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177), + R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179), + R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181), + R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183), + R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185), + R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187), + R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189), + R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191), + R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193), + R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195), + R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197), + R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199), + R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201), + R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203), + R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205), + R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207), + R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209), + R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211), +}; + +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data8_pins[] = { + /* D[0:7] */ + 157, 156, 155, 154, 153, 152, 151, 150, +}; +static const unsigned int bsc_data8_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data16_pins[] = { + /* D[0:15] */ + 157, 156, 155, 154, 153, 152, 151, 150, + 149, 148, 147, 146, 145, 144, 143, 142, +}; +static const unsigned int bsc_data16_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_data32_pins[] = { + /* D[0:31] */ + 157, 156, 155, 154, 153, 152, 151, 150, + 149, 148, 147, 146, 145, 144, 143, 142, + 171, 170, 169, 168, 167, 166, 173, 172, + 165, 164, 163, 162, 161, 160, 159, 158, +}; +static const unsigned int bsc_data32_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, + D16_MARK, D17_MARK, D18_MARK, D19_MARK, + D20_MARK, D21_MARK, D22_MARK, D23_MARK, + D24_MARK, D25_MARK, D26_MARK, D27_MARK, + D28_MARK, D29_MARK, D30_MARK, D31_MARK, +}; +static const unsigned int bsc_cs0_pins[] = { + /* CS */ + 109, +}; +static const unsigned int bsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int bsc_cs2_pins[] = { + /* CS */ + 110, +}; +static const unsigned int bsc_cs2_mux[] = { + CS2_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 111, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4_MARK, +}; +static const unsigned int bsc_cs5a_0_pins[] = { + /* CS */ + 105, +}; +static const unsigned int bsc_cs5a_0_mux[] = { + CS5A_PORT105_MARK, +}; +static const unsigned int bsc_cs5a_1_pins[] = { + /* CS */ + 19, +}; +static const unsigned int bsc_cs5a_1_mux[] = { + CS5A_PORT19_MARK, +}; +static const unsigned int bsc_cs5b_pins[] = { + /* CS */ + 103, +}; +static const unsigned int bsc_cs5b_mux[] = { + CS5B_MARK, +}; +static const unsigned int bsc_cs6a_pins[] = { + /* CS */ + 104, +}; +static const unsigned int bsc_cs6a_mux[] = { + CS6A_MARK, +}; +static const unsigned int bsc_rd_we8_pins[] = { + /* RD, WE[0] */ + 115, 113, +}; +static const unsigned int bsc_rd_we8_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, +}; +static const unsigned int bsc_rd_we16_pins[] = { + /* RD, WE[0:1] */ + 115, 113, 112, +}; +static const unsigned int bsc_rd_we16_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, +}; +static const unsigned int bsc_rd_we32_pins[] = { + /* RD, WE[0:3] */ + 115, 113, 112, 108, 107, +}; +static const unsigned int bsc_rd_we32_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK, +}; +static const unsigned int bsc_bs_pins[] = { + /* BS */ + 175, +}; +static const unsigned int bsc_bs_mux[] = { + BS_MARK, +}; +static const unsigned int bsc_rdwr_pins[] = { + /* RDWR */ + 114, +}; +static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, +}; +/* - CEU0 ------------------------------------------------------------------- */ +static const unsigned int ceu0_data_0_7_pins[] = { + /* D[0:7] */ + 34, 33, 32, 31, 30, 29, 28, 27, +}; +static const unsigned int ceu0_data_0_7_mux[] = { + VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, + VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, +}; +static const unsigned int ceu0_data_8_15_0_pins[] = { + /* D[8:15] */ + 182, 181, 180, 179, 178, 26, 25, 24, +}; +static const unsigned int ceu0_data_8_15_0_mux[] = { + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK, + VIO0_D15_PORT24_MARK, +}; +static const unsigned int ceu0_data_8_15_1_pins[] = { + /* D[8:15] */ + 182, 181, 180, 179, 178, 22, 95, 96, +}; +static const unsigned int ceu0_data_8_15_1_mux[] = { + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK, + VIO0_D15_PORT96_MARK, +}; +static const unsigned int ceu0_clk_0_pins[] = { + /* CKO */ + 36, +}; +static const unsigned int ceu0_clk_0_mux[] = { + VIO_CKO_MARK, +}; +static const unsigned int ceu0_clk_1_pins[] = { + /* CKO */ + 14, +}; +static const unsigned int ceu0_clk_1_mux[] = { + VIO_CKO1_MARK, +}; +static const unsigned int ceu0_clk_2_pins[] = { + /* CKO */ + 15, +}; +static const unsigned int ceu0_clk_2_mux[] = { + VIO_CKO2_MARK, +}; +static const unsigned int ceu0_sync_pins[] = { + /* CLK, VD, HD */ + 35, 39, 37, +}; +static const unsigned int ceu0_sync_mux[] = { + VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK, +}; +static const unsigned int ceu0_field_pins[] = { + /* FIELD */ + 38, +}; +static const unsigned int ceu0_field_mux[] = { + VIO0_FIELD_MARK, +}; +/* - CEU1 ------------------------------------------------------------------- */ +static const unsigned int ceu1_data_pins[] = { + /* D[0:7] */ + 182, 181, 180, 179, 178, 26, 25, 24, +}; +static const unsigned int ceu1_data_mux[] = { + VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, + VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, +}; +static const unsigned int ceu1_clk_pins[] = { + /* CKO */ + 23, +}; +static const unsigned int ceu1_clk_mux[] = { + VIO_CKO_1_MARK, +}; +static const unsigned int ceu1_sync_pins[] = { + /* CLK, VD, HD */ + 197, 198, 160, +}; +static const unsigned int ceu1_sync_mux[] = { + VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK, +}; +static const unsigned int ceu1_field_pins[] = { + /* FIELD */ + 21, +}; +static const unsigned int ceu1_field_mux[] = { + VIO1_FIELD_MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 11, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 10, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 12, 13, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 7, 8, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_0_pins[] = { + /* ISLD */ + 0, }; +static const unsigned int fsia_data_in_0_mux[] = { + FSIAISLD_PORT0_MARK, +}; +static const unsigned int fsia_data_in_1_pins[] = { + /* ISLD */ + 5, +}; +static const unsigned int fsia_data_in_1_mux[] = { + FSIAISLD_PORT5_MARK, +}; +static const unsigned int fsia_data_out_0_pins[] = { + /* OSLD */ + 9, +}; +static const unsigned int fsia_data_out_0_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_data_out_1_pins[] = { + /* OSLD */ + 0, +}; +static const unsigned int fsia_data_out_1_mux[] = { + FSIAOSLD1_MARK, +}; +static const unsigned int fsia_data_out_2_pins[] = { + /* OSLD */ + 1, +}; +static const unsigned int fsia_data_out_2_mux[] = { + FSIAOSLD2_MARK, +}; +static const unsigned int fsia_spdif_0_pins[] = { + /* SPDIF */ + 9, +}; +static const unsigned int fsia_spdif_0_mux[] = { + FSIASPDIF_PORT9_MARK, +}; +static const unsigned int fsia_spdif_1_pins[] = { + /* SPDIF */ + 18, +}; +static const unsigned int fsia_spdif_1_mux[] = { + FSIASPDIF_PORT18_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 11, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +/* - GETHER ----------------------------------------------------------------- */ +static const unsigned int gether_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */ + 195, 196, 194, 193, 200, 201, 199, 159, 202, 208, +}; +static const unsigned int gether_rmii_mux[] = { + RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK, + RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK, + RMII_MDC_MARK, RMII_MDIO_MARK, +}; +static const unsigned int gether_mii_pins[] = { + /* RXD[0:3], RX_CLK, RX_DV, RX_ER + * TXD[0:3], TX_CLK, TX_EN, TX_ER + * CRS, COL, MDC, MDIO, + */ + 185, 186, 187, 188, 174, 161, 204, + 171, 170, 169, 168, 184, 183, 203, + 205, 163, 206, 207, +}; +static const unsigned int gether_mii_mux[] = { + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, + ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, + ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, +}; +static const unsigned int gether_gmii_pins[] = { + /* RXD[0:7], RX_CLK, RX_DV, RX_ER + * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER + * CRS, COL, MDC, MDIO, REF125CK_MARK, + */ + 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204, + 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203, + 205, 163, 206, 207, +}; +static const unsigned int gether_gmii_mux[] = { + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK, + ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK, + ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK, + ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK, + ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK, + RMII_REF125CK_MARK, +}; +static const unsigned int gether_int_pins[] = { + /* PHY_INT */ + 164, +}; +static const unsigned int gether_int_mux[] = { + ET_PHY_INT_MARK, +}; +static const unsigned int gether_link_pins[] = { + /* LINK */ + 177, +}; +static const unsigned int gether_link_mux[] = { + ET_LINK_MARK, +}; +static const unsigned int gether_wol_pins[] = { + /* WOL */ + 175, +}; +static const unsigned int gether_wol_mux[] = { + ET_WOL_MARK, +}; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi_pins[] = { + /* HPD, CEC */ + 210, 211, +}; +static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +IRQC_PINS_MUX(0, 0, 2); +IRQC_PINS_MUX(0, 1, 13); +IRQC_PIN_MUX(1, 20); +IRQC_PINS_MUX(2, 0, 11); +IRQC_PINS_MUX(2, 1, 12); +IRQC_PINS_MUX(3, 0, 10); +IRQC_PINS_MUX(3, 1, 14); +IRQC_PINS_MUX(4, 0, 15); +IRQC_PINS_MUX(4, 1, 172); +IRQC_PINS_MUX(5, 0, 0); +IRQC_PINS_MUX(5, 1, 1); +IRQC_PINS_MUX(6, 0, 121); +IRQC_PINS_MUX(6, 1, 173); +IRQC_PINS_MUX(7, 0, 120); +IRQC_PINS_MUX(7, 1, 209); +IRQC_PIN_MUX(8, 119); +IRQC_PINS_MUX(9, 0, 118); +IRQC_PINS_MUX(9, 1, 210); +IRQC_PIN_MUX(10, 19); +IRQC_PIN_MUX(11, 104); +IRQC_PINS_MUX(12, 0, 42); +IRQC_PINS_MUX(12, 1, 97); +IRQC_PINS_MUX(13, 0, 64); +IRQC_PINS_MUX(13, 1, 98); +IRQC_PINS_MUX(14, 0, 63); +IRQC_PINS_MUX(14, 1, 99); +IRQC_PINS_MUX(15, 0, 62); +IRQC_PINS_MUX(15, 1, 100); +IRQC_PINS_MUX(16, 0, 68); +IRQC_PINS_MUX(16, 1, 211); +IRQC_PIN_MUX(17, 69); +IRQC_PIN_MUX(18, 70); +IRQC_PIN_MUX(19, 71); +IRQC_PIN_MUX(20, 67); +IRQC_PIN_MUX(21, 202); +IRQC_PIN_MUX(22, 95); +IRQC_PIN_MUX(23, 96); +IRQC_PIN_MUX(24, 180); +IRQC_PIN_MUX(25, 38); +IRQC_PINS_MUX(26, 0, 58); +IRQC_PINS_MUX(26, 1, 81); +IRQC_PINS_MUX(27, 0, 57); +IRQC_PINS_MUX(27, 1, 168); +IRQC_PINS_MUX(28, 0, 56); +IRQC_PINS_MUX(28, 1, 169); +IRQC_PINS_MUX(29, 0, 50); +IRQC_PINS_MUX(29, 1, 170); +IRQC_PINS_MUX(30, 0, 49); +IRQC_PINS_MUX(30, 1, 171); +IRQC_PINS_MUX(31, 0, 41); +IRQC_PINS_MUX(31, 1, 167); /* - LCD0 ------------------------------------------------------------------- */ static const unsigned int lcd0_data8_pins[] = { @@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = { static const unsigned int mmc0_ctrl_1_mux[] = { MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, }; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 197, 198, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 188, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 194, 193, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 195, 196, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 185, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 23, 21, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + 200, 201, +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_0_pins[] = { + /* SCK */ + 22, +}; +static const unsigned int scifa2_clk_0_mux[] = { + SCIFA2_SCK_PORT22_MARK, +}; +static const unsigned int scifa2_clk_1_pins[] = { + /* SCK */ + 199, +}; +static const unsigned int scifa2_clk_1_mux[] = { + SCIFA2_SCK_PORT199_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + 96, 95, +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS_MARK, SCIFA2_CTS_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_0_pins[] = { + /* RXD, TXD */ + 174, 175, +}; +static const unsigned int scifa3_data_0_mux[] = { + SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK, +}; +static const unsigned int scifa3_clk_0_pins[] = { + /* SCK */ + 116, +}; +static const unsigned int scifa3_clk_0_mux[] = { + SCIFA3_SCK_PORT116_MARK, +}; +static const unsigned int scifa3_ctrl_0_pins[] = { + /* RTS, CTS */ + 105, 117, +}; +static const unsigned int scifa3_ctrl_0_mux[] = { + SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK, +}; +static const unsigned int scifa3_data_1_pins[] = { + /* RXD, TXD */ + 159, 160, +}; +static const unsigned int scifa3_data_1_mux[] = { + SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK, +}; +static const unsigned int scifa3_clk_1_pins[] = { + /* SCK */ + 158, +}; +static const unsigned int scifa3_clk_1_mux[] = { + SCIFA3_SCK_PORT158_MARK, +}; +static const unsigned int scifa3_ctrl_1_pins[] = { + /* RTS, CTS */ + 161, 162, +}; +static const unsigned int scifa3_ctrl_1_mux[] = { + SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_0_pins[] = { + /* RXD, TXD */ + 12, 13, +}; +static const unsigned int scifa4_data_0_mux[] = { + SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK, +}; +static const unsigned int scifa4_data_1_pins[] = { + /* RXD, TXD */ + 204, 203, +}; +static const unsigned int scifa4_data_1_mux[] = { + SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK, +}; +static const unsigned int scifa4_data_2_pins[] = { + /* RXD, TXD */ + 94, 93, +}; +static const unsigned int scifa4_data_2_mux[] = { + SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK, +}; +static const unsigned int scifa4_clk_0_pins[] = { + /* SCK */ + 21, +}; +static const unsigned int scifa4_clk_0_mux[] = { + SCIFA4_SCK_PORT21_MARK, +}; +static const unsigned int scifa4_clk_1_pins[] = { + /* SCK */ + 205, +}; +static const unsigned int scifa4_clk_1_mux[] = { + SCIFA4_SCK_PORT205_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_0_pins[] = { + /* RXD, TXD */ + 10, 20, +}; +static const unsigned int scifa5_data_0_mux[] = { + SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK, +}; +static const unsigned int scifa5_data_1_pins[] = { + /* RXD, TXD */ + 207, 208, +}; +static const unsigned int scifa5_data_1_mux[] = { + SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK, +}; +static const unsigned int scifa5_data_2_pins[] = { + /* RXD, TXD */ + 92, 91, +}; +static const unsigned int scifa5_data_2_mux[] = { + SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK, +}; +static const unsigned int scifa5_clk_0_pins[] = { + /* SCK */ + 23, +}; +static const unsigned int scifa5_clk_0_mux[] = { + SCIFA5_SCK_PORT23_MARK, +}; +static const unsigned int scifa5_clk_1_pins[] = { + /* SCK */ + 206, +}; +static const unsigned int scifa5_clk_1_mux[] = { + SCIFA5_SCK_PORT206_MARK, +}; +/* - SCIFA6 ----------------------------------------------------------------- */ +static const unsigned int scifa6_data_pins[] = { + /* RXD, TXD */ + 25, 26, +}; +static const unsigned int scifa6_data_mux[] = { + SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, +}; +static const unsigned int scifa6_clk_pins[] = { + /* SCK */ + 24, +}; +static const unsigned int scifa6_clk_mux[] = { + SCIFA6_SCK_MARK, +}; +/* - SCIFA7 ----------------------------------------------------------------- */ +static const unsigned int scifa7_data_pins[] = { + /* RXD, TXD */ + 0, 1, +}; +static const unsigned int scifa7_data_mux[] = { + SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_0_pins[] = { + /* RXD, TXD */ + 191, 192, +}; +static const unsigned int scifb_data_0_mux[] = { + SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK, +}; +static const unsigned int scifb_clk_0_pins[] = { + /* SCK */ + 190, +}; +static const unsigned int scifb_clk_0_mux[] = { + SCIFB_SCK_PORT190_MARK, +}; +static const unsigned int scifb_ctrl_0_pins[] = { + /* RTS, CTS */ + 186, 187, +}; +static const unsigned int scifb_ctrl_0_mux[] = { + SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK, +}; +static const unsigned int scifb_data_1_pins[] = { + /* RXD, TXD */ + 3, 4, +}; +static const unsigned int scifb_data_1_mux[] = { + SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK, +}; +static const unsigned int scifb_clk_1_pins[] = { + /* SCK */ + 2, +}; +static const unsigned int scifb_clk_1_mux[] = { + SCIFB_SCK_PORT2_MARK, +}; +static const unsigned int scifb_ctrl_1_pins[] = { + /* RTS, CTS */ + 172, 173, +}; +static const unsigned int scifb_ctrl_1_mux[] = { + SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = { static const unsigned int sdhi2_wp_1_mux[] = { SDHI2_WP_PORT25_MARK, }; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + 23, +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + 21, +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_0_pins[] = { + /* TO */ + 66, +}; +static const unsigned int tpu0_to2_0_mux[] = { + TPU0TO2_PORT66_MARK, +}; +static const unsigned int tpu0_to2_1_pins[] = { + /* TO */ + 202, +}; +static const unsigned int tpu0_to2_1_mux[] = { + TPU0TO2_PORT202_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + 180, +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), + SH_PFC_PIN_GROUP(bsc_data16), + SH_PFC_PIN_GROUP(bsc_data32), + SH_PFC_PIN_GROUP(bsc_cs0), + SH_PFC_PIN_GROUP(bsc_cs2), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5a_0), + SH_PFC_PIN_GROUP(bsc_cs5a_1), + SH_PFC_PIN_GROUP(bsc_cs5b), + SH_PFC_PIN_GROUP(bsc_cs6a), + SH_PFC_PIN_GROUP(bsc_rd_we8), + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(ceu0_data_0_7), + SH_PFC_PIN_GROUP(ceu0_data_8_15_0), + SH_PFC_PIN_GROUP(ceu0_data_8_15_1), + SH_PFC_PIN_GROUP(ceu0_clk_0), + SH_PFC_PIN_GROUP(ceu0_clk_1), + SH_PFC_PIN_GROUP(ceu0_clk_2), + SH_PFC_PIN_GROUP(ceu0_sync), + SH_PFC_PIN_GROUP(ceu0_field), + SH_PFC_PIN_GROUP(ceu1_data), + SH_PFC_PIN_GROUP(ceu1_clk), + SH_PFC_PIN_GROUP(ceu1_sync), + SH_PFC_PIN_GROUP(ceu1_field), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in_0), + SH_PFC_PIN_GROUP(fsia_data_in_1), + SH_PFC_PIN_GROUP(fsia_data_out_0), + SH_PFC_PIN_GROUP(fsia_data_out_1), + SH_PFC_PIN_GROUP(fsia_data_out_2), + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(gether_rmii), + SH_PFC_PIN_GROUP(gether_mii), + SH_PFC_PIN_GROUP(gether_gmii), + SH_PFC_PIN_GROUP(gether_int), + SH_PFC_PIN_GROUP(gether_link), + SH_PFC_PIN_GROUP(gether_wol), + SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2_0), + SH_PFC_PIN_GROUP(intc_irq2_1), + SH_PFC_PIN_GROUP(intc_irq3_0), + SH_PFC_PIN_GROUP(intc_irq3_1), + SH_PFC_PIN_GROUP(intc_irq4_0), + SH_PFC_PIN_GROUP(intc_irq4_1), + SH_PFC_PIN_GROUP(intc_irq5_0), + SH_PFC_PIN_GROUP(intc_irq5_1), + SH_PFC_PIN_GROUP(intc_irq6_0), + SH_PFC_PIN_GROUP(intc_irq6_1), + SH_PFC_PIN_GROUP(intc_irq7_0), + SH_PFC_PIN_GROUP(intc_irq7_1), + SH_PFC_PIN_GROUP(intc_irq8), + SH_PFC_PIN_GROUP(intc_irq9_0), + SH_PFC_PIN_GROUP(intc_irq9_1), + SH_PFC_PIN_GROUP(intc_irq10), + SH_PFC_PIN_GROUP(intc_irq11), + SH_PFC_PIN_GROUP(intc_irq12_0), + SH_PFC_PIN_GROUP(intc_irq12_1), + SH_PFC_PIN_GROUP(intc_irq13_0), + SH_PFC_PIN_GROUP(intc_irq13_1), + SH_PFC_PIN_GROUP(intc_irq14_0), + SH_PFC_PIN_GROUP(intc_irq14_1), + SH_PFC_PIN_GROUP(intc_irq15_0), + SH_PFC_PIN_GROUP(intc_irq15_1), + SH_PFC_PIN_GROUP(intc_irq16_0), + SH_PFC_PIN_GROUP(intc_irq16_1), + SH_PFC_PIN_GROUP(intc_irq17), + SH_PFC_PIN_GROUP(intc_irq18), + SH_PFC_PIN_GROUP(intc_irq19), + SH_PFC_PIN_GROUP(intc_irq20), + SH_PFC_PIN_GROUP(intc_irq21), + SH_PFC_PIN_GROUP(intc_irq22), + SH_PFC_PIN_GROUP(intc_irq23), + SH_PFC_PIN_GROUP(intc_irq24), + SH_PFC_PIN_GROUP(intc_irq25), + SH_PFC_PIN_GROUP(intc_irq26_0), + SH_PFC_PIN_GROUP(intc_irq26_1), + SH_PFC_PIN_GROUP(intc_irq27_0), + SH_PFC_PIN_GROUP(intc_irq27_1), + SH_PFC_PIN_GROUP(intc_irq28_0), + SH_PFC_PIN_GROUP(intc_irq28_1), + SH_PFC_PIN_GROUP(intc_irq29_0), + SH_PFC_PIN_GROUP(intc_irq29_1), + SH_PFC_PIN_GROUP(intc_irq30_0), + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), SH_PFC_PIN_GROUP(lcd0_data8), SH_PFC_PIN_GROUP(lcd0_data9), SH_PFC_PIN_GROUP(lcd0_data12), @@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc0_data4_1), SH_PFC_PIN_GROUP(mmc0_data8_1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk_0), + SH_PFC_PIN_GROUP(scifa2_clk_1), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa3_data_0), + SH_PFC_PIN_GROUP(scifa3_clk_0), + SH_PFC_PIN_GROUP(scifa3_ctrl_0), + SH_PFC_PIN_GROUP(scifa3_data_1), + SH_PFC_PIN_GROUP(scifa3_clk_1), + SH_PFC_PIN_GROUP(scifa3_ctrl_1), + SH_PFC_PIN_GROUP(scifa4_data_0), + SH_PFC_PIN_GROUP(scifa4_data_1), + SH_PFC_PIN_GROUP(scifa4_data_2), + SH_PFC_PIN_GROUP(scifa4_clk_0), + SH_PFC_PIN_GROUP(scifa4_clk_1), + SH_PFC_PIN_GROUP(scifa5_data_0), + SH_PFC_PIN_GROUP(scifa5_data_1), + SH_PFC_PIN_GROUP(scifa5_data_2), + SH_PFC_PIN_GROUP(scifa5_clk_0), + SH_PFC_PIN_GROUP(scifa5_clk_1), + SH_PFC_PIN_GROUP(scifa6_data), + SH_PFC_PIN_GROUP(scifa6_clk), + SH_PFC_PIN_GROUP(scifa7_data), + SH_PFC_PIN_GROUP(scifb_data_0), + SH_PFC_PIN_GROUP(scifb_clk_0), + SH_PFC_PIN_GROUP(scifb_ctrl_0), + SH_PFC_PIN_GROUP(scifb_data_1), + SH_PFC_PIN_GROUP(scifb_clk_1), + SH_PFC_PIN_GROUP(scifb_ctrl_1), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp_0), SH_PFC_PIN_GROUP(sdhi2_cd_1), SH_PFC_PIN_GROUP(sdhi2_wp_1), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2_0), + SH_PFC_PIN_GROUP(tpu0_to2_1), + SH_PFC_PIN_GROUP(tpu0_to3), +}; + +static const char * const bsc_groups[] = { + "bsc_data8", + "bsc_data16", + "bsc_data32", + "bsc_cs0", + "bsc_cs2", + "bsc_cs4", + "bsc_cs5a_0", + "bsc_cs5a_1", + "bsc_cs5b", + "bsc_cs6a", + "bsc_rd_we8", + "bsc_rd_we16", + "bsc_rd_we32", + "bsc_bs", + "bsc_rdwr", +}; + +static const char * const ceu0_groups[] = { + "ceu0_data_0_7", + "ceu0_data_8_15_0", + "ceu0_data_8_15_1", + "ceu0_clk_0", + "ceu0_clk_1", + "ceu0_clk_2", + "ceu0_sync", + "ceu0_field", +}; + +static const char * const ceu1_groups[] = { + "ceu1_data", + "ceu1_clk", + "ceu1_sync", + "ceu1_field", +}; + +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in_0", + "fsia_data_in_1", + "fsia_data_out_0", + "fsia_data_out_1", + "fsia_data_out_2", + "fsia_spdif_0", + "fsia_spdif_1", +}; + +static const char * const fsib_groups[] = { + "fsib_mclk_in", +}; + +static const char * const gether_groups[] = { + "gether_rmii", + "gether_mii", + "gether_gmii", + "gether_int", + "gether_link", + "gether_wol", +}; + +static const char * const hdmi_groups[] = { + "hdmi", +}; + +static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", + "intc_irq1", + "intc_irq2_0", + "intc_irq2_1", + "intc_irq3_0", + "intc_irq3_1", + "intc_irq4_0", + "intc_irq4_1", + "intc_irq5_0", + "intc_irq5_1", + "intc_irq6_0", + "intc_irq6_1", + "intc_irq7_0", + "intc_irq7_1", + "intc_irq8", + "intc_irq9_0", + "intc_irq9_1", + "intc_irq10", + "intc_irq11", + "intc_irq12_0", + "intc_irq12_1", + "intc_irq13_0", + "intc_irq13_1", + "intc_irq14_0", + "intc_irq14_1", + "intc_irq15_0", + "intc_irq15_1", + "intc_irq16_0", + "intc_irq16_1", + "intc_irq17", + "intc_irq18", + "intc_irq19", + "intc_irq20", + "intc_irq21", + "intc_irq22", + "intc_irq23", + "intc_irq24", + "intc_irq25", + "intc_irq26_0", + "intc_irq26_1", + "intc_irq27_0", + "intc_irq27_1", + "intc_irq28_0", + "intc_irq28_1", + "intc_irq29_0", + "intc_irq29_1", + "intc_irq30_0", + "intc_irq30_1", + "intc_irq31_0", + "intc_irq31_1", }; static const char * const lcd0_groups[] = { @@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = { "mmc0_ctrl_1", }; +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk_0", + "scifa2_clk_1", + "scifa2_ctrl", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data_0", + "scifa3_clk_0", + "scifa3_ctrl_0", + "scifa3_data_1", + "scifa3_clk_1", + "scifa3_ctrl_1", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data_0", + "scifa4_data_1", + "scifa4_data_2", + "scifa4_clk_0", + "scifa4_clk_1", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data_0", + "scifa5_data_1", + "scifa5_data_2", + "scifa5_clk_0", + "scifa5_clk_1", +}; + +static const char * const scifa6_groups[] = { + "scifa6_data", + "scifa6_clk", +}; + +static const char * const scifa7_groups[] = { + "scifa7_data", +}; + +static const char * const scifb_groups[] = { + "scifb_data_0", + "scifb_clk_0", + "scifb_ctrl_0", + "scifb_data_1", + "scifb_clk_1", + "scifb_ctrl_1", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp_1", }; +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2_0", + "tpu0_to2_1", + "tpu0_to3", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu0), + SH_PFC_FUNCTION(ceu1), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lcd0), SH_PFC_FUNCTION(lcd1), SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifa6), + SH_PFC_FUNCTION(scifa7), + SH_PFC_FUNCTION(scifb), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(tpu0), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) - -static const struct pinmux_func pinmux_func_gpios[] = { - /* IRQ */ - GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), - GPIO_FN(IRQ1), - GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), - GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), - GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), - GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), - GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), - GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), - GPIO_FN(IRQ8), - GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), - GPIO_FN(IRQ10), - GPIO_FN(IRQ11), - GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), - GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), - GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), - GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), - GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), - GPIO_FN(IRQ17), - GPIO_FN(IRQ18), - GPIO_FN(IRQ19), - GPIO_FN(IRQ20), - GPIO_FN(IRQ21), - GPIO_FN(IRQ22), - GPIO_FN(IRQ23), - GPIO_FN(IRQ24), - GPIO_FN(IRQ25), - GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), - GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), - GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), - GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), - GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), - GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), - - /* Function */ - - /* DBGT */ - GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), - GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), - GPIO_FN(DBGMD21), - - /* FSI-A */ - GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ - GPIO_FN(FSIAISLD_PORT5), - GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ - GPIO_FN(FSIASPDIF_PORT18), - GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), - GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), - - /* FSI-B */ - GPIO_FN(FSIBCK), - - /* FMSI */ - GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ - GPIO_FN(FMSISLD_PORT6), - GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), - GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), - GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), - GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), - GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ - GPIO_FN(SCIFA2_SCK_PORT199), - GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), - GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ - GPIO_FN(SCIFA3_SCK_PORT116), - GPIO_FN(SCIFA3_CTS_PORT117), - GPIO_FN(SCIFA3_RXD_PORT174), - GPIO_FN(SCIFA3_TXD_PORT175), - - GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ - GPIO_FN(SCIFA3_SCK_PORT158), - GPIO_FN(SCIFA3_CTS_PORT162), - GPIO_FN(SCIFA3_RXD_PORT159), - GPIO_FN(SCIFA3_TXD_PORT160), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ - GPIO_FN(SCIFA4_TXD_PORT13), - - GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ - GPIO_FN(SCIFA4_TXD_PORT203), - - GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ - GPIO_FN(SCIFA4_TXD_PORT93), - - GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ - GPIO_FN(SCIFA4_SCK_PORT205), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ - GPIO_FN(SCIFA5_RXD_PORT10), - - GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ - GPIO_FN(SCIFA5_TXD_PORT208), - - GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ - GPIO_FN(SCIFA5_RXD_PORT92), - - GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ - GPIO_FN(SCIFA5_SCK_PORT206), - - /* SCIFA6 */ - GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), - - /* SCIFA7 */ - GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), - - /* SCIFAB */ - GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ - GPIO_FN(SCIFB_RXD_PORT191), - GPIO_FN(SCIFB_TXD_PORT192), - GPIO_FN(SCIFB_RTS_PORT186), - GPIO_FN(SCIFB_CTS_PORT187), - - GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ - GPIO_FN(SCIFB_RXD_PORT3), - GPIO_FN(SCIFB_TXD_PORT4), - GPIO_FN(SCIFB_RTS_PORT172), - GPIO_FN(SCIFB_CTS_PORT173), - - /* RSPI */ - GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), - GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), - GPIO_FN(RSPI_MISO_A), - - /* VIO CKO */ - GPIO_FN(VIO_CKO1), - GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_CKO_1), - GPIO_FN(VIO_CKO), - - /* VIO0 */ - GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), - GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), - GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), - GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), - GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), - GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), - - GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ - GPIO_FN(VIO0_D14_PORT25), - GPIO_FN(VIO0_D15_PORT24), - - GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ - GPIO_FN(VIO0_D14_PORT95), - GPIO_FN(VIO0_D15_PORT96), - - /* VIO1 */ - GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), - GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), - GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), - GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), - - /* TPU0 */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), - GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ - GPIO_FN(TPU0TO2_PORT202), - - /* SSP1 0 */ - GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), - GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), - GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), - GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), - - /* SSP1 1 */ - GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), - GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), - GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), - - GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ - GPIO_FN(STP1_IPEN_PORT187), - - GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ - GPIO_FN(STP1_IPEN_PORT193), - - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), - GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ - GPIO_FN(SIM_D_PORT199), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), - GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(MSIOF2_RSCK), - - /* KEYSC */ - GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), - GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), - GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), - - GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ - GPIO_FN(KEYIN1_PORT44), - GPIO_FN(KEYIN2_PORT45), - GPIO_FN(KEYIN3_PORT46), - - GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ - GPIO_FN(KEYIN1_PORT57), - GPIO_FN(KEYIN2_PORT56), - GPIO_FN(KEYIN3_PORT55), - - /* VOU */ - GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), - GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), - GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), - GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), - GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), - GPIO_FN(DV_D15), GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), - - /* MEMC */ - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), - GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), - GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), - GPIO_FN(MEMC_A0), - - /* MSIOF0 */ - GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), - GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), - GPIO_FN(MSIOF0_TSYNC), - - /* MSIOF1 */ - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), - - GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), - GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), - GPIO_FN(MSIOF1_TSYNC_PORT120), - GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ - - GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), - GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), - GPIO_FN(MSIOF1_RXD_PORT75), - GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN(GPO0), GPIO_FN(GPI0), - GPIO_FN(GPO1), GPIO_FN(GPI1), - - /* USB0 */ - GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), - - /* USB1 */ - GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), - - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), - GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), - - /* BBIF2 */ - GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ - GPIO_FN(BBIF2_RXD2_PORT60), - GPIO_FN(BBIF2_TSYNC2_PORT6), - GPIO_FN(BBIF2_TSCK2_PORT59), - - GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ - GPIO_FN(BBIF2_TXD2_PORT183), - GPIO_FN(BBIF2_TSCK2_PORT89), - GPIO_FN(BBIF2_TSYNC2_PORT184), - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5B), GPIO_FN(CS6A), - GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ - GPIO_FN(CS5A_PORT19), - GPIO_FN(IOIS16), /* ? */ - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), - GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ - GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), - GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), - GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), - GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ - GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ - GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ - GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ - GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ - GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), - GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), - GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), - GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), - - GPIO_FN(WE0_FWE), /* share with FLCTL */ - GPIO_FN(WE1), - GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ - GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ - GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), - GPIO_FN(RD_FSC), /* share with FLCTL */ - GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ - GPIO_FN(WAIT_PORT90), - - GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ - - /* IRDA */ - GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), - - /* ATAPI */ - GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), - GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), - GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), - GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), - GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), - GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), - GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), - GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), - GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), - GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), - - /* RMII */ - GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), - GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), - GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), - GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ - - /* GEther */ - GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), - GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), - GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ - GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ - GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), - GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), - GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), - GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ - GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ - GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), - GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), - GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), - - /* DMA0 */ - GPIO_FN(DREQ0), GPIO_FN(DACK0), - - /* DMA1 */ - GPIO_FN(DREQ1), GPIO_FN(DACK1), - - /* SYSC */ - GPIO_FN(RESETOUTS), - - /* IRREM */ - GPIO_FN(IROUT), - - /* LCDC */ - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), - - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), - - /* HDMI */ - GPIO_FN(HDMI_HPD), - GPIO_FN(HDMI_CEC), - - /* SYSC */ - GPIO_FN(RESETP_PULLUP), - GPIO_FN(RESETP_PLAIN), - - /* DEBUG */ - GPIO_FN(EDEBGREQ_PULLDOWN), - GPIO_FN(EDEBGREQ_PULLUP), - - GPIO_FN(TRACEAUD_FROM_VIO), - GPIO_FN(TRACEAUD_FROM_LCDC0), - GPIO_FN(TRACEAUD_FROM_MEMC), -}; +#undef PORTCR +#define PORTCR(nr, reg) \ + { \ + PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ @@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { }; static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ - PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ - PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ - PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ - PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ - PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ - PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ - PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ - PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ - PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ - PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ - PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ - PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ - PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ - PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ - PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ - PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ - PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ - PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ - PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ - PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ - PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ - PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ - PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ - PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ - PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ - PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ - PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ - PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ - PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ - PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ - PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ + PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */ + PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */ + PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */ + PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */ + PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */ + PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */ + PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */ + PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */ + PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */ + PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */ + PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */ + PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */ + PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */ + PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */ + PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */ + PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */ + PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */ + PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */ + PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */ + PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */ + PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */ + PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */ + PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */ + PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */ + PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */ + PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */ + PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */ + PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */ + PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */ + PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */ + PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */ + PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ +}; + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +struct r8a7740_portcr_group { + unsigned int end_pin; + unsigned int offset; +}; + +static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { + { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, +}; + +static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) { + const struct r8a7740_portcr_group *group = + &r8a7740_portcr_offsets[i]; + + if (i <= group->end_pin) + return pfc->window->virt + group->offset + pin; + } + + return NULL; +} + +static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { + .get_bias = r8a7740_pinmux_get_bias, + .set_bias = r8a7740_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", + .ops = &r8a7740_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, - PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, - PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, @@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c new file mode 100644 index 000000000000..1dcbabcd7b3c --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -0,0 +1,2783 @@ +/* + * r8a7778 processor support - PFC hardware block + * + * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Copyright (C) 2013 Cogent Embedded, Inc. + * + * based on + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_data/gpio-rcar.h> +#include <linux/kernel.h> +#include "sh_pfc.h" + +#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) + +#define PORT_GP_32(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ + PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) + +#define PORT_GP_27(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_27(4, fn, sfx) + +#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx + +#define _GP_GPIO(bank, pin, _name, sfx) \ + [RCAR_GP_PIN(bank, pin)] = { \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } + +#define _GP_DATA(bank, pin, name, sfx) \ + PINMUX_DATA(name##_DATA, name##_FN) + +#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + +#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn) +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) +#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) +#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */ + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */ + + /* GPSR0 */ + FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2, + FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1, + FN_A2, FN_A3, FN_IP0_15, FN_IP0_16, + FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, + FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24, + FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28, + FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1, + FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11, + + /* GPSR1 */ + FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, + FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17, + FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2, + FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13, + FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24, + FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30, + FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4, + + /* GPSR2 */ + FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11, + FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21, + FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0, + FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7, + FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13, + FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB, + FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29, + FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10, + FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16, + FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22, + FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30, + FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6, + FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29, + FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9, + + /* GPSR4 */ + FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19, + FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0, + FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, + FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24, + FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6, + FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19, + FN_IP10_24_22, FN_AVS1, FN_AVS2, + + /* IPSR0 */ + FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0, + FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B, + FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, + FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A, + FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A, + FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0, + FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5, + FN_A6, FN_A7, FN_A8, FN_A9, + FN_A10, FN_A11, FN_A12, FN_A13, + FN_A14, FN_A15, FN_A16, FN_A17, + FN_A18, FN_A19, + + /* IPSR1 */ + FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B, + FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, + FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, + FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24, + FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A, + FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A, + FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT, + FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B, + FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, + FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR, + FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0, + FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1, + FN_MMC_D4, + + /* IPSR2 */ + FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2, + FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3, + FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4, + FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A, + FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A, + FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0, + FN_PWM0_C, FN_D0, FN_D1, FN_D2, + FN_D3, FN_D4, FN_D5, FN_D6, + FN_D7, FN_D8, FN_D9, FN_D10, + FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK, + FN_IRQ1_A, + + /* IPSR3 */ + FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, + FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, + FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, + FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A, + FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, + FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, + FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B, + FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0, + FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2, + FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4, + FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3, + FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, + FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3, + FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5, + FN_DU0_DR6, FN_LCDOUT6, + + /* IPSR4 */ + FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, + FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D, + FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9, + FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D, + FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10, + FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, + FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, + FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7, + FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B, + FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6, + FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B, + FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, + FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, + FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2, + FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, + FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, + + /* IPSR5 */ + FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B, + FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B, + FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, + FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK, + FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A, + FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, + FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP, + FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK, + FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, + FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D, + FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, + FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, + FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, + FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B, + FN_RX2_A, FN_CAN0_RX_B, + + /* IPSR6 */ + FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B, + FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B, + FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5, + FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5, + FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8, + FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9, + FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, + FN_SSI_SCK012, FN_ARM_TRACEDATA_11, + FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12, + FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13, + FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, + FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0, + FN_ARM_TRACEDATA_15, + FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST, + FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK, + FN_SD0_DAT2, FN_SUB_TDI, + + /* IPSR7 */ + FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A, + FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A, + FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A, + FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A, + FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC, + FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C, + FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C, + FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A, + FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, + FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B, + FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A, + FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, + FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B, + + /* IPSR8 */ + FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, + FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0, + FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1, + FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2, + FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3, + FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4, + FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5, + FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B, + FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A, + FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, + FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, + FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B, + FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B, + + /* IPSR9 */ + FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, + FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, + FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK, + FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A, + FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2, + FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, + FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV, + FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN, + FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER, + FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A, + FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C, + FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C, + FN_RX2_D, FN_SCL2_C, + + /* IPSR10 */ + FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1, + FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1, + FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP, + FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A, + FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, + FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A, + FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B, + FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, + FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A, + FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B, + FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, + FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C, + + /* SEL */ + FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, + FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C, + FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, + FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E, + FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, + FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, + FN_SEL_SSI2_A, FN_SEL_SSI2_B, + FN_SEL_SSI1_A, FN_SEL_SSI1_B, + FN_SEL_VI1_A, FN_SEL_VI1_B, + FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D, + FN_SEL_SD2_A, FN_SEL_SD2_B, + FN_SEL_SD1_A, FN_SEL_SD1_B, + FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, + FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C, + FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, + FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, + FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, + FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, + FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, + FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, + FN_SEL_CAN1_A, FN_SEL_CAN1_B, + FN_SEL_CAN0_A, FN_SEL_CAN0_B, + FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, + FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, + FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, + FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, + FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C, + FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D, + FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C, + FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, + FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, + FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, + FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, + FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C, + FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C, + FN_SEL_I2C1_A, FN_SEL_I2C1_B, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* GPSR0 */ + PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK, + + /* GPSR1 */ + WE0_MARK, + + /* GPSR2 */ + AUDIO_CLKA_MARK, + AUDIO_CLKB_MARK, + + /* GPSR3 */ + SSI_SCK34_MARK, + + /* GPSR4 */ + AVS1_MARK, + AVS2_MARK, + + VI0_R0_C_MARK, /* see sel_vi0 */ + VI0_R1_C_MARK, /* see sel_vi0 */ + VI0_R2_C_MARK, /* see sel_vi0 */ + /* VI0_R3_C_MARK, */ + VI0_R4_C_MARK, /* see sel_vi0 */ + VI0_R5_C_MARK, /* see sel_vi0 */ + + VI0_R0_D_MARK, /* see sel_vi0 */ + VI0_R1_D_MARK, /* see sel_vi0 */ + VI0_R2_D_MARK, /* see sel_vi0 */ + VI0_R3_D_MARK, /* see sel_vi0 */ + VI0_R4_D_MARK, /* see sel_vi0 */ + VI0_R5_D_MARK, /* see sel_vi0 */ + + /* IPSR0 */ + PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, + ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK, + TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK, + GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK, + SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK, + ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK, + MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK, + A4_MARK, A5_MARK, A6_MARK, A7_MARK, + A8_MARK, A9_MARK, A10_MARK, A11_MARK, + A12_MARK, A13_MARK, A14_MARK, A15_MARK, + A16_MARK, A17_MARK, A18_MARK, A19_MARK, + + /* IPSR1 */ + A20_MARK, HSPI_CS1_B_MARK, A21_MARK, + HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK, + RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK, + TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK, + SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK, + HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK, + MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK, + RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK, + HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK, + HSPI_RX1_B_MARK, SSI_SCK1_B_MARK, + ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK, + MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK, + ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK, + TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK, + + /* IPSR2 */ + SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK, + SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK, + SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK, + EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK, + MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK, + DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK, + DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK, + D1_MARK, D2_MARK, D3_MARK, D4_MARK, + D5_MARK, D6_MARK, D7_MARK, D8_MARK, + D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK, + IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK, + + /* IPSR3 */ + MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK, + MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK, + SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK, + CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK, + TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK, + RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK, + SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK, + HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK, + HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK, + DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK, + SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK, + SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK, + ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK, + TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK, + DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, + DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, + + /* IPSR4 */ + DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, + AUDATA4_MARK, ARM_TRACEDATA_4_MARK, + TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK, + LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK, + RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK, + LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK, + LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK, + TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK, + DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK, + VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK, + ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK, + ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK, + VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK, + ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK, + TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK, + VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK, + DU0_DB4_MARK, LCDOUT20_MARK, + + /* IPSR5 */ + VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK, + DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK, + DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, + QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK, + QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK, + AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK, + DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, + QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK, + DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK, + BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK, + AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK, + SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK, + TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK, + RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK, + SSI_SCK2_A_MARK, HSPI_CS0_B_MARK, + TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK, + HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK, + + /* IPSR6 */ + SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK, + CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK, + BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK, + HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK, + RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK, + RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK, + SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK, + SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK, + SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK, + TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK, + SSI_SDATA2_MARK, HSPI_CS2_A_MARK, + ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK, + ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK, + SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK, + SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK, + SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK, + SD0_DAT2_MARK, SUB_TDI_MARK, + + /* IPSR7 */ + SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK, + SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK, + HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK, + HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK, + HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK, + VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK, + TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK, + IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK, + CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK, + VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK, + RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK, + VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK, + TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK, + DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK, + + /* IPSR8 */ + VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK, + HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK, + DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK, + DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK, + DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK, + DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK, + DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK, + DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK, + VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK, + PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK, + RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK, + DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK, + VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK, + + /* IPSR9 */ + VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK, + DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK, + VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK, + VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK, + VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK, + PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK, + DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK, + ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK, + VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK, + TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK, + IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK, + DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK, + BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK, + DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK, + RX2_D_MARK, SCL2_C_MARK, + + /* IPSR10 */ + SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK, + ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK, + ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK, + DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK, + CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK, + ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK, + PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK, + DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK, + GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK, + DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK, + GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK, + EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK, + REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK, + EX_WAIT2_B_MARK, DACK0_B_MARK, + HSPI_TX2_B_MARK, CAN_CLK_C_MARK, + + PINMUX_MARK_END, +}; + +static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(PENC0_MARK, FN_PENC0), + PINMUX_DATA(PENC1_MARK, FN_PENC1), + PINMUX_DATA(A1_MARK, FN_A1), + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(A3_MARK, FN_A3), + PINMUX_DATA(WE0_MARK, FN_WE0), + PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA), + PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB), + PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT), + PINMUX_IPSR_DATA(IP0_1_0, PWM1), + + PINMUX_IPSR_DATA(IP0_4_2, AUDATA0), + PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0), + PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C), + PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0), + PINMUX_IPSR_DATA(IP0_4_2, TX2_E), + PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B), + + PINMUX_IPSR_DATA(IP0_7_5, AUDATA1), + PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1), + PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C), + PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1), + PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E), + PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B), + + PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP0_11_8, MMC_D2), + PINMUX_IPSR_DATA(IP0_11_8, BS), + PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A), + PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A), + PINMUX_IPSR_DATA(IP0_11_8, PWM4_B), + + PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP0_14_12, MMC_D3), + PINMUX_IPSR_DATA(IP0_14_12, A0), + PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A), + PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B), + + PINMUX_IPSR_DATA(IP0_15, A4), + PINMUX_IPSR_DATA(IP0_16, A5), + PINMUX_IPSR_DATA(IP0_17, A6), + PINMUX_IPSR_DATA(IP0_18, A7), + PINMUX_IPSR_DATA(IP0_19, A8), + PINMUX_IPSR_DATA(IP0_20, A9), + PINMUX_IPSR_DATA(IP0_21, A10), + PINMUX_IPSR_DATA(IP0_22, A11), + PINMUX_IPSR_DATA(IP0_23, A12), + PINMUX_IPSR_DATA(IP0_24, A13), + PINMUX_IPSR_DATA(IP0_25, A14), + PINMUX_IPSR_DATA(IP0_26, A15), + PINMUX_IPSR_DATA(IP0_27, A16), + PINMUX_IPSR_DATA(IP0_28, A17), + PINMUX_IPSR_DATA(IP0_29, A18), + PINMUX_IPSR_DATA(IP0_30, A19), + + /* IPSR1 */ + PINMUX_IPSR_DATA(IP1_0, A20), + PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B), + + PINMUX_IPSR_DATA(IP1_1, A21), + PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B), + + PINMUX_IPSR_DATA(IP1_4_2, A22), + PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B), + PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A), + + PINMUX_IPSR_DATA(IP1_7_5, A23), + PINMUX_IPSR_DATA(IP1_7_5, HTX0_B), + PINMUX_IPSR_DATA(IP1_7_5, TX2_B), + PINMUX_IPSR_DATA(IP1_7_5, DACK2_A), + PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A), + + PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP1_10_8, MMC_D6), + PINMUX_IPSR_DATA(IP1_10_8, A24), + PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A), + PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A), + + PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP1_14_11, MMC_D7), + PINMUX_IPSR_DATA(IP1_14_11, A25), + PINMUX_IPSR_DATA(IP1_14_11, DACK1_A), + PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B), + PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C), + PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A), + + PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT), + PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B), + PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B), + + PINMUX_IPSR_NOGP(IP1_17, CS0), + PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B), + + PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B), + PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B), + PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26), + PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A), + PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B), + + PINMUX_IPSR_DATA(IP1_23_21, MMC_D5), + PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B), + PINMUX_IPSR_DATA(IP1_23_21, RD_WR), + + PINMUX_IPSR_DATA(IP1_24, WE1), + PINMUX_IPSR_DATA(IP1_24, ATAWR0_B), + + PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B), + PINMUX_IPSR_DATA(IP1_27_25, EX_CS0), + PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A), + PINMUX_IPSR_DATA(IP1_27_25, TX3_C), + PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A), + + PINMUX_IPSR_DATA(IP1_29_28, EX_CS1), + PINMUX_IPSR_DATA(IP1_29_28, MMC_D4), + + /* IPSR2 */ + PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A), + PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK), + PINMUX_IPSR_DATA(IP2_2_0, ATACS00), + PINMUX_IPSR_DATA(IP2_2_0, EX_CS2), + + PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD), + PINMUX_IPSR_DATA(IP2_5_3, ATACS10), + PINMUX_IPSR_DATA(IP2_5_3, EX_CS3), + + PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_8_6, MMC_D0), + PINMUX_IPSR_DATA(IP2_8_6, ATARD0), + PINMUX_IPSR_DATA(IP2_8_6, EX_CS4), + PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A), + + PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A), + PINMUX_IPSR_DATA(IP2_11_9, MMC_D1), + PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A), + PINMUX_IPSR_DATA(IP2_11_9, EX_CS5), + PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A), + + PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A), + PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A), + + PINMUX_IPSR_DATA(IP2_16_14, DACK0), + PINMUX_IPSR_DATA(IP2_16_14, TX3_A), + PINMUX_IPSR_DATA(IP2_16_14, DRACK0), + + PINMUX_IPSR_DATA(IP2_17, EX_WAIT0), + PINMUX_IPSR_DATA(IP2_17, PWM0_C), + + PINMUX_IPSR_NOGP(IP2_18, D0), + PINMUX_IPSR_NOGP(IP2_19, D1), + PINMUX_IPSR_NOGP(IP2_20, D2), + PINMUX_IPSR_NOGP(IP2_21, D3), + PINMUX_IPSR_NOGP(IP2_22, D4), + PINMUX_IPSR_NOGP(IP2_23, D5), + PINMUX_IPSR_NOGP(IP2_24, D6), + PINMUX_IPSR_NOGP(IP2_25, D7), + PINMUX_IPSR_NOGP(IP2_26, D8), + PINMUX_IPSR_NOGP(IP2_27, D9), + PINMUX_IPSR_NOGP(IP2_28, D10), + PINMUX_IPSR_NOGP(IP2_29, D11), + + PINMUX_IPSR_DATA(IP2_30, RD_WR_B), + PINMUX_IPSR_DATA(IP2_30, IRQ0), + + PINMUX_IPSR_DATA(IP2_31, MLB_CLK), + PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A), + + /* IPSR3 */ + PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG), + PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B), + PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A), + PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A), + + PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT), + PINMUX_IPSR_DATA(IP3_4_2, TX5_B), + PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A), + PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A), + PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B), + + PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK), + PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B), + PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B), + PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B), + + PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B), + PINMUX_IPSR_DATA(IP3_9_8, HTX0_A), + PINMUX_IPSR_DATA(IP3_9_8, TX0_A), + + PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A), + PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A), + + PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_15_13, SCK0), + PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B), + + PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_18_16, CTS0), + + PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B), + PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A), + PINMUX_IPSR_DATA(IP3_20_19, RTS0), + + PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4), + PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0), + PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0), + PINMUX_IPSR_DATA(IP3_23_21, AUDATA2), + PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2), + PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C), + PINMUX_IPSR_DATA(IP3_23_21, ADICHS1), + PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4), + PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1), + PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1), + PINMUX_IPSR_DATA(IP3_26_24, AUDATA3), + PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3), + PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C), + PINMUX_IPSR_DATA(IP3_26_24, ADICHS2), + PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP3_27, DU0_DR2), + PINMUX_IPSR_DATA(IP3_27, LCDOUT2), + + PINMUX_IPSR_DATA(IP3_28, DU0_DR3), + PINMUX_IPSR_DATA(IP3_28, LCDOUT3), + + PINMUX_IPSR_DATA(IP3_29, DU0_DR4), + PINMUX_IPSR_DATA(IP3_29, LCDOUT4), + + PINMUX_IPSR_DATA(IP3_30, DU0_DR5), + PINMUX_IPSR_DATA(IP3_30, LCDOUT5), + + PINMUX_IPSR_DATA(IP3_31, DU0_DR6), + PINMUX_IPSR_DATA(IP3_31, LCDOUT6), + + /* IPSR4 */ + PINMUX_IPSR_DATA(IP4_0, DU0_DR7), + PINMUX_IPSR_DATA(IP4_0, LCDOUT7), + + PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0), + PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8), + PINMUX_IPSR_DATA(IP4_3_1, AUDATA4), + PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4), + PINMUX_IPSR_DATA(IP4_3_1, TX1_D), + PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A), + PINMUX_IPSR_DATA(IP4_3_1, ADICHS0), + + PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1), + PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9), + PINMUX_IPSR_DATA(IP4_6_4, AUDATA5), + PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5), + PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D), + PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A), + PINMUX_IPSR_DATA(IP4_6_4, ADIDATA), + + PINMUX_IPSR_DATA(IP4_7, DU0_DG2), + PINMUX_IPSR_DATA(IP4_7, LCDOUT10), + + PINMUX_IPSR_DATA(IP4_8, DU0_DG3), + PINMUX_IPSR_DATA(IP4_8, LCDOUT11), + + PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4), + PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12), + PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B), + + PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5), + PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13), + PINMUX_IPSR_DATA(IP4_12_11, TX0_B), + + PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6), + PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14), + PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A), + + PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7), + PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15), + PINMUX_IPSR_DATA(IP4_16_15, TX4_A), + + PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B), + PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0), + PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16), + PINMUX_IPSR_DATA(IP4_20_17, AUDATA6), + PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6), + PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A), + PINMUX_IPSR_DATA(IP4_20_17, PWM0_A), + PINMUX_IPSR_DATA(IP4_20_17, ADICLK), + PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B), + + PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC), + PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1), + PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17), + PINMUX_IPSR_DATA(IP4_24_21, AUDATA7), + PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7), + PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A), + PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP), + PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B), + + PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2), + PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18), + + PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B), + PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3), + PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19), + + PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4), + PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20), + + /* IPSR5 */ + PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */ + PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5), + PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21), + + PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B), + PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6), + PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22), + + PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B), + PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7), + PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23), + + PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN), + PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS), + + PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0), + PINMUX_IPSR_DATA(IP5_7, QCLK), + + PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1), + PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE), + PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A), + PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C), + + PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B), + PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC), + PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS), + + PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP5_12, QSTB_QHE), + + PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE), + PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D), + + PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A), + PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP), + PINMUX_IPSR_DATA(IP5_17_15, QPOLA), + PINMUX_IPSR_DATA(IP5_17_15, AUDCK), + PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK), + PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D), + + PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A), + PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE), + PINMUX_IPSR_DATA(IP5_20_18, QPOLB), + PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC), + PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL), + PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D), + + PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78), + PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B), + PINMUX_IPSR_DATA(IP5_22_21, TX1_B), + + PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B), + PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78), + PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B), + PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B), + PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D), + + PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8), + PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A), + PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B), + PINMUX_IPSR_DATA(IP5_28_26, TX2_A), + PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B), + + PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7), + PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B), + PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A), + PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B), + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6), + PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A), + PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B), + PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B), + + PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6), + PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A), + PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B), + PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B), + + PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6), + PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A), + PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B), + + PINMUX_IPSR_DATA(IP6_7, SSI_SCK5), + PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C), + + PINMUX_IPSR_DATA(IP6_8, SSI_WS5), + PINMUX_IPSR_DATA(IP6_8, TX4_C), + + PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5), + PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D), + + PINMUX_IPSR_DATA(IP6_10, SSI_WS34), + PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8), + + PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A), + PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9), + + PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3), + PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10), + + PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012), + PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11), + PINMUX_IPSR_DATA(IP6_15_14, TX0_D), + + PINMUX_IPSR_DATA(IP6_16, SSI_WS012), + PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12), + + PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2), + PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A), + PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13), + PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A), + + PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1), + PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14), + PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A), + PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A), + + PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0), + PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15), + + PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK), + PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO), + + PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD), + PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST), + + PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0), + PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS), + + PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1), + PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK), + + PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2), + PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI), + + /* IPSR7 */ + PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3), + PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B), + + PINMUX_IPSR_DATA(IP7_3_2, SD0_CD), + PINMUX_IPSR_DATA(IP7_3_2, TX5_A), + + PINMUX_IPSR_DATA(IP7_5_4, SD0_WP), + PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A), + + PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB), + PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A), + PINMUX_IPSR_DATA(IP7_8_6, HTX1_A), + PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD), + PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A), + PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC), + PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A), + PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A), + PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C), + + PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC), + PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0), + PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A), + PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A), + PINMUX_IPSR_DATA(IP7_17_15, TX1_C), + + PINMUX_IPSR_DATA(IP7_20_18, TCLK0), + PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A), + PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A), + PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C), + PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C), + PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN), + + PINMUX_IPSR_DATA(IP7_21, VI0_CLK), + PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A), + + PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB), + PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0), + PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6), + PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A), + PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B), + + PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD), + PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B), + PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1), + PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7), + PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A), + PINMUX_IPSR_DATA(IP7_28_25, TX4_B), + + PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC), + PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2), + PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2), + PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A), + PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B), + + /* IPSR8 */ + PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC), + PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3), + PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3), + PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A), + PINMUX_IPSR_DATA(IP8_2_0, TX3_B), + + PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2), + PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B), + PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D), + + PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3), + PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B), + PINMUX_IPSR_DATA(IP8_8_6, TX3_D), + + PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4), + PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C), + + PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5), + PINMUX_IPSR_DATA(IP8_13_11, TX1_A), + PINMUX_IPSR_DATA(IP8_13_11, TX0_C), + + PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2), + PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A), + + PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3), + PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A), + PINMUX_IPSR_DATA(IP8_18_16, PWM4), + PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B), + + PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0), + PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4), + PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A), + PINMUX_IPSR_DATA(IP8_21_19, PWM5), + + PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1), + PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5), + PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A), + + PINMUX_IPSR_DATA(IP8_26_24, VI0_G2), + PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B), + PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4), + PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4), + PINMUX_IPSR_DATA(IP8_26_24, HTX1_B), + + PINMUX_IPSR_DATA(IP8_29_27, VI0_G3), + PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5), + PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5), + PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B), + + /* IPSR9 */ + PINMUX_IPSR_DATA(IP9_2_0, VI0_G4), + PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6), + PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6), + PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B), + + PINMUX_IPSR_DATA(IP9_5_3, VI0_G5), + PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B), + PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7), + PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7), + PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B), + + PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK), + PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN), + + PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8), + PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6), + PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0), + PINMUX_IPSR_DATA(IP9_11_9, PWM2), + PINMUX_IPSR_DATA(IP9_11_9, TCLK1), + + PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9), + PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7), + PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1), + PINMUX_IPSR_DATA(IP9_14_12, PWM3), + + PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A), + PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP9_17_15, IECLK), + PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C), + + PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN), + PINMUX_IPSR_DATA(IP9_20_18, IETX), + PINMUX_IPSR_DATA(IP9_20_18, TX2_C), + + PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */ + PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */ + PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER), + PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C), + PINMUX_IPSR_DATA(IP9_23_21, IERX), + PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C), + + PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A), + PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0), + PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C), + PINMUX_IPSR_DATA(IP9_26_24, TX2_D), + PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C), + + PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A), + PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1), + PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C), + PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D), + PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C), + + /* IPSR10 */ + PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A), + PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP10_2_0, ATARD1), + PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC), + PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B), + + PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP10_5_3, ATAWR1), + PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO), + PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B), + + PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP), + PINMUX_IPSR_DATA(IP10_8_6, ATACS01), + PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B), + PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), + PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A), + + PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE), + PINMUX_IPSR_DATA(IP10_12_9, ATACS11), + PINMUX_IPSR_DATA(IP10_12_9, DACK1_B), + PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC), + PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A), + PINMUX_IPSR_DATA(IP10_12_9, PWM6), + + PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12), + PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B), + PINMUX_IPSR_DATA(IP10_15_13, ATADIR1), + PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B), + + PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13), + PINMUX_IPSR_DATA(IP10_18_16, DACK2_B), + PINMUX_IPSR_DATA(IP10_18_16, ATAG1), + PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B), + + PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14), + PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B), + PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B), + PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B), + PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A), + + PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A), + PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15), + PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B), + PINMUX_IPSR_DATA(IP10_24_22, DACK0_B), + PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B), + PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), +}; + +static struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) + +/* - macro */ +#define SH_PFC_PINS(name, args...) \ + static const unsigned int name ##_pins[] = { args } +#define SH_PFC_MUX1(name, arg1) \ + static const unsigned int name ##_mux[] = { arg1##_MARK } +#define SH_PFC_MUX2(name, arg1, arg2) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, } +#define SH_PFC_MUX3(name, arg1, arg2, arg3) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK } +#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK } +#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \ + static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ + arg3##_MARK, arg4##_MARK, \ + arg5##_MARK, arg6##_MARK, \ + arg7##_MARK, arg8##_MARK, } + +/* - Ether ------------------------------------------------------------------ */ +SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17)); +static const unsigned int ether_rmii_mux[] = { + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, + ETH_MDIO_MARK, ETH_MDC_MARK, +}; +SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19)); +SH_PFC_MUX1(ether_link, ETH_LINK); +SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20)); +SH_PFC_MUX1(ether_magic, ETH_MAGIC); + +/* - SCIF macro ------------------------------------------------------------- */ +#define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) +#define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts) +#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck) + +/* - HSCIF0 ----------------------------------------------------------------- */ +SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A); +SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30)); +SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B); +SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A); +SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28)); +SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B); +SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19)); +SCIF_PFC_CLK(hscif0_clk, HSCK0); + +/* - HSCIF1 ----------------------------------------------------------------- */ +SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20)); +SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A); +SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B); +SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); +SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A); +SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7)); +SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B); +SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23)); +SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); +SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); +SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); + +/* - HSPI macro --------------------------------------------------------------*/ +#define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx) + +/* - HSPI0 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); +HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A, + HSPI_RX0_A, HSPI_TX0); + +HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27)); +HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B, + HSPI_RX0_B, HSPI_TX0_B); + +/* - HSPI1 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28)); +HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, + HSPI_RX1_A, HSPI_TX1_A); + +HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), + PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); +HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, + HSPI_RX1_B, HSPI_TX1_B); + +/* - HSPI2 -------------------------------------------------------------------*/ +HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30)); +HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A, + HSPI_RX2_A, HSPI_TX2_A); + +HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24)); +HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B, + HSPI_RX2_B, HSPI_TX2_B); + +/* - I2C macro ------------------------------------------------------------- */ +#define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) +#define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) + +/* - I2C1 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9)); +I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A); +I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); + +/* - I2C2 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); +I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); +I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); +I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); +I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C); + +/* - I2C3 ------------------------------------------------------------------ */ +I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15)); +I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A); +I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19)); +I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); +I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); +I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); + +/* - MMC macro -------------------------------------------------------------- */ +#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) +#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) +#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) +#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ + SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) + +/* - MMC -------------------------------------------------------------------- */ +MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); +MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); +MMC_PFC_DAT1(mmc_data1, MMC_D0); +MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, + MMC_D2, MMC_D3); +MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); +MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, + MMC_D2, MMC_D3, + MMC_D4, MMC_D5, + MMC_D6, MMC_D7); + +/* - SCIF CLOCK ------------------------------------------------------------- */ +SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); +SCIF_PFC_CLK(scif_clk, SCIF_CLK); + +/* - SCIF0 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); +SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A); +SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2)); +SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B); +SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31)); +SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C); +SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1)); +SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D); +SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0); +SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19)); +SCIF_PFC_CLK(scif0_clk, SCK0); + +/* - SCIF1 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1)); +SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A); +SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); +SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B); +SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); +SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C); +SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); +SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D); +SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); +SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A); +SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19)); +SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C); +SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2)); +SCIF_PFC_CLK(scif1_clk_a, SCK1_A); +SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20)); +SCIF_PFC_CLK(scif1_clk_c, SCK1_C); + +/* - SCIF2 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); +SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A); +SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28)); +SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B); +SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14)); +SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C); +SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); +SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D); +SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); +SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); +SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); +SCIF_PFC_CLK(scif2_clk_a, SCK2_A); +SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); +SCIF_PFC_CLK(scif2_clk_b, SCK2_B); +SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); +SCIF_PFC_CLK(scif2_clk_c, SCK2_C); + +/* - SCIF3 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9)); +SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A); +SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27)); +SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B); +SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31)); +SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C); +SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29)); +SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D); + +/* - SCIF4 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4)); +SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A); +SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25)); +SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B); +SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31)); +SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C); + +/* - SCIF5 ------------------------------------------------------------------ */ +SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18)); +SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); +SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); +SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); + +/* - SDHI macro ------------------------------------------------------------- */ +#define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) +#define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) +#define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) +#define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) +#define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) + +/* - SDHI0 ------------------------------------------------------------------ */ +SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); +SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); +SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); +SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); +SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); +SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); +SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); +SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, + SD0_DAT2, SD0_DAT3); +SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); +SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); + +/* - SDHI1 ------------------------------------------------------------------ */ +SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30)); +SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A); +SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24)); +SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B); +SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); +SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); +SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); +SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); +SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); +SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); +SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); +SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); +SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); +SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, + SD1_DAT2_A, SD1_DAT3_A); +SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); +SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, + SD1_DAT2_B, SD1_DAT3_B); +SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); +SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); +SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25)); +SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B); + +/* - SDH2 ------------------------------------------------------------------- */ +SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23)); +SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A); +SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27)); +SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B); +SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); +SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); +SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); +SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); +SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); +SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); +SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); +SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); +SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); +SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, + SD2_DAT2_A, SD2_DAT3_A); +SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); +SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, + SD2_DAT2_B, SD2_DAT3_B); +SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); +SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); +SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); +SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); + +/* - USB0 ------------------------------------------------------------------- */ +SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); +SH_PFC_MUX1(usb0, PENC0); +SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3)); +SH_PFC_MUX1(usb0_ovc, USB_OVC0); + +/* - USB1 ------------------------------------------------------------------- */ +SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2)); +SH_PFC_MUX1(usb1, PENC1); +SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); +SH_PFC_MUX1(usb1_ovc, USB_OVC1); + +/* - VIN macros ------------------------------------------------------------- */ +#define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) +#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ + SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) +#define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) +#define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync) + +/* - VIN0 ------------------------------------------------------------------- */ +VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), + RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0), + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); +VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1, + VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3, + VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5, + VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1); +VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24)); +VIN_PFC_CLK(vin0_clk, VI0_CLK); +VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28)); +VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC); +/* - VIN1 ------------------------------------------------------------------- */ +VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8)); +VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1, + VI1_DATA2, VI1_DATA3, + VI1_DATA4, VI1_DATA5, + VI1_DATA6, VI1_DATA7); +VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9)); +VIN_PFC_CLK(vin1_clk, VI1_CLK); +VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); +VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(ether_rmii), + SH_PFC_PIN_GROUP(ether_link), + SH_PFC_PIN_GROUP(ether_magic), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hspi0_a), + SH_PFC_PIN_GROUP(hspi0_b), + SH_PFC_PIN_GROUP(hspi1_a), + SH_PFC_PIN_GROUP(hspi1_b), + SH_PFC_PIN_GROUP(hspi2_a), + SH_PFC_PIN_GROUP(hspi2_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_ctrl_a), + SH_PFC_PIN_GROUP(scif1_ctrl_c), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_clk_c), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_data_d), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif2_clk_a), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_clk_c), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_cd_a), + SH_PFC_PIN_GROUP(sdhi1_cd_b), + SH_PFC_PIN_GROUP(sdhi1_ctrl_a), + SH_PFC_PIN_GROUP(sdhi1_ctrl_b), + SH_PFC_PIN_GROUP(sdhi1_data1_a), + SH_PFC_PIN_GROUP(sdhi1_data1_b), + SH_PFC_PIN_GROUP(sdhi1_data4_a), + SH_PFC_PIN_GROUP(sdhi1_data4_b), + SH_PFC_PIN_GROUP(sdhi1_wp_a), + SH_PFC_PIN_GROUP(sdhi1_wp_b), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_ctrl_a), + SH_PFC_PIN_GROUP(sdhi2_ctrl_b), + SH_PFC_PIN_GROUP(sdhi2_data1_a), + SH_PFC_PIN_GROUP(sdhi2_data1_b), + SH_PFC_PIN_GROUP(sdhi2_data4_a), + SH_PFC_PIN_GROUP(sdhi2_data4_b), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_ovc), + SH_PFC_PIN_GROUP(vin0_data8), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_sync), +}; + +static const char * const ether_groups[] = { + "ether_rmii", + "ether_link", + "ether_magic", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_data_b", + "hscif0_ctrl_a", + "hscif0_ctrl_b", + "hscif0_clk", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_data_b", + "hscif1_ctrl_a", + "hscif1_ctrl_b", + "hscif1_clk_a", + "hscif1_clk_b", +}; + +static const char * const hspi0_groups[] = { + "hspi0_a", + "hspi0_b", +}; + +static const char * const hspi1_groups[] = { + "hspi1_a", + "hspi1_b", +}; + +static const char * const hspi2_groups[] = { + "hspi2_a", + "hspi2_b", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", + "i2c2_c", +}; + +static const char * const i2c3_groups[] = { + "i2c3_a", + "i2c3_b", + "i2c3_c", +}; + +static const char * const mmc_groups[] = { + "mmc_ctrl", + "mmc_data1", + "mmc_data4", + "mmc_data8", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const scif0_groups[] = { + "scif0_data_a", + "scif0_data_b", + "scif0_data_c", + "scif0_data_d", + "scif0_ctrl", + "scif0_clk", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_data_b", + "scif1_data_c", + "scif1_data_d", + "scif1_ctrl_a", + "scif1_ctrl_c", + "scif1_clk_a", + "scif1_clk_c", +}; + +static const char * const scif2_groups[] = { + "scif2_data_a", + "scif2_data_b", + "scif2_data_c", + "scif2_data_d", + "scif2_data_e", + "scif2_clk_a", + "scif2_clk_b", + "scif2_clk_c", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_data_b", + "scif3_data_c", + "scif3_data_d", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_data_b", + "scif4_data_c", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_data_b", +}; + + +static const char * const sdhi0_groups[] = { + "sdhi0_cd", + "sdhi0_ctrl", + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_cd_a", + "sdhi1_cd_b", + "sdhi1_ctrl_a", + "sdhi1_ctrl_b", + "sdhi1_data1_a", + "sdhi1_data1_b", + "sdhi1_data4_a", + "sdhi1_data4_b", + "sdhi1_wp_a", + "sdhi1_wp_b", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_cd_a", + "sdhi2_cd_b", + "sdhi2_ctrl_a", + "sdhi2_ctrl_b", + "sdhi2_data1_a", + "sdhi2_data1_b", + "sdhi2_data4_a", + "sdhi2_data4_b", + "sdhi2_wp_a", + "sdhi2_wp_b", +}; + +static const char * const usb0_groups[] = { + "usb0", + "usb0_ovc", +}; + +static const char * const usb1_groups[] = { + "usb1", + "usb1_ovc", +}; + +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_clk", + "vin0_sync", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_clk", + "vin1_sync", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(ether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hspi0), + SH_PFC_FUNCTION(hspi1), + SH_PFC_FUNCTION(hspi2), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { + GP_0_31_FN, FN_IP1_14_11, + GP_0_30_FN, FN_IP1_10_8, + GP_0_29_FN, FN_IP1_7_5, + GP_0_28_FN, FN_IP1_4_2, + GP_0_27_FN, FN_IP1_1, + GP_0_26_FN, FN_IP1_0, + GP_0_25_FN, FN_IP0_30, + GP_0_24_FN, FN_IP0_29, + GP_0_23_FN, FN_IP0_28, + GP_0_22_FN, FN_IP0_27, + GP_0_21_FN, FN_IP0_26, + GP_0_20_FN, FN_IP0_25, + GP_0_19_FN, FN_IP0_24, + GP_0_18_FN, FN_IP0_23, + GP_0_17_FN, FN_IP0_22, + GP_0_16_FN, FN_IP0_21, + GP_0_15_FN, FN_IP0_20, + GP_0_14_FN, FN_IP0_19, + GP_0_13_FN, FN_IP0_18, + GP_0_12_FN, FN_IP0_17, + GP_0_11_FN, FN_IP0_16, + GP_0_10_FN, FN_IP0_15, + GP_0_9_FN, FN_A3, + GP_0_8_FN, FN_A2, + GP_0_7_FN, FN_A1, + GP_0_6_FN, FN_IP0_14_12, + GP_0_5_FN, FN_IP0_11_8, + GP_0_4_FN, FN_IP0_7_5, + GP_0_3_FN, FN_IP0_4_2, + GP_0_2_FN, FN_PENC1, + GP_0_1_FN, FN_PENC0, + GP_0_0_FN, FN_IP0_1_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { + GP_1_31_FN, FN_IP4_6_4, + GP_1_30_FN, FN_IP4_3_1, + GP_1_29_FN, FN_IP4_0, + GP_1_28_FN, FN_IP3_31, + GP_1_27_FN, FN_IP3_30, + GP_1_26_FN, FN_IP3_29, + GP_1_25_FN, FN_IP3_28, + GP_1_24_FN, FN_IP3_27, + GP_1_23_FN, FN_IP3_26_24, + GP_1_22_FN, FN_IP3_23_21, + GP_1_21_FN, FN_IP3_20_19, + GP_1_20_FN, FN_IP3_18_16, + GP_1_19_FN, FN_IP3_15_13, + GP_1_18_FN, FN_IP3_12_10, + GP_1_17_FN, FN_IP3_9_8, + GP_1_16_FN, FN_IP3_7_5, + GP_1_15_FN, FN_IP3_4_2, + GP_1_14_FN, FN_IP3_1_0, + GP_1_13_FN, FN_IP2_31, + GP_1_12_FN, FN_IP2_30, + GP_1_11_FN, FN_IP2_17, + GP_1_10_FN, FN_IP2_16_14, + GP_1_9_FN, FN_IP2_13_12, + GP_1_8_FN, FN_IP2_11_9, + GP_1_7_FN, FN_IP2_8_6, + GP_1_6_FN, FN_IP2_5_3, + GP_1_5_FN, FN_IP2_2_0, + GP_1_4_FN, FN_IP1_29_28, + GP_1_3_FN, FN_IP1_27_25, + GP_1_2_FN, FN_IP1_24, + GP_1_1_FN, FN_WE0, + GP_1_0_FN, FN_IP1_23_21 } + }, + { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { + GP_2_31_FN, FN_IP6_7, + GP_2_30_FN, FN_IP6_6_5, + GP_2_29_FN, FN_IP6_4_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_30_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_23, + GP_2_24_FN, FN_IP5_22_21, + GP_2_23_FN, FN_AUDIO_CLKB, + GP_2_22_FN, FN_AUDIO_CLKA, + GP_2_21_FN, FN_IP5_20_18, + GP_2_20_FN, FN_IP5_17_15, + GP_2_19_FN, FN_IP5_14_13, + GP_2_18_FN, FN_IP5_12, + GP_2_17_FN, FN_IP5_11_10, + GP_2_16_FN, FN_IP5_9_8, + GP_2_15_FN, FN_IP5_7, + GP_2_14_FN, FN_IP5_6, + GP_2_13_FN, FN_IP5_5_4, + GP_2_12_FN, FN_IP5_3_2, + GP_2_11_FN, FN_IP5_1_0, + GP_2_10_FN, FN_IP4_30_29, + GP_2_9_FN, FN_IP4_28_27, + GP_2_8_FN, FN_IP4_26_25, + GP_2_7_FN, FN_IP4_24_21, + GP_2_6_FN, FN_IP4_20_17, + GP_2_5_FN, FN_IP4_16_15, + GP_2_4_FN, FN_IP4_14_13, + GP_2_3_FN, FN_IP4_12_11, + GP_2_2_FN, FN_IP4_10_9, + GP_2_1_FN, FN_IP4_8, + GP_2_0_FN, FN_IP4_7 } + }, + { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { + GP_3_31_FN, FN_IP8_10_9, + GP_3_30_FN, FN_IP8_8_6, + GP_3_29_FN, FN_IP8_5_3, + GP_3_28_FN, FN_IP8_2_0, + GP_3_27_FN, FN_IP7_31_29, + GP_3_26_FN, FN_IP7_28_25, + GP_3_25_FN, FN_IP7_24_22, + GP_3_24_FN, FN_IP7_21, + GP_3_23_FN, FN_IP7_20_18, + GP_3_22_FN, FN_IP7_17_15, + GP_3_21_FN, FN_IP7_14_12, + GP_3_20_FN, FN_IP7_11_9, + GP_3_19_FN, FN_IP7_8_6, + GP_3_18_FN, FN_IP7_5_4, + GP_3_17_FN, FN_IP7_3_2, + GP_3_16_FN, FN_IP7_1_0, + GP_3_15_FN, FN_IP6_31_30, + GP_3_14_FN, FN_IP6_29_28, + GP_3_13_FN, FN_IP6_27_26, + GP_3_12_FN, FN_IP6_25_24, + GP_3_11_FN, FN_IP6_23_22, + GP_3_10_FN, FN_IP6_21, + GP_3_9_FN, FN_IP6_20_19, + GP_3_8_FN, FN_IP6_18_17, + GP_3_7_FN, FN_IP6_16, + GP_3_6_FN, FN_IP6_15_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12_11, + GP_3_3_FN, FN_IP6_10, + GP_3_2_FN, FN_SSI_SCK34, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_26_FN, FN_AVS2, + GP_4_25_FN, FN_AVS1, + GP_4_24_FN, FN_IP10_24_22, + GP_4_23_FN, FN_IP10_21_19, + GP_4_22_FN, FN_IP10_18_16, + GP_4_21_FN, FN_IP10_15_13, + GP_4_20_FN, FN_IP10_12_9, + GP_4_19_FN, FN_IP10_8_6, + GP_4_18_FN, FN_IP10_5_3, + GP_4_17_FN, FN_IP10_2_0, + GP_4_16_FN, FN_IP9_29_27, + GP_4_15_FN, FN_IP9_26_24, + GP_4_14_FN, FN_IP9_23_21, + GP_4_13_FN, FN_IP9_20_18, + GP_4_12_FN, FN_IP9_17_15, + GP_4_11_FN, FN_IP9_14_12, + GP_4_10_FN, FN_IP9_11_9, + GP_4_9_FN, FN_IP9_8_6, + GP_4_8_FN, FN_IP9_5_3, + GP_4_7_FN, FN_IP9_2_0, + GP_4_6_FN, FN_IP8_29_27, + GP_4_5_FN, FN_IP8_26_24, + GP_4_4_FN, FN_IP8_23_22, + GP_4_3_FN, FN_IP8_21_19, + GP_4_2_FN, FN_IP8_18_16, + GP_4_1_FN, FN_IP8_15_14, + GP_4_0_FN, FN_IP8_13_11 } + }, + + { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30 [1] */ + FN_A19, 0, + /* IP0_29 [1] */ + FN_A18, 0, + /* IP0_28 [1] */ + FN_A17, 0, + /* IP0_27 [1] */ + FN_A16, 0, + /* IP0_26 [1] */ + FN_A15, 0, + /* IP0_25 [1] */ + FN_A14, 0, + /* IP0_24 [1] */ + FN_A13, 0, + /* IP0_23 [1] */ + FN_A12, 0, + /* IP0_22 [1] */ + FN_A11, 0, + /* IP0_21 [1] */ + FN_A10, 0, + /* IP0_20 [1] */ + FN_A9, 0, + /* IP0_19 [1] */ + FN_A8, 0, + /* IP0_18 [1] */ + FN_A7, 0, + /* IP0_17 [1] */ + FN_A6, 0, + /* IP0_16 [1] */ + FN_A5, 0, + /* IP0_15 [1] */ + FN_A4, 0, + /* IP0_14_12 [3] */ + FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0, + FN_ATAG0_A, 0, FN_REMOCON_B, 0, + /* IP0_11_8 [4] */ + FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, + FN_ATADIR0_A, 0, FN_SDSELF_B, 0, + FN_PWM4_B, 0, 0, 0, + 0, 0, 0, 0, + /* IP0_7_5 [3] */ + FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1, + FN_RX2_E, FN_SCL2_B, 0, 0, + /* IP0_4_2 [3] */ + FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0, + FN_TX2_E, FN_SDA2_B, 0, 0, + /* IP0_1_0 [2] */ + FN_PRESETOUT, 0, FN_PWM1, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, + 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { + /* IP1_31 [1] */ + 0, 0, + /* IP1_30 [1] */ + 0, 0, + /* IP1_29_28 [2] */ + FN_EX_CS1, FN_MMC_D4, 0, 0, + /* IP1_27_25 [3] */ + FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C, + FN_TS_SCK0_A, 0, 0, 0, + /* IP1_24 [1] */ + FN_WE1, FN_ATAWR0_B, + /* IP1_23_21 [3] */ + FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR, + 0, 0, 0, 0, + /* IP1_20_18 [3] */ + FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, + FN_SCK2_B, 0, 0, 0, + /* IP1_17 [1] */ + FN_CS0, FN_HSPI_RX1_B, + /* IP1_16_15 [2] */ + FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0, + /* IP1_14_11 [4] */ + FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25, + FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C, + FN_TS_SDAT0_A, 0, 0, 0, + 0, 0, 0, 0, + /* IP1_10_8 [3] */ + FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, + FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, + /* IP1_7_5 [3] */ + FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, + FN_TS_SDEN0_A, 0, 0, 0, + /* IP1_4_2 [3] */ + FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, + 0, 0, 0, 0, + /* IP1_1 [1] */ + FN_A21, FN_HSPI_CLK1_B, + /* IP1_0 [1] */ + FN_A20, FN_HSPI_CS1_B, + } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { + /* IP2_31 [1] */ + FN_MLB_CLK, FN_IRQ1_A, + /* IP2_30 [1] */ + FN_RD_WR_B, FN_IRQ0, + /* IP2_29 [1] */ + FN_D11, 0, + /* IP2_28 [1] */ + FN_D10, 0, + /* IP2_27 [1] */ + FN_D9, 0, + /* IP2_26 [1] */ + FN_D8, 0, + /* IP2_25 [1] */ + FN_D7, 0, + /* IP2_24 [1] */ + FN_D6, 0, + /* IP2_23 [1] */ + FN_D5, 0, + /* IP2_22 [1] */ + FN_D4, 0, + /* IP2_21 [1] */ + FN_D3, 0, + /* IP2_20 [1] */ + FN_D2, 0, + /* IP2_19 [1] */ + FN_D1, 0, + /* IP2_18 [1] */ + FN_D0, 0, + /* IP2_17 [1] */ + FN_EX_WAIT0, FN_PWM0_C, + /* IP2_16_14 [3] */ + FN_DACK0, 0, 0, FN_TX3_A, + FN_DRACK0, 0, 0, 0, + /* IP2_13_12 [2] */ + FN_DREQ0_A, 0, 0, FN_RX3_A, + /* IP2_11_9 [3] */ + FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A, + FN_EX_CS5, FN_EX_WAIT2_A, 0, 0, + /* IP2_8_6 [3] */ + FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0, + FN_EX_CS4, FN_EX_WAIT1_A, 0, 0, + /* IP2_5_3 [3] */ + FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10, + FN_EX_CS3, 0, 0, 0, + /* IP2_2_0 [3] */ + FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, + FN_EX_CS2, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, + 1, 1, 1, 1, 1, 3, 3, 2, + 3, 3, 3, 2, 3, 3, 2) { + /* IP3_31 [1] */ + FN_DU0_DR6, FN_LCDOUT6, + /* IP3_30 [1] */ + FN_DU0_DR5, FN_LCDOUT5, + /* IP3_29 [1] */ + FN_DU0_DR4, FN_LCDOUT4, + /* IP3_28 [1] */ + FN_DU0_DR3, FN_LCDOUT3, + /* IP3_27 [1] */ + FN_DU0_DR2, FN_LCDOUT2, + /* IP3_26_24 [3] */ + FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, + FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, + /* IP3_23_21 [3] */ + FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2, + FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, + /* IP3_20_19 [2] */ + FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0, + /* IP3_18_16 [3] */ + FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0, + 0, 0, 0, 0, + /* IP3_15_13 [3] */ + FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, + 0, 0, 0, 0, + /* IP3_12_10 [3] */ + FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0, + 0, 0, 0, 0, + /* IP3_9_8 [2] */ + FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0, + /* IP3_7_5 [3] */ + FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B, + FN_SDA3_B, 0, 0, 0, + /* IP3_4_2 [3] */ + FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, + FN_SDSELF_B, 0, 0, 0, + /* IP3_1_0 [2] */ + FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, + } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, + 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { + /* IP4_31 [1] */ + 0, 0, + /* IP4_30_29 [2] */ + FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0, + /* IP4_28_27 [2] */ + FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0, + /* IP4_26_25 [2] */ + FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0, + /* IP4_24_21 [4] */ + FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, + FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0, + FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0, + 0, 0, 0, 0, + /* IP4_20_17 [4] */ + FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16, + FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A, + FN_ADICLK, FN_TS_SDAT0_B, 0, 0, + 0, 0, 0, 0, + /* IP4_16_15 [2] */ + FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0, + /* IP4_14_13 [2] */ + FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0, + /* IP4_12_11 [2] */ + FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0, + /* IP4_10_9 [2] */ + FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0, + /* IP4_8 [1] */ + FN_DU0_DG3, FN_LCDOUT11, + /* IP4_7 [1] */ + FN_DU0_DG2, FN_LCDOUT10, + /* IP4_6_4 [3] */ + FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5, + FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0, + /* IP4_3_1 [3] */ + FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4, + FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, + /* IP4_0 [1] */ + FN_DU0_DR7, FN_LCDOUT7, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, + 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { + + /* IP5_31 [1] */ + 0, 0, + /* IP5_30_29 [2] */ + FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B, + /* IP5_28_26 [3] */ + FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A, + FN_CAN0_TX_B, 0, 0, 0, + /* IP5_25_23 [3] */ + FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, + FN_CAN_CLK_D, 0, 0, 0, + /* IP5_22_21 [2] */ + FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, + /* IP5_20_18 [3] */ + FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC, + FN_ARM_TRACECTL, FN_FMIN_D, 0, 0, + /* IP5_17_15 [3] */ + FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK, + FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0, + /* IP5_14_13 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_FMCLK_D, 0, + /* IP5_12 [1] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + /* IP5_11_10 [2] */ + FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, + FN_QSTH_QHS, 0, + /* IP5_9_8 [2] */ + FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, + FN_AUDIO_CLKOUT_A, FN_REMOCON_C, + /* IP5_7 [1] */ + FN_DU0_DOTCLKO_UT0, FN_QCLK, + /* IP5_6 [1] */ + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, + /* IP5_5_4 [2] */ + FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0, + /* IP5_3_2 [2] */ + FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, + /* IP5_1_0 [2] */ + FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, + 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, + 1, 2, 1, 1, 1, 1, 2, 3, 2) { + /* IP6_31_30 [2] */ + FN_SD0_DAT2, 0, FN_SUB_TDI, 0, + /* IP6_29_28 [2] */ + FN_SD0_DAT1, 0, FN_SUB_TCK, 0, + /* IP6_27_26 [2] */ + FN_SD0_DAT0, 0, FN_SUB_TMS, 0, + /* IP6_25_24 [2] */ + FN_SD0_CMD, 0, FN_SUB_TRST, 0, + /* IP6_23_22 [2] */ + FN_SD0_CLK, 0, FN_SUB_TDO, 0, + /* IP6_21 [1] */ + FN_SSI_SDATA0, FN_ARM_TRACEDATA_15, + /* IP6_20_19 [2] */ + FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, + FN_SCL1_A, FN_SCK2_A, + /* IP6_18_17 [2] */ + FN_SSI_SDATA2, FN_HSPI_CS2_A, + FN_ARM_TRACEDATA_13, FN_SDA1_A, + /* IP6_16 [1] */ + FN_SSI_WS012, FN_ARM_TRACEDATA_12, + /* IP6_15_14 [2] */ + FN_SSI_SCK012, FN_ARM_TRACEDATA_11, + FN_TX0_D, 0, + /* IP6_13 [1] */ + FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, + /* IP6_12_11 [2] */ + FN_SSI_SDATA4, FN_SSI_WS2_A, + FN_ARM_TRACEDATA_9, 0, + /* IP6_10 [1] */ + FN_SSI_WS34, FN_ARM_TRACEDATA_8, + /* IP6_9 [1] */ + FN_SSI_SDATA5, FN_RX0_D, + /* IP6_8 [1] */ + FN_SSI_WS5, FN_TX4_C, + /* IP6_7 [1] */ + FN_SSI_SCK5, FN_RX4_C, + /* IP6_6_5 [2] */ + FN_SSI_SDATA6, FN_HSPI_TX2_A, + FN_FMIN_B, 0, + /* IP6_4_2 [3] */ + FN_SSI_WS6, FN_HSPI_CLK2_A, + FN_BPFCLK_B, FN_CAN1_RX_B, + 0, 0, 0, 0, + /* IP6_1_0 [2] */ + FN_SSI_SCK6, FN_HSPI_RX2_A, + FN_FMCLK_B, FN_CAN1_TX_B, + } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, + 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { + + /* IP7_31_29 [3] */ + FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, + 0, FN_HSPI_CS1_A, FN_RX3_B, 0, + /* IP7_28_25 [4] */ + FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1, + FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP7_24_22 [3] */ + FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, + 0, FN_HSPI_RX1_A, FN_RX4_B, 0, + /* IP7_21 [1] */ + FN_VI0_CLK, FN_CAN_CLK_A, + /* IP7_20_18 [3] */ + FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0, + FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0, + /* IP7_17_15 [3] */ + FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, + 0, FN_TX1_C, 0, 0, + /* IP7_14_12 [3] */ + FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A, + 0, FN_RX1_C, 0, 0, + /* IP7_11_9 [3] */ + FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0, + FN_SCK1_C, 0, 0, 0, + /* IP7_8_6 [3] */ + FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0, + FN_RTS1_C, 0, 0, 0, + /* IP7_5_4 [2] */ + FN_SD0_WP, 0, FN_RX5_A, 0, + /* IP7_3_2 [2] */ + FN_SD0_CD, 0, FN_TX5_A, 0, + /* IP7_1_0 [2] */ + FN_SD0_DAT3, 0, FN_IRQ1_B, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, + 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30 [1] */ + 0, 0, + /* IP8_29_27 [3] */ + FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5, + 0, FN_HRX1_B, 0, 0, + /* IP8_26_24 [3] */ + FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4, + 0, FN_HTX1_B, 0, 0, + /* IP8_23_22 [2] */ + FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, + FN_RTS1_A, 0, + /* IP8_21_19 [3] */ + FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, + FN_CTS1_A, FN_PWM5, + 0, 0, 0, 0, + /* IP8_18_16 [3] */ + FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4, + 0, FN_HSCK1_B, 0, 0, + /* IP8_15_14 [2] */ + FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0, + /* IP8_13_11 [3] */ + FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C, + 0, 0, 0, 0, + /* IP8_10_9 [2] */ + FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0, + /* IP8_8_6 [3] */ + FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, + 0, 0, 0, 0, + /* IP8_5_3 [3] */ + FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, + 0, 0, 0, 0, + /* IP8_2_0 [3] */ + FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, + 0, FN_HSPI_TX1_A, FN_TX3_B, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP9_31 [1] */ + 0, 0, + /* IP9_30 [1] */ + 0, 0, + /* IP9_29_27 [3] */ + FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_ETH_RXD1, FN_FMIN_C, + 0, FN_RX2_D, + FN_SCL2_C, 0, + /* IP9_26_24 [3] */ + FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT, + FN_ETH_RXD0, FN_BPFCLK_C, + 0, FN_TX2_D, + FN_SDA2_C, 0, + /* IP9_23_21 [3] */ + FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C, + FN_IERX, FN_RX2_C, 0, 0, + /* IP9_20_18 [3] */ + FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0, + FN_IETX, FN_TX2_C, 0, 0, + /* IP9_17_15 [3] */ + FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK, + FN_SCK2_C, 0, 0, 0, + /* IP9_14_12 [3] */ + FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1, + 0, FN_PWM3, 0, 0, + /* IP9_11_9 [3] */ + FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, + 0, FN_PWM2, FN_TCLK1, 0, + /* IP9_8_6 [3] */ + FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, + 0, 0, 0, 0, + /* IP9_5_3 [3] */ + FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7, + 0, FN_HCTS1_B, 0, 0, + /* IP9_2_0 [3] */ + FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, + 0, FN_HRTS1_B, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, + 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { + + /* IP10_31 [1] */ + 0, 0, + /* IP10_30 [1] */ + 0, 0, + /* IP10_29 [1] */ + 0, 0, + /* IP10_28 [1] */ + 0, 0, + /* IP10_27 [1] */ + 0, 0, + /* IP10_26 [1] */ + 0, 0, + /* IP10_25 [1] */ + 0, 0, + /* IP10_24_22 [3] */ + FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B, + FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0, + /* IP10_21_19 [3] */ + FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, + FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0, + /* IP10_18_16 [3] */ + FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1, + FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0, + /* IP10_15_13 [3] */ + FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, + FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0, + /* IP10_12_9 [4] */ + FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, + FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IP10_8_6 [3] */ + FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B, + FN_ETH_LINK, FN_CAN1_RX_A, 0, 0, + /* IP10_5_3 [3] */ + FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + FN_ATAWR1, FN_ETH_MDIO, + FN_SCL1_B, 0, + 0, 0, + /* IP10_2_0 [3] */ + FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_ATARD1, FN_ETH_MDC, + FN_SDA1_B, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, + 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, + 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + + /* SEL 31 [1] */ + 0, 0, + /* SEL_30 (SCIF5) [1] */ + FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, + /* SEL_29_28 (SCIF4) [2] */ + FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, + FN_SEL_SCIF4_C, 0, + /* SEL_27_26 (SCIF3) [2] */ + FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, + FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, + /* SEL_25_23 (SCIF2) [3] */ + FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, + FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, + FN_SEL_SCIF2_E, 0, + 0, 0, + /* SEL_22_21 (SCIF1) [2] */ + FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, + FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, + /* SEL_20_19 (SCIF0) [2] */ + FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, + FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, + /* SEL_18 [1] */ + 0, 0, + /* SEL_17 (SSI2) [1] */ + FN_SEL_SSI2_A, FN_SEL_SSI2_B, + /* SEL_16 (SSI1) [1] */ + FN_SEL_SSI1_A, FN_SEL_SSI1_B, + /* SEL_15 (VI1) [1] */ + FN_SEL_VI1_A, FN_SEL_VI1_B, + /* SEL_14_13 (VI0) [2] */ + FN_SEL_VI0_A, FN_SEL_VI0_B, + FN_SEL_VI0_C, FN_SEL_VI0_D, + /* SEL_12 [1] */ + 0, 0, + /* SEL_11 (SD2) [1] */ + FN_SEL_SD2_A, FN_SEL_SD2_B, + /* SEL_10 (SD1) [1] */ + FN_SEL_SD1_A, FN_SEL_SD1_B, + /* SEL_9 (IRQ3) [1] */ + FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, + /* SEL_8_7 (IRQ2) [2] */ + FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, + FN_SEL_IRQ2_C, 0, + /* SEL_6 (IRQ1) [1] */ + FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, + /* SEL_5 [1] */ + 0, 0, + /* SEL_4 (DREQ2) [1] */ + FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, + /* SEL_3 (DREQ1) [1] */ + FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, + /* SEL_2 (DREQ0) [1] */ + FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, + /* SEL_1 (WAIT2) [1] */ + FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, + /* SEL_0 (WAIT1) [1] */ + FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { + + /* SEL_31 [1] */ + 0, 0, + /* SEL_30 [1] */ + 0, 0, + /* SEL_29 [1] */ + 0, 0, + /* SEL_28 [1] */ + 0, 0, + /* SEL_27 (CAN1) [1] */ + FN_SEL_CAN1_A, FN_SEL_CAN1_B, + /* SEL_26 (CAN0) [1] */ + FN_SEL_CAN0_A, FN_SEL_CAN0_B, + /* SEL_25_24 (CANCLK) [2] */ + FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, + FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, + /* SEL_23 (HSCIF1) [1] */ + FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, + /* SEL_22 (HSCIF0) [1] */ + FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, + /* SEL_21 [1] */ + 0, 0, + /* SEL_20 [1] */ + 0, 0, + /* SEL_19 [1] */ + 0, 0, + /* SEL_18 [1] */ + 0, 0, + /* SEL_17 [1] */ + 0, 0, + /* SEL_16 [1] */ + 0, 0, + /* SEL_15 [1] */ + 0, 0, + /* SEL_14_13 (REMOCON) [2] */ + FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, + FN_SEL_REMOCON_C, 0, + /* SEL_12_11 (FM) [2] */ + FN_SEL_FM_A, FN_SEL_FM_B, + FN_SEL_FM_C, FN_SEL_FM_D, + /* SEL_10_9 (GPS) [2] */ + FN_SEL_GPS_A, FN_SEL_GPS_B, + FN_SEL_GPS_C, 0, + /* SEL_8 (TSIF0) [1] */ + FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, + /* SEL_7 (HSPI2) [1] */ + FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, + /* SEL_6 (HSPI1) [1] */ + FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, + /* SEL_5 (HSPI0) [1] */ + FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, + /* SEL_4_3 (I2C3) [2] */ + FN_SEL_I2C3_A, FN_SEL_I2C3_B, + FN_SEL_I2C3_C, 0, + /* SEL_2_1 (I2C2) [2] */ + FN_SEL_I2C2_A, FN_SEL_I2C2_B, + FN_SEL_I2C2_C, 0, + /* SEL_0 (I2C1) [1] */ + FN_SEL_I2C1_A, FN_SEL_I2C1_B, + } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7778_pinmux_info = { + .name = "r8a7778_pfc", + + .unlock_reg = 0xfffc0000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 8cd90e7e945a..8e22ca6c1044 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -1,8 +1,9 @@ /* * r8a7779 processor support - PFC hardware block * - * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm + * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +20,7 @@ */ #include <linux/kernel.h> +#include <linux/platform_data/gpio-rcar.h> #include "sh_pfc.h" @@ -79,7 +81,7 @@ #define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx #define _GP_GPIO(bank, pin, _name, sfx) \ - [(bank * 32) + pin] = { \ + [RCAR_GP_PIN(bank, pin)] = { \ .name = __stringify(_name), \ .enum_id = _name##_DATA, \ } @@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = { /* - DU0 -------------------------------------------------------------------- */ static const unsigned int du0_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ - 188, 187, 186, 185, 184, 183, - 194, 193, 192, 191, 190, 189, - 200, 199, 198, 197, 196, 195, + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), + RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 3), }; static const unsigned int du0_rgb666_mux[] = { DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, @@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = { }; static const unsigned int du0_rgb888_pins[] = { /* R[7:0], G[7:0], B[7:0] */ - 188, 187, 186, 185, 184, 183, 24, 23, - 194, 193, 192, 191, 190, 189, 26, 25, - 200, 199, 198, 197, 196, 195, 28, 27, + RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26), + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2), + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(5, 31), + RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26), + RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27), }; static const unsigned int du0_rgb888_mux[] = { DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, @@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = { }; static const unsigned int du0_clk_in_pins[] = { /* CLKIN */ - 29, + RCAR_GP_PIN(0, 29), }; static const unsigned int du0_clk_in_mux[] = { DU0_DOTCLKIN_MARK, }; static const unsigned int du0_clk_out_0_pins[] = { /* CLKOUT */ - 180, + RCAR_GP_PIN(5, 20), }; static const unsigned int du0_clk_out_0_mux[] = { DU0_DOTCLKOUT0_MARK, }; static const unsigned int du0_clk_out_1_pins[] = { /* CLKOUT */ - 30, + RCAR_GP_PIN(0, 30), }; static const unsigned int du0_clk_out_1_mux[] = { DU0_DOTCLKOUT1_MARK, }; static const unsigned int du0_sync_0_pins[] = { /* VSYNC, HSYNC, DISP */ - 182, 181, 31, + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31), }; static const unsigned int du0_sync_0_mux[] = { DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, @@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = { }; static const unsigned int du0_sync_1_pins[] = { /* VSYNC, HSYNC, DISP */ - 182, 181, 32, + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0), }; static const unsigned int du0_sync_1_mux[] = { DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, @@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = { }; static const unsigned int du0_oddf_pins[] = { /* ODDF */ - 31, + RCAR_GP_PIN(0, 31), }; static const unsigned int du0_oddf_mux[] = { DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK }; static const unsigned int du0_cde_pins[] = { /* CDE */ - 33, + RCAR_GP_PIN(1, 1), }; static const unsigned int du0_cde_mux[] = { DU0_CDE_MARK @@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = { /* - DU1 -------------------------------------------------------------------- */ static const unsigned int du1_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ - 41, 40, 39, 38, 37, 36, - 49, 48, 47, 46, 45, 44, - 57, 56, 55, 54, 53, 52, + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20), }; static const unsigned int du1_rgb666_mux[] = { DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, @@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = { }; static const unsigned int du1_rgb888_pins[] = { /* R[7:0], G[7:0], B[7:0] */ - 41, 40, 39, 38, 37, 36, 35, 34, - 49, 48, 47, 46, 45, 44, 43, 32, - 57, 56, 55, 54, 53, 52, 51, 50, + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 17), + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), }; static const unsigned int du1_rgb888_mux[] = { DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, @@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = { }; static const unsigned int du1_clk_in_pins[] = { /* CLKIN */ - 58, + RCAR_GP_PIN(1, 26), }; static const unsigned int du1_clk_in_mux[] = { DU1_DOTCLKIN_MARK, }; static const unsigned int du1_clk_out_pins[] = { /* CLKOUT */ - 59, + RCAR_GP_PIN(1, 27), }; static const unsigned int du1_clk_out_mux[] = { DU1_DOTCLKOUT_MARK, }; static const unsigned int du1_sync_0_pins[] = { /* VSYNC, HSYNC, DISP */ - 61, 60, 62, + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30), }; static const unsigned int du1_sync_0_mux[] = { DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, @@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = { }; static const unsigned int du1_sync_1_pins[] = { /* VSYNC, HSYNC, DISP */ - 61, 60, 63, + RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31), }; static const unsigned int du1_sync_1_mux[] = { DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, @@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = { }; static const unsigned int du1_oddf_pins[] = { /* ODDF */ - 62, + RCAR_GP_PIN(1, 30), }; static const unsigned int du1_oddf_mux[] = { DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK }; static const unsigned int du1_cde_pins[] = { /* CDE */ - 64, + RCAR_GP_PIN(2, 0), }; static const unsigned int du1_cde_mux[] = { DU1_CDE_MARK }; +/* - Ether ------------------------------------------------------------------ */ +static const unsigned int ether_rmii_pins[] = { + /* + * ETH_TXD0, ETH_TXD1, ETH_TX_EN, ETH_REFCLK, + * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER, + * ETH_MDIO, ETH_MDC + */ + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17), + RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28), +}; +static const unsigned int ether_rmii_mux[] = { + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, + ETH_MDIO_MARK, ETH_MDC_MARK, +}; +static const unsigned int ether_link_pins[] = { + /* ETH_LINK */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int ether_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int ether_magic_pins[] = { + /* ETH_MAGIC */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int ether_magic_mux[] = { + ETH_MAGIC_MARK, +}; /* - HSPI0 ------------------------------------------------------------------ */ static const unsigned int hspi0_pins[] = { /* CLK, CS, RX, TX */ - 150, 151, 153, 152, + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25), + RCAR_GP_PIN(4, 24), }; static const unsigned int hspi0_mux[] = { HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, @@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = { /* - HSPI1 ------------------------------------------------------------------ */ static const unsigned int hspi1_pins[] = { /* CLK, CS, RX, TX */ - 63, 58, 64, 62, + RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0), + RCAR_GP_PIN(1, 30), }; static const unsigned int hspi1_mux[] = { HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, }; static const unsigned int hspi1_b_pins[] = { /* CLK, CS, RX, TX */ - 90, 91, 93, 92, + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29), + RCAR_GP_PIN(2, 28), }; static const unsigned int hspi1_b_mux[] = { HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, }; static const unsigned int hspi1_c_pins[] = { /* CLK, CS, RX, TX */ - 141, 142, 144, 143, + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 15), }; static const unsigned int hspi1_c_mux[] = { HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, }; static const unsigned int hspi1_d_pins[] = { /* CLK, CS, RX, TX */ - 101, 102, 104, 103, + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 7), }; static const unsigned int hspi1_d_mux[] = { HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, @@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = { /* - HSPI2 ------------------------------------------------------------------ */ static const unsigned int hspi2_pins[] = { /* CLK, CS, RX, TX */ - 9, 10, 11, 14, + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 14), }; static const unsigned int hspi2_mux[] = { HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, }; static const unsigned int hspi2_b_pins[] = { /* CLK, CS, RX, TX */ - 7, 13, 8, 6, + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(0, 6), }; static const unsigned int hspi2_b_mux[] = { HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, @@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = { /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ - 78, + RCAR_GP_PIN(2, 14), }; static const unsigned int intc_irq0_mux[] = { IRQ0_MARK, }; static const unsigned int intc_irq0_b_pins[] = { /* IRQ */ - 141, + RCAR_GP_PIN(4, 13), }; static const unsigned int intc_irq0_b_mux[] = { IRQ0_B_MARK, }; static const unsigned int intc_irq1_pins[] = { /* IRQ */ - 79, + RCAR_GP_PIN(2, 15), }; static const unsigned int intc_irq1_mux[] = { IRQ1_MARK, }; static const unsigned int intc_irq1_b_pins[] = { /* IRQ */ - 142, + RCAR_GP_PIN(4, 14), }; static const unsigned int intc_irq1_b_mux[] = { IRQ1_B_MARK, }; static const unsigned int intc_irq2_pins[] = { /* IRQ */ - 88, + RCAR_GP_PIN(2, 24), }; static const unsigned int intc_irq2_mux[] = { IRQ2_MARK, }; static const unsigned int intc_irq2_b_pins[] = { /* IRQ */ - 143, + RCAR_GP_PIN(4, 15), }; static const unsigned int intc_irq2_b_mux[] = { IRQ2_B_MARK, }; static const unsigned int intc_irq3_pins[] = { /* IRQ */ - 89, + RCAR_GP_PIN(2, 25), }; static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; static const unsigned int intc_irq3_b_pins[] = { /* IRQ */ - 144, + RCAR_GP_PIN(4, 16), }; static const unsigned int intc_irq3_b_mux[] = { IRQ3_B_MARK, @@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = { /* - LSBC ------------------------------------------------------------------- */ static const unsigned int lbsc_cs0_pins[] = { /* CS */ - 13, + RCAR_GP_PIN(0, 13), }; static const unsigned int lbsc_cs0_mux[] = { CS0_MARK, }; static const unsigned int lbsc_cs1_pins[] = { /* CS */ - 14, + RCAR_GP_PIN(0, 14), }; static const unsigned int lbsc_cs1_mux[] = { CS1_A26_MARK, }; static const unsigned int lbsc_ex_cs0_pins[] = { /* CS */ - 15, + RCAR_GP_PIN(0, 15), }; static const unsigned int lbsc_ex_cs0_mux[] = { EX_CS0_MARK, }; static const unsigned int lbsc_ex_cs1_pins[] = { /* CS */ - 16, + RCAR_GP_PIN(0, 16), }; static const unsigned int lbsc_ex_cs1_mux[] = { EX_CS1_MARK, }; static const unsigned int lbsc_ex_cs2_pins[] = { /* CS */ - 17, + RCAR_GP_PIN(0, 17), }; static const unsigned int lbsc_ex_cs2_mux[] = { EX_CS2_MARK, }; static const unsigned int lbsc_ex_cs3_pins[] = { /* CS */ - 18, + RCAR_GP_PIN(0, 18), }; static const unsigned int lbsc_ex_cs3_mux[] = { EX_CS3_MARK, }; static const unsigned int lbsc_ex_cs4_pins[] = { /* CS */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int lbsc_ex_cs4_mux[] = { EX_CS4_MARK, }; static const unsigned int lbsc_ex_cs5_pins[] = { /* CS */ - 20, + RCAR_GP_PIN(0, 20), }; static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_MARK, @@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = { /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc0_data1_pins[] = { /* D[0] */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int mmc0_data1_mux[] = { MMC0_D0_MARK, }; static const unsigned int mmc0_data4_pins[] = { /* D[0:3] */ - 19, 20, 21, 2, + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), }; static const unsigned int mmc0_data4_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, }; static const unsigned int mmc0_data8_pins[] = { /* D[0:7] */ - 19, 20, 21, 2, 10, 11, 15, 16, + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), }; static const unsigned int mmc0_data8_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, @@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = { }; static const unsigned int mmc0_ctrl_pins[] = { /* CMD, CLK */ - 18, 17, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), }; static const unsigned int mmc0_ctrl_mux[] = { MMC0_CMD_MARK, MMC0_CLK_MARK, }; static const unsigned int mmc1_data1_pins[] = { /* D[0] */ - 72, + RCAR_GP_PIN(2, 8), }; static const unsigned int mmc1_data1_mux[] = { MMC1_D0_MARK, }; static const unsigned int mmc1_data4_pins[] = { /* D[0:3] */ - 72, 73, 74, 75, + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), }; static const unsigned int mmc1_data4_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, }; static const unsigned int mmc1_data8_pins[] = { /* D[0:7] */ - 72, 73, 74, 75, 76, 77, 80, 81, + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), }; static const unsigned int mmc1_data8_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, @@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = { }; static const unsigned int mmc1_ctrl_pins[] = { /* CMD, CLK */ - 68, 65, + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1), }; static const unsigned int mmc1_ctrl_mux[] = { MMC1_CMD_MARK, MMC1_CLK_MARK, @@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = { /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RXD, TXD */ - 153, 152, + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), }; static const unsigned int scif0_data_mux[] = { RX0_MARK, TX0_MARK, }; static const unsigned int scif0_clk_pins[] = { /* SCK */ - 156, + RCAR_GP_PIN(4, 28), }; static const unsigned int scif0_clk_mux[] = { SCK0_MARK, }; static const unsigned int scif0_ctrl_pins[] = { /* RTS, CTS */ - 151, 150, + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), }; static const unsigned int scif0_ctrl_mux[] = { RTS0_TANS_MARK, CTS0_MARK, }; static const unsigned int scif0_data_b_pins[] = { /* RXD, TXD */ - 20, 19, + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), }; static const unsigned int scif0_data_b_mux[] = { RX0_B_MARK, TX0_B_MARK, }; static const unsigned int scif0_clk_b_pins[] = { /* SCK */ - 33, + RCAR_GP_PIN(1, 1), }; static const unsigned int scif0_clk_b_mux[] = { SCK0_B_MARK, }; static const unsigned int scif0_ctrl_b_pins[] = { /* RTS, CTS */ - 18, 11, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), }; static const unsigned int scif0_ctrl_b_mux[] = { RTS0_B_TANS_B_MARK, CTS0_B_MARK, }; static const unsigned int scif0_data_c_pins[] = { /* RXD, TXD */ - 146, 147, + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), }; static const unsigned int scif0_data_c_mux[] = { RX0_C_MARK, TX0_C_MARK, }; static const unsigned int scif0_clk_c_pins[] = { /* SCK */ - 145, + RCAR_GP_PIN(4, 17), }; static const unsigned int scif0_clk_c_mux[] = { SCK0_C_MARK, }; static const unsigned int scif0_ctrl_c_pins[] = { /* RTS, CTS */ - 149, 148, + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), }; static const unsigned int scif0_ctrl_c_mux[] = { RTS0_C_TANS_C_MARK, CTS0_C_MARK, }; static const unsigned int scif0_data_d_pins[] = { /* RXD, TXD */ - 43, 42, + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), }; static const unsigned int scif0_data_d_mux[] = { RX0_D_MARK, TX0_D_MARK, }; static const unsigned int scif0_clk_d_pins[] = { /* SCK */ - 50, + RCAR_GP_PIN(1, 18), }; static const unsigned int scif0_clk_d_mux[] = { SCK0_D_MARK, }; static const unsigned int scif0_ctrl_d_pins[] = { /* RTS, CTS */ - 51, 35, + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3), }; static const unsigned int scif0_ctrl_d_mux[] = { RTS0_D_TANS_D_MARK, CTS0_D_MARK, @@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = { /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_pins[] = { /* RXD, TXD */ - 149, 148, + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), }; static const unsigned int scif1_data_mux[] = { RX1_MARK, TX1_MARK, }; static const unsigned int scif1_clk_pins[] = { /* SCK */ - 145, + RCAR_GP_PIN(4, 17), }; static const unsigned int scif1_clk_mux[] = { SCK1_MARK, }; static const unsigned int scif1_ctrl_pins[] = { /* RTS, CTS */ - 147, 146, + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), }; static const unsigned int scif1_ctrl_mux[] = { RTS1_TANS_MARK, CTS1_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RXD, TXD */ - 117, 114, + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18), }; static const unsigned int scif1_data_b_mux[] = { RX1_B_MARK, TX1_B_MARK, }; static const unsigned int scif1_clk_b_pins[] = { /* SCK */ - 113, + RCAR_GP_PIN(3, 17), }; static const unsigned int scif1_clk_b_mux[] = { SCK1_B_MARK, }; static const unsigned int scif1_ctrl_b_pins[] = { /* RTS, CTS */ - 115, 116, + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), }; static const unsigned int scif1_ctrl_b_mux[] = { RTS1_B_TANS_B_MARK, CTS1_B_MARK, }; static const unsigned int scif1_data_c_pins[] = { /* RXD, TXD */ - 67, 66, + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), }; static const unsigned int scif1_data_c_mux[] = { RX1_C_MARK, TX1_C_MARK, }; static const unsigned int scif1_clk_c_pins[] = { /* SCK */ - 86, + RCAR_GP_PIN(2, 22), }; static const unsigned int scif1_clk_c_mux[] = { SCK1_C_MARK, }; static const unsigned int scif1_ctrl_c_pins[] = { /* RTS, CTS */ - 69, 68, + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), }; static const unsigned int scif1_ctrl_c_mux[] = { RTS1_C_TANS_C_MARK, CTS1_C_MARK, @@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = { /* - SCIF2 ------------------------------------------------------------------ */ static const unsigned int scif2_data_pins[] = { /* RXD, TXD */ - 106, 105, + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9), }; static const unsigned int scif2_data_mux[] = { RX2_MARK, TX2_MARK, }; static const unsigned int scif2_clk_pins[] = { /* SCK */ - 107, + RCAR_GP_PIN(3, 11), }; static const unsigned int scif2_clk_mux[] = { SCK2_MARK, }; static const unsigned int scif2_data_b_pins[] = { /* RXD, TXD */ - 120, 119, + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23), }; static const unsigned int scif2_data_b_mux[] = { RX2_B_MARK, TX2_B_MARK, }; static const unsigned int scif2_clk_b_pins[] = { /* SCK */ - 118, + RCAR_GP_PIN(3, 22), }; static const unsigned int scif2_clk_b_mux[] = { SCK2_B_MARK, }; static const unsigned int scif2_data_c_pins[] = { /* RXD, TXD */ - 33, 31, + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31), }; static const unsigned int scif2_data_c_mux[] = { RX2_C_MARK, TX2_C_MARK, }; static const unsigned int scif2_clk_c_pins[] = { /* SCK */ - 32, + RCAR_GP_PIN(1, 0), }; static const unsigned int scif2_clk_c_mux[] = { SCK2_C_MARK, }; static const unsigned int scif2_data_d_pins[] = { /* RXD, TXD */ - 64, 62, + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), }; static const unsigned int scif2_data_d_mux[] = { RX2_D_MARK, TX2_D_MARK, }; static const unsigned int scif2_clk_d_pins[] = { /* SCK */ - 63, + RCAR_GP_PIN(1, 31), }; static const unsigned int scif2_clk_d_mux[] = { SCK2_D_MARK, }; static const unsigned int scif2_data_e_pins[] = { /* RXD, TXD */ - 20, 19, + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), }; static const unsigned int scif2_data_e_mux[] = { RX2_E_MARK, TX2_E_MARK, @@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = { /* - SCIF3 ------------------------------------------------------------------ */ static const unsigned int scif3_data_pins[] = { /* RXD, TXD */ - 137, 136, + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), }; static const unsigned int scif3_data_mux[] = { RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, }; static const unsigned int scif3_clk_pins[] = { /* SCK */ - 135, + RCAR_GP_PIN(4, 7), }; static const unsigned int scif3_clk_mux[] = { SCK3_MARK, @@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = { static const unsigned int scif3_data_b_pins[] = { /* RXD, TXD */ - 64, 62, + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30), }; static const unsigned int scif3_data_b_mux[] = { RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, }; static const unsigned int scif3_data_c_pins[] = { /* RXD, TXD */ - 15, 12, + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12), }; static const unsigned int scif3_data_c_mux[] = { RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, }; static const unsigned int scif3_data_d_pins[] = { /* RXD, TXD */ - 30, 29, + RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29), }; static const unsigned int scif3_data_d_mux[] = { RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, }; static const unsigned int scif3_data_e_pins[] = { /* RXD, TXD */ - 35, 34, + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), }; static const unsigned int scif3_data_e_mux[] = { RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, }; static const unsigned int scif3_clk_e_pins[] = { /* SCK */ - 42, + RCAR_GP_PIN(1, 10), }; static const unsigned int scif3_clk_e_mux[] = { SCK3_E_MARK, @@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = { /* - SCIF4 ------------------------------------------------------------------ */ static const unsigned int scif4_data_pins[] = { /* RXD, TXD */ - 123, 122, + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26), }; static const unsigned int scif4_data_mux[] = { RX4_MARK, TX4_MARK, }; static const unsigned int scif4_clk_pins[] = { /* SCK */ - 121, + RCAR_GP_PIN(3, 25), }; static const unsigned int scif4_clk_mux[] = { SCK4_MARK, }; static const unsigned int scif4_data_b_pins[] = { /* RXD, TXD */ - 111, 110, + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), }; static const unsigned int scif4_data_b_mux[] = { RX4_B_MARK, TX4_B_MARK, }; static const unsigned int scif4_clk_b_pins[] = { /* SCK */ - 112, + RCAR_GP_PIN(3, 16), }; static const unsigned int scif4_clk_b_mux[] = { SCK4_B_MARK, }; static const unsigned int scif4_data_c_pins[] = { /* RXD, TXD */ - 22, 21, + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21), }; static const unsigned int scif4_data_c_mux[] = { RX4_C_MARK, TX4_C_MARK, }; static const unsigned int scif4_data_d_pins[] = { /* RXD, TXD */ - 69, 68, + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), }; static const unsigned int scif4_data_d_mux[] = { RX4_D_MARK, TX4_D_MARK, @@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = { /* - SCIF5 ------------------------------------------------------------------ */ static const unsigned int scif5_data_pins[] = { /* RXD, TXD */ - 51, 50, + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), }; static const unsigned int scif5_data_mux[] = { RX5_MARK, TX5_MARK, }; static const unsigned int scif5_clk_pins[] = { /* SCK */ - 43, + RCAR_GP_PIN(1, 11), }; static const unsigned int scif5_clk_mux[] = { SCK5_MARK, }; static const unsigned int scif5_data_b_pins[] = { /* RXD, TXD */ - 18, 11, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11), }; static const unsigned int scif5_data_b_mux[] = { RX5_B_MARK, TX5_B_MARK, }; static const unsigned int scif5_clk_b_pins[] = { /* SCK */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int scif5_clk_b_mux[] = { SCK5_B_MARK, }; static const unsigned int scif5_data_c_pins[] = { /* RXD, TXD */ - 24, 23, + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), }; static const unsigned int scif5_data_c_mux[] = { RX5_C_MARK, TX5_C_MARK, }; static const unsigned int scif5_clk_c_pins[] = { /* SCK */ - 28, + RCAR_GP_PIN(0, 28), }; static const unsigned int scif5_clk_c_mux[] = { SCK5_C_MARK, }; static const unsigned int scif5_data_d_pins[] = { /* RXD, TXD */ - 8, 6, + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), }; static const unsigned int scif5_data_d_mux[] = { RX5_D_MARK, TX5_D_MARK, }; static const unsigned int scif5_clk_d_pins[] = { /* SCK */ - 7, + RCAR_GP_PIN(0, 7), }; static const unsigned int scif5_clk_d_mux[] = { SCK5_D_MARK, @@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = { /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ - 117, + RCAR_GP_PIN(3, 21), }; static const unsigned int sdhi0_data1_mux[] = { SD0_DAT0_MARK, }; static const unsigned int sdhi0_data4_pins[] = { /* D[0:3] */ - 117, 118, 119, 120, + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 24), }; static const unsigned int sdhi0_data4_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { /* CMD, CLK */ - 114, 113, + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17), }; static const unsigned int sdhi0_ctrl_mux[] = { SD0_CMD_MARK, SD0_CLK_MARK, }; static const unsigned int sdhi0_cd_pins[] = { /* CD */ - 115, + RCAR_GP_PIN(3, 19), }; static const unsigned int sdhi0_cd_mux[] = { SD0_CD_MARK, }; static const unsigned int sdhi0_wp_pins[] = { /* WP */ - 116, + RCAR_GP_PIN(3, 20), }; static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, @@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = { /* - SDHI1 ------------------------------------------------------------------ */ static const unsigned int sdhi1_data1_pins[] = { /* D0 */ - 19, + RCAR_GP_PIN(0, 19), }; static const unsigned int sdhi1_data1_mux[] = { SD1_DAT0_MARK, }; static const unsigned int sdhi1_data4_pins[] = { /* D[0:3] */ - 19, 20, 21, 2, + RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), + RCAR_GP_PIN(0, 2), }; static const unsigned int sdhi1_data4_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { /* CMD, CLK */ - 18, 17, + RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17), }; static const unsigned int sdhi1_ctrl_mux[] = { SD1_CMD_MARK, SD1_CLK_MARK, }; static const unsigned int sdhi1_cd_pins[] = { /* CD */ - 10, + RCAR_GP_PIN(0, 10), }; static const unsigned int sdhi1_cd_mux[] = { SD1_CD_MARK, }; static const unsigned int sdhi1_wp_pins[] = { /* WP */ - 11, + RCAR_GP_PIN(0, 11), }; static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, @@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = { /* - SDHI2 ------------------------------------------------------------------ */ static const unsigned int sdhi2_data1_pins[] = { /* D0 */ - 97, + RCAR_GP_PIN(3, 1), }; static const unsigned int sdhi2_data1_mux[] = { SD2_DAT0_MARK, }; static const unsigned int sdhi2_data4_pins[] = { /* D[0:3] */ - 97, 98, 99, 100, + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), }; static const unsigned int sdhi2_data4_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { /* CMD, CLK */ - 102, 101, + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5), }; static const unsigned int sdhi2_ctrl_mux[] = { SD2_CMD_MARK, SD2_CLK_MARK, }; static const unsigned int sdhi2_cd_pins[] = { /* CD */ - 103, + RCAR_GP_PIN(3, 7), }; static const unsigned int sdhi2_cd_mux[] = { SD2_CD_MARK, }; static const unsigned int sdhi2_wp_pins[] = { /* WP */ - 104, + RCAR_GP_PIN(3, 8), }; static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, @@ -2322,35 +2388,36 @@ static const unsigned int sdhi2_wp_mux[] = { /* - SDHI3 ------------------------------------------------------------------ */ static const unsigned int sdhi3_data1_pins[] = { /* D0 */ - 50, + RCAR_GP_PIN(1, 18), }; static const unsigned int sdhi3_data1_mux[] = { SD3_DAT0_MARK, }; static const unsigned int sdhi3_data4_pins[] = { /* D[0:3] */ - 50, 51, 52, 53, + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 21), }; static const unsigned int sdhi3_data4_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { /* CMD, CLK */ - 35, 34, + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), }; static const unsigned int sdhi3_ctrl_mux[] = { SD3_CMD_MARK, SD3_CLK_MARK, }; static const unsigned int sdhi3_cd_pins[] = { /* CD */ - 62, + RCAR_GP_PIN(1, 30), }; static const unsigned int sdhi3_cd_mux[] = { SD3_CD_MARK, }; static const unsigned int sdhi3_wp_pins[] = { /* WP */ - 64, + RCAR_GP_PIN(2, 0), }; static const unsigned int sdhi3_wp_mux[] = { SD3_WP_MARK, @@ -2358,14 +2425,14 @@ static const unsigned int sdhi3_wp_mux[] = { /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PENC */ - 154, + RCAR_GP_PIN(4, 26), }; static const unsigned int usb0_mux[] = { USB_PENC0_MARK, }; static const unsigned int usb0_ovc_pins[] = { /* USB_OVC */ - 150 + RCAR_GP_PIN(4, 22), }; static const unsigned int usb0_ovc_mux[] = { USB_OVC0_MARK, @@ -2373,14 +2440,14 @@ static const unsigned int usb0_ovc_mux[] = { /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { /* PENC */ - 155, + RCAR_GP_PIN(4, 27), }; static const unsigned int usb1_mux[] = { USB_PENC1_MARK, }; static const unsigned int usb1_ovc_pins[] = { /* USB_OVC */ - 152, + RCAR_GP_PIN(4, 24), }; static const unsigned int usb1_ovc_mux[] = { USB_OVC1_MARK, @@ -2388,18 +2455,122 @@ static const unsigned int usb1_ovc_mux[] = { /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PENC */ - 156, + RCAR_GP_PIN(4, 28), }; static const unsigned int usb2_mux[] = { USB_PENC2_MARK, }; static const unsigned int usb2_ovc_pins[] = { /* USB_OVC */ - 125, + RCAR_GP_PIN(3, 29), }; static const unsigned int usb2_ovc_mux[] = { USB_OVC2_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const unsigned int vin0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), +}; +static const unsigned int vin0_data8_mux[] = { + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, + VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_MARK, VI0_VSYNC_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const unsigned int vin1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), +}; +static const unsigned int vin1_data8_mux[] = { + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, + VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_MARK, VI1_VSYNC_MARK, +}; +/* - VIN2 ------------------------------------------------------------------- */ +static const unsigned int vin2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0), +}; +static const unsigned int vin2_data8_mux[] = { + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, + VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, +}; +static const unsigned int vin2_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 30), +}; +static const unsigned int vin2_clk_mux[] = { + VI2_CLK_MARK, +}; +static const unsigned int vin2_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), +}; +static const unsigned int vin2_sync_mux[] = { + VI2_HSYNC_MARK, VI2_VSYNC_MARK, +}; +/* - VIN3 ------------------------------------------------------------------- */ +static const unsigned int vin3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), +}; +static const unsigned int vin3_data8_mux[] = { + VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK, + VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK, + VI3_DATA6_MARK, VI3_DATA7_MARK, +}; +static const unsigned int vin3_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int vin3_clk_mux[] = { + VI3_CLK_MARK, +}; +static const unsigned int vin3_sync_pins[] = { + /* HSYNC, VSYNC */ + RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29), +}; +static const unsigned int vin3_sync_mux[] = { + VI3_HSYNC_MARK, VI3_VSYNC_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du0_rgb666), @@ -2419,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du1_sync_1), SH_PFC_PIN_GROUP(du1_oddf), SH_PFC_PIN_GROUP(du1_cde), + SH_PFC_PIN_GROUP(ether_rmii), + SH_PFC_PIN_GROUP(ether_link), + SH_PFC_PIN_GROUP(ether_magic), SH_PFC_PIN_GROUP(hspi0), SH_PFC_PIN_GROUP(hspi1), SH_PFC_PIN_GROUP(hspi1_b), @@ -2527,6 +2701,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb1_ovc), SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ovc), + SH_PFC_PIN_GROUP(vin0_data8), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_clk), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_clk), + SH_PFC_PIN_GROUP(vin3_sync), }; static const char * const du0_groups[] = { @@ -2552,6 +2738,12 @@ static const char * const du1_groups[] = { "du1_cde", }; +static const char * const ether_groups[] = { + "ether_rmii", + "ether_link", + "ether_magic", +}; + static const char * const hspi0_groups[] = { "hspi0", }; @@ -2720,9 +2912,34 @@ static const char * const usb2_groups[] = { "usb2_ovc", }; +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_clk", + "vin0_sync", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_clk", + "vin1_sync", +}; + +static const char * const vin2_groups[] = { + "vin2_data8", + "vin2_clk", + "vin2_sync", +}; + +static const char * const vin3_groups[] = { + "vin3_data8", + "vin3_clk", + "vin3_sync", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(ether), SH_PFC_FUNCTION(hspi0), SH_PFC_FUNCTION(hspi1), SH_PFC_FUNCTION(hspi2), @@ -2743,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -3547,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF [2] */ FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3, /* SEL_CANCLK [2] */ - FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0, /* SEL_CAN0 [1] */ FN_SEL_CAN0_0, FN_SEL_CAN0_1, /* SEL_HSCIF1 [1] */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c new file mode 100644 index 000000000000..85d77a417c0e --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -0,0 +1,3835 @@ +/* + * R8A7790 processor support + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <linux/kernel.h> +#include <linux/platform_data/gpio-rcar.h> + +#include "core.h" +#include "sh_pfc.h" + +#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) + +#define PORT_GP_32(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ + PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) + +#define PORT_GP_32_REV(bank, fn, sfx) \ + PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ + PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ + PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ + PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ + PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ + PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ + PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ + PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ + PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ + PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ + PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ + PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ + PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ + PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ + PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ + PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_32(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_32(3, fn, sfx), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_32(5, fn, sfx) + +#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx + +#define _GP_GPIO(bank, pin, _name, sfx) \ + [(bank * 32) + pin] = { \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + } + +#define _GP_DATA(bank, pin, name, sfx) \ + PINMUX_DATA(name##_DATA, name##_FN) + +#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, + FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, + FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, + FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, + FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, + FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, + FN_IP3_14_12, FN_IP3_17_15, + + /* GPSR1 */ + FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, + FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, + FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, + FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, + FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, + FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, + + /* GPSR2 */ + FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, + FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, + FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, + FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, + FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, + FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, + + /* GPSR3 */ + FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, + FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, + FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, + FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, + FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, + FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, + FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, + + /* GPSR4 */ + FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, + FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, + FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, + FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, + FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, + FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, + FN_IP14_15_12, FN_IP14_18_16, + + /* GPSR5 */ + FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, + FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, + FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, + FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, + FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, + FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, + FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, + + /* IPSR0 */ + FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, + FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, + FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, + FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, + FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, + FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, + FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, + FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + + /* IPSR1 */ + FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, + FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, + FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, + FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, + FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, + FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, + FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, + FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, + FN_A0, FN_PWM3, FN_A1, FN_PWM4, + + /* IPSR2 */ + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, + FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, + FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, + FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, + FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B, + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, + FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B, + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, + + /* IPSR3 */ + FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, + FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, + FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, + FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, + FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, + FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, + FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, + FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, + FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, + FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, + FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, + FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, + FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, + + /* IPSR4 */ + FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, + FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, + FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, + FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, + FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, + FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, + FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, + FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, + FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, + FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, + FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, + FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, + FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, + FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, + FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, + + /* IPSR5 */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, + FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, + FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX, + FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, + FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, + FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B, + FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, + FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, + FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, + FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, + FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, + FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, + FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, + FN_SSI_WS78_B, + + /* IPSR6 */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, + FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, + FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, + FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, + FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + + /* IPSR8 */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, + FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, + FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, + FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, + FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, + FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, + FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, + FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, + FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, + FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, + FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, + FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, + FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, + FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, + + /* IPSR9 */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, + FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, + FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, + FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, + FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, + FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, + FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, + FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, + FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, + FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, + FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, + FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, + FN_VI3_CLK_B, + + /* IPSR10 */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, + FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, + FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, + FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, + FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, + + /* IPSR11 */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, + FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, + FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, + FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, + FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, + FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, + FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, + FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, + + /* IPSR12 */ + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, + FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, + FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, + FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, + FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, + FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, + FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, + FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, + FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, + FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, + FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, + FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, + FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, + FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, + FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, + FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, + FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, + FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, + FN_CAN_DEBUGOUT4, + + /* IPSR13 */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, + FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, + FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6, + FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, + FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, + FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, + FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, + FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, + FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, + FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, + FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B, + FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8, + FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, + FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, + FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, + FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, + + /* IPSR14 */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, + FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C, + FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, + FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, + FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, + FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, + FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, + FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, + + /* IPSR15 */ + FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, + FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS, + FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17, + FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0, + FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, + FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, + FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, + FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, + FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, + FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, + FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0, + FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, + FN_DU2_DG6, FN_LCDOUT14, + + /* IPSR16 */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, + FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, + FN_TCLK1_B, + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFB1_4, + FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, + FN_SEL_VI3_0, FN_SEL_VI3_1, + FN_SEL_VI2_0, FN_SEL_VI2_1, + FN_SEL_VI1_0, FN_SEL_VI1_1, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_LBS_0, FN_SEL_LBS_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + VI1_DATA7_VI1_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, + USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, + DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, + + D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, + D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, + VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, + VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, + VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, + SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, + VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, + SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, + VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, + SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, + SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, + VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, + D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + + D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, + VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, + SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, + VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, + SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, + VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, + D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, + VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, + D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, + VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, + SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, + VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, + D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, + VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, + A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, + + A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, + PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, + TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, + A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, + SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, + A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, + VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, + A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, + VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, + A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, + VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, + + A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, + VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, + A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, + VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, + A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, + MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, + VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, + ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, + ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, + A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, + AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, + ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, + VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, + + A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, + A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, + VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, + VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, + VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, + VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, + VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, + VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, + CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, + VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, + VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, + MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, + HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, + VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, + VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, + + EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, + VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, + EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, + VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, + INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, + MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, + VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, + SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, + CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, + CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, + VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, + INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, + WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, + VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, + MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, + VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, + SSI_WS78_B_MARK, + + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, + DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, + SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, + INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, + SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, + SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, + RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, + ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + + ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, + RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, + ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, + ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, + MII_RXD2_MARK, + + VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, + MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, + AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, + AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, + AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, + AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, + MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, + MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, + MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, + AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, + SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, + VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, + MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, + AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, + AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, + AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, + SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, + SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + + SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, + SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, + SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, + GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, + SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, + MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, + GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, + SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, + AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, + AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, + SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, + SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, + MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, + AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, + SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, + SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, + TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, + SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, + VI3_CLK_B_MARK, + + SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, + GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, + SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, + VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, + VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, + VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, + TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, + SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, + VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, + TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, + SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, + VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, + TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, + SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, + VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, + GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, + MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, + HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, + VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, + TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, + VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, + GLO_I0_B_MARK, VI3_DATA6_B_MARK, + + SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, + GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, + TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, + SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, + MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, + SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, + MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, + SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, + VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, + MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, + RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, + RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, + SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, + RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, + + SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, + SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, + SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, + SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, + SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, + MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, + STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, + CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, + SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, + SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, + MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, + SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, + MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, + SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, + CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, + IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, + CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, + IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, + CAN_DEBUGOUT4_MARK, + + SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, + LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, + SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, + DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, + BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, + SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, + LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, + FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, + CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, + SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, + CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, + SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, + LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, + STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, + TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, + BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, + FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, + STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, + CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, + STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, + SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, + SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, + + AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, + DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, + REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, + MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, + SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, + DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, + TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, + HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, + LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, + SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, + MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, + SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, + DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, + LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, + CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, + SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, + MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, + HRTS0_N_C_MARK, + + SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, + LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, + DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, + SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, + SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, + DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, + DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, + LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, + LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, + LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, + DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, + SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, + SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, + DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, + DU2_DG6_MARK, LCDOUT14_MARK, + + MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, + DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, + MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, + ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, + USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, + TCLK1_B_MARK, + PINMUX_MARK_END, +}; + +static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), + PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), + PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), + PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), + + PINMUX_IPSR_DATA(IP0_2_0, D0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_5_3, D1), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_8_6, D2), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_11_9, D3), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), + PINMUX_IPSR_DATA(IP0_15_12, D4), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_19_16, D5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP0_22_20, D6), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_26_23, D7), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2), + PINMUX_IPSR_DATA(IP0_30_27, D8), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), + PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), + + PINMUX_IPSR_DATA(IP1_3_0, D9), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), + PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_7_4, D10), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), + PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_11_8, D11), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), + PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_14_12, D12), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), + PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_17_15, D13), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_21_18, D14), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_25_22, D15), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), + PINMUX_IPSR_DATA(IP1_27_26, A0), + PINMUX_IPSR_DATA(IP1_27_26, PWM3), + PINMUX_IPSR_DATA(IP1_29_28, A1), + PINMUX_IPSR_DATA(IP1_29_28, PWM4), + + PINMUX_IPSR_DATA(IP2_2_0, A2), + PINMUX_IPSR_DATA(IP2_2_0, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_5_3, A3), + PINMUX_IPSR_DATA(IP2_5_3, PWM6), + PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_8_6, A4), + PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), + PINMUX_IPSR_DATA(IP2_11_9, A5), + PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), + PINMUX_IPSR_DATA(IP2_14_12, A6), + PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), + PINMUX_IPSR_DATA(IP2_17_15, A7), + PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), + PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), + PINMUX_IPSR_DATA(IP2_21_18, A8), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_25_22, A9), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP2_28_26, A10), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), + + PINMUX_IPSR_DATA(IP3_3_0, A11), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), + PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B), + PINMUX_IPSR_DATA(IP3_7_4, A12), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), + PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B), + PINMUX_IPSR_DATA(IP3_11_8, A13), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), + PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), + PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0), + PINMUX_IPSR_DATA(IP3_14_12, A14), + PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), + PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), + PINMUX_IPSR_DATA(IP3_17_15, A15), + PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), + PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), + PINMUX_IPSR_DATA(IP3_19_18, A16), + PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), + PINMUX_IPSR_DATA(IP3_22_20, A17), + PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), + PINMUX_IPSR_DATA(IP3_25_23, A18), + PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), + PINMUX_IPSR_DATA(IP3_28_26, A19), + PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), + PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), + PINMUX_IPSR_DATA(IP3_31_29, A20), + PINMUX_IPSR_DATA(IP3_31_29, SPCLK), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), + + PINMUX_IPSR_DATA(IP4_2_0, A21), + PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), + PINMUX_IPSR_DATA(IP4_5_3, A22), + PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), + PINMUX_IPSR_DATA(IP4_8_6, A23), + PINMUX_IPSR_DATA(IP4_8_6, IO2), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), + PINMUX_IPSR_DATA(IP4_11_9, A24), + PINMUX_IPSR_DATA(IP4_11_9, IO3), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_14_12, A25), + PINMUX_IPSR_DATA(IP4_14_12, SSL), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_17_15, CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), + PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), + PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), + PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), + PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), + PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), + + PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), + PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), + PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0), + PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), + PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0), + PINMUX_IPSR_DATA(IP5_12_10, BS_N), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP5_12_10, DRACK0), + PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP5_14_13, RD_N), + PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), + PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), + PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), + PINMUX_IPSR_DATA(IP5_20_18, WE0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP5_23_21, WE1_N), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0), + PINMUX_IPSR_DATA(IP5_26_24, IRQ3), + PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), + + PINMUX_IPSR_DATA(IP6_2_0, DACK0), + PINMUX_IPSR_DATA(IP6_2_0, IRQ0), + PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP6_8_6, DACK1), + PINMUX_IPSR_DATA(IP6_8_6, IRQ1), + PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_13_11, DACK2), + PINMUX_IPSR_DATA(IP6_13_11, IRQ2), + PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), + PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), + PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), + PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), + PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), + PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), + PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_18_16, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), + PINMUX_IPSR_DATA(IP7_24_22, PWM2), + PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), + PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), + PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + + PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), + PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), + PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), + PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), + PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), + PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), + PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), + PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), + PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), + PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), + PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), + PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), + PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), + PINMUX_IPSR_DATA(IP8_28, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), + + PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), + PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), + PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), + PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), + PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), + PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), + PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), + PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), + PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), + PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), + PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), + PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), + PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), + PINMUX_IPSR_DATA(IP9_25_24, MII_COL), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), + PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), + PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), + PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), + PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), + PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), + PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), + PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), + PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), + PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), + PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), + PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), + PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP11_4, SD3_CLK), + PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), + PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MTS_N), + PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), + PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), + PINMUX_IPSR_DATA(IP11_8_7, STM_N), + PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), + PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), + PINMUX_IPSR_DATA(IP11_10_9, MDATA), + PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), + PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), + PINMUX_IPSR_DATA(IP11_12_11, SDATA), + PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), + PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), + PINMUX_IPSR_DATA(IP11_14_13, SCKZ), + PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), + PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP11_17_15, VSP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), + PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), + PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), + PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP11_31_30, MOUT0), + + PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP12_1_0, MOUT1), + PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP12_3_2, MOUT2), + PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), + PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_DATA(IP12_5_4, MOUT5), + PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), + PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_DATA(IP12_7_6, MOUT6), + PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), + PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), + PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), + PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), + PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), + PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), + PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), + PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), + PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), + PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), + PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), + PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), + PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), + PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), + PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), + + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), + PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), + PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), + PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), + PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), + PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), + PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), + PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), + PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), + PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), + PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), + PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), + PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), + PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), + PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), + PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), + PINMUX_IPSR_DATA(IP13_22_19, TCLK2), + PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), + PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), + PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), + PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), + PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), + PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), + PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), + + PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), + PINMUX_IPSR_DATA(IP14_2_0, REMOCON), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_5_3, SCK0), + PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), + PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), + PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), + PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), + PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), + PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), + PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS), + PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), + PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), + PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), + PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), + PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), + PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), + PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_27_25, QCLK), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), + PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), + PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), + + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), + PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), + PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), + PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), + PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), + PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), + PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0), + PINMUX_IPSR_DATA(IP15_11_9, HSCK0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), + PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0), + PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), + PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), + PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), + PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), + PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), + PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), + PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), + PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), + PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), + PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), + PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_22_20, ADICLK), + PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), + PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), + PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), + PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), + PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), + PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), + PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), + PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), + PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), + PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), + PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), + PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), + PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), + + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), + PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), + PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), + PINMUX_IPSR_DATA(IP16_2_0, QPOLA), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), + PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), + PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), + PINMUX_IPSR_DATA(IP16_5_3, QPOLB), + PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), + PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), + PINMUX_IPSR_DATA(IP16_7, USB1_OVC), + PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), +}; + +static struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - ETH -------------------------------------------------------------------- */ +static const unsigned int eth_link_pins[] = { + /* LINK */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int eth_link_mux[] = { + ETH_LINK_MARK, +}; +static const unsigned int eth_magic_pins[] = { + /* MAGIC */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int eth_magic_mux[] = { + ETH_MAGIC_MARK, +}; +static const unsigned int eth_mdio_pins[] = { + /* MDC, MDIO */ + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), +}; +static const unsigned int eth_mdio_mux[] = { + ETH_MDC_MARK, ETH_MDIO_MARK, +}; +static const unsigned int eth_rmii_pins[] = { + /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), +}; +static const unsigned int eth_rmii_mux[] = { + ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, + ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +static const unsigned int intc_irq0_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int intc_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_irq1_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int intc_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_irq2_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int intc_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_irq3_pins[] = { + /* IRQ */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int intc_irq3_mux[] = { + IRQ3_MARK, +}; +/* - SCIF0 ----------------------------------------------------------------- */ +static const unsigned int scif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_TANS_MARK, CTS0_N_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +/* - SCIF1 ----------------------------------------------------------------- */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scif1_data_c_mux[] = { + RX1_C_MARK, TX1_C_MARK, +}; +static const unsigned int scif1_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +}; +static const unsigned int scif1_data_d_mux[] = { + RX1_D_MARK, TX1_D_MARK, +}; +static const unsigned int scif1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scif1_clk_d_mux[] = { + SCK1_D_MARK, +}; +static const unsigned int scif1_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scif1_data_e_mux[] = { + RX1_E_MARK, TX1_E_MARK, +}; +static const unsigned int scif1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int scif1_clk_e_mux[] = { + SCK1_E_MARK, +}; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 27), +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, +}; +static const unsigned int scifa0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), +}; +static const unsigned int scifa0_data_b_mux[] = { + SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK +}; +static const unsigned int scifa0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int scifa0_clk_b_mux[] = { + SCIFA0_SCK_B_MARK, +}; +static const unsigned int scifa0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), +}; +static const unsigned int scifa0_ctrl_b_mux[] = { + SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, +}; +static const unsigned int scifa1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), +}; +static const unsigned int scifa1_data_b_mux[] = { + SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, +}; +static const unsigned int scifa1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int scifa1_clk_b_mux[] = { + SCIFA1_SCK_B_MARK, +}; +static const unsigned int scifa1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifa1_ctrl_b_mux[] = { + SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, +}; +static const unsigned int scifa1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scifa1_data_c_mux[] = { + SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, +}; +static const unsigned int scifa1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scifa1_clk_c_mux[] = { + SCIFA1_SCK_C_MARK, +}; +static const unsigned int scifa1_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scifa1_ctrl_c_mux[] = { + SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, +}; +static const unsigned int scifa1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int scifa1_data_d_mux[] = { + SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, +}; +static const unsigned int scifa1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int scifa1_clk_d_mux[] = { + SCIFA1_SCK_D_MARK, +}; +static const unsigned int scifa1_ctrl_d_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +}; +static const unsigned int scifa1_ctrl_d_mux[] = { + SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, +}; +static const unsigned int scifa2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), +}; +static const unsigned int scifa2_data_b_mux[] = { + SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, +}; +static const unsigned int scifa2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), +}; +static const unsigned int scifa2_data_c_mux[] = { + SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, +}; +static const unsigned int scifa2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 29), +}; +static const unsigned int scifa2_clk_c_mux[] = { + SCIFA2_SCK_C_MARK, +}; +/* - SCIFB0 ----------------------------------------------------------------- */ +static const unsigned int scifb0_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), +}; +static const unsigned int scifb0_data_mux[] = { + SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, +}; +static const unsigned int scifb0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 8), +}; +static const unsigned int scifb0_clk_mux[] = { + SCIFB0_SCK_MARK, +}; +static const unsigned int scifb0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), +}; +static const unsigned int scifb0_ctrl_mux[] = { + SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, +}; +static const unsigned int scifb0_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int scifb0_data_b_mux[] = { + SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, +}; +static const unsigned int scifb0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int scifb0_clk_b_mux[] = { + SCIFB0_SCK_B_MARK, +}; +static const unsigned int scifb0_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +}; +static const unsigned int scifb0_ctrl_b_mux[] = { + SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, +}; +static const unsigned int scifb0_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scifb0_data_c_mux[] = { + SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, +}; +/* - SCIFB1 ----------------------------------------------------------------- */ +static const unsigned int scifb1_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int scifb1_data_mux[] = { + SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, +}; +static const unsigned int scifb1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int scifb1_clk_mux[] = { + SCIFB1_SCK_MARK, +}; +static const unsigned int scifb1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), +}; +static const unsigned int scifb1_ctrl_mux[] = { + SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, +}; +static const unsigned int scifb1_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), +}; +static const unsigned int scifb1_data_b_mux[] = { + SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, +}; +static const unsigned int scifb1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int scifb1_clk_b_mux[] = { + SCIFB1_SCK_B_MARK, +}; +static const unsigned int scifb1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), +}; +static const unsigned int scifb1_ctrl_b_mux[] = { + SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, +}; +static const unsigned int scifb1_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int scifb1_data_c_mux[] = { + SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, +}; +static const unsigned int scifb1_data_d_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scifb1_data_d_mux[] = { + SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, +}; +static const unsigned int scifb1_data_e_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), +}; +static const unsigned int scifb1_data_e_mux[] = { + SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, +}; +static const unsigned int scifb1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int scifb1_clk_e_mux[] = { + SCIFB1_SCK_E_MARK, +}; +static const unsigned int scifb1_data_f_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int scifb1_data_f_mux[] = { + SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, +}; +static const unsigned int scifb1_data_g_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), +}; +static const unsigned int scifb1_data_g_mux[] = { + SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, +}; +static const unsigned int scifb1_clk_g_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int scifb1_clk_g_mux[] = { + SCIFB1_SCK_G_MARK, +}; +/* - SCIFB2 ----------------------------------------------------------------- */ +static const unsigned int scifb2_data_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scifb2_data_mux[] = { + SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, +}; +static const unsigned int scifb2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 21), +}; +static const unsigned int scifb2_clk_mux[] = { + SCIFB2_SCK_MARK, +}; +static const unsigned int scifb2_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), +}; +static const unsigned int scifb2_ctrl_mux[] = { + SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, +}; +static const unsigned int scifb2_data_b_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), +}; +static const unsigned int scifb2_data_b_mux[] = { + SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, +}; +static const unsigned int scifb2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 31), +}; +static const unsigned int scifb2_clk_b_mux[] = { + SCIFB2_SCK_B_MARK, +}; +static const unsigned int scifb2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), +}; +static const unsigned int scifb2_ctrl_b_mux[] = { + SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, +}; +static const unsigned int scifb2_data_c_pins[] = { + /* RXD, TXD */ + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), +}; +static const unsigned int scifb2_data_c_mux[] = { + SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, +}; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 22), +}; +static const unsigned int tpu0_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + RCAR_GP_PIN(0, 23), +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; + +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc0_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int mmc0_data1_mux[] = { + MMC0_D0_MARK, +}; +static const unsigned int mmc0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int mmc0_data4_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, +}; +static const unsigned int mmc0_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), + RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), + RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int mmc0_data8_mux[] = { + MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, + MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, +}; +static const unsigned int mmc0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +}; +static const unsigned int mmc0_ctrl_mux[] = { + MMC0_CLK_MARK, MMC0_CMD_MARK, +}; + +static const unsigned int mmc1_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int mmc1_data1_mux[] = { + MMC1_D0_MARK, +}; +static const unsigned int mmc1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +}; +static const unsigned int mmc1_data4_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, +}; +static const unsigned int mmc1_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), + RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), + RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +}; +static const unsigned int mmc1_data8_mux[] = { + MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, + MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, +}; +static const unsigned int mmc1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +}; +static const unsigned int mmc1_ctrl_mux[] = { + MMC1_CLK_MARK, MMC1_CMD_MARK, +}; + +/* - SDHI ------------------------------------------------------------------- */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; + +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; + +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 22), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 23), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; + +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 26), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 30), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 31), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), +}; + +static const char * const eth_groups[] = { + "eth_link", + "eth_magic", + "eth_mdio", + "eth_rmii", +}; + +static const char * const intc_groups[] = { + "intc_irq0", + "intc_irq1", + "intc_irq2", + "intc_irq3", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", + "scif0_data_b", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", + "scif1_data_c", + "scif1_data_d", + "scif1_clk_d", + "scif1_data_e", + "scif1_clk_e", +}; + +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", + "scifa0_data_b", + "scifa0_clk_b", + "scifa0_ctrl_b", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", + "scifa1_data_b", + "scifa1_clk_b", + "scifa1_ctrl_b", + "scifa1_data_c", + "scifa1_clk_c", + "scifa1_ctrl_c", + "scifa1_data_d", + "scifa1_clk_d", + "scifa1_ctrl_d", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_ctrl", + "scifa2_data_b", + "scifa2_data_c", + "scifa2_clk_c", +}; + +static const char * const scifb0_groups[] = { + "scifb0_data", + "scifb0_clk", + "scifb0_ctrl", + "scifb0_data_b", + "scifb0_clk_b", + "scifb0_ctrl_b", + "scifb0_data_c", +}; + +static const char * const scifb1_groups[] = { + "scifb1_data", + "scifb1_clk", + "scifb1_ctrl", + "scifb1_data_b", + "scifb1_clk_b", + "scifb1_ctrl_b", + "scifb1_data_c", + "scifb1_data_d", + "scifb1_data_e", + "scifb1_clk_e", + "scifb1_data_f", + "scifb1_data_g", + "scifb1_clk_g", +}; + +static const char * const scifb2_groups[] = { + "scifb2_data", + "scifb2_clk", + "scifb2_ctrl", + "scifb2_data_b", + "scifb2_clk_b", + "scifb2_ctrl_b", + "scifb2_data_c", +}; + +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2", + "tpu0_to3", +}; + +static const char * const mmc0_groups[] = { + "mmc0_data1", + "mmc0_data4", + "mmc0_data8", + "mmc0_ctrl", +}; + +static const char * const mmc1_groups[] = { + "mmc1_data1", + "mmc1_data4", + "mmc1_data8", + "mmc1_ctrl", +}; + +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, + GP_0_30_FN, FN_IP3_14_12, + GP_0_29_FN, FN_IP3_11_8, + GP_0_28_FN, FN_IP3_7_4, + GP_0_27_FN, FN_IP3_3_0, + GP_0_26_FN, FN_IP2_28_26, + GP_0_25_FN, FN_IP2_25_22, + GP_0_24_FN, FN_IP2_21_18, + GP_0_23_FN, FN_IP2_17_15, + GP_0_22_FN, FN_IP2_14_12, + GP_0_21_FN, FN_IP2_11_9, + GP_0_20_FN, FN_IP2_8_6, + GP_0_19_FN, FN_IP2_5_3, + GP_0_18_FN, FN_IP2_2_0, + GP_0_17_FN, FN_IP1_29_28, + GP_0_16_FN, FN_IP1_27_26, + GP_0_15_FN, FN_IP1_25_22, + GP_0_14_FN, FN_IP1_21_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_12, + GP_0_11_FN, FN_IP1_11_8, + GP_0_10_FN, FN_IP1_7_4, + GP_0_9_FN, FN_IP1_3_0, + GP_0_8_FN, FN_IP0_30_27, + GP_0_7_FN, FN_IP0_26_23, + GP_0_6_FN, FN_IP0_22_20, + GP_0_5_FN, FN_IP0_19_16, + GP_0_4_FN, FN_IP0_15_12, + GP_0_3_FN, FN_IP0_11_9, + GP_0_2_FN, FN_IP0_8_6, + GP_0_1_FN, FN_IP0_5_3, + GP_0_0_FN, FN_IP0_2_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_FN, FN_IP6_13_11, + GP_1_28_FN, FN_IP6_10_9, + GP_1_27_FN, FN_IP6_8_6, + GP_1_26_FN, FN_IP6_5_3, + GP_1_25_FN, FN_IP6_2_0, + GP_1_24_FN, FN_IP5_29_27, + GP_1_23_FN, FN_IP5_26_24, + GP_1_22_FN, FN_IP5_23_21, + GP_1_21_FN, FN_IP5_20_18, + GP_1_20_FN, FN_IP5_17_15, + GP_1_19_FN, FN_IP5_14_13, + GP_1_18_FN, FN_IP5_12_10, + GP_1_17_FN, FN_IP5_9_6, + GP_1_16_FN, FN_IP5_5_3, + GP_1_15_FN, FN_IP5_2_0, + GP_1_14_FN, FN_IP4_29_27, + GP_1_13_FN, FN_IP4_26_24, + GP_1_12_FN, FN_IP4_23_21, + GP_1_11_FN, FN_IP4_20_18, + GP_1_10_FN, FN_IP4_17_15, + GP_1_9_FN, FN_IP4_14_12, + GP_1_8_FN, FN_IP4_11_9, + GP_1_7_FN, FN_IP4_8_6, + GP_1_6_FN, FN_IP4_5_3, + GP_1_5_FN, FN_IP4_2_0, + GP_1_4_FN, FN_IP3_31_29, + GP_1_3_FN, FN_IP3_28_26, + GP_1_2_FN, FN_IP3_25_23, + GP_1_1_FN, FN_IP3_22_20, + GP_1_0_FN, FN_IP3_19_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, FN_IP7_15_13, + GP_2_28_FN, FN_IP7_12_10, + GP_2_27_FN, FN_IP7_9_8, + GP_2_26_FN, FN_IP7_7_6, + GP_2_25_FN, FN_IP7_5_3, + GP_2_24_FN, FN_IP7_2_0, + GP_2_23_FN, FN_IP6_31_29, + GP_2_22_FN, FN_IP6_28_26, + GP_2_21_FN, FN_IP6_25_23, + GP_2_20_FN, FN_IP6_22_20, + GP_2_19_FN, FN_IP6_19_17, + GP_2_18_FN, FN_IP6_16_14, + GP_2_17_FN, FN_VI1_DATA7_VI1_B7, + GP_2_16_FN, FN_IP8_27, + GP_2_15_FN, FN_IP8_26, + GP_2_14_FN, FN_IP8_25_24, + GP_2_13_FN, FN_IP8_23_22, + GP_2_12_FN, FN_IP8_21_20, + GP_2_11_FN, FN_IP8_19_18, + GP_2_10_FN, FN_IP8_17_16, + GP_2_9_FN, FN_IP8_15_14, + GP_2_8_FN, FN_IP8_13_12, + GP_2_7_FN, FN_IP8_11_10, + GP_2_6_FN, FN_IP8_9_8, + GP_2_5_FN, FN_IP8_7_6, + GP_2_4_FN, FN_IP8_5_4, + GP_2_3_FN, FN_IP8_3_2, + GP_2_2_FN, FN_IP8_1_0, + GP_2_1_FN, FN_IP7_30_29, + GP_2_0_FN, FN_IP7_28_27 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP11_21_18, + GP_3_30_FN, FN_IP11_17_15, + GP_3_29_FN, FN_IP11_14_13, + GP_3_28_FN, FN_IP11_12_11, + GP_3_27_FN, FN_IP11_10_9, + GP_3_26_FN, FN_IP11_8_7, + GP_3_25_FN, FN_IP11_6_5, + GP_3_24_FN, FN_IP11_4, + GP_3_23_FN, FN_IP11_3_0, + GP_3_22_FN, FN_IP10_29_26, + GP_3_21_FN, FN_IP10_25_23, + GP_3_20_FN, FN_IP10_22_19, + GP_3_19_FN, FN_IP10_18_15, + GP_3_18_FN, FN_IP10_14_11, + GP_3_17_FN, FN_IP10_10_7, + GP_3_16_FN, FN_IP10_6_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_26, + GP_3_12_FN, FN_IP9_25_24, + GP_3_11_FN, FN_IP9_23_22, + GP_3_10_FN, FN_IP9_21_20, + GP_3_9_FN, FN_IP9_19_18, + GP_3_8_FN, FN_IP9_17_16, + GP_3_7_FN, FN_IP9_15_12, + GP_3_6_FN, FN_IP9_11_8, + GP_3_5_FN, FN_IP9_7_6, + GP_3_4_FN, FN_IP9_5_4, + GP_3_3_FN, FN_IP9_3_2, + GP_3_2_FN, FN_IP9_1_0, + GP_3_1_FN, FN_IP8_30_29, + GP_3_0_FN, FN_IP8_28 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP14_18_16, + GP_4_30_FN, FN_IP14_15_12, + GP_4_29_FN, FN_IP14_11_9, + GP_4_28_FN, FN_IP14_8_6, + GP_4_27_FN, FN_IP14_5_3, + GP_4_26_FN, FN_IP14_2_0, + GP_4_25_FN, FN_IP13_30_29, + GP_4_24_FN, FN_IP13_28_26, + GP_4_23_FN, FN_IP13_25_23, + GP_4_22_FN, FN_IP13_22_19, + GP_4_21_FN, FN_IP13_18_16, + GP_4_20_FN, FN_IP13_15_13, + GP_4_19_FN, FN_IP13_12_10, + GP_4_18_FN, FN_IP13_9_7, + GP_4_17_FN, FN_IP13_6_3, + GP_4_16_FN, FN_IP13_2_0, + GP_4_15_FN, FN_IP12_30_28, + GP_4_14_FN, FN_IP12_27_25, + GP_4_13_FN, FN_IP12_24_23, + GP_4_12_FN, FN_IP12_22_20, + GP_4_11_FN, FN_IP12_19_17, + GP_4_10_FN, FN_IP12_16_14, + GP_4_9_FN, FN_IP12_13_11, + GP_4_8_FN, FN_IP12_10_8, + GP_4_7_FN, FN_IP12_7_6, + GP_4_6_FN, FN_IP12_5_4, + GP_4_5_FN, FN_IP12_3_2, + GP_4_4_FN, FN_IP12_1_0, + GP_4_3_FN, FN_IP11_31_30, + GP_4_2_FN, FN_IP11_29_27, + GP_4_1_FN, FN_IP11_26_24, + GP_4_0_FN, FN_IP11_23_22 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP7_24_22, + GP_5_30_FN, FN_IP7_21_19, + GP_5_29_FN, FN_IP7_18_16, + GP_5_28_FN, FN_DU_DOTCLKIN2, + GP_5_27_FN, FN_IP7_26_25, + GP_5_26_FN, FN_DU_DOTCLKIN0, + GP_5_25_FN, FN_AVS2, + GP_5_24_FN, FN_AVS1, + GP_5_23_FN, FN_USB2_OVC, + GP_5_22_FN, FN_USB2_PWEN, + GP_5_21_FN, FN_IP16_7, + GP_5_20_FN, FN_IP16_6, + GP_5_19_FN, FN_USB0_OVC_VBUS, + GP_5_18_FN, FN_USB0_PWEN, + GP_5_17_FN, FN_IP16_5_3, + GP_5_16_FN, FN_IP16_2_0, + GP_5_15_FN, FN_IP15_29_28, + GP_5_14_FN, FN_IP15_27_26, + GP_5_13_FN, FN_IP15_25_23, + GP_5_12_FN, FN_IP15_22_20, + GP_5_11_FN, FN_IP15_19_18, + GP_5_10_FN, FN_IP15_17_16, + GP_5_9_FN, FN_IP15_15_14, + GP_5_8_FN, FN_IP15_13_12, + GP_5_7_FN, FN_IP15_11_9, + GP_5_6_FN, FN_IP15_8_6, + GP_5_5_FN, FN_IP15_5_3, + GP_5_4_FN, FN_IP15_2_0, + GP_5_3_FN, FN_IP14_30_28, + GP_5_2_FN, FN_IP14_27_25, + GP_5_1_FN, FN_IP14_24_22, + GP_5_0_FN, FN_IP14_21_19 } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { + /* IP0_31 [1] */ + 0, 0, + /* IP0_30_27 [4] */ + FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, + FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_26_23 [4] */ + FN_D7, FN_AD_DI_B, FN_SDA2_C, + FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_22_20 [3] */ + FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, + FN_SCL2_CIS_C, 0, 0, + /* IP0_19_16 [4] */ + FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, + FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_15_12 [4] */ + FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, + FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_11_9 [3] */ + FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, + 0, 0, 0, + /* IP0_8_6 [3] */ + FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, + 0, 0, 0, + /* IP0_5_3 [3] */ + FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, + 0, 0, 0, + /* IP0_2_0 [3] */ + FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, + 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { + /* IP1_31_30 [2] */ + 0, 0, 0, 0, + /* IP1_29_28 [2] */ + FN_A1, FN_PWM4, 0, 0, + /* IP1_27_26 [2] */ + FN_A0, FN_PWM3, 0, 0, + /* IP1_25_22 [4] */ + FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, + FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_21_18 [4] */ + FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, + FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_17_15 [3] */ + FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, + FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, + 0, 0, 0, + /* IP1_14_12 [3] */ + FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, + FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, + 0, 0, + /* IP1_11_8 [4] */ + FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, + FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_7_4 [4] */ + FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, + FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP1_3_0 [4] */ + FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, + FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { + /* IP2_31_29 [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_28_26 [3] */ + FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, + FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, + /* IP2_25_22 [4] */ + FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, + FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_21_18 [4] */ + FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, + FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_17_15 [3] */ + FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, + 0, 0, 0, 0, + /* IP2_14_12 [3] */ + FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, + /* IP2_11_9 [3] */ + FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, + /* IP2_8_6 [3] */ + FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, + /* IP2_5_3 [3] */ + FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, + /* IP2_2_0 [3] */ + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, + 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { + /* IP3_31_29 [3] */ + FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, + 0, 0, 0, + /* IP3_28_26 [3] */ + FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, + 0, 0, 0, 0, + /* IP3_25_23 [3] */ + FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, + /* IP3_22_20 [3] */ + FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, + /* IP3_19_18 [2] */ + FN_A16, FN_ATAWR1_N, 0, 0, + /* IP3_17_15 [3] */ + FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, + 0, 0, 0, 0, + /* IP3_14_12 [3] */ + FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, + 0, 0, 0, 0, + /* IP3_11_8 [4] */ + FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, + FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, + FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_7_4 [4] */ + FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, + FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP3_3_0 [4] */ + FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, + FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, + 0, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, + 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP4_31_30 [2] */ + 0, 0, 0, 0, + /* IP4_29_27 [3] */ + FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, + FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, + /* IP4_26_24 [3] */ + FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, + FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, + /* IP4_23_21 [3] */ + FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, + FN_HTX0_B, FN_MSIOF0_SS1_B, 0, + /* IP4_20_18 [3] */ + FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, + FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, + /* IP4_17_15 [3] */ + FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, + 0, 0, 0, + /* IP4_14_12 [3] */ + FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, + FN_VI2_FIELD_B, 0, 0, + /* IP4_11_9 [3] */ + FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, + FN_VI2_CLKENB_B, 0, 0, + /* IP4_8_6 [3] */ + FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, + /* IP4_5_3 [3] */ + FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, + /* IP4_2_0 [3] */ + FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, + 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { + /* IP5_31_30 [2] */ + 0, 0, 0, 0, + /* IP5_29_27 [3] */ + FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, + FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, + /* IP5_26_24 [3] */ + FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, + FN_MSIOF0_SCK_B, 0, + /* IP5_23_21 [3] */ + FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, + FN_IERX_C, 0, + /* IP5_20_18 [3] */ + FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, + /* IP5_17_15 [3] */ + FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, + FN_INTC_IRQ4_N, 0, 0, + /* IP5_14_13 [2] */ + FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, + /* IP5_12_10 [3] */ + FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, + 0, 0, + /* IP5_9_6 [4] */ + FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, + FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N, + FN_SDA1_CIS, 0, 0, 0, 0, 0, 0, + /* IP5_5_3 [3] */ + FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, + FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B, + FN_INTC_EN0_N, FN_SCL1_CIS, + /* IP5_2_0 [3] */ + FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, + FN_VI2_R3, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ + FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ + FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ + FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + /* IP6_10_9 [2] */ + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, + /* IP6_8_6 [3] */ + FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, + FN_SSI_SDATA8_C, 0, 0, 0, + /* IP6_5_3 [3] */ + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, + /* IP6_2_0 [3] */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + /* IP7_26_25 [2] */ + FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, + /* IP7_21_19 [3] */ + FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, + FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, + /* IP7_18_16 [3] */ + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ + FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ + FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ + FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30_29 [2] */ + FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, + /* IP8_28 [1] */ + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, + /* IP8_27 [1] */ + FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + /* IP8_26 [1] */ + FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, + /* IP8_25_24 [2] */ + FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_MII_MAGIC, + /* IP8_23_22 [2] */ + FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, + /* IP8_21_20 [2] */ + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_MII_MDIO, + /* IP8_19_18 [2] */ + FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, + /* IP8_17_16 [2] */ + FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, + /* IP8_15_14 [2] */ + FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, + /* IP8_13_12 [2] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, + /* IP8_11_10 [2] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, + /* IP8_9_8 [2] */ + FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, + /* IP8_7_6 [2] */ + FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, + /* IP8_5_4 [2] */ + FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, + /* IP8_3_2 [2] */ + FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, + /* IP8_1_0 [2] */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + /* IP9_31_28 [4] */ + FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, + FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, + FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, + /* IP9_27_26 [2] */ + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, + /* IP9_25_24 [2] */ + FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, + /* IP9_23_22 [2] */ + FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, + /* IP9_21_20 [2] */ + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, + /* IP9_19_18 [2] */ + FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + /* IP9_17_16 [2] */ + FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, + /* IP9_15_12 [4] */ + FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, + FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_11_8 [4] */ + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, + FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_7_6 [2] */ + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, + /* IP9_5_4 [2] */ + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, + /* IP9_3_2 [2] */ + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, + /* IP9_1_0 [2] */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 2, 4, 3, 4, 4, 4, 4, 3, 4) { + /* IP10_31_30 [2] */ + 0, 0, 0, 0, + /* IP10_29_26 [4] */ + FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, + /* IP10_25_23 [3] */ + FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, + /* IP10_22_19 [4] */ + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, + /* IP10_18_15 [4] */ + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + 0, 0, 0, 0, 0, 0, + /* IP10_14_11 [4] */ + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_10_7 [4] */ + FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_6_4 [3] */ + FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, 0, + /* IP10_3_0 [4] */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + /* IP11_31_30 [2] */ + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ + FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, 0, 0, + /* IP11_26_24 [3] */ + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, + 0, 0, 0, + /* IP11_23_22 [2] */ + FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, + /* IP11_21_18 [4] */ + FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, + FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0, + /* IP11_17_15 [3] */ + FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, + /* IP11_14_13 [2] */ + FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, + /* IP11_12_11 [2] */ + FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, + /* IP11_10_9 [2] */ + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, + /* IP11_8_7 [2] */ + FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, + /* IP11_6_5 [2] */ + FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, + /* IP11_4 [1] */ + FN_SD3_CLK, FN_MMC1_CLK, + /* IP11_3_0 [4] */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + /* IP12_31 [1] */ + 0, 0, + /* IP12_30_28 [3] */ + FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, + FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, + FN_CAN_DEBUGOUT4, 0, 0, + /* IP12_27_25 [3] */ + FN_SSI_SCK5, FN_SCIFB1_SCK, + FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, + FN_CAN_DEBUGOUT3, 0, 0, + /* IP12_24_23 [2] */ + FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, + FN_CAN_DEBUGOUT2, + /* IP12_22_20 [3] */ + FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, + FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, + /* IP12_19_17 [3] */ + FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, + FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, + /* IP12_16_14 [3] */ + FN_SSI_SDATA3, FN_STP_ISCLK_0, + FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, + /* IP12_13_11 [3] */ + FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, + FN_CAN_STEP0, 0, 0, 0, + /* IP12_10_8 [3] */ + FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, + FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, + /* IP12_7_6 [2] */ + FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, + /* IP12_5_4 [2] */ + FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, + /* IP12_3_2 [2] */ + FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, + /* IP12_1_0 [2] */ + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, + 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { + /* IP13_31 [1] */ + 0, 0, + /* IP13_30_29 [2] */ + FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, + /* IP13_28_26 [3] */ + FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, + FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, + /* IP13_25_23 [3] */ + FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, + FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, + /* IP13_22_19 [4] */ + FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, + FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, + FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F, + 0, 0, 0, 0, + /* IP13_18_16 [3] */ + FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, + FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, + /* IP13_15_13 [3] */ + FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, + FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, + /* IP13_12_10 [3] */ + FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5, + FN_CAN_DEBUGOUT8, 0, 0, + /* IP13_9_7 [3] */ + FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, + FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, + /* IP13_6_3 [4] */ + FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C, + FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, + FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0, + /* IP13_2_0 [3] */ + FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, + 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { + /* IP14_30 [1] */ + 0, 0, + /* IP14_30_28 [3] */ + FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS, + FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, + FN_HRTS0_N_C, 0, + /* IP14_27_25 [3] */ + FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, + FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, + /* IP14_24_22 [3] */ + FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, + FN_LCDOUT9, 0, 0, 0, + /* IP14_21_19 [3] */ + FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, + FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, + /* IP14_18_16 [3] */ + FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS, + FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, + /* IP14_15_12 [4] */ + FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, + FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C, + 0, 0, 0, 0, 0, 0, 0, + /* IP14_11_9 [3] */ + FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, + 0, 0, 0, + /* IP14_8_6 [3] */ + FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, + 0, 0, 0, + /* IP14_5_3 [3] */ + FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, + FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C, + /* IP14_2_0 [3] */ + FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, + FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, + FN_REMOCON, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, + 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { + /* IP15_31_30 [2] */ + 0, 0, 0, 0, + /* IP15_29_28 [2] */ + FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, + /* IP15_27_26 [2] */ + FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, + /* IP15_25_23 [3] */ + FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, + FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0, + /* IP15_22_20 [3] */ + FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, + FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, + /* IP15_19_18 [2] */ + FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, + /* IP15_17_16 [2] */ + FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, + /* IP15_15_14 [2] */ + FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, + /* IP15_13_12 [2] */ + FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, + /* IP15_11_9 [3] */ + FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, + 0, 0, 0, + /* IP15_8_6 [3] */ + FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17, + FN_SDA2, FN_SDA2_CIS, 0, + /* IP15_5_3 [3] */ + FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16, + FN_SCL2, FN_SCL2_CIS, 0, + /* IP15_2_0 [3] */ + FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7, + FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, + 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { + /* IP16_31_28 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_27_24 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_23_20 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_19_16 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_15_12 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_11_8 [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_7 [1] */ + FN_USB1_OVC, FN_TCLK1_B, + /* IP16_6 [1] */ + FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, + /* IP16_5_3 [3] */ + FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, + FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0, + /* IP16_2_0 [3] */ + FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + /* SEL_SCIF1 [3] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, 0, 0, 0, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, + FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, + FN_SEL_SCIFB1_6, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SCIFA1_3, + /* SEL_SCIF0 [1] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + /* SEL_SCIFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_SOF1 [1] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + /* SEL_SSI7 [2] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI5 [2] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, + /* SEL_VI3 [1] */ + FN_SEL_VI3_0, FN_SEL_VI3_1, + /* SEL_VI2 [1] */ + FN_SEL_VI2_0, FN_SEL_VI2_1, + /* SEL_VI1 [1] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, + /* SEL_VI0 [1] */ + FN_SEL_VI0_0, FN_SEL_VI0_1, + /* SEL_TSIF1 [2] */ + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF3 [1] */ + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + /* SEL_SOF0 [1] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 1, 2, 1, 2, 1, 2, + 1, 1, 1, 3, 3, 2, 3, 2, 2) { + /* RESERVED [3] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_SCIFCLK [1] */ + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CANCLK [1] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + /* SEL_SCIFA2 [2] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, + /* SEL_CAN1 [1] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */ + 0, 0, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_SSP [1] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, + /* SEL_HSCIF0 [3] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, + /* SEL_RDS [3] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0, + /* SEL_SIM [2] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, + /* SEL_SSI8 [2] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 1, 1, 2, 4, 4, 2, 2, + 4, 2, 3, 2, 3, 2) { + /* SEL_IICDVFS [1] */ + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + /* SEL_IIC0 [1] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [3] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, 0, 0, 0, + /* SEL_IIC1 [2] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, + /* SEL_I2C2 [3] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, 0, 0, 0, + /* SEL_I2C1 [2] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a7790_pinmux_info = { + .name = "r8a77900_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c index df0ae21a5ac8..6dfb18772574 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -20,10 +20,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/io.h> #include <linux/kernel.h> +#include <linux/pinctrl/pinconf-generic.h> + #include <mach/irqs.h> #include <mach/sh7372.h> +#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -34,6 +38,35 @@ PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \ PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx) +#undef _GPIO_PORT +#define _GPIO_PORT(gpio, sfx) \ + [gpio] = { \ + .name = __stringify(PORT##gpio), \ + .enum_id = PORT##gpio##_DATA, \ + } + +#define IRQC_PIN_MUX(irq, pin) \ +static const unsigned int intc_irq##irq##_pins[] = { \ + pin, \ +}; \ +static const unsigned int intc_irq##irq##_mux[] = { \ + IRQ##irq##_MARK, \ +} + +#define IRQC_PINS_MUX(irq, pin0, pin1) \ +static const unsigned int intc_irq##irq##_0_pins[] = { \ + pin0, \ +}; \ +static const unsigned int intc_irq##irq##_0_mux[] = { \ + IRQ##irq##_##pin0##_MARK, \ +}; \ +static const unsigned int intc_irq##irq##_1_pins[] = { \ + pin1, \ +}; \ +static const unsigned int intc_irq##irq##_1_mux[] = { \ + IRQ##irq##_##pin1##_MARK, \ +} + enum { PINMUX_RESERVED = 0, @@ -47,16 +80,6 @@ enum { PORT_ALL(IN), PINMUX_INPUT_END, - /* PORT0_IN_PU -> PORT190_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT190_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - /* PORT0_OUT -> PORT190_OUT */ PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), @@ -368,124 +391,11 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) - /* specify valid pin states for each pin in GPIO mode */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_O(2), PORT_DATA_I_PD(3), - PORT_DATA_I_PD(4), PORT_DATA_I_PD(5), - PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7), - PORT_DATA_IO_PD(8), PORT_DATA_O(9), - - PORT_DATA_O(10), PORT_DATA_O(11), - PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_O(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_I_PD(18), PORT_DATA_IO(19), - - PORT_DATA_IO(20), PORT_DATA_IO(21), - PORT_DATA_IO(22), PORT_DATA_IO(23), - PORT_DATA_IO(24), PORT_DATA_IO(25), - PORT_DATA_IO(26), PORT_DATA_IO(27), - PORT_DATA_IO(28), PORT_DATA_IO(29), - - PORT_DATA_IO(30), PORT_DATA_IO(31), - PORT_DATA_IO(32), PORT_DATA_IO(33), - PORT_DATA_IO(34), PORT_DATA_IO(35), - PORT_DATA_IO(36), PORT_DATA_IO(37), - PORT_DATA_IO(38), PORT_DATA_IO(39), - - PORT_DATA_IO(40), PORT_DATA_IO(41), - PORT_DATA_IO(42), PORT_DATA_IO(43), - PORT_DATA_IO(44), PORT_DATA_IO(45), - PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47), - PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49), - - PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51), - PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53), - PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55), - PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57), - PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59), - - PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61), - PORT_DATA_IO(62), PORT_DATA_O(63), - PORT_DATA_O(64), PORT_DATA_IO_PU(65), - PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/ - PORT_DATA_O(68), PORT_DATA_IO(69), - - PORT_DATA_IO(70), PORT_DATA_IO(71), - PORT_DATA_O(72), PORT_DATA_I_PU(73), - PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85), - PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87), - PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89), - - PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/ - - PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101), - PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103), - PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), - PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107), - PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109), - - PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111), - PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), - PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115), - PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117), - PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), - - PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125), - PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127), - PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129), - - PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131), - PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133), - PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135), - PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137), - PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139), - - PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141), - PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143), - PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145), - PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147), - PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149), - - PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), - PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153), - PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155), - PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), - PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_O(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_I_PD(166), PORT_DATA_I_PD(167), - PORT_DATA_I_PD(168), PORT_DATA_I_PD(169), - - PORT_DATA_I_PD(170), PORT_DATA_O(171), - PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173), - PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175), - PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179), - - PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181), - PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183), - PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185), - PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187), - PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189), - - PORT_DATA_IO_PU_PD(190), +static const pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* IRQ */ PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0), @@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), }; +#define SH7372_PIN(pin, cfgs) \ + { \ + .name = __stringify(PORT##pin), \ + .enum_id = PORT##pin##_DATA, \ + .configs = cfgs, \ + } + +#define __I (SH_PFC_PIN_CFG_INPUT) +#define __O (SH_PFC_PIN_CFG_OUTPUT) +#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) +#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) +#define __PU (SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) + +#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD) +#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU) +#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD) +#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO) +#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD) +#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU) +#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD) +#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O) +#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD) + static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), + /* Table 57-1 (I/O and Pull U/D) */ + SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), + SH7372_PIN_O(2), SH7372_PIN_I_PD(3), + SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5), + SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7), + SH7372_PIN_IO_PD(8), SH7372_PIN_O(9), + SH7372_PIN_O(10), SH7372_PIN_O(11), + SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13), + SH7372_PIN_IO_PD(14), SH7372_PIN_O(15), + SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17), + SH7372_PIN_I_PD(18), SH7372_PIN_IO(19), + SH7372_PIN_IO(20), SH7372_PIN_IO(21), + SH7372_PIN_IO(22), SH7372_PIN_IO(23), + SH7372_PIN_IO(24), SH7372_PIN_IO(25), + SH7372_PIN_IO(26), SH7372_PIN_IO(27), + SH7372_PIN_IO(28), SH7372_PIN_IO(29), + SH7372_PIN_IO(30), SH7372_PIN_IO(31), + SH7372_PIN_IO(32), SH7372_PIN_IO(33), + SH7372_PIN_IO(34), SH7372_PIN_IO(35), + SH7372_PIN_IO(36), SH7372_PIN_IO(37), + SH7372_PIN_IO(38), SH7372_PIN_IO(39), + SH7372_PIN_IO(40), SH7372_PIN_IO(41), + SH7372_PIN_IO(42), SH7372_PIN_IO(43), + SH7372_PIN_IO(44), SH7372_PIN_IO(45), + SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47), + SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49), + SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51), + SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53), + SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55), + SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57), + SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59), + SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61), + SH7372_PIN_IO(62), SH7372_PIN_O(63), + SH7372_PIN_O(64), SH7372_PIN_IO_PU(65), + SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67), + SH7372_PIN_O(68), SH7372_PIN_IO(69), + SH7372_PIN_IO(70), SH7372_PIN_IO(71), + SH7372_PIN_O(72), SH7372_PIN_I_PU(73), + SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75), + SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77), + SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79), + SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81), + SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83), + SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85), + SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87), + SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89), + SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91), + SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93), + SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95), + SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97), + SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99), + SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101), + SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103), + SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105), + SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107), + SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109), + SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111), + SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113), + SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115), + SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117), + SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119), + SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121), + SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123), + SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125), + SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127), + SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129), + SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131), + SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133), + SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135), + SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137), + SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139), + SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141), + SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143), + SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145), + SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147), + SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149), + SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151), + SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153), + SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155), + SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157), + SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159), + SH7372_PIN_O(160), SH7372_PIN_IO_PD(161), + SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163), + SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165), + SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167), + SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169), + SH7372_PIN_I_PD(170), SH7372_PIN_O(171), + SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173), + SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175), + SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177), + SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179), + SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181), + SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183), + SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185), + SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187), + SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189), + SH7372_PIN_IO_PU_PD(190), }; +/* - BSC -------------------------------------------------------------------- */ +static const unsigned int bsc_data8_pins[] = { + /* D[0:7] */ + 46, 47, 48, 49, 50, 51, 52, 53, +}; +static const unsigned int bsc_data8_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, +}; +static const unsigned int bsc_data16_pins[] = { + /* D[0:15] */ + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int bsc_data16_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int bsc_cs0_pins[] = { + /* CS */ + 62, +}; +static const unsigned int bsc_cs0_mux[] = { + CS0_MARK, +}; +static const unsigned int bsc_cs2_pins[] = { + /* CS */ + 63, +}; +static const unsigned int bsc_cs2_mux[] = { + CS2_MARK, +}; +static const unsigned int bsc_cs4_pins[] = { + /* CS */ + 64, +}; +static const unsigned int bsc_cs4_mux[] = { + CS4_MARK, +}; +static const unsigned int bsc_cs5a_pins[] = { + /* CS */ + 65, +}; +static const unsigned int bsc_cs5a_mux[] = { + CS5A_MARK, +}; +static const unsigned int bsc_cs5b_pins[] = { + /* CS */ + 66, +}; +static const unsigned int bsc_cs5b_mux[] = { + CS5B_MARK, +}; +static const unsigned int bsc_cs6a_pins[] = { + /* CS */ + 67, +}; +static const unsigned int bsc_cs6a_mux[] = { + CS6A_MARK, +}; +static const unsigned int bsc_rd_we8_pins[] = { + /* RD, WE[0] */ + 69, 70, +}; +static const unsigned int bsc_rd_we8_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, +}; +static const unsigned int bsc_rd_we16_pins[] = { + /* RD, WE[0:1] */ + 69, 70, 71, +}; +static const unsigned int bsc_rd_we16_mux[] = { + RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, +}; +static const unsigned int bsc_bs_pins[] = { + /* BS */ + 19, +}; +static const unsigned int bsc_bs_mux[] = { + BS_MARK, +}; +static const unsigned int bsc_rdwr_pins[] = { + /* RDWR */ + 75, +}; +static const unsigned int bsc_rdwr_mux[] = { + RDWR_MARK, +}; +static const unsigned int bsc_wait_pins[] = { + /* WAIT */ + 74, +}; +static const unsigned int bsc_wait_mux[] = { + WAIT_MARK, +}; +/* - CEU -------------------------------------------------------------------- */ +static const unsigned int ceu_data_0_7_pins[] = { + /* D[0:7] */ + 102, 103, 104, 105, 106, 107, 108, 109, +}; +static const unsigned int ceu_data_0_7_mux[] = { + VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK, + VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK, +}; +static const unsigned int ceu_data_8_15_pins[] = { + /* D[8:15] */ + 110, 111, 112, 113, 114, 115, 116, 117, +}; +static const unsigned int ceu_data_8_15_mux[] = { + VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK, + VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK, +}; +static const unsigned int ceu_clk_0_pins[] = { + /* CKO */ + 120, +}; +static const unsigned int ceu_clk_0_mux[] = { + VIO_CKO_MARK, +}; +static const unsigned int ceu_clk_1_pins[] = { + /* CKO */ + 16, +}; +static const unsigned int ceu_clk_1_mux[] = { + VIO_CKO1_MARK, +}; +static const unsigned int ceu_clk_2_pins[] = { + /* CKO */ + 17, +}; +static const unsigned int ceu_clk_2_mux[] = { + VIO_CKO2_MARK, +}; +static const unsigned int ceu_sync_pins[] = { + /* CLK, VD, HD */ + 118, 100, 101, +}; +static const unsigned int ceu_sync_mux[] = { + VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, +}; +static const unsigned int ceu_field_pins[] = { + /* FIELD */ + 119, +}; +static const unsigned int ceu_field_mux[] = { + VIO_FIELD_MARK, +}; +/* - FLCTL ------------------------------------------------------------------ */ +static const unsigned int flctl_data_pins[] = { + /* NAF[0:15] */ + 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, +}; +static const unsigned int flctl_data_mux[] = { + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, + D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, + D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, +}; +static const unsigned int flctl_ce0_pins[] = { + /* CE */ + 68, +}; +static const unsigned int flctl_ce0_mux[] = { + FCE0_MARK, +}; +static const unsigned int flctl_ce1_pins[] = { + /* CE */ + 66, +}; +static const unsigned int flctl_ce1_mux[] = { + FCE1_MARK, +}; +static const unsigned int flctl_ctrl_pins[] = { + /* FCDE, FOE, FSC, FWE, FRB */ + 24, 23, 69, 70, 73, +}; +static const unsigned int flctl_ctrl_mux[] = { + A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK, +}; +/* - FSIA ------------------------------------------------------------------- */ +static const unsigned int fsia_mclk_in_pins[] = { + /* CK */ + 4, +}; +static const unsigned int fsia_mclk_in_mux[] = { + FSIACK_MARK, +}; +static const unsigned int fsia_mclk_out_pins[] = { + /* OMC */ + 8, +}; +static const unsigned int fsia_mclk_out_mux[] = { + FSIAOMC_MARK, +}; +static const unsigned int fsia_sclk_in_pins[] = { + /* ILR, IBT */ + 5, 6, +}; +static const unsigned int fsia_sclk_in_mux[] = { + FSIAILR_MARK, FSIAIBT_MARK, +}; +static const unsigned int fsia_sclk_out_pins[] = { + /* OLR, OBT */ + 9, 10, +}; +static const unsigned int fsia_sclk_out_mux[] = { + FSIAOLR_MARK, FSIAOBT_MARK, +}; +static const unsigned int fsia_data_in_pins[] = { + /* ISLD */ + 7, +}; +static const unsigned int fsia_data_in_mux[] = { + FSIAISLD_MARK, +}; +static const unsigned int fsia_data_out_pins[] = { + /* OSLD */ + 11, +}; +static const unsigned int fsia_data_out_mux[] = { + FSIAOSLD_MARK, +}; +static const unsigned int fsia_spdif_0_pins[] = { + /* SPDIF */ + 11, +}; +static const unsigned int fsia_spdif_0_mux[] = { + FSIASPDIF_11_MARK, +}; +static const unsigned int fsia_spdif_1_pins[] = { + /* SPDIF */ + 15, +}; +static const unsigned int fsia_spdif_1_mux[] = { + FSIASPDIF_15_MARK, +}; +/* - FSIB ------------------------------------------------------------------- */ +static const unsigned int fsib_mclk_in_pins[] = { + /* CK */ + 4, +}; +static const unsigned int fsib_mclk_in_mux[] = { + FSIBCK_MARK, +}; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi_pins[] = { + /* HPD, CEC */ + 169, 170, +}; +static const unsigned int hdmi_mux[] = { + HDMI_HPD_MARK, HDMI_CEC_MARK, +}; +/* - INTC ------------------------------------------------------------------- */ +IRQC_PINS_MUX(0, 6, 162); +IRQC_PIN_MUX(1, 12); +IRQC_PINS_MUX(2, 4, 5); +IRQC_PINS_MUX(3, 8, 16); +IRQC_PINS_MUX(4, 17, 163); +IRQC_PIN_MUX(5, 18); +IRQC_PINS_MUX(6, 39, 164); +IRQC_PINS_MUX(7, 40, 167); +IRQC_PINS_MUX(8, 41, 168); +IRQC_PINS_MUX(9, 42, 169); +IRQC_PIN_MUX(10, 65); +IRQC_PIN_MUX(11, 67); +IRQC_PINS_MUX(12, 80, 137); +IRQC_PINS_MUX(13, 81, 145); +IRQC_PINS_MUX(14, 82, 146); +IRQC_PINS_MUX(15, 83, 147); +IRQC_PINS_MUX(16, 84, 170); +IRQC_PIN_MUX(17, 85); +IRQC_PIN_MUX(18, 86); +IRQC_PIN_MUX(19, 87); +IRQC_PIN_MUX(20, 92); +IRQC_PIN_MUX(21, 93); +IRQC_PIN_MUX(22, 94); +IRQC_PIN_MUX(23, 95); +IRQC_PIN_MUX(24, 112); +IRQC_PIN_MUX(25, 119); +IRQC_PINS_MUX(26, 121, 172); +IRQC_PINS_MUX(27, 122, 180); +IRQC_PINS_MUX(28, 123, 181); +IRQC_PINS_MUX(29, 129, 182); +IRQC_PINS_MUX(30, 130, 183); +IRQC_PINS_MUX(31, 138, 184); +/* - KEYSC ------------------------------------------------------------------ */ +static const unsigned int keysc_in04_0_pins[] = { + /* KEYIN[0:4] */ + 136, 135, 134, 133, 132, +}; +static const unsigned int keysc_in04_0_mux[] = { + KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in04_1_pins[] = { + /* KEYIN[0:4] */ + 121, 122, 123, 124, 132, +}; +static const unsigned int keysc_in04_1_mux[] = { + KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK, + KEYIN4_MARK, +}; +static const unsigned int keysc_in5_pins[] = { + /* KEYIN5 */ + 131, +}; +static const unsigned int keysc_in5_mux[] = { + KEYIN5_MARK, +}; +static const unsigned int keysc_in6_pins[] = { + /* KEYIN6 */ + 130, +}; +static const unsigned int keysc_in6_mux[] = { + KEYIN6_MARK, +}; +static const unsigned int keysc_in7_pins[] = { + /* KEYIN7 */ + 129, +}; +static const unsigned int keysc_in7_mux[] = { + KEYIN7_MARK, +}; +static const unsigned int keysc_out4_pins[] = { + /* KEYOUT[0:3] */ + 128, 127, 126, 125, +}; +static const unsigned int keysc_out4_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, +}; +static const unsigned int keysc_out5_pins[] = { + /* KEYOUT[0:4] */ + 128, 127, 126, 125, 124, +}; +static const unsigned int keysc_out5_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, +}; +static const unsigned int keysc_out6_pins[] = { + /* KEYOUT[0:5] */ + 128, 127, 126, 125, 124, 123, +}; +static const unsigned int keysc_out6_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, +}; +static const unsigned int keysc_out8_pins[] = { + /* KEYOUT[0:7] */ + 128, 127, 126, 125, 124, 123, 122, 121, +}; +static const unsigned int keysc_out8_mux[] = { + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, +}; +/* - LCD -------------------------------------------------------------------- */ +static const unsigned int lcd_data8_pins[] = { + /* D[0:7] */ + 121, 122, 123, 124, 125, 126, 127, 128, +}; +static const unsigned int lcd_data8_mux[] = { + /* LCDC */ + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, +}; +static const unsigned int lcd_data9_pins[] = { + /* D[0:8] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, + 137, 138, 139, 140, 141, 142, 143, 144, +}; +static const unsigned int lcd_data9_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, +}; +static const unsigned int lcd_data12_pins[] = { + /* D[0:11] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, +}; +static const unsigned int lcd_data12_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, +}; +static const unsigned int lcd_data16_pins[] = { + /* D[0:15] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, +}; +static const unsigned int lcd_data16_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, +}; +static const unsigned int lcd_data18_pins[] = { + /* D[0:17] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, +}; +static const unsigned int lcd_data18_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, +}; +static const unsigned int lcd_data24_pins[] = { + /* D[0:23] */ + 121, 122, 123, 124, 125, 126, 127, 128, + 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, 139, 140, 141, 142, 143, 144, +}; +static const unsigned int lcd_data24_mux[] = { + LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, + LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, + LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, + LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, + LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, + LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, +}; +static const unsigned int lcd_display_pins[] = { + /* DON */ + 151, +}; +static const unsigned int lcd_display_mux[] = { + LCDDON_MARK, +}; +static const unsigned int lcd_lclk_pins[] = { + /* LCLK */ + 150, +}; +static const unsigned int lcd_lclk_mux[] = { + LCDLCLK_MARK, +}; +static const unsigned int lcd_sync_pins[] = { + /* VSYN, HSYN, DCK, DISP */ + 146, 145, 147, 149, +}; +static const unsigned int lcd_sync_mux[] = { + LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, +}; +static const unsigned int lcd_sys_pins[] = { + /* CS, WR, RD, RS */ + 145, 147, 148, 149, +}; +static const unsigned int lcd_sys_mux[] = { + LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK, +}; /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc0_data1_0_pins[] = { /* D[0] */ @@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = { static const unsigned int mmc0_ctrl_1_mux[] = { MMCCMD1_MARK, MMCCLK1_MARK, }; +/* - SCIFA0 ----------------------------------------------------------------- */ +static const unsigned int scifa0_data_pins[] = { + /* RXD, TXD */ + 153, 152, +}; +static const unsigned int scifa0_data_mux[] = { + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, +}; +static const unsigned int scifa0_clk_pins[] = { + /* SCK */ + 156, +}; +static const unsigned int scifa0_clk_mux[] = { + SCIFA0_SCK_MARK, +}; +static const unsigned int scifa0_ctrl_pins[] = { + /* RTS, CTS */ + 157, 158, +}; +static const unsigned int scifa0_ctrl_mux[] = { + SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, +}; +/* - SCIFA1 ----------------------------------------------------------------- */ +static const unsigned int scifa1_data_pins[] = { + /* RXD, TXD */ + 155, 154, +}; +static const unsigned int scifa1_data_mux[] = { + SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, +}; +static const unsigned int scifa1_clk_pins[] = { + /* SCK */ + 159, +}; +static const unsigned int scifa1_clk_mux[] = { + SCIFA1_SCK_MARK, +}; +static const unsigned int scifa1_ctrl_pins[] = { + /* RTS, CTS */ + 160, 161, +}; +static const unsigned int scifa1_ctrl_mux[] = { + SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, +}; +/* - SCIFA2 ----------------------------------------------------------------- */ +static const unsigned int scifa2_data_pins[] = { + /* RXD, TXD */ + 97, 96, +}; +static const unsigned int scifa2_data_mux[] = { + SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, +}; +static const unsigned int scifa2_clk_pins[] = { + /* SCK */ + 98, +}; +static const unsigned int scifa2_clk_mux[] = { + SCIFA2_SCK1_MARK, +}; +static const unsigned int scifa2_ctrl_pins[] = { + /* RTS, CTS */ + 95, 94, +}; +static const unsigned int scifa2_ctrl_mux[] = { + SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK, +}; +/* - SCIFA3 ----------------------------------------------------------------- */ +static const unsigned int scifa3_data_pins[] = { + /* RXD, TXD */ + 144, 143, +}; +static const unsigned int scifa3_data_mux[] = { + SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, +}; +static const unsigned int scifa3_clk_pins[] = { + /* SCK */ + 142, +}; +static const unsigned int scifa3_clk_mux[] = { + SCIFA3_SCK_MARK, +}; +static const unsigned int scifa3_ctrl_0_pins[] = { + /* RTS, CTS */ + 44, 43, +}; +static const unsigned int scifa3_ctrl_0_mux[] = { + SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK, +}; +static const unsigned int scifa3_ctrl_1_pins[] = { + /* RTS, CTS */ + 141, 140, +}; +static const unsigned int scifa3_ctrl_1_mux[] = { + SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK, +}; +/* - SCIFA4 ----------------------------------------------------------------- */ +static const unsigned int scifa4_data_pins[] = { + /* RXD, TXD */ + 5, 6, +}; +static const unsigned int scifa4_data_mux[] = { + SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, +}; +/* - SCIFA5 ----------------------------------------------------------------- */ +static const unsigned int scifa5_data_pins[] = { + /* RXD, TXD */ + 8, 12, +}; +static const unsigned int scifa5_data_mux[] = { + SCIFA5_RXD_MARK, SCIFA5_TXD_MARK, +}; +/* - SCIFB ------------------------------------------------------------------ */ +static const unsigned int scifb_data_pins[] = { + /* RXD, TXD */ + 166, 165, +}; +static const unsigned int scifb_data_mux[] = { + SCIFB_RXD_MARK, SCIFB_TXD_MARK, +}; +static const unsigned int scifb_clk_pins[] = { + /* SCK */ + 162, +}; +static const unsigned int scifb_clk_mux[] = { + SCIFB_SCK_MARK, +}; +static const unsigned int scifb_ctrl_pins[] = { + /* RTS, CTS */ + 163, 164, +}; +static const unsigned int scifb_ctrl_mux[] = { + SCIFB_RTS_MARK, SCIFB_CTS_MARK, +}; /* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data1_pins[] = { /* D0 */ @@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = { static const unsigned int sdhi2_ctrl_mux[] = { SDHICMD2_MARK, SDHICLK2_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_vbus_pins[] = { + /* VBUS */ + 167, +}; +static const unsigned int usb0_vbus_mux[] = { + VBUS0_0_MARK, +}; +static const unsigned int usb0_otg_id_pins[] = { + /* IDIN */ + 113, +}; +static const unsigned int usb0_otg_id_mux[] = { + IDIN_0_MARK, +}; +static const unsigned int usb0_otg_ctrl_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 116, 114, 117, 115, +}; +static const unsigned int usb0_otg_ctrl_mux[] = { + PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_vbus_pins[] = { + /* VBUS */ + 168, +}; +static const unsigned int usb1_vbus_mux[] = { + VBUS0_1_MARK, +}; +static const unsigned int usb1_otg_id_0_pins[] = { + /* IDIN */ + 113, +}; +static const unsigned int usb1_otg_id_0_mux[] = { + IDIN_1_113_MARK, +}; +static const unsigned int usb1_otg_id_1_pins[] = { + /* IDIN */ + 18, +}; +static const unsigned int usb1_otg_id_1_mux[] = { + IDIN_1_18_MARK, +}; +static const unsigned int usb1_otg_ctrl_0_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 115, 116, 114, 117, 113, +}; +static const unsigned int usb1_otg_ctrl_0_mux[] = { + PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK, +}; +static const unsigned int usb1_otg_ctrl_1_pins[] = { + /* PWEN, EXTLP, OVCN, OVCN2 */ + 138, 116, 162, 117, 18, +}; +static const unsigned int usb1_otg_ctrl_1_mux[] = { + PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(bsc_data8), + SH_PFC_PIN_GROUP(bsc_data16), + SH_PFC_PIN_GROUP(bsc_cs0), + SH_PFC_PIN_GROUP(bsc_cs2), + SH_PFC_PIN_GROUP(bsc_cs4), + SH_PFC_PIN_GROUP(bsc_cs5a), + SH_PFC_PIN_GROUP(bsc_cs5b), + SH_PFC_PIN_GROUP(bsc_cs6a), + SH_PFC_PIN_GROUP(bsc_rd_we8), + SH_PFC_PIN_GROUP(bsc_rd_we16), + SH_PFC_PIN_GROUP(bsc_bs), + SH_PFC_PIN_GROUP(bsc_rdwr), + SH_PFC_PIN_GROUP(ceu_data_0_7), + SH_PFC_PIN_GROUP(ceu_data_8_15), + SH_PFC_PIN_GROUP(ceu_clk_0), + SH_PFC_PIN_GROUP(ceu_clk_1), + SH_PFC_PIN_GROUP(ceu_clk_2), + SH_PFC_PIN_GROUP(ceu_sync), + SH_PFC_PIN_GROUP(ceu_field), + SH_PFC_PIN_GROUP(flctl_data), + SH_PFC_PIN_GROUP(flctl_ce0), + SH_PFC_PIN_GROUP(flctl_ce1), + SH_PFC_PIN_GROUP(flctl_ctrl), + SH_PFC_PIN_GROUP(fsia_mclk_in), + SH_PFC_PIN_GROUP(fsia_mclk_out), + SH_PFC_PIN_GROUP(fsia_sclk_in), + SH_PFC_PIN_GROUP(fsia_sclk_out), + SH_PFC_PIN_GROUP(fsia_data_in), + SH_PFC_PIN_GROUP(fsia_data_out), + SH_PFC_PIN_GROUP(fsia_spdif_0), + SH_PFC_PIN_GROUP(fsia_spdif_1), + SH_PFC_PIN_GROUP(fsib_mclk_in), + SH_PFC_PIN_GROUP(hdmi), + SH_PFC_PIN_GROUP(intc_irq0_0), + SH_PFC_PIN_GROUP(intc_irq0_1), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2_0), + SH_PFC_PIN_GROUP(intc_irq2_1), + SH_PFC_PIN_GROUP(intc_irq3_0), + SH_PFC_PIN_GROUP(intc_irq3_1), + SH_PFC_PIN_GROUP(intc_irq4_0), + SH_PFC_PIN_GROUP(intc_irq4_1), + SH_PFC_PIN_GROUP(intc_irq5), + SH_PFC_PIN_GROUP(intc_irq6_0), + SH_PFC_PIN_GROUP(intc_irq6_1), + SH_PFC_PIN_GROUP(intc_irq7_0), + SH_PFC_PIN_GROUP(intc_irq7_1), + SH_PFC_PIN_GROUP(intc_irq8_0), + SH_PFC_PIN_GROUP(intc_irq8_1), + SH_PFC_PIN_GROUP(intc_irq9_0), + SH_PFC_PIN_GROUP(intc_irq9_1), + SH_PFC_PIN_GROUP(intc_irq10), + SH_PFC_PIN_GROUP(intc_irq11), + SH_PFC_PIN_GROUP(intc_irq12_0), + SH_PFC_PIN_GROUP(intc_irq12_1), + SH_PFC_PIN_GROUP(intc_irq13_0), + SH_PFC_PIN_GROUP(intc_irq13_1), + SH_PFC_PIN_GROUP(intc_irq14_0), + SH_PFC_PIN_GROUP(intc_irq14_1), + SH_PFC_PIN_GROUP(intc_irq15_0), + SH_PFC_PIN_GROUP(intc_irq15_1), + SH_PFC_PIN_GROUP(intc_irq16_0), + SH_PFC_PIN_GROUP(intc_irq16_1), + SH_PFC_PIN_GROUP(intc_irq17), + SH_PFC_PIN_GROUP(intc_irq18), + SH_PFC_PIN_GROUP(intc_irq19), + SH_PFC_PIN_GROUP(intc_irq20), + SH_PFC_PIN_GROUP(intc_irq21), + SH_PFC_PIN_GROUP(intc_irq22), + SH_PFC_PIN_GROUP(intc_irq23), + SH_PFC_PIN_GROUP(intc_irq24), + SH_PFC_PIN_GROUP(intc_irq25), + SH_PFC_PIN_GROUP(intc_irq26_0), + SH_PFC_PIN_GROUP(intc_irq26_1), + SH_PFC_PIN_GROUP(intc_irq27_0), + SH_PFC_PIN_GROUP(intc_irq27_1), + SH_PFC_PIN_GROUP(intc_irq28_0), + SH_PFC_PIN_GROUP(intc_irq28_1), + SH_PFC_PIN_GROUP(intc_irq29_0), + SH_PFC_PIN_GROUP(intc_irq29_1), + SH_PFC_PIN_GROUP(intc_irq30_0), + SH_PFC_PIN_GROUP(intc_irq30_1), + SH_PFC_PIN_GROUP(intc_irq31_0), + SH_PFC_PIN_GROUP(intc_irq31_1), + SH_PFC_PIN_GROUP(keysc_in04_0), + SH_PFC_PIN_GROUP(keysc_in04_1), + SH_PFC_PIN_GROUP(keysc_in5), + SH_PFC_PIN_GROUP(keysc_in6), + SH_PFC_PIN_GROUP(keysc_in7), + SH_PFC_PIN_GROUP(keysc_out4), + SH_PFC_PIN_GROUP(keysc_out5), + SH_PFC_PIN_GROUP(keysc_out6), + SH_PFC_PIN_GROUP(keysc_out8), + SH_PFC_PIN_GROUP(lcd_data8), + SH_PFC_PIN_GROUP(lcd_data9), + SH_PFC_PIN_GROUP(lcd_data12), + SH_PFC_PIN_GROUP(lcd_data16), + SH_PFC_PIN_GROUP(lcd_data18), + SH_PFC_PIN_GROUP(lcd_data24), + SH_PFC_PIN_GROUP(lcd_display), + SH_PFC_PIN_GROUP(lcd_lclk), + SH_PFC_PIN_GROUP(lcd_sync), + SH_PFC_PIN_GROUP(lcd_sys), SH_PFC_PIN_GROUP(mmc0_data1_0), SH_PFC_PIN_GROUP(mmc0_data4_0), SH_PFC_PIN_GROUP(mmc0_data8_0), @@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc0_data4_1), SH_PFC_PIN_GROUP(mmc0_data8_1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_ctrl_0), + SH_PFC_PIN_GROUP(scifa3_ctrl_1), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifb_data), + SH_PFC_PIN_GROUP(scifb_clk), + SH_PFC_PIN_GROUP(scifb_ctrl), SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(sdhi0_ctrl), @@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(usb0_vbus), + SH_PFC_PIN_GROUP(usb0_otg_id), + SH_PFC_PIN_GROUP(usb0_otg_ctrl), + SH_PFC_PIN_GROUP(usb1_vbus), + SH_PFC_PIN_GROUP(usb1_otg_id_0), + SH_PFC_PIN_GROUP(usb1_otg_id_1), + SH_PFC_PIN_GROUP(usb1_otg_ctrl_0), + SH_PFC_PIN_GROUP(usb1_otg_ctrl_1), +}; + +static const char * const bsc_groups[] = { + "bsc_data8", + "bsc_data16", + "bsc_cs0", + "bsc_cs2", + "bsc_cs4", + "bsc_cs5a", + "bsc_cs5b", + "bsc_cs6a", + "bsc_rd_we8", + "bsc_rd_we16", + "bsc_bs", + "bsc_rdwr", +}; + +static const char * const ceu_groups[] = { + "ceu_data_0_7", + "ceu_data_8_15", + "ceu_clk_0", + "ceu_clk_1", + "ceu_clk_2", + "ceu_sync", + "ceu_field", +}; + +static const char * const flctl_groups[] = { + "flctl_data", + "flctl_ce0", + "flctl_ce1", + "flctl_ctrl", +}; + +static const char * const fsia_groups[] = { + "fsia_mclk_in", + "fsia_mclk_out", + "fsia_sclk_in", + "fsia_sclk_out", + "fsia_data_in", + "fsia_data_out", + "fsia_spdif_0", + "fsia_spdif_1", +}; + +static const char * const fsib_groups[] = { + "fsib_mclk_in", +}; + +static const char * const hdmi_groups[] = { + "hdmi", +}; + +static const char * const intc_groups[] = { + "intc_irq0_0", + "intc_irq0_1", + "intc_irq1", + "intc_irq2_0", + "intc_irq2_1", + "intc_irq3_0", + "intc_irq3_1", + "intc_irq4_0", + "intc_irq4_1", + "intc_irq5", + "intc_irq6_0", + "intc_irq6_1", + "intc_irq7_0", + "intc_irq7_1", + "intc_irq8_0", + "intc_irq8_1", + "intc_irq9_0", + "intc_irq9_1", + "intc_irq10", + "intc_irq11", + "intc_irq12_0", + "intc_irq12_1", + "intc_irq13_0", + "intc_irq13_1", + "intc_irq14_0", + "intc_irq14_1", + "intc_irq15_0", + "intc_irq15_1", + "intc_irq16_0", + "intc_irq16_1", + "intc_irq17", + "intc_irq18", + "intc_irq19", + "intc_irq20", + "intc_irq21", + "intc_irq22", + "intc_irq23", + "intc_irq24", + "intc_irq25", + "intc_irq26_0", + "intc_irq26_1", + "intc_irq27_0", + "intc_irq27_1", + "intc_irq28_0", + "intc_irq28_1", + "intc_irq29_0", + "intc_irq29_1", + "intc_irq30_0", + "intc_irq30_1", + "intc_irq31_0", + "intc_irq31_1", +}; + +static const char * const keysc_groups[] = { + "keysc_in04_0", + "keysc_in04_1", + "keysc_in5", + "keysc_in6", + "keysc_in7", + "keysc_out4", + "keysc_out5", + "keysc_out6", + "keysc_out8", +}; + +static const char * const lcd_groups[] = { + "lcd_data8", + "lcd_data9", + "lcd_data12", + "lcd_data16", + "lcd_data18", + "lcd_data24", + "lcd_display", + "lcd_lclk", + "lcd_sync", + "lcd_sys", }; static const char * const mmc0_groups[] = { @@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = { "mmc0_ctrl_1", }; +static const char * const scifa0_groups[] = { + "scifa0_data", + "scifa0_clk", + "scifa0_ctrl", +}; + +static const char * const scifa1_groups[] = { + "scifa1_data", + "scifa1_clk", + "scifa1_ctrl", +}; + +static const char * const scifa2_groups[] = { + "scifa2_data", + "scifa2_clk", + "scifa2_ctrl", +}; + +static const char * const scifa3_groups[] = { + "scifa3_data", + "scifa3_clk", + "scifa3_ctrl_0", + "scifa3_ctrl_1", +}; + +static const char * const scifa4_groups[] = { + "scifa4_data", +}; + +static const char * const scifa5_groups[] = { + "scifa5_data", +}; + +static const char * const scifb_groups[] = { + "scifb_data", + "scifb_clk", + "scifb_ctrl", +}; + static const char * const sdhi0_groups[] = { "sdhi0_data1", "sdhi0_data4", @@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = { "sdhi2_ctrl", }; +static const char * const usb0_groups[] = { + "usb0_vbus", + "usb0_otg_id", + "usb0_otg_ctrl", +}; + +static const char * const usb1_groups[] = { + "usb1_vbus", + "usb1_otg_id_0", + "usb1_otg_id_1", + "usb1_otg_ctrl_0", + "usb1_otg_ctrl_1", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(bsc), + SH_PFC_FUNCTION(ceu), + SH_PFC_FUNCTION(flctl), + SH_PFC_FUNCTION(fsia), + SH_PFC_FUNCTION(fsib), + SH_PFC_FUNCTION(hdmi), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(keysc), + SH_PFC_FUNCTION(lcd), SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), }; -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) - -static const struct pinmux_func pinmux_func_gpios[] = { - /* IRQ */ - GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), - GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), - GPIO_FN(IRQ3_16), GPIO_FN(IRQ4_17), GPIO_FN(IRQ4_163), - GPIO_FN(IRQ5), GPIO_FN(IRQ6_39), GPIO_FN(IRQ6_164), - GPIO_FN(IRQ7_40), GPIO_FN(IRQ7_167), GPIO_FN(IRQ8_41), - GPIO_FN(IRQ8_168), GPIO_FN(IRQ9_42), GPIO_FN(IRQ9_169), - GPIO_FN(IRQ10), GPIO_FN(IRQ11), GPIO_FN(IRQ12_80), - GPIO_FN(IRQ12_137), GPIO_FN(IRQ13_81), GPIO_FN(IRQ13_145), - GPIO_FN(IRQ14_82), GPIO_FN(IRQ14_146), GPIO_FN(IRQ15_83), - GPIO_FN(IRQ15_147), GPIO_FN(IRQ16_84), GPIO_FN(IRQ16_170), - GPIO_FN(IRQ17), GPIO_FN(IRQ18), GPIO_FN(IRQ19), - GPIO_FN(IRQ20), GPIO_FN(IRQ21), GPIO_FN(IRQ22), - GPIO_FN(IRQ23), GPIO_FN(IRQ24), GPIO_FN(IRQ25), - GPIO_FN(IRQ26_121), GPIO_FN(IRQ26_172), GPIO_FN(IRQ27_122), - GPIO_FN(IRQ27_180), GPIO_FN(IRQ28_123), GPIO_FN(IRQ28_181), - GPIO_FN(IRQ29_129), GPIO_FN(IRQ29_182), GPIO_FN(IRQ30_130), - GPIO_FN(IRQ30_183), GPIO_FN(IRQ31_138), GPIO_FN(IRQ31_184), - - /* MSIOF0 */ - GPIO_FN(MSIOF0_TSYNC), GPIO_FN(MSIOF0_TSCK), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_MCK0), - GPIO_FN(MSIOF0_MCK1), GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - - /* MSIOF1 */ - GPIO_FN(MSIOF1_TSCK_39), GPIO_FN(MSIOF1_TSCK_88), - GPIO_FN(MSIOF1_TSYNC_40), GPIO_FN(MSIOF1_TSYNC_89), - GPIO_FN(MSIOF1_TXD_41), GPIO_FN(MSIOF1_TXD_90), - GPIO_FN(MSIOF1_RXD_42), GPIO_FN(MSIOF1_RXD_91), - GPIO_FN(MSIOF1_SS1_43), GPIO_FN(MSIOF1_SS1_92), - GPIO_FN(MSIOF1_SS2_44), GPIO_FN(MSIOF1_SS2_93), - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_RSCK), GPIO_FN(MSIOF2_RSYNC), GPIO_FN(MSIOF2_MCK0), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_SS1), GPIO_FN(MSIOF2_SS2), - GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), - GPIO_FN(MSIOF2_TXD), - - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), - GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), - - /* BBIF2 */ - GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), - - /* FSI */ - GPIO_FN(FSIACK), GPIO_FN(FSIBCK), GPIO_FN(FSIAILR), - GPIO_FN(FSIAIBT), GPIO_FN(FSIAISLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIAOLR), GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), - GPIO_FN(FSIASPDIF_11), GPIO_FN(FSIASPDIF_15), - - /* FMSI */ - GPIO_FN(FMSOCK), GPIO_FN(FMSOOLR), GPIO_FN(FMSIOLR), - GPIO_FN(FMSOOBT), GPIO_FN(FMSIOBT), GPIO_FN(FMSOSLD), - GPIO_FN(FMSOILR), GPIO_FN(FMSIILR), GPIO_FN(FMSOIBT), - GPIO_FN(FMSIIBT), GPIO_FN(FMSISLD), GPIO_FN(FMSICK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_TXD), GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_SCK), - GPIO_FN(SCIFA0_RTS), GPIO_FN(SCIFA0_CTS), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RTS), GPIO_FN(SCIFA1_CTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_CTS1), GPIO_FN(SCIFA2_RTS1), GPIO_FN(SCIFA2_TXD1), - GPIO_FN(SCIFA2_RXD1), GPIO_FN(SCIFA2_SCK1), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_CTS_43), GPIO_FN(SCIFA3_CTS_140), - GPIO_FN(SCIFA3_RTS_44), GPIO_FN(SCIFA3_RTS_141), - GPIO_FN(SCIFA3_SCK), GPIO_FN(SCIFA3_TXD), - GPIO_FN(SCIFA3_RXD), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD), GPIO_FN(SCIFA4_TXD), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_RXD), GPIO_FN(SCIFA5_TXD), - - /* SCIFB */ - GPIO_FN(SCIFB_SCK), GPIO_FN(SCIFB_RTS), GPIO_FN(SCIFB_CTS), - GPIO_FN(SCIFB_TXD), GPIO_FN(SCIFB_RXD), - - /* CEU */ - GPIO_FN(VIO_HD), GPIO_FN(VIO_CKO1), GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_VD), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD), - GPIO_FN(VIO_CKO), GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), - GPIO_FN(VIO_D2), GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), - GPIO_FN(VIO_D5), GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), - GPIO_FN(VIO_D8), GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), - GPIO_FN(VIO_D11), GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), - GPIO_FN(VIO_D14), GPIO_FN(VIO_D15), - - /* USB0 */ - GPIO_FN(IDIN_0), GPIO_FN(EXTLP_0), GPIO_FN(OVCN2_0), - GPIO_FN(PWEN_0), GPIO_FN(OVCN_0), GPIO_FN(VBUS0_0), - - /* USB1 */ - GPIO_FN(IDIN_1_18), GPIO_FN(IDIN_1_113), - GPIO_FN(OVCN_1_114), GPIO_FN(OVCN_1_162), - GPIO_FN(PWEN_1_115), GPIO_FN(PWEN_1_138), - GPIO_FN(EXTLP_1), GPIO_FN(OVCN2_1), - GPIO_FN(VBUS0_1), - - /* GPIO */ - GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPO0), GPIO_FN(GPO1), - - /* BSC */ - GPIO_FN(BS), GPIO_FN(WE1), GPIO_FN(CKO), - GPIO_FN(WAIT), GPIO_FN(RDWR), - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), - GPIO_FN(A3), GPIO_FN(A6), GPIO_FN(A7), - GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), - GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), - GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19), - GPIO_FN(A20), GPIO_FN(A21), GPIO_FN(A22), - GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(CS6A), - - /* BSC/FLCTL */ - GPIO_FN(RD_FSC), GPIO_FN(WE0_FWE), GPIO_FN(A4_FOE), - GPIO_FN(A5_FCDE), GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), GPIO_FN(D4_NAF4), - GPIO_FN(D5_NAF5), GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), GPIO_FN(D10_NAF10), - GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), - - /* SPU2 */ - GPIO_FN(VINT_I), - - /* FLCTL */ - GPIO_FN(FCE1), GPIO_FN(FCE0), GPIO_FN(FRB), - - /* HSI */ - GPIO_FN(GP_RX_FLAG), GPIO_FN(GP_RX_DATA), GPIO_FN(GP_TX_READY), - GPIO_FN(GP_RX_WAKE), GPIO_FN(MP_TX_FLAG), GPIO_FN(MP_TX_DATA), - GPIO_FN(MP_RX_READY), GPIO_FN(MP_TX_WAKE), - - /* MFI */ - GPIO_FN(MFIv6), - GPIO_FN(MFIv4), - - GPIO_FN(MEMC_BUSCLK_MEMC_A0), GPIO_FN(MEMC_ADV_MEMC_DREQ0), - GPIO_FN(MEMC_WAIT_MEMC_DREQ1), GPIO_FN(MEMC_CS1_MEMC_A1), - GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_NOE), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_INT), - - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), - - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), GPIO_FN(SIM_D), - - /* TPU */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO2_93), - GPIO_FN(TPU0TO2_99), GPIO_FN(TPU0TO3), - - /* I2C2 */ - GPIO_FN(I2C_SCL2), GPIO_FN(I2C_SDA2), - - /* I2C3(1) */ - GPIO_FN(I2C_SCL3), GPIO_FN(I2C_SDA3), - - /* I2C3(2) */ - GPIO_FN(I2C_SCL3S), GPIO_FN(I2C_SDA3S), - - /* I2C4(2) */ - GPIO_FN(I2C_SCL4), GPIO_FN(I2C_SDA4), - - /* I2C4(2) */ - GPIO_FN(I2C_SCL4S), GPIO_FN(I2C_SDA4S), - - /* KEYSC */ - GPIO_FN(KEYOUT0), GPIO_FN(KEYIN0_121), GPIO_FN(KEYIN0_136), - GPIO_FN(KEYOUT1), GPIO_FN(KEYIN1_122), GPIO_FN(KEYIN1_135), - GPIO_FN(KEYOUT2), GPIO_FN(KEYIN2_123), GPIO_FN(KEYIN2_134), - GPIO_FN(KEYOUT3), GPIO_FN(KEYIN3_124), GPIO_FN(KEYIN3_133), - GPIO_FN(KEYOUT4), GPIO_FN(KEYIN4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYIN5), GPIO_FN(KEYOUT6), GPIO_FN(KEYIN6), - GPIO_FN(KEYOUT7), GPIO_FN(KEYIN7), - - /* LCDC */ - GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDVSYN), - GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(LCDRD), - GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(LCDLCLK), - GPIO_FN(LCDDON), - - GPIO_FN(LCDD0), GPIO_FN(LCDD1), GPIO_FN(LCDD2), - GPIO_FN(LCDD3), GPIO_FN(LCDD4), GPIO_FN(LCDD5), - GPIO_FN(LCDD6), GPIO_FN(LCDD7), GPIO_FN(LCDD8), - GPIO_FN(LCDD9), GPIO_FN(LCDD10), GPIO_FN(LCDD11), - GPIO_FN(LCDD12), GPIO_FN(LCDD13), GPIO_FN(LCDD14), - GPIO_FN(LCDD15), GPIO_FN(LCDD16), GPIO_FN(LCDD17), - GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), - GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), - - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), - - /* IRDA */ - GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), - GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), - - /* TSIF1 */ - GPIO_FN(TS0_1SELECT), - GPIO_FN(TS0_2SELECT), - GPIO_FN(TS1_1SELECT), - GPIO_FN(TS1_2SELECT), - - GPIO_FN(TS_SPSYNC1), GPIO_FN(TS_SDAT1), - GPIO_FN(TS_SDEN1), GPIO_FN(TS_SCK1), - - /* TSIF2 */ - GPIO_FN(TS_SPSYNC2), GPIO_FN(TS_SDAT2), - GPIO_FN(TS_SDEN2), GPIO_FN(TS_SCK2), - - /* HDMI */ - GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), - - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), -}; +#undef PORTCR +#define PORTCR(nr, reg) \ + { \ + PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ + _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 } \ + } static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xE6051000), /* PORT0CR */ @@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), - PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), - PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), - PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), - PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), - PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), - PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), - PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), - PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), - PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), - PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), - PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), - PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), - PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), - PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), - PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), - PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), - PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), - PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), - PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), - PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), - PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), - PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), - PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), - PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), - PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), - PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), - PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), - PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), - PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), - PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), - PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), + PINMUX_IRQ(EXT_IRQ16L(0), 6, 162), + PINMUX_IRQ(EXT_IRQ16L(1), 12), + PINMUX_IRQ(EXT_IRQ16L(2), 4, 5), + PINMUX_IRQ(EXT_IRQ16L(3), 8, 16), + PINMUX_IRQ(EXT_IRQ16L(4), 17, 163), + PINMUX_IRQ(EXT_IRQ16L(5), 18), + PINMUX_IRQ(EXT_IRQ16L(6), 39, 164), + PINMUX_IRQ(EXT_IRQ16L(7), 40, 167), + PINMUX_IRQ(EXT_IRQ16L(8), 41, 168), + PINMUX_IRQ(EXT_IRQ16L(9), 42, 169), + PINMUX_IRQ(EXT_IRQ16L(10), 65), + PINMUX_IRQ(EXT_IRQ16L(11), 67), + PINMUX_IRQ(EXT_IRQ16L(12), 80, 137), + PINMUX_IRQ(EXT_IRQ16L(13), 81, 145), + PINMUX_IRQ(EXT_IRQ16L(14), 82, 146), + PINMUX_IRQ(EXT_IRQ16L(15), 83, 147), + PINMUX_IRQ(EXT_IRQ16H(16), 84, 170), + PINMUX_IRQ(EXT_IRQ16H(17), 85), + PINMUX_IRQ(EXT_IRQ16H(18), 86), + PINMUX_IRQ(EXT_IRQ16H(19), 87), + PINMUX_IRQ(EXT_IRQ16H(20), 92), + PINMUX_IRQ(EXT_IRQ16H(21), 93), + PINMUX_IRQ(EXT_IRQ16H(22), 94), + PINMUX_IRQ(EXT_IRQ16H(23), 95), + PINMUX_IRQ(EXT_IRQ16H(24), 112), + PINMUX_IRQ(EXT_IRQ16H(25), 119), + PINMUX_IRQ(EXT_IRQ16H(26), 121, 172), + PINMUX_IRQ(EXT_IRQ16H(27), 122, 180), + PINMUX_IRQ(EXT_IRQ16H(28), 123, 181), + PINMUX_IRQ(EXT_IRQ16H(29), 129, 182), + PINMUX_IRQ(EXT_IRQ16H(30), 130, 183), + PINMUX_IRQ(EXT_IRQ16H(31), 138, 184), +}; + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +struct sh7372_portcr_group { + unsigned int end_pin; + unsigned int offset; +}; + +static const struct sh7372_portcr_group sh7372_portcr_offsets[] = { + { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 }, + { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 }, +}; + +static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) { + const struct sh7372_portcr_group *group = + &sh7372_portcr_offsets[i]; + + if (i <= group->end_pin) + return pfc->window->virt + group->offset + pin; + } + + return NULL; +} + +static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *addr = sh7372_pinmux_portcr(pfc, pin); + u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; + } + + iowrite8(value, addr); +} + +static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { + .get_bias = sh7372_pinmux_get_bias, + .set_bias = sh7372_pinmux_set_bias, }; const struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", + .ops = &sh7372_pinmux_ops, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 587f7772abf2..7956df58d751 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -20,9 +20,12 @@ */ #include <linux/io.h> #include <linux/kernel.h> +#include <linux/module.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/slab.h> -#include <mach/sh73a0.h> #include <mach/irqs.h> #include "core.h" @@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = { static const unsigned int sdhi2_ctrl_mux[] = { SDHICMD2_MARK, SDHICLK2_MARK, }; +/* - TPU0 ------------------------------------------------------------------- */ +static const unsigned int tpu0_to0_pins[] = { + /* TO */ + 55, +}; +static const unsigned int tpu0_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu0_to1_pins[] = { + /* TO */ + 59, +}; +static const unsigned int tpu0_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu0_to2_pins[] = { + /* TO */ + 140, +}; +static const unsigned int tpu0_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu0_to3_pins[] = { + /* TO */ + 141, +}; +static const unsigned int tpu0_to3_mux[] = { + TPU0TO3_MARK, +}; +/* - TPU1 ------------------------------------------------------------------- */ +static const unsigned int tpu1_to0_pins[] = { + /* TO */ + 246, +}; +static const unsigned int tpu1_to0_mux[] = { + TPU1TO0_MARK, +}; +static const unsigned int tpu1_to1_0_pins[] = { + /* TO */ + 28, +}; +static const unsigned int tpu1_to1_0_mux[] = { + PORT28_TPU1TO1_MARK, +}; +static const unsigned int tpu1_to1_1_pins[] = { + /* TO */ + 29, +}; +static const unsigned int tpu1_to1_1_mux[] = { + PORT29_TPU1TO1_MARK, +}; +static const unsigned int tpu1_to2_pins[] = { + /* TO */ + 153, +}; +static const unsigned int tpu1_to2_mux[] = { + TPU1TO2_MARK, +}; +static const unsigned int tpu1_to3_pins[] = { + /* TO */ + 145, +}; +static const unsigned int tpu1_to3_mux[] = { + TPU1TO3_MARK, +}; +/* - TPU2 ------------------------------------------------------------------- */ +static const unsigned int tpu2_to0_pins[] = { + /* TO */ + 248, +}; +static const unsigned int tpu2_to0_mux[] = { + TPU2TO0_MARK, +}; +static const unsigned int tpu2_to1_pins[] = { + /* TO */ + 197, +}; +static const unsigned int tpu2_to1_mux[] = { + TPU2TO1_MARK, +}; +static const unsigned int tpu2_to2_pins[] = { + /* TO */ + 50, +}; +static const unsigned int tpu2_to2_mux[] = { + TPU2TO2_MARK, +}; +static const unsigned int tpu2_to3_pins[] = { + /* TO */ + 51, +}; +static const unsigned int tpu2_to3_mux[] = { + TPU2TO3_MARK, +}; +/* - TPU3 ------------------------------------------------------------------- */ +static const unsigned int tpu3_to0_pins[] = { + /* TO */ + 163, +}; +static const unsigned int tpu3_to0_mux[] = { + TPU3TO0_MARK, +}; +static const unsigned int tpu3_to1_pins[] = { + /* TO */ + 247, +}; +static const unsigned int tpu3_to1_mux[] = { + TPU3TO1_MARK, +}; +static const unsigned int tpu3_to2_pins[] = { + /* TO */ + 54, +}; +static const unsigned int tpu3_to2_mux[] = { + TPU3TO2_MARK, +}; +static const unsigned int tpu3_to3_pins[] = { + /* TO */ + 53, +}; +static const unsigned int tpu3_to3_mux[] = { + TPU3TO3_MARK, +}; +/* - TPU4 ------------------------------------------------------------------- */ +static const unsigned int tpu4_to0_pins[] = { + /* TO */ + 241, +}; +static const unsigned int tpu4_to0_mux[] = { + TPU4TO0_MARK, +}; +static const unsigned int tpu4_to1_pins[] = { + /* TO */ + 199, +}; +static const unsigned int tpu4_to1_mux[] = { + TPU4TO1_MARK, +}; +static const unsigned int tpu4_to2_pins[] = { + /* TO */ + 58, +}; +static const unsigned int tpu4_to2_mux[] = { + TPU4TO2_MARK, +}; +static const unsigned int tpu4_to3_pins[] = { + /* TO */ +}; +static const unsigned int tpu4_to3_mux[] = { + TPU4TO3_MARK, +}; /* - USB -------------------------------------------------------------------- */ static const unsigned int usb_vbus_pins[] = { /* VBUS */ @@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(tpu1_to0), + SH_PFC_PIN_GROUP(tpu1_to1_0), + SH_PFC_PIN_GROUP(tpu1_to1_1), + SH_PFC_PIN_GROUP(tpu1_to2), + SH_PFC_PIN_GROUP(tpu1_to3), + SH_PFC_PIN_GROUP(tpu2_to0), + SH_PFC_PIN_GROUP(tpu2_to1), + SH_PFC_PIN_GROUP(tpu2_to2), + SH_PFC_PIN_GROUP(tpu2_to3), + SH_PFC_PIN_GROUP(tpu3_to0), + SH_PFC_PIN_GROUP(tpu3_to1), + SH_PFC_PIN_GROUP(tpu3_to2), + SH_PFC_PIN_GROUP(tpu3_to3), + SH_PFC_PIN_GROUP(tpu4_to0), + SH_PFC_PIN_GROUP(tpu4_to1), + SH_PFC_PIN_GROUP(tpu4_to2), + SH_PFC_PIN_GROUP(tpu4_to3), SH_PFC_PIN_GROUP(usb_vbus), }; @@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = { "usb_vbus", }; +static const char * const tpu0_groups[] = { + "tpu0_to0", + "tpu0_to1", + "tpu0_to2", + "tpu0_to3", +}; + +static const char * const tpu1_groups[] = { + "tpu1_to0", + "tpu1_to1_0", + "tpu1_to1_1", + "tpu1_to2", + "tpu1_to3", +}; + +static const char * const tpu2_groups[] = { + "tpu2_to0", + "tpu2_to1", + "tpu2_to2", + "tpu2_to3", +}; + +static const char * const tpu3_groups[] = { + "tpu3_to0", + "tpu3_to1", + "tpu3_to2", + "tpu3_to3", +}; + +static const char * const tpu4_groups[] = { + "tpu4_to0", + "tpu4_to1", + "tpu4_to2", + "tpu4_to3", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(bsc), SH_PFC_FUNCTION(fsia), @@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(tpu1), + SH_PFC_FUNCTION(tpu2), + SH_PFC_FUNCTION(tpu3), + SH_PFC_FUNCTION(tpu4), SH_PFC_FUNCTION(usb), }; -#define PINMUX_FN_BASE GPIO_FN_GPI0 - -static const struct pinmux_func pinmux_func_gpios[] = { - /* Table 25-1 (Functions 0-7) */ - GPIO_FN(GPI0), - GPIO_FN(GPI1), - GPIO_FN(GPI2), - GPIO_FN(GPI3), - GPIO_FN(GPI4), - GPIO_FN(GPI5), - GPIO_FN(GPI6), - GPIO_FN(GPI7), - GPIO_FN(GPO7), \ - GPIO_FN(MFG0_OUT2), - GPIO_FN(GPO6), \ - GPIO_FN(MFG1_OUT2), - GPIO_FN(GPO5), \ - GPIO_FN(PORT16_VIO_CKOR), - GPIO_FN(PORT19_VIO_CKO2), - GPIO_FN(GPO0), - GPIO_FN(GPO1), - GPIO_FN(GPO2), \ - GPIO_FN(STATUS0), - GPIO_FN(GPO3), \ - GPIO_FN(STATUS1), - GPIO_FN(GPO4), \ - GPIO_FN(STATUS2), - GPIO_FN(VINT), - GPIO_FN(TCKON), - GPIO_FN(XDVFS1), \ - GPIO_FN(MFG0_OUT1), \ - GPIO_FN(PORT27_IROUT), - GPIO_FN(XDVFS2), \ - GPIO_FN(PORT28_TPU1TO1), - GPIO_FN(SIM_RST), \ - GPIO_FN(PORT29_TPU1TO1), - GPIO_FN(SIM_CLK), \ - GPIO_FN(PORT30_VIO_CKOR), - GPIO_FN(SIM_D), \ - GPIO_FN(PORT31_IROUT), - GPIO_FN(XWUP), - GPIO_FN(VACK), - GPIO_FN(XTAL1L), - GPIO_FN(PORT49_IROUT), \ - GPIO_FN(BBIF2_TSYNC2), \ - GPIO_FN(TPU2TO2), \ - - GPIO_FN(BBIF2_TSCK2), \ - GPIO_FN(TPU2TO3), \ - GPIO_FN(BBIF2_TXD2), - GPIO_FN(TPU3TO3), \ - GPIO_FN(TPU3TO2), \ - GPIO_FN(TPU0TO0), - GPIO_FN(A0), \ - GPIO_FN(BS_), - GPIO_FN(A12), \ - GPIO_FN(TPU4TO2), - GPIO_FN(A13), \ - GPIO_FN(TPU0TO1), - GPIO_FN(A14), \ - GPIO_FN(A15), \ - GPIO_FN(A16), \ - GPIO_FN(MSIOF0_SS1), - GPIO_FN(A17), \ - GPIO_FN(MSIOF0_TSYNC), - GPIO_FN(A18), \ - GPIO_FN(MSIOF0_TSCK), - GPIO_FN(A19), \ - GPIO_FN(MSIOF0_TXD), - GPIO_FN(A20), \ - GPIO_FN(MSIOF0_RSCK), - GPIO_FN(A21), \ - GPIO_FN(MSIOF0_RSYNC), - GPIO_FN(A22), \ - GPIO_FN(MSIOF0_MCK0), - GPIO_FN(A23), \ - GPIO_FN(MSIOF0_MCK1), - GPIO_FN(A24), \ - GPIO_FN(MSIOF0_RXD), - GPIO_FN(A25), \ - GPIO_FN(MSIOF0_SS2), - GPIO_FN(A26), \ - GPIO_FN(FCE1_), - GPIO_FN(DACK0), - GPIO_FN(FCE0_), \ - GPIO_FN(WAIT_), \ - GPIO_FN(DREQ0), - GPIO_FN(FRB), - GPIO_FN(CKO), - GPIO_FN(NBRSTOUT_), - GPIO_FN(NBRST_), - GPIO_FN(BBIF2_TXD), - GPIO_FN(BBIF2_RXD), - GPIO_FN(BBIF2_SYNC), - GPIO_FN(BBIF2_SCK), - GPIO_FN(MFG3_IN2), - GPIO_FN(MFG3_IN1), - GPIO_FN(BBIF1_SS2), \ - GPIO_FN(MFG3_OUT1), - GPIO_FN(HSI_RX_DATA), \ - GPIO_FN(BBIF1_RXD), - GPIO_FN(HSI_TX_WAKE), \ - GPIO_FN(BBIF1_TSCK), - GPIO_FN(HSI_TX_DATA), \ - GPIO_FN(BBIF1_TSYNC), - GPIO_FN(HSI_TX_READY), \ - GPIO_FN(BBIF1_TXD), - GPIO_FN(HSI_RX_READY), \ - GPIO_FN(BBIF1_RSCK), \ - GPIO_FN(HSI_RX_WAKE), \ - GPIO_FN(BBIF1_RSYNC), \ - GPIO_FN(HSI_RX_FLAG), \ - GPIO_FN(BBIF1_SS1), \ - GPIO_FN(BBIF1_FLOW), - GPIO_FN(HSI_TX_FLAG), - GPIO_FN(VIO_VD), \ - GPIO_FN(VIO2_VD), \ - - GPIO_FN(VIO_HD), \ - GPIO_FN(VIO2_HD), \ - GPIO_FN(VIO_D0), \ - GPIO_FN(PORT130_MSIOF2_RXD), \ - GPIO_FN(VIO_D1), \ - GPIO_FN(PORT131_MSIOF2_SS1), \ - GPIO_FN(VIO_D2), \ - GPIO_FN(PORT132_MSIOF2_SS2), \ - GPIO_FN(VIO_D3), \ - GPIO_FN(MSIOF2_TSYNC), \ - GPIO_FN(VIO_D4), \ - GPIO_FN(MSIOF2_TXD), \ - GPIO_FN(VIO_D5), \ - GPIO_FN(MSIOF2_TSCK), \ - GPIO_FN(VIO_D6), \ - GPIO_FN(VIO_D7), \ - GPIO_FN(VIO_D8), \ - GPIO_FN(VIO2_D0), \ - GPIO_FN(VIO_D9), \ - GPIO_FN(VIO2_D1), \ - GPIO_FN(VIO_D10), \ - GPIO_FN(TPU0TO2), \ - GPIO_FN(VIO2_D2), \ - GPIO_FN(VIO_D11), \ - GPIO_FN(TPU0TO3), \ - GPIO_FN(VIO2_D3), \ - GPIO_FN(VIO_D12), \ - GPIO_FN(VIO2_D4), \ - GPIO_FN(VIO_D13), \ - GPIO_FN(VIO2_D5), \ - GPIO_FN(VIO_D14), \ - GPIO_FN(VIO2_D6), \ - GPIO_FN(VIO_D15), \ - GPIO_FN(TPU1TO3), \ - GPIO_FN(VIO2_D7), \ - GPIO_FN(VIO_CLK), \ - GPIO_FN(VIO2_CLK), \ - GPIO_FN(VIO_FIELD), \ - GPIO_FN(VIO2_FIELD), \ - GPIO_FN(VIO_CKO), - GPIO_FN(A27), \ - GPIO_FN(MFG0_IN1), \ - GPIO_FN(MFG0_IN2), - GPIO_FN(TS_SPSYNC3), \ - GPIO_FN(MSIOF2_RSCK), - GPIO_FN(TS_SDAT3), \ - GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(TPU1TO2), \ - GPIO_FN(TS_SDEN3), \ - GPIO_FN(PORT153_MSIOF2_SS1), - GPIO_FN(MSIOF2_MCK0), - GPIO_FN(MSIOF2_MCK1), - GPIO_FN(PORT156_MSIOF2_SS2), - GPIO_FN(PORT157_MSIOF2_RXD), - GPIO_FN(DINT_), \ - GPIO_FN(TS_SCK3), - GPIO_FN(NMI), - GPIO_FN(TPU3TO0), - GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(BBIF2_TSCK1), - GPIO_FN(BBIF2_TXD1), - GPIO_FN(MFG2_OUT2), \ - GPIO_FN(TPU2TO1), - GPIO_FN(TPU4TO1), \ - GPIO_FN(MFG4_OUT2), - GPIO_FN(D16), - GPIO_FN(D17), - GPIO_FN(D18), - GPIO_FN(D19), - GPIO_FN(D20), - GPIO_FN(D21), - GPIO_FN(D22), - GPIO_FN(PORT207_MSIOF0L_SS1), \ - GPIO_FN(D23), - GPIO_FN(PORT208_MSIOF0L_SS2), \ - GPIO_FN(D24), - GPIO_FN(D25), - GPIO_FN(DREQ2), \ - GPIO_FN(PORT210_MSIOF0L_SS1), \ - GPIO_FN(D26), - GPIO_FN(PORT211_MSIOF0L_SS2), \ - GPIO_FN(D27), - GPIO_FN(TS_SPSYNC1), \ - GPIO_FN(MSIOF0L_MCK0), \ - GPIO_FN(D28), - GPIO_FN(TS_SDAT1), \ - GPIO_FN(MSIOF0L_MCK1), \ - GPIO_FN(D29), - GPIO_FN(TS_SDEN1), \ - GPIO_FN(MSIOF0L_RSCK), \ - GPIO_FN(D30), - GPIO_FN(TS_SCK1), \ - GPIO_FN(MSIOF0L_RSYNC), \ - GPIO_FN(D31), - GPIO_FN(DACK2), \ - GPIO_FN(MSIOF0L_TSYNC), \ - GPIO_FN(VIO2_FIELD3), \ - GPIO_FN(DACK3), \ - GPIO_FN(PORT218_VIO_CKOR), - GPIO_FN(DREQ3), \ - GPIO_FN(MSIOF0L_TSCK), \ - GPIO_FN(VIO2_CLK3), \ - GPIO_FN(DREQ1), \ - GPIO_FN(PWEN), \ - GPIO_FN(MSIOF0L_RXD), \ - GPIO_FN(VIO2_HD3), \ - GPIO_FN(DACK1), \ - GPIO_FN(OVCN), \ - GPIO_FN(MSIOF0L_TXD), \ - GPIO_FN(VIO2_VD3), \ - - GPIO_FN(OVCN2), - GPIO_FN(EXTLP), \ - GPIO_FN(PORT226_VIO_CKO2), - GPIO_FN(IDIN), - GPIO_FN(MFG1_IN1), - GPIO_FN(MSIOF1_TXD), \ - GPIO_FN(MSIOF1_TSYNC), \ - GPIO_FN(MSIOF1_TSCK), \ - GPIO_FN(MSIOF1_RXD), \ - GPIO_FN(MSIOF1_RSCK), \ - GPIO_FN(VIO2_CLK2), \ - GPIO_FN(MSIOF1_RSYNC), \ - GPIO_FN(MFG1_IN2), \ - GPIO_FN(VIO2_VD2), \ - GPIO_FN(MSIOF1_MCK0), \ - GPIO_FN(MSIOF1_MCK1), \ - GPIO_FN(MSIOF1_SS1), \ - GPIO_FN(VIO2_FIELD2), \ - GPIO_FN(MSIOF1_SS2), \ - GPIO_FN(VIO2_HD2), \ - GPIO_FN(PORT241_IROUT), \ - GPIO_FN(MFG4_OUT1), \ - GPIO_FN(TPU4TO0), - GPIO_FN(MFG4_IN2), - GPIO_FN(PORT243_VIO_CKO2), - GPIO_FN(MFG2_IN1), \ - GPIO_FN(MSIOF2R_RXD), - GPIO_FN(MFG2_IN2), \ - GPIO_FN(MSIOF2R_TXD), - GPIO_FN(MFG1_OUT1), \ - GPIO_FN(TPU1TO0), - GPIO_FN(MFG3_OUT2), \ - GPIO_FN(TPU3TO1), - GPIO_FN(MFG2_OUT1), \ - GPIO_FN(TPU2TO0), \ - GPIO_FN(MSIOF2R_TSCK), - GPIO_FN(PORT249_IROUT), \ - GPIO_FN(MFG4_IN1), \ - GPIO_FN(MSIOF2R_TSYNC), - GPIO_FN(SDHICLK0), - GPIO_FN(SDHICD0), - GPIO_FN(SDHID0_0), - GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), - GPIO_FN(SDHID0_3), - GPIO_FN(SDHICMD0), - GPIO_FN(SDHIWP0), - GPIO_FN(SDHICLK1), - GPIO_FN(SDHID1_0), \ - GPIO_FN(TS_SPSYNC2), - GPIO_FN(SDHID1_1), \ - GPIO_FN(TS_SDAT2), - GPIO_FN(SDHID1_2), \ - GPIO_FN(TS_SDEN2), - GPIO_FN(SDHID1_3), \ - GPIO_FN(TS_SCK2), - GPIO_FN(SDHICMD1), - GPIO_FN(SDHICLK2), - GPIO_FN(SDHID2_0), \ - GPIO_FN(TS_SPSYNC4), - GPIO_FN(SDHID2_1), \ - GPIO_FN(TS_SDAT4), - GPIO_FN(SDHID2_2), \ - GPIO_FN(TS_SDEN4), - GPIO_FN(SDHID2_3), \ - GPIO_FN(TS_SCK4), - GPIO_FN(SDHICMD2), - GPIO_FN(MMCCLK0), - GPIO_FN(MMCD0_0), - GPIO_FN(MMCD0_1), - GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), - GPIO_FN(MMCD0_4), \ - GPIO_FN(TS_SPSYNC5), - GPIO_FN(MMCD0_5), \ - GPIO_FN(TS_SDAT5), - GPIO_FN(MMCD0_6), \ - GPIO_FN(TS_SDEN5), - GPIO_FN(MMCD0_7), \ - GPIO_FN(TS_SCK5), - GPIO_FN(MMCCMD0), - GPIO_FN(RESETOUTS_), \ - GPIO_FN(EXTAL2OUT), - GPIO_FN(MCP_WAIT__MCP_FRB), - GPIO_FN(MCP_CKO), \ - GPIO_FN(MMCCLK1), - GPIO_FN(MCP_D15_MCP_NAF15), - GPIO_FN(MCP_D14_MCP_NAF14), - GPIO_FN(MCP_D13_MCP_NAF13), - GPIO_FN(MCP_D12_MCP_NAF12), - GPIO_FN(MCP_D11_MCP_NAF11), - GPIO_FN(MCP_D10_MCP_NAF10), - GPIO_FN(MCP_D9_MCP_NAF9), - GPIO_FN(MCP_D8_MCP_NAF8), \ - GPIO_FN(MMCCMD1), - GPIO_FN(MCP_D7_MCP_NAF7), \ - GPIO_FN(MMCD1_7), - - GPIO_FN(MCP_D6_MCP_NAF6), \ - GPIO_FN(MMCD1_6), - GPIO_FN(MCP_D5_MCP_NAF5), \ - GPIO_FN(MMCD1_5), - GPIO_FN(MCP_D4_MCP_NAF4), \ - GPIO_FN(MMCD1_4), - GPIO_FN(MCP_D3_MCP_NAF3), \ - GPIO_FN(MMCD1_3), - GPIO_FN(MCP_D2_MCP_NAF2), \ - GPIO_FN(MMCD1_2), - GPIO_FN(MCP_D1_MCP_NAF1), \ - GPIO_FN(MMCD1_1), - GPIO_FN(MCP_D0_MCP_NAF0), \ - GPIO_FN(MMCD1_0), - GPIO_FN(MCP_NBRSTOUT_), - GPIO_FN(MCP_WE0__MCP_FWE), \ - GPIO_FN(MCP_RDWR_MCP_FWE), - - /* MSEL2 special cases */ - GPIO_FN(TSIF2_TS_XX1), - GPIO_FN(TSIF2_TS_XX2), - GPIO_FN(TSIF2_TS_XX3), - GPIO_FN(TSIF2_TS_XX4), - GPIO_FN(TSIF2_TS_XX5), - GPIO_FN(TSIF1_TS_XX1), - GPIO_FN(TSIF1_TS_XX2), - GPIO_FN(TSIF1_TS_XX3), - GPIO_FN(TSIF1_TS_XX4), - GPIO_FN(TSIF1_TS_XX5), - GPIO_FN(TSIF0_TS_XX1), - GPIO_FN(TSIF0_TS_XX2), - GPIO_FN(TSIF0_TS_XX3), - GPIO_FN(TSIF0_TS_XX4), - GPIO_FN(TSIF0_TS_XX5), - GPIO_FN(MST1_TS_XX1), - GPIO_FN(MST1_TS_XX2), - GPIO_FN(MST1_TS_XX3), - GPIO_FN(MST1_TS_XX4), - GPIO_FN(MST1_TS_XX5), - GPIO_FN(MST0_TS_XX1), - GPIO_FN(MST0_TS_XX2), - GPIO_FN(MST0_TS_XX3), - GPIO_FN(MST0_TS_XX4), - GPIO_FN(MST0_TS_XX5), - - /* MSEL3 special cases */ - GPIO_FN(SDHI0_VCCQ_MC0_ON), - GPIO_FN(SDHI0_VCCQ_MC0_OFF), - GPIO_FN(DEBUG_MON_VIO), - GPIO_FN(DEBUG_MON_LCDD), - GPIO_FN(LCDC_LCDC0), - GPIO_FN(LCDC_LCDC1), - - /* MSEL4 special cases */ - GPIO_FN(IRQ9_MEM_INT), - GPIO_FN(IRQ9_MCP_INT), - GPIO_FN(A11), - GPIO_FN(TPU4TO3), - GPIO_FN(RESETA_N_PU_ON), - GPIO_FN(RESETA_N_PU_OFF), - GPIO_FN(EDBGREQ_PD), - GPIO_FN(EDBGREQ_PU), -}; - #undef PORTCR #define PORTCR(nr, reg) \ { \ @@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(EXT_IRQ16L(9), 308), }; +/* ----------------------------------------------------------------------------- + * VCCQ MC0 regulator + */ + +static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) +{ + struct sh_pfc *pfc = reg->reg_data; + void __iomem *addr = pfc->window[1].virt + 4; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pfc->lock, flags); + + value = ioread32(addr); + + if (enable) + value |= BIT(28); + else + value &= ~BIT(28); + + iowrite32(value, addr); + + spin_unlock_irqrestore(&pfc->lock, flags); +} + +static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg) +{ + sh73a0_vccq_mc0_endisable(reg, true); + return 0; +} + +static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) +{ + sh73a0_vccq_mc0_endisable(reg, false); + return 0; +} + +static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) +{ + struct sh_pfc *pfc = reg->reg_data; + void __iomem *addr = pfc->window[1].virt + 4; + unsigned long flags; + u32 value; + + spin_lock_irqsave(&pfc->lock, flags); + value = ioread32(addr); + spin_unlock_irqrestore(&pfc->lock, flags); + + return !!(value & BIT(28)); +} + +static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) +{ + return 3300000; +} + +static struct regulator_ops sh73a0_vccq_mc0_ops = { + .enable = sh73a0_vccq_mc0_enable, + .disable = sh73a0_vccq_mc0_disable, + .is_enabled = sh73a0_vccq_mc0_is_enabled, + .get_voltage = sh73a0_vccq_mc0_get_voltage, +}; + +static const struct regulator_desc sh73a0_vccq_mc0_desc = { + .owner = THIS_MODULE, + .name = "vccq_mc0", + .type = REGULATOR_VOLTAGE, + .ops = &sh73a0_vccq_mc0_ops, +}; + +static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = { + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), +}; + +static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers), + .consumer_supplies = sh73a0_vccq_mc0_consumers, +}; + +/* ----------------------------------------------------------------------------- + * Pin bias + */ + #define PORTnCR_PULMD_OFF (0 << 6) #define PORTnCR_PULMD_DOWN (2 << 6) #define PORTnCR_PULMD_UP (3 << 6) @@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, iowrite8(value, addr); } +/* ----------------------------------------------------------------------------- + * SoC information + */ + +struct sh73a0_pinmux_data { + struct regulator_dev *vccq_mc0; +}; + +static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) +{ + struct sh73a0_pinmux_data *data; + struct regulator_config cfg = { }; + int ret; + + data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + + cfg.dev = pfc->dev; + cfg.init_data = &sh73a0_vccq_mc0_init_data; + cfg.driver_data = pfc; + + data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg); + if (IS_ERR(data->vccq_mc0)) { + ret = PTR_ERR(data->vccq_mc0); + dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", + ret); + return ret; + } + + pfc->soc_data = data; + + return 0; +} + +static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc) +{ + struct sh73a0_pinmux_data *data = pfc->soc_data; + + regulator_unregister(data->vccq_mc0); +} + static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { + .init = sh73a0_pinmux_soc_init, + .exit = sh73a0_pinmux_soc_exit, .get_bias = sh73a0_pinmux_get_bias, .set_bias = sh73a0_pinmux_set_bias, }; @@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { .functions = pinmux_functions, .nr_functions = ARRAY_SIZE(pinmux_functions), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), - .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 3b785fc428d5..830ae1ffd0b5 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -11,8 +11,8 @@ #ifndef __SH_PFC_H #define __SH_PFC_H +#include <linux/bug.h> #include <linux/stringify.h> -#include <asm-generic/gpio.h> typedef unsigned short pinmux_enum_t; @@ -129,6 +129,8 @@ struct pinmux_range { struct sh_pfc; struct sh_pfc_soc_operations { + int (*init)(struct sh_pfc *pfc); + void (*exit)(struct sh_pfc *pfc); unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index d4d377c40ec9..ce1743d0b679 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -14,8 +14,9 @@ config OMAP_REMOTEPROC depends on HAS_DMA depends on ARCH_OMAP4 || SOC_OMAP5 depends on OMAP_IOMMU - depends on OMAP_MBOX_FWK select REMOTEPROC + select MAILBOX + select OMAP2PLUS_MBOX select RPMSG help Say y here to support OMAP's remote processors (dual M3 diff --git a/drivers/remoteproc/omap_remoteproc.c b/drivers/remoteproc/omap_remoteproc.c index 0e396c155b3b..51689721ea7a 100644 --- a/drivers/remoteproc/omap_remoteproc.c +++ b/drivers/remoteproc/omap_remoteproc.c @@ -27,8 +27,8 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/remoteproc.h> +#include <linux/omap-mailbox.h> -#include <plat/mailbox.h> #include <linux/platform_data/remoteproc-omap.h> #include "omap_remoteproc.h" diff --git a/drivers/staging/tidspbridge/Kconfig b/drivers/staging/tidspbridge/Kconfig index 60848f198b48..165b918b8171 100644 --- a/drivers/staging/tidspbridge/Kconfig +++ b/drivers/staging/tidspbridge/Kconfig @@ -5,7 +5,8 @@ menuconfig TIDSPBRIDGE tristate "DSP Bridge driver" depends on ARCH_OMAP3 && !ARCH_MULTIPLATFORM - select OMAP_MBOX_FWK + select MAILBOX + select OMAP2PLUS_MBOX help DSP/BIOS Bridge is designed for platforms that contain a GPP and one or more attached DSPs. The GPP is considered the master or diff --git a/drivers/staging/tidspbridge/include/dspbridge/host_os.h b/drivers/staging/tidspbridge/include/dspbridge/host_os.h index 7f3a1db31619..d1441db469fc 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/host_os.h +++ b/drivers/staging/tidspbridge/include/dspbridge/host_os.h @@ -41,7 +41,7 @@ #include <linux/ioport.h> #include <linux/platform_device.h> #include <linux/clk.h> -#include <plat/mailbox.h> +#include <linux/omap-mailbox.h> #include <linux/pagemap.h> #include <asm/cacheflush.h> #include <linux/dma-mapping.h> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index f41aa0d0c414..1a27ef1df409 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -155,7 +155,7 @@ config USB_LPC32XX config USB_ATMEL_USBA tristate "Atmel USBA" - depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 + depends on AVR32 || ARCH_AT91 help USBA is the integrated high-speed USB Device controller on the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index 5a5128a226f7..1d9722203ca6 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -22,15 +22,13 @@ #include <linux/usb/atmel_usba_udc.h> #include <linux/delay.h> #include <linux/platform_data/atmel.h> +#include <linux/of.h> +#include <linux/of_gpio.h> #include <asm/gpio.h> #include "atmel_usba_udc.h" - -static struct usba_udc the_udc; -static struct usba_ep *usba_ep; - #ifdef CONFIG_USB_GADGET_DEBUG_FS #include <linux/debugfs.h> #include <linux/uaccess.h> @@ -1014,16 +1012,13 @@ static void nop_release(struct device *dev) } -static struct usba_udc the_udc = { - .gadget = { - .ops = &usba_udc_ops, - .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list), - .max_speed = USB_SPEED_HIGH, - .name = "atmel_usba_udc", - .dev = { - .init_name = "gadget", - .release = nop_release, - }, +struct usb_gadget usba_gadget_template = { + .ops = &usba_udc_ops, + .max_speed = USB_SPEED_HIGH, + .name = "atmel_usba_udc", + .dev = { + .init_name = "gadget", + .release = nop_release, }, }; @@ -1147,7 +1142,7 @@ static int do_test_mode(struct usba_udc *udc) * Test_SE0_NAK: Force high-speed mode and set up ep0 * for Bulk IN transfers */ - ep = &usba_ep[0]; + ep = &udc->usba_ep[0]; usba_writel(udc, TST, USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH)); usba_ep_writel(ep, CFG, @@ -1165,7 +1160,7 @@ static int do_test_mode(struct usba_udc *udc) break; case 0x0400: /* Test_Packet */ - ep = &usba_ep[0]; + ep = &udc->usba_ep[0]; usba_ep_writel(ep, CFG, USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) | USBA_EPT_DIR_IN @@ -1668,7 +1663,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid) for (i = 1; i < USBA_NR_ENDPOINTS; i++) if (dma_status & (1 << i)) - usba_dma_irq(udc, &usba_ep[i]); + usba_dma_irq(udc, &udc->usba_ep[i]); } ep_status = USBA_BFEXT(EPT_INT, status); @@ -1677,10 +1672,10 @@ static irqreturn_t usba_udc_irq(int irq, void *devid) for (i = 0; i < USBA_NR_ENDPOINTS; i++) if (ep_status & (1 << i)) { - if (ep_is_control(&usba_ep[i])) - usba_control_irq(udc, &usba_ep[i]); + if (ep_is_control(&udc->usba_ep[i])) + usba_control_irq(udc, &udc->usba_ep[i]); else - usba_ep_irq(udc, &usba_ep[i]); + usba_ep_irq(udc, &udc->usba_ep[i]); } } @@ -1705,7 +1700,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid) DBG(DBG_BUS, "%s bus reset detected\n", usb_speed_string(udc->gadget.speed)); - ep0 = &usba_ep[0]; + ep0 = &udc->usba_ep[0]; ep0->ep.desc = &usba_ep0_desc; ep0->state = WAIT_FOR_SETUP; usba_ep_writel(ep0, CFG, @@ -1835,17 +1830,158 @@ static int atmel_usba_stop(struct usb_gadget *gadget, return 0; } -static int __init usba_udc_probe(struct platform_device *pdev) +#ifdef CONFIG_OF +static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev, + struct usba_udc *udc) +{ + u32 val; + const char *name; + enum of_gpio_flags flags; + struct device_node *np = pdev->dev.of_node; + struct device_node *pp; + int i, ret; + struct usba_ep *eps, *ep; + + udc->num_ep = 0; + + udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0, + &flags); + udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; + + pp = NULL; + while ((pp = of_get_next_child(np, pp))) + udc->num_ep++; + + eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep, + GFP_KERNEL); + if (!eps) + return ERR_PTR(-ENOMEM); + + udc->gadget.ep0 = &eps[0].ep; + + INIT_LIST_HEAD(&eps[0].ep.ep_list); + + pp = NULL; + i = 0; + while ((pp = of_get_next_child(np, pp))) { + ep = &eps[i]; + + ret = of_property_read_u32(pp, "reg", &val); + if (ret) { + dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret); + goto err; + } + ep->index = val; + + ret = of_property_read_u32(pp, "atmel,fifo-size", &val); + if (ret) { + dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret); + goto err; + } + ep->fifo_size = val; + + ret = of_property_read_u32(pp, "atmel,nb-banks", &val); + if (ret) { + dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret); + goto err; + } + ep->nr_banks = val; + + ep->can_dma = of_property_read_bool(pp, "atmel,can-dma"); + ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc"); + + ret = of_property_read_string(pp, "name", &name); + ep->ep.name = name; + + ep->ep_regs = udc->regs + USBA_EPT_BASE(i); + ep->dma_regs = udc->regs + USBA_DMA_BASE(i); + ep->fifo = udc->fifo + USBA_FIFO_BASE(i); + ep->ep.ops = &usba_ep_ops; + ep->ep.maxpacket = ep->fifo_size; + ep->udc = udc; + INIT_LIST_HEAD(&ep->queue); + + if (i) + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + + i++; + } + + return eps; +err: + return ERR_PTR(ret); +} +#else +static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev, + struct usba_udc *udc) +{ + return ERR_PTR(-ENOSYS); +} +#endif + +static struct usba_ep * usba_udc_pdata(struct platform_device *pdev, + struct usba_udc *udc) { struct usba_platform_data *pdata = pdev->dev.platform_data; + struct usba_ep *eps; + int i; + + if (!pdata) + return ERR_PTR(-ENXIO); + + eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep, + GFP_KERNEL); + if (!eps) + return ERR_PTR(-ENOMEM); + + udc->gadget.ep0 = &eps[0].ep; + + udc->vbus_pin = pdata->vbus_pin; + udc->vbus_pin_inverted = pdata->vbus_pin_inverted; + udc->num_ep = pdata->num_ep; + + INIT_LIST_HEAD(&eps[0].ep.ep_list); + + for (i = 0; i < pdata->num_ep; i++) { + struct usba_ep *ep = &eps[i]; + + ep->ep_regs = udc->regs + USBA_EPT_BASE(i); + ep->dma_regs = udc->regs + USBA_DMA_BASE(i); + ep->fifo = udc->fifo + USBA_FIFO_BASE(i); + ep->ep.ops = &usba_ep_ops; + ep->ep.name = pdata->ep[i].name; + ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size; + ep->udc = udc; + INIT_LIST_HEAD(&ep->queue); + ep->nr_banks = pdata->ep[i].nr_banks; + ep->index = pdata->ep[i].index; + ep->can_dma = pdata->ep[i].can_dma; + ep->can_isoc = pdata->ep[i].can_isoc; + + if (i) + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + } + + return eps; +} + +static int __init usba_udc_probe(struct platform_device *pdev) +{ struct resource *regs, *fifo; struct clk *pclk, *hclk; - struct usba_udc *udc = &the_udc; + struct usba_udc *udc; int irq, ret, i; + udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); + if (!udc) + return -ENOMEM; + + udc->gadget = usba_gadget_template; + INIT_LIST_HEAD(&udc->gadget.ep_list); + regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID); fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID); - if (!regs || !fifo || !pdata) + if (!regs || !fifo) return -ENXIO; irq = platform_get_irq(pdev, 0); @@ -1891,46 +2027,14 @@ static int __init usba_udc_probe(struct platform_device *pdev) usba_writel(udc, CTRL, USBA_DISABLE_MASK); clk_disable(pclk); - usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep, - GFP_KERNEL); - if (!usba_ep) - goto err_alloc_ep; - - the_udc.gadget.ep0 = &usba_ep[0].ep; - - INIT_LIST_HEAD(&usba_ep[0].ep.ep_list); - usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0); - usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0); - usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0); - usba_ep[0].ep.ops = &usba_ep_ops; - usba_ep[0].ep.name = pdata->ep[0].name; - usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size; - usba_ep[0].udc = &the_udc; - INIT_LIST_HEAD(&usba_ep[0].queue); - usba_ep[0].fifo_size = pdata->ep[0].fifo_size; - usba_ep[0].nr_banks = pdata->ep[0].nr_banks; - usba_ep[0].index = pdata->ep[0].index; - usba_ep[0].can_dma = pdata->ep[0].can_dma; - usba_ep[0].can_isoc = pdata->ep[0].can_isoc; - - for (i = 1; i < pdata->num_ep; i++) { - struct usba_ep *ep = &usba_ep[i]; - - ep->ep_regs = udc->regs + USBA_EPT_BASE(i); - ep->dma_regs = udc->regs + USBA_DMA_BASE(i); - ep->fifo = udc->fifo + USBA_FIFO_BASE(i); - ep->ep.ops = &usba_ep_ops; - ep->ep.name = pdata->ep[i].name; - ep->ep.maxpacket = pdata->ep[i].fifo_size; - ep->udc = &the_udc; - INIT_LIST_HEAD(&ep->queue); - ep->fifo_size = pdata->ep[i].fifo_size; - ep->nr_banks = pdata->ep[i].nr_banks; - ep->index = pdata->ep[i].index; - ep->can_dma = pdata->ep[i].can_dma; - ep->can_isoc = pdata->ep[i].can_isoc; + if (pdev->dev.of_node) + udc->usba_ep = atmel_udc_of_init(pdev, udc); + else + udc->usba_ep = usba_udc_pdata(pdev, udc); - list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + if (IS_ERR(udc->usba_ep)) { + ret = PTR_ERR(udc->usba_ep); + goto err_alloc_ep; } ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc); @@ -1941,16 +2045,12 @@ static int __init usba_udc_probe(struct platform_device *pdev) } udc->irq = irq; - if (gpio_is_valid(pdata->vbus_pin)) { - if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) { - udc->vbus_pin = pdata->vbus_pin; - udc->vbus_pin_inverted = pdata->vbus_pin_inverted; - + if (gpio_is_valid(udc->vbus_pin)) { + if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) { ret = request_irq(gpio_to_irq(udc->vbus_pin), usba_vbus_irq, 0, "atmel_usba_udc", udc); if (ret) { - gpio_free(udc->vbus_pin); udc->vbus_pin = -ENODEV; dev_warn(&udc->pdev->dev, "failed to request vbus irq; " @@ -1969,20 +2069,17 @@ static int __init usba_udc_probe(struct platform_device *pdev) goto err_add_udc; usba_init_debugfs(udc); - for (i = 1; i < pdata->num_ep; i++) - usba_ep_init_debugfs(udc, &usba_ep[i]); + for (i = 1; i < udc->num_ep; i++) + usba_ep_init_debugfs(udc, &udc->usba_ep[i]); return 0; err_add_udc: - if (gpio_is_valid(pdata->vbus_pin)) { + if (gpio_is_valid(udc->vbus_pin)) free_irq(gpio_to_irq(udc->vbus_pin), udc); - gpio_free(udc->vbus_pin); - } free_irq(irq, udc); err_request_irq: - kfree(usba_ep); err_alloc_ep: iounmap(udc->fifo); err_map_fifo: @@ -1999,23 +2096,20 @@ static int __exit usba_udc_remove(struct platform_device *pdev) { struct usba_udc *udc; int i; - struct usba_platform_data *pdata = pdev->dev.platform_data; udc = platform_get_drvdata(pdev); usb_del_gadget_udc(&udc->gadget); - for (i = 1; i < pdata->num_ep; i++) - usba_ep_cleanup_debugfs(&usba_ep[i]); + for (i = 1; i < udc->num_ep; i++) + usba_ep_cleanup_debugfs(&udc->usba_ep[i]); usba_cleanup_debugfs(udc); if (gpio_is_valid(udc->vbus_pin)) { free_irq(gpio_to_irq(udc->vbus_pin), udc); - gpio_free(udc->vbus_pin); } free_irq(udc->irq, udc); - kfree(usba_ep); iounmap(udc->fifo); iounmap(udc->regs); clk_put(udc->hclk); @@ -2024,11 +2118,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev) return 0; } +#if defined(CONFIG_OF) +static const struct of_device_id atmel_udc_dt_ids[] = { + { .compatible = "atmel,at91sam9rl-udc" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids); +#endif + static struct platform_driver udc_driver = { .remove = __exit_p(usba_udc_remove), .driver = { .name = "atmel_usba_udc", .owner = THIS_MODULE, + .of_match_table = of_match_ptr(atmel_udc_dt_ids), }, }; diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h index d65a61851d3d..2922db50befe 100644 --- a/drivers/usb/gadget/atmel_usba_udc.h +++ b/drivers/usb/gadget/atmel_usba_udc.h @@ -317,8 +317,10 @@ struct usba_udc { int irq; int vbus_pin; int vbus_pin_inverted; + int num_ep; struct clk *pclk; struct clk *hclk; + struct usba_ep *usba_ep; u16 devstatus; diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c index 2c80004e0a83..f0beee7b868e 100644 --- a/drivers/usb/musb/ux500.c +++ b/drivers/usb/musb/ux500.c @@ -25,11 +25,19 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/usb/musb-ux500.h> #include "musb_core.h" +static struct musb_hdrc_config ux500_musb_hdrc_config = { + .multipoint = true, + .dyn_fifo = true, + .num_eps = 16, + .ram_bits = 16, +}; + struct ux500_glue { struct device *dev; struct platform_device *musb; @@ -187,14 +195,57 @@ static const struct musb_platform_ops ux500_ops = { .set_vbus = ux500_musb_set_vbus, }; +static struct musb_hdrc_platform_data * +ux500_of_probe(struct platform_device *pdev, struct device_node *np) +{ + struct musb_hdrc_platform_data *pdata; + const char *mode; + int strlen; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return NULL; + + mode = of_get_property(np, "dr_mode", &strlen); + if (!mode) { + dev_err(&pdev->dev, "No 'dr_mode' property found\n"); + return NULL; + } + + if (strlen > 0) { + if (!strcmp(mode, "host")) + pdata->mode = MUSB_HOST; + if (!strcmp(mode, "otg")) + pdata->mode = MUSB_OTG; + if (!strcmp(mode, "peripheral")) + pdata->mode = MUSB_PERIPHERAL; + } + + return pdata; +} + static int ux500_probe(struct platform_device *pdev) { struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; + struct device_node *np = pdev->dev.of_node; struct platform_device *musb; struct ux500_glue *glue; struct clk *clk; int ret = -ENOMEM; + if (!pdata) { + if (np) { + pdata = ux500_of_probe(pdev, np); + if (!pdata) + goto err0; + + pdev->dev.platform_data = pdata; + } else { + dev_err(&pdev->dev, "no pdata or device tree found\n"); + goto err0; + } + } + glue = kzalloc(sizeof(*glue), GFP_KERNEL); if (!glue) { dev_err(&pdev->dev, "failed to allocate glue context\n"); @@ -221,14 +272,16 @@ static int ux500_probe(struct platform_device *pdev) } musb->dev.parent = &pdev->dev; - musb->dev.dma_mask = pdev->dev.dma_mask; + musb->dev.dma_mask = &pdev->dev.coherent_dma_mask; musb->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask; + musb->dev.of_node = pdev->dev.of_node; glue->dev = &pdev->dev; glue->musb = musb; glue->clk = clk; pdata->platform_ops = &ux500_ops; + pdata->config = &ux500_musb_hdrc_config; platform_set_drvdata(pdev, glue); @@ -320,12 +373,18 @@ static const struct dev_pm_ops ux500_pm_ops = { #define DEV_PM_OPS NULL #endif +static const struct of_device_id ux500_match[] = { + { .compatible = "stericsson,db8500-musb", }, + {} +}; + static struct platform_driver ux500_driver = { .probe = ux500_probe, .remove = ux500_remove, .driver = { .name = "musb-ux500", .pm = DEV_PM_OPS, + .of_match_table = ux500_match, }, }; diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c index 338120641145..7d80699a5ff7 100644 --- a/drivers/usb/musb/ux500_dma.c +++ b/drivers/usb/musb/ux500_dma.c @@ -34,6 +34,11 @@ #include <linux/platform_data/usb-musb-ux500.h> #include "musb_core.h" +static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12", + "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" }; +static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12", + "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" }; + struct ux500_dma_channel { struct dma_channel channel; struct ux500_dma_controller *controller; @@ -48,10 +53,8 @@ struct ux500_dma_channel { struct ux500_dma_controller { struct dma_controller controller; - struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS]; - struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS]; - u32 num_rx_channels; - u32 num_tx_channels; + struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]; + struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]; void *private_data; dma_addr_t phy_base; }; @@ -144,19 +147,15 @@ static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c, struct ux500_dma_channel *ux500_channel = NULL; struct musb *musb = controller->private_data; u8 ch_num = hw_ep->epnum - 1; - u32 max_ch; - /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated + /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated * to specified hw_ep. For example DMA channel 0 can only be allocated * to hw_ep 1 and 9. */ if (ch_num > 7) ch_num -= 8; - max_ch = is_tx ? controller->num_tx_channels : - controller->num_rx_channels; - - if (ch_num >= max_ch) + if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS) return NULL; ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : @@ -264,7 +263,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c) struct dma_channel *channel; u8 ch_num; - for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) { + for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) { channel = &controller->rx_channel[ch_num].channel; ux500_channel = channel->private_data; @@ -274,7 +273,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c) dma_release_channel(ux500_channel->dma_chan); } - for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) { + for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) { channel = &controller->tx_channel[ch_num].channel; ux500_channel = channel->private_data; @@ -295,34 +294,36 @@ static int ux500_dma_controller_start(struct dma_controller *c) struct musb *musb = controller->private_data; struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; - struct ux500_musb_board_data *data = plat->board_data; + struct ux500_musb_board_data *data; struct dma_channel *dma_channel = NULL; + char **chan_names; u32 ch_num; u8 dir; u8 is_tx = 0; void **param_array; struct ux500_dma_channel *channel_array; - u32 ch_count; dma_cap_mask_t mask; - if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) || - (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS)) + if (!plat) { + dev_err(musb->controller, "No platform data\n"); return -EINVAL; + } - controller->num_rx_channels = data->num_rx_channels; - controller->num_tx_channels = data->num_tx_channels; + data = plat->board_data; dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); /* Prepare the loop for RX channels */ channel_array = controller->rx_channel; - ch_count = data->num_rx_channels; - param_array = data->dma_rx_param_array; + param_array = data ? data->dma_rx_param_array : NULL; + chan_names = (char **)iep_chan_names; for (dir = 0; dir < 2; dir++) { - for (ch_num = 0; ch_num < ch_count; ch_num++) { + for (ch_num = 0; + ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; + ch_num++) { ux500_channel = &channel_array[ch_num]; ux500_channel->controller = controller; ux500_channel->ch_num = ch_num; @@ -333,9 +334,15 @@ static int ux500_dma_controller_start(struct dma_controller *c) dma_channel->status = MUSB_DMA_STATUS_FREE; dma_channel->max_len = SZ_16M; - ux500_channel->dma_chan = dma_request_channel(mask, - data->dma_filter, - param_array[ch_num]); + ux500_channel->dma_chan = + dma_request_slave_channel(dev, chan_names[ch_num]); + + if (!ux500_channel->dma_chan) + ux500_channel->dma_chan = + dma_request_channel(mask, + data->dma_filter, + param_array[ch_num]); + if (!ux500_channel->dma_chan) { ERR("Dma pipe allocation error dir=%d ch=%d\n", dir, ch_num); @@ -350,8 +357,8 @@ static int ux500_dma_controller_start(struct dma_controller *c) /* Prepare the loop for TX channels */ channel_array = controller->tx_channel; - ch_count = data->num_tx_channels; - param_array = data->dma_tx_param_array; + param_array = data ? data->dma_tx_param_array : NULL; + chan_names = (char **)oep_chan_names; is_tx = 1; } diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h new file mode 100644 index 000000000000..d7988b4d8af9 --- /dev/null +++ b/include/dt-bindings/pinctrl/at91.h @@ -0,0 +1,35 @@ +/* + * This header provides constants for most at91 pinctrl bindings. + * + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * GPLv2 only + */ + +#ifndef __DT_BINDINGS_AT91_PINCTRL_H__ +#define __DT_BINDINGS_AT91_PINCTRL_H__ + +#define AT91_PINCTRL_NONE (0 << 0) +#define AT91_PINCTRL_PULL_UP (1 << 0) +#define AT91_PINCTRL_MULTI_DRIVE (1 << 1) +#define AT91_PINCTRL_DEGLITCH (1 << 2) +#define AT91_PINCTRL_PULL_DOWN (1 << 3) +#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) +#define AT91_PINCTRL_DEBOUNCE (1 << 16) +#define AT91_PINCTRL_DEBOUNCE_VA(x) (x << 17) + +#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) + +#define AT91_PIOA 0 +#define AT91_PIOB 1 +#define AT91_PIOC 2 +#define AT91_PIOD 3 +#define AT91_PIOE 4 + +#define AT91_PERIPH_GPIO 0 +#define AT91_PERIPH_A 1 +#define AT91_PERIPH_B 2 +#define AT91_PERIPH_C 3 +#define AT91_PERIPH_D 4 + +#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h index dd755ce2a5eb..07261d52a6df 100644 --- a/include/linux/dw_apb_timer.h +++ b/include/linux/dw_apb_timer.h @@ -53,5 +53,4 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs); cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs); void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs); -extern void dw_apb_timer_init(void); #endif /* __DW_APB_TIMER_H__ */ diff --git a/include/linux/omap-mailbox.h b/include/linux/omap-mailbox.h new file mode 100644 index 000000000000..f8322d9cd235 --- /dev/null +++ b/include/linux/omap-mailbox.h @@ -0,0 +1,29 @@ +/* + * omap-mailbox: interprocessor communication module for OMAP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef OMAP_MAILBOX_H +#define OMAP_MAILBOX_H + +typedef u32 mbox_msg_t; +struct omap_mbox; + +typedef int __bitwise omap_mbox_irq_t; +#define IRQ_TX ((__force omap_mbox_irq_t) 1) +#define IRQ_RX ((__force omap_mbox_irq_t) 2) + +int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); + +struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb); +void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb); + +void omap_mbox_save_ctx(struct omap_mbox *mbox); +void omap_mbox_restore_ctx(struct omap_mbox *mbox); +void omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq); +void omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq); + +#endif /* OMAP_MAILBOX_H */ diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h index 4b781014b0a0..1bb9b1852256 100644 --- a/include/linux/platform_data/dma-ste-dma40.h +++ b/include/linux/platform_data/dma-ste-dma40.h @@ -70,23 +70,8 @@ enum stedma40_flow_ctrl { STEDMA40_FLOW_CTRL, }; -enum stedma40_periph_data_width { - STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT, - STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT, - STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT, - STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT -}; - -enum stedma40_xfer_dir { - STEDMA40_MEM_TO_MEM = 1, - STEDMA40_MEM_TO_PERIPH, - STEDMA40_PERIPH_TO_MEM, - STEDMA40_PERIPH_TO_PERIPH -}; - - /** - * struct stedma40_chan_cfg - dst/src channel configuration + * struct stedma40_half_channel_info - dst/src channel configuration * * @big_endian: true if the src/dst should be read as big endian * @data_width: Data width of the src/dst hardware @@ -95,7 +80,7 @@ enum stedma40_xfer_dir { */ struct stedma40_half_channel_info { bool big_endian; - enum stedma40_periph_data_width data_width; + enum dma_slave_buswidth data_width; int psize; enum stedma40_flow_ctrl flow_ctrl; }; @@ -109,8 +94,7 @@ struct stedma40_half_channel_info { * version 3+, i.e DB8500v2+ * @mode: channel mode: physical, logical, or operation * @mode_opt: options for the chosen channel mode - * @src_dev_type: Src device type - * @dst_dev_type: Dst device type + * @dev_type: src/dst device type (driver uses dir to figure out which) * @src_info: Parameters for dst half channel * @dst_info: Parameters for dst half channel * @use_fixed_channel: if true, use physical channel specified by phy_channel @@ -121,13 +105,12 @@ struct stedma40_half_channel_info { * */ struct stedma40_chan_cfg { - enum stedma40_xfer_dir dir; + enum dma_transfer_direction dir; bool high_priority; bool realtime; enum stedma40_mode mode; enum stedma40_mode_opt mode_opt; - int src_dev_type; - int dst_dev_type; + int dev_type; struct stedma40_half_channel_info src_info; struct stedma40_half_channel_info dst_info; @@ -138,13 +121,8 @@ struct stedma40_chan_cfg { /** * struct stedma40_platform_data - Configuration struct for the dma device. * - * @dev_len: length of dev_tx and dev_rx * @dev_tx: mapping between destination event line and io address * @dev_rx: mapping between source event line and io address - * @memcpy: list of memcpy event lines - * @memcpy_len: length of memcpy - * @memcpy_conf_phy: default configuration of physical channel memcpy - * @memcpy_conf_log: default configuration of logical channel memcpy * @disabled_channels: A vector, ending with -1, that marks physical channels * that are for different reasons not available for the driver. * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW @@ -154,22 +132,17 @@ struct stedma40_chan_cfg { * @num_of_soft_lli_chans: The number of channels that needs to be configured * to use SoftLLI. * @use_esram_lcla: flag for mapping the lcla into esram region + * @num_of_memcpy_chans: The number of channels reserved for memcpy. * @num_of_phy_chans: The number of physical channels implemented in HW. * 0 means reading the number of channels from DMA HW but this is only valid * for 'multiple of 4' channels, like 8. */ struct stedma40_platform_data { - u32 dev_len; - const dma_addr_t *dev_tx; - const dma_addr_t *dev_rx; - int *memcpy; - u32 memcpy_len; - struct stedma40_chan_cfg *memcpy_conf_phy; - struct stedma40_chan_cfg *memcpy_conf_log; int disabled_channels[STEDMA40_MAX_PHYS]; int *soft_lli_chans; int num_of_soft_lli_chans; bool use_esram_lcla; + int num_of_memcpy_chans; int num_of_phy_chans; }; diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h index b253f77a7ddf..2d8d69432813 100644 --- a/include/linux/platform_data/gpio-rcar.h +++ b/include/linux/platform_data/gpio-rcar.h @@ -17,10 +17,13 @@ #define __GPIO_RCAR_H__ struct gpio_rcar_config { - unsigned int gpio_base; + int gpio_base; unsigned int irq_base; unsigned int number_of_pins; const char *pctl_name; + unsigned has_both_edge_trigger:1; }; +#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) + #endif /* __GPIO_RCAR_H__ */ diff --git a/include/linux/platform_data/mailbox-omap.h b/include/linux/platform_data/mailbox-omap.h new file mode 100644 index 000000000000..4631dbb4255e --- /dev/null +++ b/include/linux/platform_data/mailbox-omap.h @@ -0,0 +1,58 @@ +/* + * mailbox-omap.h + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLAT_MAILBOX_H +#define _PLAT_MAILBOX_H + +/* Interrupt register configuration types */ +#define MBOX_INTR_CFG_TYPE1 (0) +#define MBOX_INTR_CFG_TYPE2 (1) + +/** + * struct omap_mbox_dev_info - OMAP mailbox device attribute info + * @name: name of the mailbox device + * @tx_id: mailbox queue id used for transmitting messages + * @rx_id: mailbox queue id on which messages are received + * @irq_id: irq identifier number to use from the hwmod data + * @usr_id: mailbox user id for identifying the interrupt into + * the MPU interrupt controller. + */ +struct omap_mbox_dev_info { + const char *name; + u32 tx_id; + u32 rx_id; + u32 irq_id; + u32 usr_id; +}; + +/** + * struct omap_mbox_pdata - OMAP mailbox platform data + * @intr_type: type of interrupt configuration registers used + while programming mailbox queue interrupts + * @num_users: number of users (processor devices) that the mailbox + * h/w block can interrupt + * @num_fifos: number of h/w fifos within the mailbox h/w block + * @info_cnt: number of mailbox devices for the platform + * @info: array of mailbox device attributes + */ +struct omap_mbox_pdata { + u32 intr_type; + u32 num_users; + u32 num_fifos; + u32 info_cnt; + struct omap_mbox_dev_info *info; +}; + +#endif /* _PLAT_MAILBOX_H */ diff --git a/include/linux/platform_data/usb-musb-ux500.h b/include/linux/platform_data/usb-musb-ux500.h index 4c1cc50a595a..dd9c83ac7de0 100644 --- a/include/linux/platform_data/usb-musb-ux500.h +++ b/include/linux/platform_data/usb-musb-ux500.h @@ -9,14 +9,11 @@ #include <linux/dmaengine.h> -#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8 -#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8 +#define UX500_MUSB_DMA_NUM_RX_TX_CHANNELS 8 struct ux500_musb_board_data { void **dma_rx_param_array; void **dma_tx_param_array; - u32 num_rx_channels; - u32 num_tx_channels; bool (*dma_filter)(struct dma_chan *chan, void *filter_param); }; diff --git a/sound/soc/ux500/ux500_pcm.c b/sound/soc/ux500/ux500_pcm.c index b6e5ae277299..31f9bbc74521 100644 --- a/sound/soc/ux500/ux500_pcm.c +++ b/sound/soc/ux500/ux500_pcm.c @@ -76,20 +76,20 @@ static struct dma_chan *ux500_pcm_request_chan(struct snd_soc_pcm_runtime *rtd, dma_params = snd_soc_dai_get_dma_data(dai, substream); dma_cfg = dma_params->dma_cfg; - mem_data_width = STEDMA40_HALFWORD_WIDTH; + mem_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES; switch (dma_params->data_size) { case 32: - per_data_width = STEDMA40_WORD_WIDTH; + per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES; break; case 16: - per_data_width = STEDMA40_HALFWORD_WIDTH; + per_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES; break; case 8: - per_data_width = STEDMA40_BYTE_WIDTH; + per_data_width = DMA_SLAVE_BUSWIDTH_1_BYTE; break; default: - per_data_width = STEDMA40_WORD_WIDTH; + per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES; } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |