diff options
| -rw-r--r-- | Documentation/devicetree/bindings/net/ti,dp83822.yaml | 16 | ||||
| -rw-r--r-- | drivers/net/phy/dp83822.c | 44 |
2 files changed, 60 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml index 8f4350be689c..8f23254c0458 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83822.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml @@ -80,6 +80,22 @@ properties: 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000] default: 10000 + ti,rmii-mode: + description: | + If present, select the RMII operation mode. Two modes are + available: + - RMII master, where the PHY operates from a 25MHz clock reference, + provided by a crystal or a CMOS-level oscillator + - RMII slave, where the PHY operates from a 50MHz clock reference, + provided by a CMOS-level oscillator + The RMII operation mode can also be configured by its straps. + If the strap pin is not set correctly or not set at all, then this can be + used to configure it. + $ref: /schemas/types.yaml#/definitions/string + enum: + - master + - slave + required: - reg diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index 30f2616ab1c2..edc39ae4c241 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -100,6 +100,8 @@ #define DP83822_WOL_CLR_INDICATION BIT(11) /* RCSR bits */ +#define DP83822_RMII_MODE_EN BIT(5) +#define DP83822_RMII_MODE_SEL BIT(7) #define DP83822_RGMII_MODE_EN BIT(9) #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) @@ -494,12 +496,54 @@ static int dp83822_config_init(struct phy_device *phydev) return dp8382x_disable_wol(phydev); } +static int dp83826_config_rmii_mode(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + const char *of_val; + int ret; + + if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { + if (strcmp(of_val, "master") == 0) { + ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RMII_MODE_SEL); + } else if (strcmp(of_val, "slave") == 0) { + ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RMII_MODE_SEL); + } else { + phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", + of_val); + ret = -EINVAL; + } + + if (ret) + return ret; + } + + return 0; +} + static int dp83826_config_init(struct phy_device *phydev) { struct dp83822_private *dp83822 = phydev->priv; u16 val, mask; int ret; + if (phydev->interface == PHY_INTERFACE_MODE_RMII) { + ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RMII_MODE_EN); + if (ret) + return ret; + + ret = dp83826_config_rmii_mode(phydev); + if (ret) + return ret; + } else { + ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RMII_MODE_EN); + if (ret) + return ret; + } + if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, |