diff options
236 files changed, 9312 insertions, 2540 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml new file mode 100644 index 000000000000..a77f88223801 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Corstone1000 Device Tree Bindings + +maintainers: + - Vishnu Banavath <vishnu.banavath@arm.com> + - Rui Miguel Silva <rui.silva@linaro.org> + +description: |+ + ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that + provides a flexible compute architecture that combines Cortex‑A and Cortex‑M + processors. + + Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion + systems for M-Class (or other) processors for adding sensors, connectivity, + video, audio and machine learning at the edge System and security IPs to build + a secure SoC for a range of rich IoT applications, for example gateways, smart + cameras and embedded systems. + + Integrated Secure Enclave providing hardware Root of Trust and supporting + seamless integration of the optional CryptoCellâ„¢-312 cryptographic + accelerator. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA + implementation of the Corstone1000 in the MPS3 prototyping board. See + ARM document DAI0550. + items: + - const: arm,corstone1000-mps3 + - description: Corstone1000 FVP is the Fixed Virtual Platform + implementation of this system. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-fvp + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 434d3c6db61e..8b7e87fb6c34 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -64,6 +64,7 @@ properties: - description: BCM47094 based boards items: - enum: + - asus,rt-ac88u - dlink,dir-885l - linksys,panamera - luxul,abr-4500-v1 @@ -83,9 +84,14 @@ properties: - brcm,bcm953012er - brcm,bcm953012hr - brcm,bcm953012k + - const: brcm,bcm53012 + - const: brcm,bcm4708 + + - description: BCM53016 based boards + items: + - enum: - meraki,mr32 - - const: brcm,brcm53012 - - const: brcm,brcm53016 + - const: brcm,bcm53016 - const: brcm,bcm4708 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml new file mode 100644 index 000000000000..5fb455840417 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC device tree bindings + +description: + Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless + chips that can be used as home gateway, router and WLAN AP for residential, + enterprise and carrier applications. + +maintainers: + - William Zhang <william.zhang@broadcom.com> + - Anand Gore <anand.gore@broadcom.com> + - Kursad Oney <kursad.oney@broadcom.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM47622 based boards + items: + - enum: + - brcm,bcm947622 + - const: brcm,bcm47622 + - const: brcm,bcmbca + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 3eb6d7afff14..431ef8c56a13 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -31,12 +31,17 @@ Required properties: (base address and length) - clocks: clocks for this module - clockdomains: clockdomains for this module +- #clock-cells: From common clock binding +- clock-output-names: From common clock binding + Example: -cm: cm@48004000 { +cm: clock@48004000 { compatible = "ti,omap3-cm"; reg = <0x48004000 0x4000>; + #clock-cells = <0>; + clock-output-names = "cm"; cm_clocks: clocks { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index fa435d6fda77..f61807103867 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -406,6 +406,8 @@ properties: - description: RZ/G2UL (R9A07G043) items: - enum: + - renesas,smarc-evk # SMARC EVK + - enum: - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043 diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index fa0a1b84122e..8b31565fee59 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -14,21 +14,6 @@ properties: const: "/" compatible: oneOf: - - description: DH STM32MP1 SoM based Boards - items: - - enum: - - arrow,stm32mp157a-avenger96 # Avenger96 - - dh,stm32mp153c-dhcom-drc02 - - dh,stm32mp157c-dhcom-pdk2 - - dh,stm32mp157c-dhcom-picoitx - - enum: - - dh,stm32mp153c-dhcom-som - - dh,stm32mp157a-dhcor-som - - dh,stm32mp157c-dhcom-som - - enum: - - st,stm32mp153 - - st,stm32mp157 - - description: emtrion STM32MP1 Argon based Boards items: - const: emtrion,stm32mp157c-emsbc-argon @@ -65,6 +50,21 @@ properties: - enum: - st,stm32mp135f-dk - const: st,stm32mp135 + + - description: ST STM32MP151 based Boards + items: + - enum: + - prt,prtt1a # Protonic PRTT1A + - prt,prtt1c # Protonic PRTT1C + - prt,prtt1s # Protonic PRTT1S + - const: st,stm32mp151 + + - description: DH STM32MP153 SoM based Boards + items: + - const: dh,stm32mp153c-dhcom-drc02 + - const: dh,stm32mp153c-dhcom-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box @@ -72,13 +72,45 @@ properties: - st,stm32mp157c-ed1 - st,stm32mp157a-dk1 - st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157a-dk1-scmi + - const: st,stm32mp157a-dk1 - const: st,stm32mp157 - items: + - const: st,stm32mp157c-dk2-scmi + - const: st,stm32mp157c-dk2 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ed1-scmi + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1 + - const: st,stm32mp157c-ed1 + - const: st,stm32mp157 + - items: + - const: st,stm32mp157c-ev1-scmi - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - const: dh,stm32mp157a-dhcor-som + - const: st,stm32mp157 + + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - dh,stm32mp157c-dhcom-pdk2 + - dh,stm32mp157c-dhcom-picoitx + - const: dh,stm32mp157c-dhcom-som + - const: st,stm32mp157 + - description: Engicam i.Core STM32MP1 SoM based Boards items: - enum: @@ -103,6 +135,7 @@ properties: - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt index d8b48f2edf1b..851f48ead927 100644 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -18,10 +18,6 @@ stable binding/ABI. --------------------------------------------------------------- -Boards with the Synaptics AS370 SoC shall have the following properties: - Required root node property: - compatible: "syna,as370" - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: diff --git a/Documentation/devicetree/bindings/arm/ux500.yaml b/Documentation/devicetree/bindings/arm/ux500.yaml index a46193ad94e0..17accb31bca0 100644 --- a/Documentation/devicetree/bindings/arm/ux500.yaml +++ b/Documentation/devicetree/bindings/arm/ux500.yaml @@ -40,6 +40,11 @@ properties: - const: samsung,codina - const: st-ericsson,u8500 + - description: Samsung Galaxy Exhibit (SGH-T599) + items: + - const: samsung,codina-tmo + - const: st-ericsson,u8500 + - description: Samsung Galaxy Beam (GT-I8530) items: - const: samsung,gavini diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index a0ae4867ed27..bb0e0b92e907 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -58,6 +58,8 @@ properties: - st,stm32mp1-rcc-secure - st,stm32mp1-rcc - const: syscon + clocks: true + clock-names: true reg: maxItems: 1 @@ -68,6 +70,38 @@ required: - compatible - reg +if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-rcc-secure +then: + properties: + clocks: + description: Specifies oscillators. + maxItems: 5 + + clock-names: + items: + - const: hse + - const: hsi + - const: csi + - const: lse + - const: lsi + required: + - clocks + - clock-names +else: + properties: + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt index 18af6b9409e3..d20db7974a38 100644 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt @@ -21,6 +21,7 @@ Required properties : "ti,clkctrl-l4-per" "ti,clkctrl-l4-secure" "ti,clkctrl-l4-wkup" +- clock-output-names : from common clock binding - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index @@ -32,7 +33,8 @@ Example: Clock controller node on omap 4430: l4per: cm@1400 { cm_l4per@0 { cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt index cb76b3f2b341..9c6199249ce5 100644 --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt @@ -17,6 +17,9 @@ Required properties: - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of clocks within this domain +Optional properties: +- clock-output-names : from common clock binding. + Examples: dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt index 5f43c4706b09..33ac7c9ad053 100644 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -27,6 +27,9 @@ Required properties: - clocks : link phandles of component clocks - #clock-cells : from common clock binding; shall be set to 0. +Optional properties: +- clock-output-names : from common clock binding. + Examples: usb_l4_gate_ick: usb_l4_gate_ick { diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt index 662b36d53bf0..518e3c142276 100644 --- a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt +++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt @@ -16,6 +16,7 @@ Required properties: - clocks: parent clock. Optional properties: +- clock-output-names : from common clock binding. - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, see [2] - reg: offset for the autoidle register of this clock, see [2] diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt index 56d603c1f716..b4820b1de4f0 100644 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt @@ -36,6 +36,7 @@ Required properties: ti,clkdm-gate-clock type Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for programming the clock gate, invalid for ti,clkdm-gate-clock type - ti,set-bit-to-disable : inverts default gate programming. Setting the bit diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt index 3f4704040140..94ec77dc3c59 100644 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt @@ -28,6 +28,7 @@ Required properties: - reg : base address for the control register Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) Examples: diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt index eec8994b9be8..e17425a58621 100644 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -42,6 +42,7 @@ Required properties: - reg : register offset for register controlling adjustable mux Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : number of bits to shift the bit-mask, defaults to 0 if not present - ti,index-starts-at-one : valid input select programming starts at 1, not diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index bb433e75a0ee..c31eeb66319f 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -10,8 +10,8 @@ maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> description: - The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI - and supports following functions, + The RZ/{G2L,V2L}-alike System Controller (SYSC) performs system control of + the LSI and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -20,6 +20,7 @@ description: properties: compatible: enum: + - renesas,r9a07g043-sysc # RZ/G2UL - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L diff --git a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml index 105725a127ab..ce107fe45d7c 100644 --- a/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml +++ b/Documentation/devicetree/bindings/staging/net/wireless/silabs,wfx.yaml @@ -39,6 +39,7 @@ properties: compatible: items: - enum: + - prt,prtt1c-wfm200 # Protonic PRTT1C Board - silabs,brd4001a # WGM160P Evaluation Board - silabs,brd8022a # WF200 Evaluation Board - silabs,brd8023a # WFM200 Evaluation Board diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..e75d1ee122dc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -103,6 +103,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp2.dtb \ bcm4708-linksys-ea6300-v1.dtb \ bcm4708-linksys-ea6500-v2.dtb \ bcm4708-luxul-xap-1510.dtb \ @@ -179,6 +181,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ @@ -1156,10 +1160,14 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ @@ -1170,9 +1178,12 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ stm32mp157c-emsbc-argon.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ @@ -1382,6 +1393,7 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-ux500-samsung-janice.dtb \ ste-ux500-samsung-gavini.dtb \ ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ ste-ux500-samsung-skomer.dtb \ ste-ux500-samsung-kyle.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 366702630290..d3eafee79a23 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -285,7 +285,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 56ae5095a5b8..02e04a12a270 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -405,3 +405,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-bone-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 659e99eabe66..b9745a2f0e4d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -782,3 +782,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index a2db65538e51..9c458e5a95b7 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -719,3 +719,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 1918766c1f80..1a7e187b1953 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -29,39 +29,44 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - gpio_keys { + guardian_buttons: gpio-keys { + pinctrl-names = "default"; + pinctrl-0 = <&guardian_button_pins>; compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - button21 { + select-button { + label = "guardian-select-button"; + linux,code = <KEY_5>; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + power-button { label = "guardian-power-button"; linux,code = <KEY_POWER>; - gpios = <&gpio2 21 0>; + gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; wakeup-source; }; }; - leds { - compatible = "gpio-leds"; + guardian_leds: gpio-leds { pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; + pinctrl-0 = <&guardian_led_pins>; + compatible = "gpio-leds"; - led1 { - label = "green:heartbeat"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + life-led { + label = "guardian:life-led"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + }; - led2 { - label = "green:mmc0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; }; panel { @@ -100,20 +105,36 @@ }; - pwm7: dmtimer-pwm { + guardian_beeper: dmtimer-pwm@7 { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer7>; pinctrl-names = "default"; - pinctrl-0 = <&dmtimer7_pins>; + pinctrl-0 = <&guardian_beeper_pins>; ti,clock-source = <0x01>; }; - vmmcsd_fixed: regulator-3v3 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + mt_keypad: mt_keypad@0 { + compatible = "gpio-mt-keypad"; + debounce-delay-ms = <10>; + col-scan-delay-us = <2>; + keypad,num-lines = <5>; + linux,no-autorepeat; + gpio-activelow; + line-gpios = < + &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/ + &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/ + &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/ + &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/ + &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/ + >; + }; }; &elm { @@ -133,28 +154,29 @@ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; + gpmc,we-off-ns = <15>; + gpmc,oe-on-ns = <1>; + gpmc,oe-off-ns = <15>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; + gpmc,wr-access-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* @@ -198,18 +220,33 @@ }; partition@6 { - label = "u-boot-env"; - reg = <0x300000 0x40000>; + label = "u-boot-2"; + reg = <0x300000 0x100000>; }; partition@7 { - label = "u-boot-env.backup1"; - reg = <0x340000 0x40000>; + label = "u-boot-2.backup1"; + reg = <0x400000 0x100000>; }; partition@8 { + label = "u-boot-env"; + reg = <0x500000 0x40000>; + }; + + partition@9 { + label = "u-boot-env.backup1"; + reg = <0x540000 0x40000>; + }; + + partition@10 { + label = "splash-screen"; + reg = <0x580000 0x40000>; + }; + + partition@11 { label = "UBI"; - reg = <0x380000 0x1fc80000>; + reg = <0x5c0000 0x1fa40000>; }; }; }; @@ -228,6 +265,11 @@ &lcdc { blue-and-red-wiring = "crossed"; status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <0>; + }; + }; }; &mmc1 { @@ -242,7 +284,6 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; - system-power-controller; }; &spi0 { @@ -255,14 +296,34 @@ #include "tps65217.dtsi" &tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ ti,pmic-shutdown-controller; interrupt-parent = <&intc>; interrupts = <7>; /* NMI */ backlight { isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ - default-brightness = <100>; + fdim = <500>; /* TPS65217_BL_FDIM_500HZ */ + default-brightness = <50>; + /* 1(on) - enable current sink, while initialization */ + /* 0(off) - disable current sink, while initialization */ + isink-en = <1>; }; regulators { @@ -272,6 +333,7 @@ }; dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1351500>; @@ -280,6 +342,7 @@ }; dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; @@ -319,171 +382,364 @@ }; }; +&gpio0 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MirxWakeup", + "", + ""; +}; + +&gpio3 { + ti,gpio-always-on; + ti,no-reset-on-init; + gpio-line-names = + "", + "MirxBtReset", + "", + "CcVolAdcEn", + "MirxBlePause", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AspEn", + "", + "", + "", + "", + "", + "", + "BatVolAdcEn", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + &usb0 { dr_mode = "peripheral"; }; &usb1 { dr_mode = "host"; + /delete-property/dmas; + /delete-property/dma-names; }; &am33xx_pinmux { pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin &gpio_pins>; + pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < + /* xdma_event_intr1.clkout2 */ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; }; - dmtimer7_pins: pinmux_dmtimer7_pins { + guardian_interface_pins: pinmux_interface_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) + /* ADC_BATSENSE_EN */ + /* (A14) MCASP0_AHCLKx.gpio3[21] */ + AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ADC_COINCELL_EN */ + /* (J16) MII1_TX_EN.gpio3[3] */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ASP_ENABLE */ + /* (A13) MCASP0_ACLKx.gpio3[14] */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* (D16) uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) + /* (D15) uart1_txd.uart1_txd */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) + /*SWITCH-OFF_3V6*/ + /* (M18) gpio0[1] */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* MIRACULIX */ + /* (H17) gmii1_crs.gpio3[1] */ + AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (H18) rmii1_refclk.gpio0[29] */ + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 ) + /* (J17) gmii1_rxdv.gpio3[4] */ + AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) >; }; - gpio_keys_pins: pinmux_gpio_keys_pins { + guardian_beeper_pins: pinmux_dmtimer7_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ >; }; - gpio_pins: pinmux_gpio_pins { + guardian_button_pins: pinmux_guardian_button_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ >; }; + i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + led_bl_pins: gpio_led_bl_pins { + pinctrl-single,pins = < + /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) >; }; lcd_disen_pins: pinmux_lcd_disen_pins { pinctrl-single,pins = < + /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) >; }; lcd_pins_default: pinmux_lcd_pins_default { pinctrl-single,pins = < + /* (U10) gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T10) gpmc_ad9.lcd_data22 */ AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T11) gpmc_ad10.lcd_data21 */ AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U12) gpmc_ad11.lcd_data20 */ AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T12) gpmc_ad12.lcd_data19 */ AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (R12) gpmc_ad13.lcd_data18 */ AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (V13) gpmc_ad14.lcd_data17 */ AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U13) gpmc_ad15.lcd_data16 */ AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) >; }; lcd_pins_sleep: pinmux_lcd_pins_sleep { pinctrl-single,pins = < + /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) >; }; - leds_pins: pinmux_leds_pins { + guardian_led_pins: pinmux_guardian_led_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < + /* SPI0_CLK - spi0_clk.spi */ AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + /* SPI0_MOSI - spi0_d0.spi0 */ AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + /* SPI0_MISO - spi0_d1.spi0 */ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) + /* SPI0_CS0 - spi */ AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < + /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + /* K18 uart2_rxd.mirx_txd */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) + /* L18 uart2_txd.mirx_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) + >; + }; + nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < + /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) + /* (V7) gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) + /* (R8) gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) + /* (T8) gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) + /* (U8) gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) + /* (V8) gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) + /* (R9) gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) + /* (T9) gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) + /* (T17) gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) + /* (U17) gpmc_wpn.gpmc_wpn */ AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) + /* (V6) gpmc_csn0.gpmc_csn0 */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) + /* (R7) gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) + /* (T7) gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) + /* (U6) gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) + /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) >; }; diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index 245c35f41cdf..6eea18b29355 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -27,6 +27,13 @@ reg = <0x80000000 0x10000000>; }; + clk32k: clk32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + + #clock-cells = <0>; + }; + vdd_mod: vdd_mod_reg { compatible = "regulator-fixed"; regulator-name = "vdd-mod"; @@ -124,9 +131,6 @@ gpmc,wr-data-mux-bus-ns = <0>; ti,elm-id = <&elm>; ti,nand-ecc-opt = "bch8"; - - #address-cells = <1>; - #size-cells = <1>; }; }; @@ -149,6 +153,8 @@ }; &rtc { + clocks = <&clk32k>; + clock-names = "ext-clk"; system-power-controller; }; diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts index 1479fd95dec2..9d81d4cc6890 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts @@ -227,14 +227,20 @@ }; &nand0 { - partition@0 { - label = "MLO"; - reg = <0x00000 0x20000>; - }; + nand_parts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@20000 { - label = "boot"; - reg = <0x20000 0x80000>; + partition@0 { + label = "MLO"; + reg = <0x00000 0x20000>; + }; + + partition@80000 { + label = "boot"; + reg = <0x80000 0x100000>; + }; }; }; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index b7b7106f2dee..d34483ae1778 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -5,251 +5,288 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-22@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; + clock@664 { + compatible = "ti,clksel"; + reg = <0x664>; + #clock-cells = <2>; + #address-cells = <0>; - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; + ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + }; - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; + ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + }; + + ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + }; }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; clock-frequency = <32000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck@490 { + dpll_core_ck: clock@490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@480 { + dpll_core_m4_ck: clock-dpll-core-m4@480 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0480>; ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck@484 { + dpll_core_m5_ck: clock-dpll-core-m5@484 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0484>; ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { + dpll_core_m6_ck: clock-dpll-core-m6@4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x04d8>; ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck@488 { + dpll_mpu_ck: clock@488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x04a8>; ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck@494 { + dpll_ddr_ck: clock@494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; reg = <0x04a0>; ti,index-starts-at-one; }; - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { + dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_ddr_m2_div2_ck"; clocks = <&dpll_ddr_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck@498 { + dpll_disp_ck: clock@498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_disp_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { + dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; reg = <0x04a4>; @@ -257,418 +294,484 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@48c { + dpll_per_ck: clock@48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; - dpll_per_m2_ck: dpll_per_m2_ck@4ac { + dpll_per_m2_ck: clock-dpll-per-m2@4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x04ac>; ti,index-starts-at-one; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@530 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck@914 { + mmu_fck: clock-mmu-fck-1@914 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "mmu_fck"; clocks = <&dpll_core_m4_ck>; ti,bit-shift = <1>; reg = <0x0914>; }; - timer1_fck: timer1_fck@528 { + timer1_fck: clock-timer1-fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck@508 { + timer2_fck: clock-timer2-fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; - timer3_fck: timer3_fck@50c { + timer3_fck: clock-timer3-fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; - timer4_fck: timer4_fck@510 { + timer4_fck: clock-timer4-fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; - timer5_fck: timer5_fck@518 { + timer5_fck: clock-timer5-fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; - timer6_fck: timer6_fck@51c { + timer6_fck: clock-timer6-fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; - timer7_fck: timer7_fck@504 { + timer7_fck: clock-timer7-fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck@47c { + usbotg_fck: clock-usbotg-fck-8@47c { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usbotg_fck"; clocks = <&dpll_per_ck>; ti,bit-shift = <8>; reg = <0x047c>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <2>; }; - ieee5000_fck: ieee5000_fck@e4 { + ieee5000_fck: clock-ieee5000-fck-1@e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ieee5000_fck"; clocks = <&dpll_core_m4_div2_ck>; ti,bit-shift = <1>; reg = <0x00e4>; }; - wdt1_fck: wdt1_fck@538 { + wdt1_fck: clock-wdt1-fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; - l4_rtc_gclk: l4_rtc_gclk { + l4_rtc_gclk: clock-l4-rtc-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4_rtc_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4fw_gclk: l4fw_gclk { + l4fw_gclk: clock-l4fw-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4fw_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - sysclk_div_ck: sysclk_div_ck { + sysclk_div_ck: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div_ck"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; - lcd_gclk: lcd_gclk@534 { + lcd_gclk: clock-lcd-gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "lcd_gclk"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x0534>; ti,set-rate-parent; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x052c>; - }; + clock@52c { + compatible = "ti,clksel"; + reg = <0x52c>; + #clock-cells = <2>; + #address-cells = <0>; - gfx_fck_div_ck: gfx_fck_div_ck@52c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x052c>; - ti,max-div = <2>; - }; + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + }; - sysclkout_pre_ck: sysclkout_pre_ck@700 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; - reg = <0x0700>; + gfx_fck_div_ck: clock-gfx-fck-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; + clocks = <&gfx_fclk_clksel_ck>; + ti,max-div = <2>; + }; }; - clkout2_div_ck: clkout2_div_ck@700 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x0700>; - }; + clock@700 { + compatible = "ti,clksel"; + reg = <0x700>; + #clock-cells = <2>; + #address-cells = <0>; - clkout2_ck: clkout2_ck@700 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; - reg = <0x0700>; + sysclkout_pre_ck: clock-sysclkout-pre { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sysclkout_pre_ck"; + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; + }; + + clkout2_div_ck: clock-clkout2-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout2_div_ck"; + clocks = <&sysclkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + }; + + clkout2_ck: clock-clkout2 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkout2_ck"; + clocks = <&clkout2_div_ck>; + ti,bit-shift = <7>; + }; }; }; &prcm { - per_cm: per-cm@0 { + per_cm: clock@0 { compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; reg = <0x0 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x400>; - l4ls_clkctrl: l4ls-clkctrl@38 { + l4ls_clkctrl: clock@38 { compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@1c { + l3s_clkctrl: clock@1c { compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; #clock-cells = <2>; }; - l3_clkctrl: l3-clkctrl@24 { + l3_clkctrl: clock@24 { compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; #clock-cells = <2>; }; - l4hs_clkctrl: l4hs-clkctrl@120 { + l4hs_clkctrl: clock@120 { compatible = "ti,clkctrl"; + clock-output-names = "l4hs_clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { + pruss_ocp_clkctrl: clock@e8 { compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; reg = <0xe8 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { + cpsw_125mhz_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; reg = <0x0 0x18>; #clock-cells = <2>; }; - lcdc_clkctrl: lcdc-clkctrl@18 { + lcdc_clkctrl: clock@18 { compatible = "ti,clkctrl"; + clock-output-names = "lcdc_clkctrl"; reg = <0x18 0x4>; #clock-cells = <2>; }; - clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { + clk_24mhz_clkctrl: clock@14c { compatible = "ti,clkctrl"; + clock-output-names = "clk_24mhz_clkctrl"; reg = <0x14c 0x4>; #clock-cells = <2>; }; }; - wkup_cm: wkup-cm@400 { + wkup_cm: clock@400 { compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - l4_wkup_clkctrl: l4-wkup-clkctrl@0 { + l4_wkup_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x0 0x10>, <0xb4 0x24>; #clock-cells = <2>; }; - l3_aon_clkctrl: l3-aon-clkctrl@14 { + l3_aon_clkctrl: clock@14 { compatible = "ti,clkctrl"; + clock-output-names = "l3_aon_clkctrl"; reg = <0x14 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { + l4_wkup_aon_clkctrl: clock@b0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; reg = <0xb0 0x4>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@600 { + mpu_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - mpu_clkctrl: mpu-clkctrl@0 { + mpu_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@800 { + l4_rtc_cm: clock@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@0 { + l4_rtc_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@900 { + gfx_l3_cm: clock@900 { compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@0 { + gfx_l3_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_cefuse_cm: l4-cefuse-cm@a00 { + l4_cefuse_cm: clock@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_cefuse_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { + l4_cefuse_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_cefuse_clkctrl"; reg = <0x0 0x24>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6ec85d58dd1..9a8698bd2852 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -461,8 +461,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 220d0a52797e..0ee7afaa0e8e 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -62,12 +62,27 @@ }; }; &cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + ipss_ick: clock-ipss-ick { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clock-output-names = "ipss_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + uart4_ick_am35xx: clock-uart4-ick-am35xx { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick_am35xx"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; }; rmii_ck: rmii_ck { @@ -82,20 +97,19 @@ clock-frequency = <27000000>; }; - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; + uart4_fck_am35xx: clock-uart4-fck-am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck_am35xx"; + clocks = <&core_48m_fck>; + ti,bit-shift = <23>; + }; }; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 4416ddb559e4..46d5361fe876 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1127,6 +1127,11 @@ cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + ti,set-io-isolation; + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 0bc391243816..036f3831dc26 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -893,6 +893,10 @@ }; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 1165804658bc..27f4ce855549 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -1019,6 +1019,10 @@ cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 66e892fa3398..9a5437b3d6a8 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -5,217 +5,246 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-31@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; ti,bit-shift = <31>; reg = <0x0040>; }; - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { + crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "crystal_freq_sel_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <29>; reg = <0x0040>; }; - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sysboot_freq_sel_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <0>; reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <1>; reg = <0x0664>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <2>; reg = <0x0664>; }; - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { + ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm3_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <4>; reg = <0x0664>; }; - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { + ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm4_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <5>; reg = <0x0664>; }; - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { + ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm5_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <6>; reg = <0x0664>; }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; clock-frequency = <32768>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; clock-frequency = <26000000>; }; - dpll_core_ck: dpll_core_ck@2d20 { + dpll_core_ck: clock@2d20 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { + dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -224,9 +253,10 @@ ti,invert-autoidle-bit; }; - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { + dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -235,9 +265,10 @@ ti,invert-autoidle-bit; }; - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { + dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -246,16 +277,18 @@ ti,invert-autoidle-bit; }; - dpll_mpu_ck: dpll_mpu_ck@2d60 { + dpll_mpu_ck: clock@2d60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -264,24 +297,27 @@ ti,invert-autoidle-bit; }; - mpu_periphclk: mpu_periphclk { + mpu_periphclk: clock-mpu-periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - dpll_ddr_ck: dpll_ddr_ck@2da0 { + dpll_ddr_ck: clock@2da0 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -290,16 +326,18 @@ ti,invert-autoidle-bit; }; - dpll_disp_ck: dpll_disp_ck@2e20 { + dpll_disp_ck: clock@2e20 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_disp_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { + dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -309,16 +347,18 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@2de0 { + dpll_per_ck: clock@2de0 { #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { + dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -327,119 +367,135 @@ ti,invert-autoidle-bit; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick@2a38 { + clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkdiv32k_ick"; clocks = <&clkdiv32k_ck>; ti,bit-shift = <8>; reg = <0x2a38>; }; - sysclk_div: sysclk_div { + sysclk_div: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@4248 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; reg = <0x4248>; }; - clk_32k_tpm_ck: clk_32k_tpm_ck { + clk_32k_tpm_ck: clock-clk-32k-tpm { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32k_tpm_ck"; clock-frequency = <32768>; }; - timer1_fck: timer1_fck@4200 { + timer1_fck: clock-timer1-fck@4200 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4200>; }; - timer2_fck: timer2_fck@4204 { + timer2_fck: clock-timer2-fck@4204 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4204>; }; - timer3_fck: timer3_fck@4208 { + timer3_fck: clock-timer3-fck@4208 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4208>; }; - timer4_fck: timer4_fck@420c { + timer4_fck: clock-timer4-fck@420c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x420c>; }; - timer5_fck: timer5_fck@4210 { + timer5_fck: clock-timer5-fck@4210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4210>; }; - timer6_fck: timer6_fck@4214 { + timer6_fck: clock-timer6-fck@4214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4214>; }; - timer7_fck: timer7_fck@4218 { + timer7_fck: clock-timer7-fck@4218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4218>; }; - wdt1_fck: wdt1_fck@422c { + wdt1_fck: clock-wdt1-fck@422c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; reg = <0x422c>; }; @@ -451,125 +507,141 @@ reg = <0x424c>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; reg = <0x4238>; }; - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { + dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_clksel_mac_clk"; clocks = <&dpll_core_m5_ck>; reg = <0x4234>; ti,bit-shift = <2>; ti,dividers = <2>, <5>; }; - clk_32k_mosc_ck: clk_32k_mosc_ck { + clk_32k_mosc_ck: clock-clk-32k-mosc { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32k_mosc_ck"; clock-frequency = <32768>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; reg = <0x4240>; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; clocks = <&sysclk_div>, <&dpll_per_m2_ck>; ti,bit-shift = <1>; reg = <0x423c>; }; - gfx_fck_div_ck: gfx_fck_div_ck@423c { + gfx_fck_div_ck: clock-gfx-fck-div@423c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; clocks = <&gfx_fclk_clksel_ck>; reg = <0x423c>; ti,max-div = <2>; }; - disp_clk: disp_clk@4244 { + disp_clk: clock-disp@4244 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "disp_clk"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; ti,set-rate-parent; }; - dpll_extdev_ck: dpll_extdev_ck@2e60 { + dpll_extdev_ck: clock@2e60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_extdev_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { + dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_extdev_m2_ck"; clocks = <&dpll_extdev_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -578,66 +650,75 @@ ti,invert-autoidle-bit; }; - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { + mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mux_synctimer32k_ck"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; reg = <0x4230>; }; - timer8_fck: timer8_fck@421c { + timer8_fck: clock-timer8-fck@421c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer8_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x421c>; }; - timer9_fck: timer9_fck@4220 { + timer9_fck: clock-timer9-fck@4220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer9_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4220>; }; - timer10_fck: timer10_fck@4224 { + timer10_fck: clock-timer10-fck@4224 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer10_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4224>; }; - timer11_fck: timer11_fck@4228 { + timer11_fck: clock-timer11-fck@4228 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer11_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4228>; }; - cpsw_50m_clkdiv: cpsw_50m_clkdiv { + cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_50m_clkdiv"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_5m_clkdiv: cpsw_5m_clkdiv { + cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_5m_clkdiv"; clocks = <&cpsw_50m_clkdiv>; clock-mult = <1>; clock-div = <10>; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { + dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m4_ck"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -646,9 +727,10 @@ ti,invert-autoidle-bit; }; - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { + dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_per_clkdcoldo"; clocks = <&dpll_per_ck>; ti,clock-mult = <1>; ti,clock-div = <1>; @@ -657,91 +739,102 @@ ti,invert-autoidle-bit; }; - dll_aging_clk_div: dll_aging_clk_div@4250 { + dll_aging_clk_div: clock-dll-aging-clk-div@4250 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dll_aging_clk_div"; clocks = <&sys_clkin_ck>; reg = <0x4250>; ti,dividers = <8>, <16>, <32>; }; - div_core_25m_ck: div_core_25m_ck { + div_core_25m_ck: clock-div-core-25m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "div_core_25m_ck"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <8>; }; - func_12m_clk: func_12m_clk { + func_12m_clk: clock-func-12m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <16>; }; - vtp_clk_div: vtp_clk_div { + vtp_clk_div: clock-vtp-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "vtp_clk_div"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <2>; }; - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { + usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "usbphy_32khz_clkmux"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { + usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy0_always_on_clk32k"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a40>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a48>; }; - clkout1_osc_div_ck: clkout1-osc-div-ck { + clkout1_osc_div_ck: clock-clkout1-osc-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_osc_div_ck"; clocks = <&sys_clkin_ck>; ti,bit-shift = <20>; ti,max-div = <4>; reg = <0x4100>; }; - clkout1_src2_mux_ck: clkout1-src2-mux-ck { + clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkout1_src2_mux_ck"; clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, <&dpll_mpu_m2_ck>; reg = <0x4100>; }; - clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { + clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_pre_div_ck"; clocks = <&clkout1_src2_mux_ck>; ti,bit-shift = <4>; ti,max-div = <8>; reg = <0x4100>; }; - clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { + clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_post_div_ck"; clocks = <&clkout1_src2_pre_div_ck>; ti,bit-shift = <8>; ti,max-div = <32>; @@ -749,18 +842,20 @@ reg = <0x4100>; }; - clkout1_mux_ck: clkout1-mux-ck { + clkout1_mux_ck: clock-clkout1-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkout1_mux_ck"; clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; ti,bit-shift = <16>; reg = <0x4100>; }; - clkout1_ck: clkout1-ck { + clkout1_ck: clock-clkout1-ck { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkout1_ck"; clocks = <&clkout1_mux_ck>; ti,bit-shift = <23>; reg = <0x4100>; @@ -768,120 +863,138 @@ }; &prcm { - wkup_cm: wkup-cm@2800 { + wkup_cm: clock@2800 { compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; reg = <0x2800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x400>; - l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { + l3s_tsc_clkctrl: clock@120 { compatible = "ti,clkctrl"; + clock-output-names = "l3s_tsc_clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { + l4_wkup_aon_clkctrl: clock@228 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; reg = <0x228 0xc>; #clock-cells = <2>; }; - l4_wkup_clkctrl: l4-wkup-clkctrl@220 { + l4_wkup_clkctrl: clock@220 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x220 0x4>, <0x328 0x44>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@8300 { + mpu_cm: clock@8300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x8300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8300 0x100>; - mpu_clkctrl: mpu-clkctrl@20 { + mpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@8400 { + gfx_l3_cm: clock@8400 { compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; reg = <0x8400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8400 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@20 { + gfx_l3_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@8500 { + l4_rtc_cm: clock@8500 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; reg = <0x8500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@20 { + l4_rtc_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - per_cm: per-cm@8800 { + per_cm: clock@8800 { compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; reg = <0x8800 0xc00>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8800 0xc00>; - l3_clkctrl: l3-clkctrl@20 { + l3_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; reg = <0x20 0x3c>, <0x78 0x2c>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@68 { + l3s_clkctrl: clock@68 { compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; reg = <0x68 0xc>, <0x220 0x4c>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { + pruss_ocp_clkctrl: clock@320 { compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; reg = <0x320 0x4>; #clock-cells = <2>; }; - l4ls_clkctrl: l4ls-clkctrl@420 { + l4ls_clkctrl: clock@420 { compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; reg = <0x420 0x1a4>; #clock-cells = <2>; }; - emif_clkctrl: emif-clkctrl@720 { + emif_clkctrl: clock@720 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x720 0x4>; #clock-cells = <2>; }; - dss_clkctrl: dss-clkctrl@a20 { + dss_clkctrl: clock@a20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0xa20 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { + cpsw_125mhz_clkctrl: clock@b20 { compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; reg = <0xb20 0x4>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index ad65be871938..f9f79ed82518 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -397,8 +397,8 @@ #size-cells = <0>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi_0>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -409,8 +409,8 @@ #size-cells = <0>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi_1>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -421,8 +421,8 @@ #size-cells = <0>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi_2>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 40b9405f1a8e..9b9a18bbb20a 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -32,7 +32,6 @@ * This is based on the unreleased schematic for the Model A+. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -67,21 +66,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ + "", /* GPIO30 */ + "", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ + "", /* GPIO33 */ + "", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ + "", /* GPIO36 */ + "", /* GPIO37 */ "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 11edb581dbaf..f664e4fced93 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -26,7 +26,6 @@ * RPI00021 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -42,41 +41,41 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "CAM_GPIO0", /* Binary number representing build/revision */ "CONFIG0", "CONFIG1", "CONFIG2", "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 1b435c64bd9c..248feb2ed23d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -34,7 +34,6 @@ * RPI-BPLUS sheet 1 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -69,21 +68,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ + "", /* GPIO30 */ "LAN_RUN", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ + "", /* GPIO33 */ + "", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ + "", /* GPIO36 */ + "", /* GPIO37 */ "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "ETHCLK", /* GPIO44 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "ETH_CLK", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index a23c25c00eea..f5b66d3f4ff3 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -27,7 +27,6 @@ * RPI00022 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -43,40 +42,40 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "CAM_GPIO", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "GPIO27", "GPIO28", "GPIO29", "GPIO30", "GPIO31", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 1b63d6b19750..f589bede2b11 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -27,7 +27,6 @@ * RPI00021 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -43,41 +42,40 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "GPIO21", + "", /* GPIO19 */ + "", /* GPIO20 */ + "CAM_GPIO0", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ - "CAM_GPIO0", - /* Binary number representing build/revision */ - "CONFIG0", - "CONFIG1", - "CONFIG2", - "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts index a75c882e6575..87958a96c3e0 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts @@ -13,7 +13,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 243236bc1e00..596bb1ef994e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -39,7 +39,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -74,19 +73,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", "CAM_GPIO1", /* GPIO40 */ "WL_ON", /* GPIO41 */ - "NC", /* GPIO42 */ + "", /* GPIO42 */ "WIFI_CLK", /* GPIO43 */ "CAM_GPIO0", /* GPIO44 */ "BT_ON", /* GPIO45 */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 6f9b3a908f28..a65c2bca69ea 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -29,7 +29,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -64,22 +63,22 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ + "", /* GPIO30 */ + "", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "NC", /* GPIO40 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "NC", /* GPIO45 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED_N", /* Used by SD Card */ diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index d8af8eeac7b6..3635502b1e0a 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -34,7 +34,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -83,7 +82,7 @@ "CAM_GPIO0", "SMPS_SCL", "SMPS_SDA", - "ETHCLK", + "ETH_CLK", "PWM1_OUT", "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index d73daf5bff1d..f7222a28903e 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -55,7 +55,6 @@ * This is mostly based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index e12938baaf12..ec721d323ac5 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -45,7 +45,7 @@ #gpio-cells = <2>; gpio-line-names = "BT_ON", "WL_ON", - "STATUS_LED_R", + "PWR_LED_R", "LAN_RUN", "", "CAM_GPIO0", @@ -61,7 +61,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -110,7 +109,7 @@ "SD1_DATA3", "PWM0_OUT", "PWM1_OUT", - "ETHCLK", + "ETH_CLK", "WIFI_CLK", "SDA0", "SCL0", diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 42b5383b55d8..fb6a417d73e7 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -54,7 +54,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -103,7 +102,7 @@ "SD1_DATA3", "PWM0_OUT", "PWM1_OUT", - "ETHCLK", + "ETH_CLK", "WIFI_CLK", "SDA0", "SCL0", diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts index 588d9411ceb6..cf84e69fced8 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts @@ -13,7 +13,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -63,8 +62,8 @@ "GPIO43", "GPIO44", "GPIO45", - "GPIO46", - "GPIO47", + "SMPS_SCL", + "SMPS_SDA", /* Used by eMMC */ "SD_CLK_R", "SD_CMD_R", diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 828a20561b96..f57b4ca145dd 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -41,12 +41,12 @@ #gpio-cells = <2>; gpio-line-names = "HDMI_HPD_N", "EMMC_EN_N", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; + "", + "", + "", + "", + "", + ""; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi index 967e081cb9c2..882b13807075 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi index dc7ae776db5f..4273b90b53cc 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi @@ -11,7 +11,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi new file mode 100644 index 000000000000..d659e409a17e --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2 + * + * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com> + */ + + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + gpio-sck = <&chipcommon 7 0>; + gpio-mosi = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + usb { + /* label = "bcm53xx:blue:usb"; */ + function = LED_FUNCTION_USB; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>, <&ohci_port2>, + <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + power0 { + /* label = "bcm53xx:red:power"; */ + function = LED_FUNCTION_FAULT; + color = <LED_COLOR_ID_RED>; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + + power1 { + /* label = "bcm53xx:white:power"; */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_WHITE>; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router0 { + /* label = "bcm53xx:blue:router"; */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router1 { + /* label = "bcm53xx:amber:router"; */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_AMBER>; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + wan { + /* label = "bcm53xx:blue:wan"; */ + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + wireless0 { + /* label = "bcm53xx:blue:wireless"; */ + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + wireless1 { + /* label = "bcm53xx:amber:wireless"; */ + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_AMBER>; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + aoss { + label = "AOSS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + mode { + label = "Mode"; + linux,code = <KEY_SETUP>; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + sw_ap { + label = "AP"; + linux,code = <BTN_0>; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + eject { + label = "USB eject"; + linux,code = <KEY_EJECTCD>; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts new file mode 100644 index 000000000000..8e506269fa1a --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts new file mode 100644 index 000000000000..596129027074 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP2 + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP2"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 82f9629f0abb..d8503758342b 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright (C) 2021 Arınç ÃœNAL <arinc.unal@arinc9.com> + * Copyright (C) 2021-2022 Arınç ÃœNAL <arinc.unal@arinc9.com> */ /dts-v1/; @@ -25,6 +25,9 @@ nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x00180000>; + + et1macaddr: et1macaddr { + }; }; leds { @@ -177,9 +180,6 @@ dsa,member = <0 0>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; @@ -208,6 +208,7 @@ sw0_p5: port@5 { reg = <5>; label = "extsw"; + phy-mode = "rgmii"; fixed-link { speed = <1000>; @@ -231,7 +232,6 @@ reg = <8>; ethernet = <&gmac2>; label = "cpu"; - status = "disabled"; fixed-link { speed = <1000>; @@ -241,6 +241,15 @@ }; }; +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi new file mode 100644 index 000000000000..c016e12b7372 --- /dev/null +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm47622", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x818000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 66c64a6ec414..daca63f25134 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -13,7 +13,7 @@ #include <dt-bindings/leds/common.h> / { - compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; + compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; model = "Meraki MR32"; chosen { diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index be9a00ff752d..bdf1b4a608e6 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -10,8 +10,6 @@ nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "brcm,bcm947xx-cfe-partitions"; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 603c700c706f..65f8a759f1e3 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -455,7 +455,7 @@ reg = <0x180 0x4>; }; - pinctrl: pin-controller@1c0 { + pinctrl: pinctrl@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts index 2e7fda9b998c..975f854f652f 100644 --- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -34,7 +34,7 @@ status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { compatible = "m25p80"; reg = <0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts new file mode 100644 index 000000000000..6f083724ab8e --- /dev/null +++ b/arch/arm/boot/dts/bcm947622.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 52feca0fb906..dd63a148a16b 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -37,7 +37,7 @@ / { model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; memory@0 { device_type = "memory"; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 9140be7ec053..b070b69466bd 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -37,7 +37,7 @@ / { model = "NorthStar HR (BCM953012HR)"; - compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index de40bd59a5fa..f1e6bcaa1edd 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -36,7 +36,7 @@ / { model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; aliases { serial0 = &uart0; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 60376b62cd5f..15f023656df0 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -136,7 +136,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index 8eeb319f5b54..9b9c225a1fb3 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -136,7 +136,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index dc86d5a91292..ca9311452739 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -152,7 +152,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index c457e53d886e..9db3c851451a 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -140,7 +140,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index c06871915a1c..32786e7c4e12 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -144,7 +144,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index b22fc6624ae4..74263d98de73 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -151,7 +151,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 0183f8965a74..69ebc7a913a7 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -155,7 +155,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 007e34715956..e96bc3f2d5cf 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -140,7 +140,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 7702e048e110..a92630113f57 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -167,8 +167,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index a9e7274806f4..eb0a95da94b2 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -655,8 +655,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 2365554eef3c..04a7a6d1d529 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -5,210 +5,244 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_core_aon_clocks { - atl_clkin0_ck: atl_clkin0_ck { + atl_clkin0_ck: clock-atl-clkin0 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin0_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin1_ck: atl_clkin1_ck { + atl_clkin1_ck: clock-atl-clkin1 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin1_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin2_ck: atl_clkin2_ck { + atl_clkin2_ck: clock-atl-clkin2 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin2_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin3_ck: atl_clkin3_ck { + atl_clkin3_ck: clock-atl-clkin3 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin3_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - hdmi_clkin_ck: hdmi_clkin_ck { + hdmi_clkin_ck: clock-hdmi-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "hdmi_clkin_ck"; clock-frequency = <0>; }; - mlb_clkin_ck: mlb_clkin_ck { + mlb_clkin_ck: clock-mlb-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "mlb_clkin_ck"; clock-frequency = <0>; }; - mlbp_clkin_ck: mlbp_clkin_ck { + mlbp_clkin_ck: clock-mlbp-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "mlbp_clkin_ck"; clock-frequency = <0>; }; - pciesref_acs_clk_ck: pciesref_acs_clk_ck { + pciesref_acs_clk_ck: clock-pciesref-acs { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pciesref_acs_clk_ck"; clock-frequency = <100000000>; }; - ref_clkin0_ck: ref_clkin0_ck { + ref_clkin0_ck: clock-ref-clkin0 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin0_ck"; clock-frequency = <0>; }; - ref_clkin1_ck: ref_clkin1_ck { + ref_clkin1_ck: clock-ref-clkin1 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin1_ck"; clock-frequency = <0>; }; - ref_clkin2_ck: ref_clkin2_ck { + ref_clkin2_ck: clock-ref-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin2_ck"; clock-frequency = <0>; }; - ref_clkin3_ck: ref_clkin3_ck { + ref_clkin3_ck: clock-ref-clkin3 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin3_ck"; clock-frequency = <0>; }; - rmii_clk_ck: rmii_clk_ck { + rmii_clk_ck: clock-rmii { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "rmii_clk_ck"; clock-frequency = <0>; }; - sdvenc_clkin_ck: sdvenc_clkin_ck { + sdvenc_clkin_ck: clock-sdvenc-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sdvenc_clkin_ck"; clock-frequency = <0>; }; - secure_32k_clk_src_ck: secure_32k_clk_src_ck { + secure_32k_clk_src_ck: clock-secure-32k-clk-src { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; - sys_clk32_crystal_ck: sys_clk32_crystal_ck { + sys_clk32_crystal_ck: clock-sys-clk32-crystal { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_clk32_crystal_ck"; clock-frequency = <32768>; }; - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { + sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sys_clk32_pseudo_ck"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <610>; }; - virt_12000000_ck: virt_12000000_ck { + virt_12000000_ck: clock-virt-12000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; - virt_13000000_ck: virt_13000000_ck { + virt_13000000_ck: clock-virt-13000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; - virt_16800000_ck: virt_16800000_ck { + virt_16800000_ck: clock-virt-16800000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_20000000_ck: virt_20000000_ck { + virt_20000000_ck: clock-virt-20000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_20000000_ck"; clock-frequency = <20000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - virt_27000000_ck: virt_27000000_ck { + virt_27000000_ck: clock-virt-27000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; - virt_38400000_ck: virt_38400000_ck { + virt_38400000_ck: clock-virt-38400000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; - sys_clkin2: sys_clkin2 { + sys_clkin2: clock-sys-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_clkin2"; clock-frequency = <22579200>; }; - usb_otg_clkin_ck: usb_otg_clkin_ck { + usb_otg_clkin_ck: clock-usb-otg-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "usb_otg_clkin_ck"; clock-frequency = <0>; }; - video1_clkin_ck: video1_clkin_ck { + video1_clkin_ck: clock-video1-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video1_clkin_ck"; clock-frequency = <0>; }; - video1_m2_clkin_ck: video1_m2_clkin_ck { + video1_m2_clkin_ck: clock-video1-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video1_m2_clkin_ck"; clock-frequency = <0>; }; - video2_clkin_ck: video2_clkin_ck { + video2_clkin_ck: clock-video2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video2_clkin_ck"; clock-frequency = <0>; }; - video2_m2_clkin_ck: video2_m2_clkin_ck { + video2_m2_clkin_ck: clock-video2-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video2_m2_clkin_ck"; clock-frequency = <0>; }; - dpll_abe_ck: dpll_abe_ck@1e0 { + dpll_abe_ck: clock@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; - dpll_abe_x2_ck: dpll_abe_x2_ck { + dpll_abe_x2_ck: clock-dpll-abe-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { + dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -217,18 +251,20 @@ ti,invert-autoidle-bit; }; - abe_clk: abe_clk@108 { + abe_clk: clock-abe@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; ti,index-power-of-two; }; - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { + dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -237,9 +273,10 @@ ti,invert-autoidle-bit; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { + dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -248,30 +285,34 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: dpll_core_byp_mux@12c { + dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck@120 { + dpll_core_ck: clock@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { + dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -280,24 +321,27 @@ ti,invert-autoidle-bit; }; - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck@160 { + dpll_mpu_ck: clock@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -306,42 +350,47 @@ ti,invert-autoidle-bit; }; - mpu_dclk_div: mpu_dclk_div { + mpu_dclk_div: clock-mpu-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dclk_div"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { + dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dsp_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { + dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_dsp_byp_mux"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0240>; }; - dpll_dsp_ck: dpll_dsp_ck@234 { + dpll_dsp_ck: clock@234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_dsp_ck"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; assigned-clocks = <&dpll_dsp_ck>; assigned-clock-rates = <600000000>; }; - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { + dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m2_ck"; clocks = <&dpll_dsp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -352,34 +401,38 @@ assigned-clock-rates = <600000000>; }; - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { + dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck@1a0 { + dpll_iva_ck: clock@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; assigned-clock-rates = <1165000000>; }; - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { + dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m2_ck"; clocks = <&dpll_iva_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -390,34 +443,38 @@ assigned-clock-rates = <388333334>; }; - iva_dclk: iva_dclk { + iva_dclk: clock-iva-dclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dclk"; clocks = <&dpll_iva_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { + dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_gpu_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02e4>; }; - dpll_gpu_ck: dpll_gpu_ck@2d8 { + dpll_gpu_ck: clock@2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gpu_ck"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; assigned-clocks = <&dpll_gpu_ck>; assigned-clock-rates = <1277000000>; }; - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { + dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gpu_m2_ck"; clocks = <&dpll_gpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -428,9 +485,10 @@ assigned-clock-rates = <425666667>; }; - dpll_core_m2_ck: dpll_core_m2_ck@130 { + dpll_core_m2_ck: clock-dpll-core-m2-8@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -439,32 +497,36 @@ ti,invert-autoidle-bit; }; - core_dpll_out_dclk_div: core_dpll_out_dclk_div { + core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "core_dpll_out_dclk_div"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { + dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_ddr_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x021c>; }; - dpll_ddr_ck: dpll_ddr_ck@210 { + dpll_ddr_ck: clock@210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -473,24 +535,27 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { + dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_gmac_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02b4>; }; - dpll_gmac_ck: dpll_gmac_ck@2a8 { + dpll_gmac_ck: clock@2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gmac_ck"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { + dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m2_ck"; clocks = <&dpll_gmac_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -499,72 +564,81 @@ ti,invert-autoidle-bit; }; - video2_dclk_div: video2_dclk_div { + video2_dclk_div: clock-video2-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_dclk_div"; clocks = <&video2_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video1_dclk_div: video1_dclk_div { + video1_dclk_div: clock-video1-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_dclk_div"; clocks = <&video1_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - hdmi_dclk_div: hdmi_dclk_div { + hdmi_dclk_div: clock-hdmi-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_dclk_div"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - per_dpll_hs_clk_div: per_dpll_hs_clk_div { + per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; }; - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; }; - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { + eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "eve_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { + dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_eve_byp_mux"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0290>; }; - dpll_eve_ck: dpll_eve_ck@284 { + dpll_eve_ck: clock@284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_eve_ck"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { + dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_eve_m2_ck"; clocks = <&dpll_eve_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -573,17 +647,19 @@ ti,invert-autoidle-bit; }; - eve_dclk_div: eve_dclk_div { + eve_dclk_div: clock-eve-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "eve_dclk_div"; clocks = <&dpll_eve_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { + dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -592,9 +668,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { + dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -603,9 +680,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { + dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -614,9 +692,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { + dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -625,9 +704,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { + dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -636,15 +716,17 @@ ti,invert-autoidle-bit; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { + dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_h11x2_ck"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -653,15 +735,17 @@ ti,invert-autoidle-bit; }; - dpll_dsp_x2_ck: dpll_dsp_x2_ck { + dpll_dsp_x2_ck: clock-dpll-dsp-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_dsp_x2_ck"; clocks = <&dpll_dsp_ck>; }; - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { + dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m3x2_ck"; clocks = <&dpll_dsp_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -672,15 +756,17 @@ assigned-clock-rates = <400000000>; }; - dpll_gmac_x2_ck: dpll_gmac_x2_ck { + dpll_gmac_x2_ck: clock-dpll-gmac-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_gmac_x2_ck"; clocks = <&dpll_gmac_ck>; }; - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { + dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h11x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -689,9 +775,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { + dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h12x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -700,9 +787,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { + dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h13x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -711,9 +799,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { + dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m3x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -722,33 +811,37 @@ ti,invert-autoidle-bit; }; - gmii_m_clk_div: gmii_m_clk_div { + gmii_m_clk_div: clock-gmii-m-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gmii_m_clk_div"; clocks = <&dpll_gmac_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; - hdmi_clk2_div: hdmi_clk2_div { + hdmi_clk2_div: clock-hdmi-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_clk2_div"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - hdmi_div_clk: hdmi_div_clk { + hdmi_div_clk: clock-hdmi-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_div_clk"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - l3_iclk_div: l3_iclk_div@100 { + l3_iclk_div: clock-l3-iclk-div-4@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x0100>; @@ -756,374 +849,420 @@ ti,index-power-of-two; }; - l4_root_clk_div: l4_root_clk_div { + l4_root_clk_div: clock-l4-root-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4_root_clk_div"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <2>; }; - video1_clk2_div: video1_clk2_div { + video1_clk2_div: clock-video1-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_clk2_div"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video1_div_clk: video1_div_clk { + video1_div_clk: clock-video1-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_div_clk"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video2_clk2_div: video2_clk2_div { + video2_clk2_div: clock-video2-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_clk2_div"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video2_div_clk: video2_div_clk { + video2_div_clk: clock-video2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_div_clk"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dummy_ck: dummy_ck { + dummy_ck: clock-dummy { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; &prm_clocks { - sys_clkin1: sys_clkin1@110 { + sys_clkin1: clock-sys-clkin1@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin1"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { + abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_sys_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { + abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { + abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; - abe_24m_fclk: abe_24m_fclk@11c { + abe_24m_fclk: clock-abe-24m@11c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x011c>; ti,dividers = <8>, <16>; }; - aess_fclk: aess_fclk@178 { + aess_fclk: clock-aess@178 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; clocks = <&abe_clk>; reg = <0x0178>; ti,max-div = <2>; }; - abe_giclk_div: abe_giclk_div@174 { + abe_giclk_div: clock-abe-giclk-div@174 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_giclk_div"; clocks = <&aess_fclk>; reg = <0x0174>; ti,max-div = <2>; }; - abe_lp_clk_div: abe_lp_clk_div@1d8 { + abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_lp_clk_div"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x01d8>; ti,dividers = <16>, <32>; }; - abe_sys_clk_div: abe_sys_clk_div@120 { + abe_sys_clk_div: clock-abe-sys-clk-div@120 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_sys_clk_div"; clocks = <&sys_clkin1>; reg = <0x0120>; ti,max-div = <2>; }; - adc_gfclk_mux: adc_gfclk_mux@1dc { + adc_gfclk_mux: clock-adc-gfclk-mux@1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "adc_gfclk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { + sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sys_clk1_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c8>; ti,index-power-of-two; }; - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { + sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sys_clk2_dclk_div"; clocks = <&sys_clkin2>; ti,max-div = <64>; reg = <0x01cc>; ti,index-power-of-two; }; - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { + per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_dclk_div"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x01bc>; ti,index-power-of-two; }; - dsp_gclk_div: dsp_gclk_div@18c { + dsp_gclk_div: clock-dsp-gclk-div@18c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dsp_gclk_div"; clocks = <&dpll_dsp_m2_ck>; ti,max-div = <64>; reg = <0x018c>; ti,index-power-of-two; }; - gpu_dclk: gpu_dclk@1a0 { + gpu_dclk: clock-gpu-dclk@1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gpu_dclk"; clocks = <&dpll_gpu_m2_ck>; ti,max-div = <64>; reg = <0x01a0>; ti,index-power-of-two; }; - emif_phy_dclk_div: emif_phy_dclk_div@190 { + emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "emif_phy_dclk_div"; clocks = <&dpll_ddr_m2_ck>; ti,max-div = <64>; reg = <0x0190>; ti,index-power-of-two; }; - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { + gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gmac_250m_dclk_div"; clocks = <&dpll_gmac_m2_ck>; ti,max-div = <64>; reg = <0x019c>; ti,index-power-of-two; }; - gmac_main_clk: gmac_main_clk { + gmac_main_clk: clock-gmac-main { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gmac_main_clk"; clocks = <&gmac_250m_dclk_div>; clock-mult = <1>; clock-div = <2>; }; - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { + l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_480m_dclk_div"; clocks = <&dpll_usb_m2_ck>; ti,max-div = <64>; reg = <0x01ac>; ti,index-power-of-two; }; - usb_otg_dclk_div: usb_otg_dclk_div@184 { + usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "usb_otg_dclk_div"; clocks = <&usb_otg_clkin_ck>; ti,max-div = <64>; reg = <0x0184>; ti,index-power-of-two; }; - sata_dclk_div: sata_dclk_div@1c0 { + sata_dclk_div: clock-sata-dclk-div@1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sata_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c0>; ti,index-power-of-two; }; - pcie2_dclk_div: pcie2_dclk_div@1b8 { + pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "pcie2_dclk_div"; clocks = <&dpll_pcie_ref_m2_ck>; ti,max-div = <64>; reg = <0x01b8>; ti,index-power-of-two; }; - pcie_dclk_div: pcie_dclk_div@1b4 { + pcie_dclk_div: clock-pcie-dclk-div@1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "pcie_dclk_div"; clocks = <&apll_pcie_m2_ck>; ti,max-div = <64>; reg = <0x01b4>; ti,index-power-of-two; }; - emu_dclk_div: emu_dclk_div@194 { + emu_dclk_div: clock-emu-dclk-div@194 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "emu_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x0194>; ti,index-power-of-two; }; - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { + secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "secure_32k_dclk_div"; clocks = <&secure_32k_clk_src_ck>; ti,max-div = <64>; reg = <0x01c4>; ti,index-power-of-two; }; - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { + clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux0_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { + clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux1_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { + clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux2_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0160>; }; - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <2>; }; - eve_clk: eve_clk@180 { + eve_clk: clock-eve@180 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "eve_clk"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { + hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "hdmi_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; - mlb_clk: mlb_clk@134 { + mlb_clk: clock-mlb@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "mlb_clk"; clocks = <&mlb_clkin_ck>; ti,max-div = <64>; reg = <0x0134>; ti,index-power-of-two; }; - mlbp_clk: mlbp_clk@130 { + mlbp_clk: clock-mlbp@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "mlbp_clk"; clocks = <&mlbp_clkin_ck>; ti,max-div = <64>; reg = <0x0130>; ti,index-power-of-two; }; - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { + per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_gfclk2_div"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x0138>; ti,index-power-of-two; }; - timer_sys_clk_div: timer_sys_clk_div@144 { + timer_sys_clk_div: clock-timer-sys-clk-div@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "timer_sys_clk_div"; clocks = <&sys_clkin1>; reg = <0x0144>; ti,max-div = <2>; }; - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { + video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "video1_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { + video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "video2_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { + wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; }; &cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { + dpll_pcie_ref_ck: clock@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_pcie_ref_ck"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { + dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2ldo_ck"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1132,23 +1271,26 @@ ti,invert-autoidle-bit; }; - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { compatible = "ti,mux-clock"; + clock-output-names = "apll_pcie_in_clk_mux"; clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; }; - apll_pcie_ck: apll_pcie_ck@21c { + apll_pcie_ck: clock@21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; + clock-output-names = "apll_pcie_ck"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { compatible = "ti,divider-clock"; + clock-output-names = "optfclk_pciephy_div"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; @@ -1157,48 +1299,54 @@ ti,max-div = <2>; }; - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { + apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { + apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo_div"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - apll_pcie_m2_ck: apll_pcie_m2_ck { + apll_pcie_m2_ck: clock-apll-pcie-m2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_m2_ck"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_per_byp_mux: dpll_per_byp_mux@14c { + dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck@140 { + dpll_per_ck: clock@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck@150 { + dpll_per_m2_ck: clock-dpll-per-m2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1207,32 +1355,36 @@ ti,invert-autoidle-bit; }; - func_96m_aon_dclk_div: func_96m_aon_dclk_div { + func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_aon_dclk_div"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { + dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck@180 { + dpll_usb_ck: clock@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { + dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -1241,9 +1393,10 @@ ti,invert-autoidle-bit; }; - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { + dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2_ck"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -1252,15 +1405,17 @@ ti,invert-autoidle-bit; }; - dpll_per_x2_ck: dpll_per_x2_ck { + dpll_per_x2_ck: clock-dpll-per-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { + dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1269,9 +1424,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { + dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1280,9 +1436,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { + dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h13x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1291,9 +1448,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { + dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1302,9 +1460,10 @@ ti,invert-autoidle-bit; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { + dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1313,105 +1472,118 @@ ti,invert-autoidle-bit; }; - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; }; - func_128m_clk: func_128m_clk { + func_128m_clk: clock-func-128m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; - func_12m_fclk: func_12m_fclk { + func_12m_fclk: clock-func-12m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; - func_24m_clk: func_24m_clk { + func_24m_clk: clock-func-24m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - func_48m_fclk: func_48m_fclk { + func_48m_fclk: clock-func-48m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; }; - func_96m_fclk: func_96m_fclk { + func_96m_fclk: clock-func-96m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk@104 { + l3init_60m_fclk: clock-l3init-60m@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; }; - clkout2_clk: clkout2_clk@6b0 { + clkout2_clk: clock-clkout2-8@6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkout2_clk"; clocks = <&clkoutmux2_clk_mux>; ti,bit-shift = <8>; reg = <0x06b0>; }; - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { + l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "l3init_960m_gfclk"; clocks = <&dpll_usb_clkdcoldo>; ti,bit-shift = <8>; reg = <0x06c0>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; }; - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { + usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy2_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0688>; }; - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { + usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy3_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0698>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { + gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; @@ -1419,9 +1591,10 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { + gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; @@ -1429,34 +1602,38 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { + l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3instr_ts_gclk_div"; clocks = <&wkupaon_iclk_mux>; ti,bit-shift = <24>; reg = <0x0e50>; ti,dividers = <8>, <16>, <32>; }; - vip1_gclk_mux: vip1_gclk_mux@1020 { + vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip1_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1020>; }; - vip2_gclk_mux: vip2_gclk_mux@1028 { + vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip2_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1028>; }; - vip3_gclk_mux: vip3_gclk_mux@1030 { + vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip3_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1030>; @@ -1464,48 +1641,54 @@ }; &cm_core_clockdomains { - coreaon_clkdm: coreaon_clkdm { + coreaon_clkdm: clock-coreaon-clkdm { compatible = "ti,clockdomain"; + clock-output-names = "coreaon_clkdm"; clocks = <&dpll_usb_ck>; }; }; &scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk@558 { + dss_deshdcp_clk: clock-dss-deshdcp-0@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "dss_deshdcp_clk"; clocks = <&l3_iclk_div>; ti,bit-shift = <0>; reg = <0x558>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@558 { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <20>; reg = <0x0558>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk@558 { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <21>; reg = <0x0558>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk@558 { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <22>; reg = <0x0558>; }; - sys_32k_ck: sys_32k_ck { + sys_32k_ck: clock-sys-32k { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_32k_ck"; clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; ti,bit-shift = <8>; reg = <0x6c4>; @@ -1513,97 +1696,110 @@ }; &cm_core_aon { - mpu_cm: mpu-cm@300 { + mpu_cm: clock@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; - mpu_clkctrl: mpu-clkctrl@20 { + mpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - dsp1_cm: dsp1-cm@400 { + dsp1_cm: clock@400 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp1_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - dsp1_clkctrl: dsp1-clkctrl@20 { + dsp1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - ipu_cm: ipu-cm@500 { + ipu_cm: clock@500 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; - ipu1_clkctrl: ipu1-clkctrl@20 { + ipu1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; assigned-clock-parents = <&dpll_core_h22x2_ck>; }; - ipu_clkctrl: ipu-clkctrl@50 { + ipu_clkctrl: clock@50 { compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; reg = <0x50 0x34>; #clock-cells = <2>; }; }; - dsp2_cm: dsp2-cm@600 { + dsp2_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp2_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - dsp2_clkctrl: dsp2-clkctrl@20 { + dsp2_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - rtc_cm: rtc-cm@700 { + rtc_cm: clock@700 { compatible = "ti,omap4-cm"; + clock-output-names = "rtc_cm"; reg = <0x700 0x60>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x60>; - rtc_clkctrl: rtc-clkctrl@20 { + rtc_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "rtc_clkctrl"; reg = <0x20 0x28>; #clock-cells = <2>; }; }; - vpe_cm: vpe-cm@760 { + vpe_cm: clock@760 { compatible = "ti,omap4-cm"; + clock-output-names = "vpe_cm"; reg = <0x760 0xc>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x760 0xc>; - vpe_clkctrl: vpe-clkctrl@0 { + vpe_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "vpe_clkctrl"; reg = <0x0 0xc>; #clock-cells = <2>; }; @@ -1612,212 +1808,242 @@ }; &cm_core { - coreaon_cm: coreaon-cm@600 { + coreaon_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "coreaon_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - coreaon_clkctrl: coreaon-clkctrl@20 { + coreaon_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "coreaon_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; - l3main1_cm: l3main1-cm@700 { + l3main1_cm: clock@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; - l3main1_clkctrl: l3main1-clkctrl@20 { + l3main1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; reg = <0x20 0x74>; #clock-cells = <2>; }; }; - ipu2_cm: ipu2-cm@900 { + ipu2_cm: clock@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu2_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - ipu2_clkctrl: ipu2-clkctrl@20 { + ipu2_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - dma_cm: dma-cm@a00 { + dma_cm: clock@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - dma_clkctrl: dma-clkctrl@20 { + dma_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - emif_cm: emif-cm@b00 { + emif_cm: clock@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; - emif_clkctrl: emif-clkctrl@20 { + emif_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - atl_cm: atl-cm@c00 { + atl_cm: clock@c00 { compatible = "ti,omap4-cm"; + clock-output-names = "atl_cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xc00 0x100>; - atl_clkctrl: atl-clkctrl@0 { + atl_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "atl_clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - l4cfg_cm: l4cfg-cm@d00 { + l4cfg_cm: clock@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; - l4cfg_clkctrl: l4cfg-clkctrl@20 { + l4cfg_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; reg = <0x20 0x84>; #clock-cells = <2>; }; }; - l3instr_cm: l3instr-cm@e00 { + l3instr_cm: clock@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; - l3instr_clkctrl: l3instr-clkctrl@20 { + l3instr_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - iva_cm: iva-cm@f00 { + iva_cm: clock@f00 { compatible = "ti,omap4-cm"; + clock-output-names = "iva_cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xf00 0x100>; - iva_clkctrl: iva-clkctrl@20 { + iva_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "iva_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - cam_cm: cam-cm@1000 { + cam_cm: clock@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "cam_cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x100>; - cam_clkctrl: cam-clkctrl@20 { + cam_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "cam_clkctrl"; reg = <0x20 0x2c>; #clock-cells = <2>; }; }; - dss_cm: dss-cm@1100 { + dss_cm: clock@1100 { compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1100 0x100>; - dss_clkctrl: dss-clkctrl@20 { + dss_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; - gpu_cm: gpu-cm@1200 { + gpu_cm: clock@1200 { compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1200 0x100>; - gpu_clkctrl: gpu-clkctrl@20 { + gpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l3init_cm: l3init-cm@1300 { + l3init_cm: clock@1300 { compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1300 0x100>; - l3init_clkctrl: l3init-clkctrl@20 { + l3init_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; reg = <0x20 0x6c>, <0xe0 0x14>; #clock-cells = <2>; }; - pcie_clkctrl: pcie-clkctrl@b0 { + pcie_clkctrl: clock@b0 { compatible = "ti,clkctrl"; + clock-output-names = "pcie_clkctrl"; reg = <0xb0 0xc>; #clock-cells = <2>; }; - gmac_clkctrl: gmac-clkctrl@d0 { + gmac_clkctrl: clock@d0 { compatible = "ti,clkctrl"; + clock-output-names = "gmac_clkctrl"; reg = <0xd0 0x4>; #clock-cells = <2>; }; }; - l4per_cm: l4per-cm@1700 { + l4per_cm: clock@1700 { compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; reg = <0x1700 0x300>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1700 0x300>; - l4per_clkctrl: l4per-clkctrl@28 { + l4per_clkctrl: clock@28 { compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; #clock-cells = <2>; @@ -1825,20 +2051,23 @@ assigned-clock-parents = <&abe_24m_fclk>; }; - l4sec_clkctrl: l4sec-clkctrl@1a0 { + l4sec_clkctrl: clock@1a0 { compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; reg = <0x1a0 0x2c>; #clock-cells = <2>; }; - l4per2_clkctrl: l4per2-clkctrl@c { + l4per2_clkctrl: clock@c { compatible = "ti,clkctrl"; + clock-output-names = "l4per2_clkctrl"; reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; #clock-cells = <2>; }; - l4per3_clkctrl: l4per3-clkctrl@14 { + l4per3_clkctrl: clock@14 { compatible = "ti,clkctrl"; + clock-output-names = "l4per3_clkctrl"; reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; #clock-cells = <2>; }; @@ -1847,15 +2076,17 @@ }; &prm { - wkupaon_cm: wkupaon-cm@1800 { + wkupaon_cm: clock@1800 { compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1800 0x100>; - wkupaon_clkctrl: wkupaon-clkctrl@20 { + wkupaon_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index ae644315855d..41bb421e67c2 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -269,7 +269,8 @@ }; timer@10050000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e81b3ee4e0f7..5fd17bc52321 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -373,7 +373,7 @@ status = "disabled"; }; - ehci: ehci@12580000 { + ehci: usb@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -384,7 +384,7 @@ phy-names = "host", "hsic0", "hsic1"; }; - ohci: ohci@12590000 { + ohci: usb@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index efaf7533e84f..36c369c42b77 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -119,8 +119,8 @@ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; - ethernet: usbether@2 { - compatible = "usb0424,9730"; + ethernet: ethernet@2 { + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index a9fada51eb50..1f17cc30ed14 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -70,19 +70,19 @@ phy-names = "hsic0"; hub@2 { - compatible = "usb0424,3503"; + compatible = "usb424,3503"; reg = <2>; #address-cells = <1>; #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { - compatible = "usb0424,ec00"; + ethernet: ethernet@1 { + compatible = "usb424,ec00"; reg = <1>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5baaa7eb71a4..df80ddfada2d 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -245,7 +245,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; @@ -817,15 +818,14 @@ status = "disabled"; }; - dp_phy: video-phy { + dp_phy: video-phy-0 { compatible = "samsung,exynos5250-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; - mipi_phy: video-phy@10040710 { + mipi_phy: video-phy-1 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10040710 0x100>; #phy-cells = <1>; syscon = <&pmu_system_controller>; }; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 56271e7c4587..ff1ee409eff3 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -333,7 +333,8 @@ }; mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index e54a3391854d..d1cbc6b8a570 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -655,8 +655,8 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@2 { - compatible = "usb0424,9730"; + ethernet: ethernet@2 { + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 2f65dcf6ba73..35818c4cd852 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,6 @@ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; @@ -358,10 +356,9 @@ tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings { compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 62c5928aa994..e3154a1cae23 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -113,13 +113,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { - compatible = "usb0424,ec00"; + ethernet: ethernet@1 { + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index cecaeb69e623..a378d4937ff7 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -80,13 +80,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { - compatible = "usb0424,ec00"; + ethernet: ethernet@1 { + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 2ddb7a5f12b3..3ec43761d8b9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,7 +74,8 @@ }; mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0xb00>; interrupts-extended = <&combiner 23 3>, <&combiner 23 4>, diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index b56524cc7fe2..5475e5de3d78 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -27,6 +27,8 @@ /* HS USB Host PHY on PORT 1 */ hsusb2_phy: hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_reset_pin>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ #phy-cells = <0>; @@ -144,6 +146,8 @@ }; &usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; port2-mode = "ehci-phy"; }; @@ -151,10 +155,7 @@ phys = <0 &hsusb2_phy>; }; - &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; mmc3_pins: pinmux_mm3_pins { pinctrl-single,pins = < @@ -250,8 +251,7 @@ }; &omap3_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; + hsusb2_reset_pin: pinmux_hsusb1_reset_pin { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 61ec929ab86e..56ea875c418c 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -65,7 +65,7 @@ pinctrl-0 = <&spi_nor_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25l1606e"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index a858ebfa1500..35eced6521ef 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -370,7 +370,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 2ec3628d3315..24adfac26be0 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -46,37 +46,61 @@ ti,bit-shift = <2>; }; - d2d_26m_fck: d2d_26m_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <3>; - }; - - fshostusb_fck: fshostusb_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <5>; - }; - - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + d2d_26m_fck: clock-d2d-26m-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "d2d_26m_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + fshostusb_fck: clock-fshostusb-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "fshostusb_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <5>; + }; + + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; + }; + + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + usb_l4_div_ick: clock-usb-l4-div-ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "usb_l4_div_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + ti,index-starts-at-one; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es1 { @@ -93,20 +117,43 @@ clock-div = <2>; }; - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - fac_ick: fac_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <8>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es1"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + fac_ick: clock-fac-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "fac_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <8>; + }; + + ssi_ick: clock-ssi-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "ssi_ick_3430es1"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; + + usb_l4_gate_ick: clock-usb-l4-gate-ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clock-output-names = "usb_l4_gate_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -117,45 +164,26 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@a10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; - }; - - usb_l4_div_ick: usb_l4_div_ick@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - usb_l4_ick: usb_l4_ick { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es1"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es1@e10 { diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 21079cdf2663..8374532f20e2 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -13,45 +13,76 @@ clock-div = <1>; }; - aes1_ick: aes1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - reg = <0x0a14>; - }; + clock@a14 { + compatible = "ti,clksel"; + reg = <0xa14>; + #clock-cells = <2>; + #address-cells = <0>; - rng_ick: rng_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <2>; - }; + aes1_ick: clock-aes1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + }; - sha11_ick: sha11_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <1>; - }; + rng_ick: clock-rng-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "rng_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <2>; + }; - des1_ick: des1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <0>; + sha11_ick: clock-sha11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha11_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <1>; + }; + + des1_ick: clock-des1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <0>; + }; + + pka_ick: clock-pka-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "pka_ick"; + clocks = <&security_l3_ick>; + ti,bit-shift = <4>; + }; }; - cam_mclk: cam_mclk@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - reg = <0x0f00>; - ti,set-rate-parent; + /* CM_FCLKEN_CAM */ + clock@f00 { + compatible = "ti,clksel"; + reg = <0xf00>; + #clock-cells = <2>; + #address-cells = <0>; + + cam_mclk: clock-cam-mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "cam_mclk"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + + csi2_96m_fck: clock-csi2-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "csi2_96m_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <1>; + }; }; cam_ick: cam_ick@f10 { @@ -62,14 +93,6 @@ ti,bit-shift = <0>; }; - csi2_96m_fck: csi2_96m_fck@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0f00>; - ti,bit-shift = <1>; - }; - security_l3_ick: security_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -78,44 +101,51 @@ clock-div = <1>; }; - pka_ick: pka_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l3_ick>; - reg = <0x0a14>; - ti,bit-shift = <4>; - }; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; - icr_ick: icr_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <29>; - }; + icr_ick: clock-icr-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "icr_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <29>; + }; - des2_ick: des2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <26>; - }; + des2_ick: clock-des2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <26>; + }; - mspro_ick: mspro_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; + mspro_ick: clock-mspro-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mspro_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; - mailboxes_ick: mailboxes_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <7>; + mailboxes_ick: clock-mailboxes-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mailboxes_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <7>; + }; + + sad2d_ick: clock-sad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -126,20 +156,27 @@ clock-div = <1>; }; - sr1_fck: sr1_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <6>; - }; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; - sr2_fck: sr2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <7>; + sr1_fck: clock-sr1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr1_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + sr2_fck: clock-sr2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr2_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; }; sr_l4_ick: sr_l4_ick { @@ -187,37 +224,45 @@ ti,bit-shift = <0>; }; - modem_fck: modem_fck@a00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <31>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; - sad2d_ick: sad2d_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <3>; - }; + modem_fck: clock-modem-fck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "modem_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <31>; + }; - mad2d_ick: mad2d_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a18>; - ti,bit-shift = <3>; + mspro_fck: clock-mspro-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mspro_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <23>; + }; }; - mspro_fck: mspro_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + mad2d_ick: clock-mad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; + }; &cm_clockdomains { diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 9974d5226971..dcc5cfcd1fe6 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -133,37 +133,66 @@ ti,bit-shift = <2>; }; - usbtll_ick: usbtll_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a18>; - ti,bit-shift = <2>; + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + usbtll_ick: clock-usbtll-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usbtll_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <2>; + }; }; - mmchs3_ick: mmchs3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <30>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_ick: clock-mmchs3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <30>; + }; }; - mmchs3_fck: mmchs3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <30>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_fck: clock-mmchs3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <30>; + }; }; - dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es2"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es2@e10 { diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 4e9cc9003594..c5fdb2bd765d 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -58,12 +58,19 @@ ti,set-bit-to-disable; }; - uart4_fck: uart4_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - ti,bit-shift = <18>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck: clock-uart4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <18>; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 945537aee3ca..c94eb86d3da7 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -5,21 +5,35 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; + }; + + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es2 { @@ -36,12 +50,27 @@ clock-div = <2>; }; - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es2"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + ssi_ick: clock-ssi-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clock-output-names = "ssi_ick_3430es2"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -52,20 +81,19 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; - usim_gate_fck: usim_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - reg = <0x0c00>; + usim_gate_fck: clock-usim-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "usim_gate_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + }; }; sys_d2_ck: sys_d2_ck { @@ -140,13 +168,20 @@ clock-div = <20>; }; - usim_mux_fck: usim_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_mux_fck: clock-usim-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "usim_mux_fck"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + ti,index-starts-at-one; + }; }; usim_fck: usim_fck { @@ -155,12 +190,19 @@ clocks = <&usim_gate_fck>, <&usim_mux_fck>; }; - usim_ick: usim_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <9>; + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_ick: clock-usim-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usim_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <9>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 0656c32439d2..2e13ca11ceea 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -78,12 +78,35 @@ }; &scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; + /* CONTROL_DEVCONF1 */ + clock@68 { + compatible = "ti,clksel"; reg = <0x68>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp5_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + + mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp3_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + }; + + mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp4_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; }; mcbsp5_fck: mcbsp5_fck { @@ -92,12 +115,28 @@ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; }; - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x04>; + /* CONTROL_DEVCONF0 */ + clock@4 { + compatible = "ti,clksel"; + reg = <0x4>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp1_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + + mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp2_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + }; }; mcbsp1_fck: mcbsp1_fck { @@ -106,41 +145,18 @@ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x04>; - }; - mcbsp2_fck: mcbsp2_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; }; - mcbsp3_mux_fck: mcbsp3_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x68>; - }; - mcbsp3_fck: mcbsp3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; - mcbsp4_mux_fck: mcbsp4_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x68>; - }; - mcbsp4_fck: mcbsp4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; @@ -238,14 +254,87 @@ reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; + /* CM_CLKSEL1_EMU */ + clock@1140 { + compatible = "ti,clksel"; reg = <0x1140>; - ti,index-starts-at-one; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m3_ck: clock-dpll3-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m3_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + dpll4_m6_ck: clock-dpll4-m6 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m6_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + ti,index-starts-at-one; + }; + + emu_src_mux_ck: clock-emu-src-mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "emu_src_mux_ck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + }; + + pclk_fck: clock-pclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + + pclkx2_fck: clock-pclkx2-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclkx2_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + atclk_fck: clock-atclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "atclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: clock-traceclk-src-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "traceclk_src_fck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + }; + + traceclk_fck: clock-traceclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "traceclk_fck"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; }; dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { @@ -285,16 +374,6 @@ clock-frequency = <0x0>; }; - dpll3_m2_ck: dpll3_m2_ck@d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - reg = <0x0d40>; - ti,index-starts-at-one; - }; - core_ck: core_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -345,22 +424,73 @@ clock-div = <1>; }; - omap_96m_fck: omap_96m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0d40>; - }; - - dpll4_m3_ck: dpll4_m3_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; + /* CM_CLKSEL1_PLL */ + clock@d40 { + compatible = "ti,clksel"; + reg = <0xd40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m2_ck: clock-dpll3-m2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m2_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + omap_96m_fck: clock-omap-96m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_96m_fck"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + omap_54m_fck: clock-omap-54m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_54m_fck"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + }; + + omap_48m_fck: clock-omap-48m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_48m_fck"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + }; + }; + + /* CM_CLKSEL_DSS */ + clock@e40 { + compatible = "ti,clksel"; + reg = <0xe40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll4_m3_ck: clock-dpll4-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m3_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-starts-at-one; + }; + + dpll4_m4_ck: clock-dpll4-m4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m4_ck"; + clocks = <&dpll4_ck>; + ti,max-div = <16>; + ti,index-starts-at-one; + }; }; dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { @@ -380,14 +510,6 @@ ti,set-bit-to-disable; }; - omap_54m_fck: omap_54m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - reg = <0x0d40>; - }; - cm_96m_d2_fck: cm_96m_d2_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -396,14 +518,6 @@ clock-div = <2>; }; - omap_48m_fck: omap_48m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - reg = <0x0d40>; - }; - omap_12m_fck: omap_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -412,15 +526,6 @@ clock-div = <4>; }; - dpll4_m4_ck: dpll4_m4_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <16>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; @@ -468,16 +573,6 @@ ti,set-rate-parent; }; - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -503,19 +598,37 @@ clock-div = <1>; }; - clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0d70>; - }; - - clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - reg = <0x0d70>; + /* CM_CLKOUT_CTRL */ + clock@d70 { + compatible = "ti,clksel"; + reg = <0xd70>; + #clock-cells = <2>; + #address-cells = <0>; + + clkout2_src_gate_ck: clock-clkout2-src-gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "clkout2_src_gate_ck"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + }; + + clkout2_src_mux_ck: clock-clkout2-src-mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "clkout2_src_mux_ck"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + }; + + sys_clkout2: clock-sys-clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clkout2"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + ti,index-power-of-two; + }; }; clkout2_src_ck: clkout2_src_ck { @@ -524,16 +637,6 @@ clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; }; - sys_clkout2: sys_clkout2@d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0d70>; - ti,index-power-of-two; - }; - mpu_ck: mpu_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -558,49 +661,208 @@ clock-div = <1>; }; - l3_ick: l3_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - l4_ick: l4_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - rm_ick: rm_ick@c40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; - }; - - gpt10_gate_fck: gpt10_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - reg = <0x0a00>; - }; - - gpt10_mux_fck: gpt10_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0a40>; + /* CM_CLKSEL_CORE */ + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + l3_ick: clock-l3-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_ick"; + clocks = <&core_ck>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + l4_ick: clock-l4-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt10_mux_fck: clock-gpt10-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt10_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt11_mux_fck: clock-gpt11-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt11_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; + }; + + /* CM_CLKSEL_WKUP */ + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + rm_ick: clock-rm-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "rm_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt1_mux_fck: clock-gpt1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt1_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + }; + + /* CM_FCLKEN1_CORE */ + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt10_gate_fck: clock-gpt10-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt10_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + }; + + gpt11_gate_fck: clock-gpt11-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt11_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + }; + + mmchs2_fck: clock-mmchs2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: clock-mmchs1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <24>; + }; + + i2c3_fck: clock-i2c3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <17>; + }; + + i2c2_fck: clock-i2c2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <16>; + }; + + i2c1_fck: clock-i2c1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp5_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + }; + + mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp1_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + }; + + mcspi4_fck: clock-mcspi4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi4_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: clock-mcspi3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi3_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: clock-mcspi2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: clock-mcspi1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <18>; + }; + + uart2_fck: clock-uart2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <14>; + }; + + uart1_fck: clock-uart1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <13>; + }; + + hdq_fck: clock-hdq-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "hdq_fck"; + clocks = <&core_12m_fck>; + ti,bit-shift = <22>; + }; }; gpt10_fck: gpt10_fck { @@ -609,22 +871,6 @@ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_gate_fck: gpt11_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - reg = <0x0a00>; - }; - - gpt11_mux_fck: gpt11_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x0a40>; - }; - gpt11_fck: gpt11_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; @@ -639,62 +885,6 @@ clock-div = <1>; }; - mmchs2_fck: mmchs2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: mmchs1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <24>; - }; - - i2c3_fck: i2c3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <17>; - }; - - i2c2_fck: i2c2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <16>; - }; - - i2c1_fck: i2c1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - reg = <0x0a00>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - reg = <0x0a00>; - }; - core_48m_fck: core_48m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -703,54 +893,6 @@ clock-div = <1>; }; - mcspi4_fck: mcspi4_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: mcspi3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: mcspi2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: mcspi1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <18>; - }; - - uart2_fck: uart2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <14>; - }; - - uart1_fck: uart1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <13>; - }; - core_12m_fck: core_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -759,14 +901,6 @@ clock-div = <1>; }; - hdq_fck: hdq_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_12m_fck>; - reg = <0x0a00>; - ti,bit-shift = <22>; - }; - core_l3_ick: core_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -775,12 +909,172 @@ clock-div = <1>; }; - sdrc_ick: sdrc_ick@a10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <1>; + /* CM_ICLKEN1_CORE */ + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + sdrc_ick: clock-sdrc-ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sdrc_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <1>; + }; + + mmchs2_ick: clock-mmchs2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: clock-mmchs1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <24>; + }; + + hdq_ick: clock-hdq-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "hdq_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: clock-mcspi4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi4_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: clock-mcspi3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: clock-mcspi2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: clock-mcspi1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <18>; + }; + + i2c3_ick: clock-i2c3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <17>; + }; + + i2c2_ick: clock-i2c2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <16>; + }; + + i2c1_ick: clock-i2c1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <15>; + }; + + uart2_ick: clock-uart2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <14>; + }; + + uart1_ick: clock-uart1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <13>; + }; + + gpt11_ick: clock-gpt11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt11_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <12>; + }; + + gpt10_ick: clock-gpt10-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt10_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: clock-mcbsp5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp5_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: clock-mcbsp1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: clock-omapctrl-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omapctrl_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <6>; + }; + + aes2_ick: clock-aes2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + }; + + sha12_ick: clock-sha12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha12_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <27>; + }; }; gpmc_fck: gpmc_fck { @@ -799,164 +1093,36 @@ clock-div = <1>; }; - mmchs2_ick: mmchs2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: mmchs1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <24>; - }; - - hdq_ick: hdq_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: mcspi4_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: mcspi3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: mcspi2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: mcspi1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <18>; - }; - - i2c3_ick: i2c3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <17>; - }; - - i2c2_ick: i2c2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <16>; - }; - - i2c1_ick: i2c1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <15>; - }; - - uart2_ick: uart2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <14>; - }; - - uart1_ick: uart1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <13>; - }; - - gpt11_ick: gpt11_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <12>; - }; - - gpt10_ick: gpt10_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: mcbsp5_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: mcbsp1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: omapctrl_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <6>; - }; - - dss_tv_fck: dss_tv_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_54m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss_96m_fck: dss_96m_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_96m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss2_alwon_fck: dss2_alwon_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0e00>; - ti,bit-shift = <1>; + /* CM_FCLKEN_DSS */ + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss_tv_fck: clock-dss-tv-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_tv_fck"; + clocks = <&omap_54m_fck>; + ti,bit-shift = <2>; + }; + + dss_96m_fck: clock-dss-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_96m_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: clock-dss2-alwon-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss2_alwon_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + }; }; dummy_ck: dummy_ck { @@ -965,19 +1131,36 @@ clock-frequency = <0>; }; - gpt1_gate_fck: gpt1_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0c00>; - }; - - gpt1_mux_fck: gpt1_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x0c40>; + /* CM_FCLKEN_WKUP */ + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt1_gate_fck: clock-gpt1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt1_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + }; + + gpio1_dbck: clock-gpio1-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio1_dbck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <3>; + }; + + wdt2_fck: clock-wdt2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt2_fck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <5>; + }; }; gpt1_fck: gpt1_fck { @@ -986,14 +1169,6 @@ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; - aes2_ick: aes2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - reg = <0x0a10>; - }; - wkup_32k_fck: wkup_32k_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1002,76 +1177,60 @@ clock-div = <1>; }; - gpio1_dbck: gpio1_dbck@c00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <3>; - }; - - sha12_ick: sha12_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <27>; - }; - - wdt2_fck: wdt2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <5>; - }; - - wdt2_ick: wdt2_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <5>; - }; - - wdt1_ick: wdt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <4>; - }; - - gpio1_ick: gpio1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <3>; - }; - - omap_32ksync_ick: omap_32ksync_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <2>; - }; - - gpt12_ick: gpt12_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <1>; - }; - - gpt1_ick: gpt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <0>; + /* CM_ICLKEN_WKUP */ + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + wdt2_ick: clock-wdt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt2_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <5>; + }; + + wdt1_ick: clock-wdt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <4>; + }; + + gpio1_ick: clock-gpio1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <3>; + }; + + omap_32ksync_ick: clock-omap-32ksync-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omap_32ksync_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <2>; + }; + + gpt12_ick: clock-gpt12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt12_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <1>; + }; + + gpt1_ick: clock-gpt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <0>; + }; }; per_96m_fck: per_96m_fck { @@ -1090,27 +1249,227 @@ clock-div = <1>; }; - uart3_fck: uart3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; - reg = <0x1000>; - ti,bit-shift = <11>; - }; - - gpt2_gate_fck: gpt2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; + /* CM_FCLKEN_PER */ + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - }; - - gpt2_mux_fck: gpt2_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; + #clock-cells = <2>; + #address-cells = <0>; + + uart3_fck: clock-uart3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart3_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: clock-gpt2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt2_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt3_gate_fck: clock-gpt3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt3_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt4_gate_fck: clock-gpt4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt4_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt5_gate_fck: clock-gpt5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt5_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt6_gate_fck: clock-gpt6-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt6_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; + + gpt7_gate_fck: clock-gpt7-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt7_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + }; + + gpt8_gate_fck: clock-gpt8-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt8_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + }; + + gpt9_gate_fck: clock-gpt9-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt9_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + }; + + gpio6_dbck: clock-gpio6-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio6_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: clock-gpio5-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio5_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: clock-gpio4-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio4_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: clock-gpio3-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio3_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: clock-gpio2-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio2_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <13>; + }; + + wdt3_fck: clock-wdt3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt3_fck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <12>; + }; + + mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp2_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + }; + + mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp3_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + }; + + mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp4_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + }; + + /* CM_CLKSEL_PER */ + clock@1040 { + compatible = "ti,clksel"; reg = <0x1040>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt2_mux_fck: clock-gpt2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt2_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + + gpt3_mux_fck: clock-gpt3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt3_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + }; + + gpt4_mux_fck: clock-gpt4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt4_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + }; + + gpt5_mux_fck: clock-gpt5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt5_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt6_mux_fck: clock-gpt6-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt6_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt7_mux_fck: clock-gpt7-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt7_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt8_mux_fck: clock-gpt8-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt8_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt9_mux_fck: clock-gpt9-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt9_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; }; gpt2_fck: gpt2_fck { @@ -1119,154 +1478,42 @@ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_gate_fck: gpt3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1000>; - }; - - gpt3_mux_fck: gpt3_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x1040>; - }; - gpt3_fck: gpt3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_gate_fck: gpt4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1000>; - }; - - gpt4_mux_fck: gpt4_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x1040>; - }; - gpt4_fck: gpt4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_gate_fck: gpt5_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1000>; - }; - - gpt5_mux_fck: gpt5_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1040>; - }; - gpt5_fck: gpt5_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_gate_fck: gpt6_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1000>; - }; - - gpt6_mux_fck: gpt6_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1040>; - }; - gpt6_fck: gpt6_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_gate_fck: gpt7_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - reg = <0x1000>; - }; - - gpt7_mux_fck: gpt7_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1040>; - }; - gpt7_fck: gpt7_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_gate_fck: gpt8_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - reg = <0x1000>; - }; - - gpt8_mux_fck: gpt8_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1040>; - }; - gpt8_fck: gpt8_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_gate_fck: gpt9_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - reg = <0x1000>; - }; - - gpt9_mux_fck: gpt9_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1040>; - }; - gpt9_fck: gpt9_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; @@ -1281,54 +1528,6 @@ clock-div = <1>; }; - gpio6_dbck: gpio6_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: gpio5_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: gpio4_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: gpio3_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: gpio2_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <13>; - }; - - wdt3_fck: wdt3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <12>; - }; - per_l4_ick: per_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1337,187 +1536,164 @@ clock-div = <1>; }; - gpio6_ick: gpio6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <17>; - }; - - gpio5_ick: gpio5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <16>; - }; - - gpio4_ick: gpio4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <15>; - }; - - gpio3_ick: gpio3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <14>; - }; - - gpio2_ick: gpio2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <13>; - }; - - wdt3_ick: wdt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <12>; - }; - - uart3_ick: uart3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <11>; - }; - - uart4_ick: uart4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <18>; - }; - - gpt9_ick: gpt9_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <10>; - }; - - gpt8_ick: gpt8_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <9>; - }; - - gpt7_ick: gpt7_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <8>; - }; - - gpt6_ick: gpt6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <7>; - }; - - gpt5_ick: gpt5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <6>; - }; - - gpt4_ick: gpt4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <5>; - }; - - gpt3_ick: gpt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <4>; - }; - - gpt2_ick: gpt2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <3>; - }; - - mcbsp2_ick: mcbsp2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <0>; - }; - - mcbsp3_ick: mcbsp3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <1>; - }; - - mcbsp4_ick: mcbsp4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; + /* CM_ICLKEN_PER */ + clock@1010 { + compatible = "ti,clksel"; reg = <0x1010>; - ti,bit-shift = <2>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - reg = <0x1000>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - reg = <0x1000>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x1000>; - }; - - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; + #clock-cells = <2>; + #address-cells = <0>; + + gpio6_ick: clock-gpio6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <17>; + }; + + gpio5_ick: clock-gpio5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <16>; + }; + + gpio4_ick: clock-gpio4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <15>; + }; + + gpio3_ick: clock-gpio3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <14>; + }; + + gpio2_ick: clock-gpio2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <13>; + }; + + wdt3_ick: clock-wdt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <12>; + }; + + uart3_ick: clock-uart3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <11>; + }; + + uart4_ick: clock-uart4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <18>; + }; + + gpt9_ick: clock-gpt9-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt9_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <10>; + }; + + gpt8_ick: clock-gpt8-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt8_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <9>; + }; + + gpt7_ick: clock-gpt7-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt7_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <8>; + }; + + gpt6_ick: clock-gpt6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <7>; + }; + + gpt5_ick: clock-gpt5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <6>; + }; + + gpt4_ick: clock-gpt4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <5>; + }; + + gpt3_ick: clock-gpt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <4>; + }; + + gpt2_ick: clock-gpt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <3>; + }; + + mcbsp2_ick: clock-mcbsp2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <0>; + }; + + mcbsp3_ick: clock-mcbsp3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: clock-mcbsp4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <2>; + }; }; emu_src_ck: emu_src_ck { @@ -1526,54 +1702,6 @@ clocks = <&emu_src_mux_ck>; }; - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - secure_32k_fck: secure_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 609a8dea946b..518652a599bd 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -558,7 +558,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi index 39297868ec85..581e088231b5 100644 --- a/arch/arm/boot/dts/omap443x-clocks.dtsi +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi @@ -8,6 +8,7 @@ bandgap_fclk: bandgap_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_fclk"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi index 0f41714cffbb..d9362fef6720 100644 --- a/arch/arm/boot/dts/omap446x-clocks.dtsi +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi @@ -8,6 +8,7 @@ div_ts_ck: div_ts_ck@1888 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_ts_ck"; clocks = <&l4_wkup_clk_mux_ck>; ti,bit-shift = <24>; reg = <0x1888>; @@ -17,6 +18,7 @@ bandgap_ts_fclk: bandgap_ts_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_ts_fclk"; clocks = <&div_ts_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 1f1c04d8f472..8df73d285638 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -8,18 +8,21 @@ extalt_clkin_ck: extalt_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "extalt_clkin_ck"; clock-frequency = <59000000>; }; pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; @@ -28,24 +31,28 @@ pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_slimbus_core_clks_ck"; clock-frequency = <12000000>; }; secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; @@ -54,84 +61,98 @@ sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; tie_low_clock_ck: tie_low_clock_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tie_low_clock_ck"; clock-frequency = <0>; }; utmi_phy_clkout_ck: utmi_phy_clkout_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "utmi_phy_clkout_ck"; clock-frequency = <60000000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; clock-frequency = <60000000>; }; xclk60motg_ck: xclk60motg_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60motg_ck"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; @@ -139,6 +160,7 @@ dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; reg = <0x01f0>; }; @@ -146,6 +168,7 @@ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -157,6 +180,7 @@ abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -165,6 +189,7 @@ abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; @@ -175,6 +200,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -186,6 +212,7 @@ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "core_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; @@ -194,6 +221,7 @@ dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; @@ -201,12 +229,14 @@ dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -218,6 +248,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -229,6 +260,7 @@ ddrphy_ck: ddrphy_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "ddrphy_ck"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <2>; @@ -237,6 +269,7 @@ dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -248,6 +281,7 @@ div_core_ck: div_core_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_core_ck"; clocks = <&dpll_core_m5x2_ck>; reg = <0x0100>; ti,max-div = <2>; @@ -256,6 +290,7 @@ div_iva_hs_clk: div_iva_hs_clk@1dc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_iva_hs_clk"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x01dc>; @@ -265,6 +300,7 @@ div_mpu_hs_clk: div_mpu_hs_clk@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_mpu_hs_clk"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x019c>; @@ -274,6 +310,7 @@ dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -285,6 +322,7 @@ dll_clk_div_ck: dll_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dll_clk_div_ck"; clocks = <&dpll_core_m4x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -293,6 +331,7 @@ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; reg = <0x01f0>; @@ -302,6 +341,7 @@ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_core_m3x2_gate_ck"; clocks = <&dpll_core_x2_ck>; ti,bit-shift = <8>; reg = <0x0134>; @@ -310,6 +350,7 @@ dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_core_m3x2_div_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; @@ -319,12 +360,14 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "dpll_core_m3x2_ck"; clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; }; dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m7x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -336,6 +379,7 @@ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "iva_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; ti,bit-shift = <23>; reg = <0x01ac>; @@ -344,6 +388,7 @@ dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; @@ -353,12 +398,14 @@ dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; clocks = <&dpll_iva_ck>; }; dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m4x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -372,6 +419,7 @@ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m5x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -385,6 +433,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; @@ -392,6 +441,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -403,6 +453,7 @@ per_hs_clk_div_ck: per_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_hs_clk_div_ck"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -411,6 +462,7 @@ usb_hs_clk_div_ck: usb_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_hs_clk_div_ck"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; @@ -419,6 +471,7 @@ l3_div_ck: l3_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_div_ck"; clocks = <&div_core_ck>; ti,bit-shift = <4>; ti,max-div = <2>; @@ -428,6 +481,7 @@ l4_div_ck: l4_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l4_div_ck"; clocks = <&l3_div_ck>; ti,bit-shift = <8>; ti,max-div = <2>; @@ -437,6 +491,7 @@ lp_clk_div_ck: lp_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "lp_clk_div_ck"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -445,6 +500,7 @@ mpu_periphclk: mpu_periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; clocks = <&dpll_mpu_ck>; clock-mult = <1>; clock-div = <2>; @@ -453,6 +509,7 @@ ocp_abe_iclk: ocp_abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "ocp_abe_iclk"; clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; ti,bit-shift = <24>; reg = <0x0528>; @@ -462,6 +519,7 @@ per_abe_24m_fclk: per_abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_abe_24m_fclk"; clocks = <&dpll_abe_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -470,6 +528,7 @@ dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; @@ -478,6 +537,7 @@ sys_clkin_ck: sys_clkin_ck@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; @@ -486,6 +546,7 @@ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; reg = <0x0108>; @@ -494,6 +555,7 @@ abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_refclk_mux_ck"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; reg = <0x010c>; }; @@ -501,6 +563,7 @@ dbgclk_mux_ck: dbgclk_mux_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dbgclk_mux_ck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; @@ -509,6 +572,7 @@ l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "l4_wkup_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; reg = <0x0108>; }; @@ -516,6 +580,7 @@ syc_clk_div_ck: syc_clk_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "syc_clk_div_ck"; clocks = <&sys_clkin_ck>; reg = <0x0100>; ti,max-div = <2>; @@ -524,6 +589,7 @@ usim_ck: usim_ck@1858 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "usim_ck"; clocks = <&dpll_per_m4x2_ck>; ti,bit-shift = <24>; reg = <0x1858>; @@ -533,6 +599,7 @@ usim_fclk: usim_fclk@1858 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usim_fclk"; clocks = <&usim_ck>; ti,bit-shift = <8>; reg = <0x1858>; @@ -541,6 +608,7 @@ trace_clk_div_ck: trace_clk_div_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; + clock-output-names = "trace_clk_div_ck"; clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; }; }; @@ -548,6 +616,7 @@ &prm_clockdomains { emu_sys_clkdm: emu_sys_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "emu_sys_clkdm"; clocks = <&trace_clk_div_ck>; }; }; @@ -556,6 +625,7 @@ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "per_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; ti,bit-shift = <23>; reg = <0x014c>; @@ -564,6 +634,7 @@ dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; @@ -571,6 +642,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -580,6 +652,7 @@ dpll_per_x2_ck: dpll_per_x2_ck@150 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; reg = <0x0150>; }; @@ -587,6 +660,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -598,6 +672,7 @@ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_per_m3x2_gate_ck"; clocks = <&dpll_per_x2_ck>; ti,bit-shift = <8>; reg = <0x0154>; @@ -606,6 +681,7 @@ dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_per_m3x2_div_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; @@ -615,12 +691,14 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "dpll_per_m3x2_ck"; clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; }; dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m4x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -632,6 +710,7 @@ dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m5x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -643,6 +722,7 @@ dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m6x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -654,6 +734,7 @@ dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m7x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -665,6 +746,7 @@ dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; @@ -672,6 +754,7 @@ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo_ck"; clocks = <&dpll_usb_ck>; ti,clock-div = <1>; ti,autoidle-shift = <8>; @@ -683,6 +766,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -694,6 +778,7 @@ ducati_clk_mux_ck: ducati_clk_mux_ck@100 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "ducati_clk_mux_ck"; clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; reg = <0x0100>; }; @@ -701,6 +786,7 @@ func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -709,6 +795,7 @@ func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -717,6 +804,7 @@ func_24mc_fclk: func_24mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24mc_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -725,6 +813,7 @@ func_48m_fclk: func_48m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <4>, <8>; @@ -733,6 +822,7 @@ func_48mc_fclk: func_48mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48mc_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; @@ -741,6 +831,7 @@ func_64m_fclk: func_64m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_64m_fclk"; clocks = <&dpll_per_m4x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; @@ -749,6 +840,7 @@ func_96m_fclk: func_96m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; @@ -757,6 +849,7 @@ init_60m_fclk: init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; @@ -765,6 +858,7 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_nc_fclk"; clocks = <&dpll_abe_m2_ck>; reg = <0x0108>; ti,max-div = <2>; @@ -773,6 +867,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; @@ -782,6 +877,7 @@ &cm2_clockdomains { l3_init_clkdm: l3_init_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "l3_init_clkdm"; clocks = <&dpll_usb_ck>; }; }; @@ -790,6 +886,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; @@ -798,6 +895,7 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; @@ -806,12 +904,14 @@ auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -821,6 +921,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; @@ -829,6 +930,7 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; @@ -837,12 +939,14 @@ auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -852,6 +956,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; @@ -860,6 +965,7 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; @@ -868,12 +974,14 @@ auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -883,6 +991,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; @@ -891,6 +1000,7 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; @@ -899,12 +1009,14 @@ auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -914,6 +1026,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; @@ -922,6 +1035,7 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; @@ -930,12 +1044,14 @@ auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -945,6 +1061,7 @@ auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk5_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0324>; @@ -953,6 +1070,7 @@ auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk5_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0324>; @@ -961,12 +1079,14 @@ auxclk5_src_ck: auxclk5_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk5_src_ck"; clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; }; auxclk5_ck: auxclk5_ck@324 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk5_ck"; clocks = <&auxclk5_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -976,6 +1096,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0210>; @@ -984,6 +1105,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0214>; @@ -992,6 +1114,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0218>; @@ -1000,6 +1123,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x021c>; @@ -1008,6 +1132,7 @@ auxclkreq4_ck: auxclkreq4_ck@220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq4_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0220>; @@ -1016,6 +1141,7 @@ auxclkreq5_ck: auxclkreq5_ck@224 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq5_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0224>; @@ -1025,6 +1151,7 @@ &cm1 { mpuss_cm: mpuss_cm@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpuss_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1032,6 +1159,7 @@ mpuss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpuss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1039,6 +1167,7 @@ tesla_cm: tesla_cm@400 { compatible = "ti,omap4-cm"; + clock-output-names = "tesla_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1046,6 +1175,7 @@ tesla_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "tesla_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1053,6 +1183,7 @@ abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1060,6 +1191,7 @@ abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; @@ -1070,6 +1202,7 @@ &cm2 { l4_ao_cm: l4_ao_cm@600 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_ao_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1077,6 +1210,7 @@ l4_ao_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_ao_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1084,6 +1218,7 @@ l3_1_cm: l3_1_cm@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1091,6 +1226,7 @@ l3_1_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1098,6 +1234,7 @@ l3_2_cm: l3_2_cm@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_2_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1105,6 +1242,7 @@ l3_2_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_2_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1112,6 +1250,7 @@ ducati_cm: ducati_cm@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ducati_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1119,6 +1258,7 @@ ducati_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ducati_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1126,6 +1266,7 @@ l3_dma_cm: l3_dma_cm@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1133,6 +1274,7 @@ l3_dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1140,6 +1282,7 @@ l3_emif_cm: l3_emif_cm@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1147,6 +1290,7 @@ l3_emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_emif_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1154,6 +1298,7 @@ d2d_cm: d2d_cm@c00 { compatible = "ti,omap4-cm"; + clock-output-names = "d2d_cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1161,6 +1306,7 @@ d2d_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "d2d_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1168,6 +1314,7 @@ l4_cfg_cm: l4_cfg_cm@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1175,6 +1322,7 @@ l4_cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_cfg_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1182,6 +1330,7 @@ l3_instr_cm: l3_instr_cm@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1189,6 +1338,7 @@ l3_instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_instr_clkctrl"; reg = <0x20 0x24>; #clock-cells = <2>; }; @@ -1196,6 +1346,7 @@ ivahd_cm: ivahd_cm@f00 { compatible = "ti,omap4-cm"; + clock-output-names = "ivahd_cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1203,6 +1354,7 @@ ivahd_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ivahd_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1210,6 +1362,7 @@ iss_cm: iss_cm@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "iss_cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1217,6 +1370,7 @@ iss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "iss_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1224,6 +1378,7 @@ l3_dss_cm: l3_dss_cm@1100 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_dss_cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1231,6 +1386,7 @@ l3_dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_dss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1238,6 +1394,7 @@ l3_gfx_cm: l3_gfx_cm@1200 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_gfx_cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1245,6 +1402,7 @@ l3_gfx_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_gfx_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1252,6 +1410,7 @@ l3_init_cm: l3_init_cm@1300 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_init_cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1259,26 +1418,30 @@ l3_init_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_init_clkctrl"; reg = <0x20 0xc4>; #clock-cells = <2>; }; }; - l4_per_cm: l4_per_cm@1400 { + l4_per_cm: clock@1400 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_per_cm"; reg = <0x1400 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1400 0x200>; l4_per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_per_clkctrl"; reg = <0x20 0x144>; #clock-cells = <2>; }; l4_secure_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_secure_clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; }; @@ -1288,6 +1451,7 @@ &prm { l4_wkup_cm: l4_wkup_cm@1800 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_wkup_cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1295,6 +1459,7 @@ l4_wkup_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; @@ -1302,6 +1467,7 @@ emu_sys_cm: emu_sys_cm@1a00 { compatible = "ti,omap4-cm"; + clock-output-names = "emu_sys_cm"; reg = <0x1a00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1309,6 +1475,7 @@ emu_sys_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "emu_sys_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 76e499d89d24..3851120857d7 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -128,7 +128,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@3 { + ethernet: ethernet@3 { compatible = "usb424,7500"; reg = <3>; }; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 51d5fcae5081..453da9f18a99 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -209,7 +209,7 @@ #size-cells = <0>; }; - ethernet: usbether@3 { + ethernet: ethernet@3 { compatible = "usb424,9730"; reg = <3>; }; diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 42f2c447727d..5cf3b0e78c15 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -8,12 +8,14 @@ pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; @@ -22,18 +24,21 @@ secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; @@ -42,66 +47,77 @@ sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; @@ -109,12 +125,14 @@ dpll_abe_x2_ck: dpll_abe_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; }; dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f0>; @@ -124,6 +142,7 @@ abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -132,6 +151,7 @@ abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; @@ -141,6 +161,7 @@ abe_iclk: abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_iclk"; clocks = <&aess_fclk>; ti,bit-shift = <24>; reg = <0x0528>; @@ -150,6 +171,7 @@ abe_lp_clk_div: abe_lp_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_lp_clk_div"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -158,6 +180,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f4>; @@ -167,6 +190,7 @@ dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; @@ -175,6 +199,7 @@ dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; @@ -182,12 +207,14 @@ dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h21x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0150>; @@ -197,6 +224,7 @@ c2c_fclk: c2c_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "c2c_fclk"; clocks = <&dpll_core_h21x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -205,6 +233,7 @@ c2c_iclk: c2c_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "c2c_iclk"; clocks = <&c2c_fclk>; clock-mult = <1>; clock-div = <2>; @@ -213,6 +242,7 @@ dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h11x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0138>; @@ -222,6 +252,7 @@ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x013c>; @@ -231,6 +262,7 @@ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0140>; @@ -240,6 +272,7 @@ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0144>; @@ -249,6 +282,7 @@ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0154>; @@ -258,6 +292,7 @@ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0158>; @@ -267,6 +302,7 @@ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x015c>; @@ -276,6 +312,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; reg = <0x0130>; @@ -285,6 +322,7 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m3x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; @@ -294,6 +332,7 @@ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -302,6 +341,7 @@ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; @@ -310,6 +350,7 @@ dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; @@ -319,12 +360,14 @@ dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; clocks = <&dpll_iva_ck>; }; dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h11x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01b8>; @@ -336,6 +379,7 @@ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h12x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01bc>; @@ -347,6 +391,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -355,6 +400,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; @@ -362,6 +408,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x0170>; @@ -371,6 +418,7 @@ per_dpll_hs_clk_div: per_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -379,6 +427,7 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; @@ -387,6 +436,7 @@ l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x100>; @@ -397,6 +447,7 @@ gpu_l3_iclk: gpu_l3_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gpu_l3_iclk"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <1>; @@ -405,6 +456,7 @@ l4_root_clk_div: l4_root_clk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l4_root_clk_div"; ti,max-div = <2>; ti,bit-shift = <8>; reg = <0x100>; @@ -415,6 +467,7 @@ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus1_slimbus_clk"; clocks = <&slimbus_clk>; ti,bit-shift = <11>; reg = <0x0560>; @@ -423,6 +476,7 @@ aess_fclk: aess_fclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; clocks = <&abe_clk>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -432,6 +486,7 @@ mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mcasp_sync_mux_ck"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; ti,bit-shift = <26>; reg = <0x0540>; @@ -440,6 +495,7 @@ mcasp_gfclk: mcasp_gfclk@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mcasp_gfclk"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; ti,bit-shift = <24>; reg = <0x0540>; @@ -448,6 +504,7 @@ dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; @@ -455,6 +512,7 @@ sys_clkin: sys_clkin@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; @@ -463,6 +521,7 @@ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x0108>; }; @@ -470,6 +529,7 @@ abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x010c>; }; @@ -477,6 +537,7 @@ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <2>; @@ -485,6 +546,7 @@ dss_syc_gfclk_div: dss_syc_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dss_syc_gfclk_div"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <1>; @@ -493,6 +555,7 @@ wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; clocks = <&sys_clkin>, <&abe_lp_clk_div>; reg = <0x0108>; }; @@ -500,6 +563,7 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3instr_ts_gclk_div"; clocks = <&wkupaon_iclk_mux>; clock-mult = <1>; clock-div = <1>; @@ -511,6 +575,7 @@ dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; @@ -519,6 +584,7 @@ dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; @@ -526,12 +592,14 @@ dpll_per_x2_ck: dpll_per_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; }; dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0158>; @@ -541,6 +609,7 @@ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x015c>; @@ -550,6 +619,7 @@ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0164>; @@ -559,6 +629,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -568,6 +639,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -577,6 +649,7 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m3x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; @@ -586,6 +659,7 @@ dpll_unipro1_ck: dpll_unipro1_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro1_ck"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; @@ -593,6 +667,7 @@ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro1_clkdcoldo"; clocks = <&dpll_unipro1_ck>; clock-mult = <1>; clock-div = <1>; @@ -601,6 +676,7 @@ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro1_m2_ck"; clocks = <&dpll_unipro1_ck>; ti,max-div = <127>; reg = <0x0210>; @@ -610,6 +686,7 @@ dpll_unipro2_ck: dpll_unipro2_ck@1c0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro2_ck"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; }; @@ -617,6 +694,7 @@ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro2_clkdcoldo"; clocks = <&dpll_unipro2_ck>; clock-mult = <1>; clock-div = <1>; @@ -625,6 +703,7 @@ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro2_m2_ck"; clocks = <&dpll_unipro2_ck>; ti,max-div = <127>; reg = <0x01d0>; @@ -634,6 +713,7 @@ dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; @@ -642,6 +722,7 @@ dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; @@ -649,6 +730,7 @@ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; @@ -657,6 +739,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; reg = <0x0190>; @@ -666,6 +749,7 @@ func_128m_clk: func_128m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -674,6 +758,7 @@ func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -682,6 +767,7 @@ func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -690,6 +776,7 @@ func_48m_fclk: func_48m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; @@ -698,6 +785,7 @@ func_96m_fclk: func_96m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -706,6 +794,7 @@ l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; @@ -714,6 +803,7 @@ iss_ctrlclk: iss_ctrlclk@1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "iss_ctrlclk"; clocks = <&func_96m_fclk>; ti,bit-shift = <8>; reg = <0x1320>; @@ -722,6 +812,7 @@ lli_txphy_clk: lli_txphy_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_clk"; clocks = <&dpll_unipro1_clkdcoldo>; ti,bit-shift = <8>; reg = <0x0f20>; @@ -730,6 +821,7 @@ lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_ls_clk"; clocks = <&dpll_unipro1_m2_ck>; ti,bit-shift = <9>; reg = <0x0f20>; @@ -738,6 +830,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; @@ -746,6 +839,7 @@ fdif_fclk: fdif_fclk@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "fdif_fclk"; clocks = <&dpll_per_h11x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -755,6 +849,7 @@ gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <24>; reg = <0x1520>; @@ -763,6 +858,7 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <25>; reg = <0x1520>; @@ -771,6 +867,7 @@ hsi_fclk: hsi_fclk@1638 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "hsi_fclk"; clocks = <&dpll_per_m2x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -781,6 +878,7 @@ &cm_core_clockdomains { l3init_clkdm: l3init_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "l3init_clkdm"; clocks = <&dpll_usb_ck>; }; }; @@ -789,6 +887,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; @@ -797,6 +896,7 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; @@ -805,12 +905,14 @@ auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -820,6 +922,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; @@ -828,6 +931,7 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; @@ -836,12 +940,14 @@ auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -851,6 +957,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; @@ -859,6 +966,7 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; @@ -867,12 +975,14 @@ auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -882,6 +992,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; @@ -890,6 +1001,7 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; @@ -898,12 +1010,14 @@ auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -913,6 +1027,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; @@ -921,6 +1036,7 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; @@ -929,12 +1045,14 @@ auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -944,6 +1062,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0210>; @@ -952,6 +1071,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0214>; @@ -960,6 +1080,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0218>; @@ -968,6 +1089,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x021c>; @@ -977,6 +1099,7 @@ &cm_core_aon { mpu_cm: mpu_cm@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -984,6 +1107,7 @@ mpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -991,6 +1115,7 @@ dsp_cm: dsp_cm@400 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -998,6 +1123,7 @@ dsp_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1005,6 +1131,7 @@ abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1012,6 +1139,7 @@ abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; reg = <0x20 0x64>; #clock-cells = <2>; }; @@ -1022,6 +1150,7 @@ &cm_core { l3main1_cm: l3main1_cm@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1029,6 +1158,7 @@ l3main1_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1036,6 +1166,7 @@ l3main2_cm: l3main2_cm@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main2_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1043,6 +1174,7 @@ l3main2_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1050,6 +1182,7 @@ ipu_cm: ipu_cm@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1057,6 +1190,7 @@ ipu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1064,6 +1198,7 @@ dma_cm: dma_cm@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1071,6 +1206,7 @@ dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1078,6 +1214,7 @@ emif_cm: emif_cm@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1085,6 +1222,7 @@ emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1092,6 +1230,7 @@ l4cfg_cm: l4cfg_cm@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1099,6 +1238,7 @@ l4cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1106,6 +1246,7 @@ l3instr_cm: l3instr_cm@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1113,26 +1254,30 @@ l3instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - l4per_cm: l4per_cm@1000 { + l4per_cm: clock@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; reg = <0x1000 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x200>; l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; reg = <0x20 0x15c>; #clock-cells = <2>; }; l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; }; @@ -1140,6 +1285,7 @@ dss_cm: dss_cm@1400 { compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; reg = <0x1400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1147,6 +1293,7 @@ dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1154,6 +1301,7 @@ gpu_cm: gpu_cm@1500 { compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; reg = <0x1500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1161,6 +1309,7 @@ gpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1168,6 +1317,7 @@ l3init_cm: l3init_cm@1600 { compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; reg = <0x1600 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1175,6 +1325,7 @@ l3init_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; reg = <0x20 0xd4>; #clock-cells = <2>; }; @@ -1184,6 +1335,7 @@ &prm { wkupaon_cm: wkupaon_cm@1900 { compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; reg = <0x1900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1191,6 +1343,7 @@ wkupaon_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; @@ -1201,6 +1354,7 @@ fref_xtal_ck: fref_xtal_ck { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "fref_xtal_ck"; clocks = <&sys_clkin>; ti,bit-shift = <28>; reg = <0x14>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 3502b5dcc04f..c0c145a5fe8d 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -140,6 +140,7 @@ compatible = "renesas,r8a7743-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index f5d4b8b85b6d..3f4fb53dd6df 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -140,6 +140,7 @@ compatible = "renesas,r8a7744-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index f877c51f769c..fe8e98a66d93 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -270,6 +270,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7745-wdt", "renesas,rcar-gen2-wdt"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 13ef1e9bf4d5..c90f2a270214 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -91,6 +91,7 @@ compatible = "renesas,r8a77470-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ed6dd4fcc503..a640488d513b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -274,6 +274,7 @@ compatible = "renesas,r8a7790-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0ccc162d3c2c..542ed0a71872 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -161,6 +161,7 @@ compatible = "renesas,r8a7791-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 9cdb73894ac2..a6d9367f8fa0 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -111,6 +111,7 @@ compatible = "renesas,r8a7792-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index dea4b1e108af..9ebe7bfaf0ed 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -146,6 +146,7 @@ compatible = "renesas,r8a7793-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index eac9ed8df0be..b601ee6f7580 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -128,6 +128,7 @@ compatible = "renesas,r8a7794-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 636a6ab31c58..2257706ce84f 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -214,8 +214,7 @@ }; timer { - compatible = "arm,cortex-a7-timer", - "arm,armv7-timer"; + compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; arm,cpu-registers-not-fw-configured; always-on; diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 54de3bc77c30..bc0b7354b6c0 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -29,8 +29,7 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x18000000>; + reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>; }; pmic_ap_clk: clock-0 { diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index c8f1c324a6c2..daa1067055c8 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -24,9 +24,9 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; }; reserved-memory { @@ -564,7 +564,6 @@ reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; vdd3-supply = <&ldo7_reg>; vci-supply = <&ldo17_reg>; - spi-cs-high; spi-max-frequency = <1200000>; pinctrl-names = "default"; @@ -636,7 +635,7 @@ }; &i2s0 { - dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>; + dmas = <&pdma0 10>, <&pdma0 9>, <&pdma0 11>; status = "okay"; }; @@ -895,7 +894,7 @@ device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gph2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; + interrupt-names = "host-wakeup"; }; }; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index c6f39147cb96..d32f42dd1bf5 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -30,9 +30,9 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; }; pmic_ap_clk: clock-0 { diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 353ba7b09a0c..ac281f42e8f5 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -117,7 +117,7 @@ }; }; - pdma0: dma@e0900000 { + pdma0: dma-controller@e0900000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xe0900000 0x1000>; interrupt-parent = <&vic0>; @@ -129,7 +129,7 @@ #dma-requests = <32>; }; - pdma1: dma@e0a00000 { + pdma1: dma-controller@e0a00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xe0a00000 0x1000>; interrupt-parent = <&vic0>; @@ -239,8 +239,8 @@ reg = <0xeee30000 0x1000>; interrupt-parent = <&vic2>; interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; + dma-names = "tx", "rx", "tx-sec"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 11>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; @@ -259,8 +259,8 @@ reg = <0xe2100000 0x1000>; interrupt-parent = <&vic2>; interrupts = <17>; - dma-names = "rx", "tx"; - dmas = <&pdma1 12>, <&pdma1 13>; + dma-names = "tx", "rx"; + dmas = <&pdma1 13>, <&pdma1 12>; clock-names = "iis", "i2s_opclk0"; clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; pinctrl-names = "default"; @@ -274,8 +274,8 @@ reg = <0xe2a00000 0x1000>; interrupt-parent = <&vic2>; interrupts = <18>; - dma-names = "rx", "tx"; - dmas = <&pdma1 14>, <&pdma1 15>; + dma-names = "tx", "rx"; + dmas = <&pdma1 15>, <&pdma1 14>; clock-names = "iis", "i2s_opclk0"; clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; pinctrl-names = "default"; @@ -427,38 +427,28 @@ status = "disabled"; }; - ehci: ehci@ec200000 { + ehci: usb@ec200000 { compatible = "samsung,exynos4210-ehci"; reg = <0xec200000 0x100>; interrupts = <23>; interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; - ohci: ohci@ec300000 { + ohci: usb@ec300000 { compatible = "samsung,exynos4210-ohci"; reg = <0xec300000 0x100>; interrupts = <23>; interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; mfc: codec@f1700000 { @@ -528,7 +518,7 @@ clock-names = "sclk_fimg2d", "fimg2d"; }; - mdma1: mdma@fa200000 { + mdma1: dma-controller@fa200000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xfa200000 0x1000>; interrupt-parent = <&vic0>; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index dc0bcc7020f1..c28b32640254 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -772,7 +772,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -790,7 +790,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ <&dma 0 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -807,7 +807,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ <&dma 35 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -824,7 +824,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ <&dma 33 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -841,7 +841,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts new file mode 100644 index 000000000000..d6940e0afa86 --- /dev/null +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -0,0 +1,785 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO, + * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively + * for T-Mobile in the United States. + * + * This phone is closely related to the Codina, but has: + * - No CPU speed cap, full ~1GHz rate + * - Different power management IC, AB8505 + * - As AB8505 has a micro USB phy, no TI TSU6111 + * - Different power routing such as the removal of the external LDO for the + * touchscreen in favor of using the AB8505 + * - Using a regulator for the key backlight LED + * - Using the Samsung S6D27A1 panel by default + * - The panel is using one of the ordinary AB8505 regulators for 1.8V + * - WiFi/Bluetooth combi chip upgraded to BCM4334 + * - GPIO for backlight control moved from 68 to 69 + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Samsung Galaxy Exhibit (SGH-T599)"; + compatible = "samsung,codina-tmo", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both the 3.0V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 "MOT_EN" */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = <KEY_HOME>; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = <KEY_VOLUMEUP>; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = <KEY_VOLUMEDOWN>; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + led-touchkeys { + compatible = "regulator-led"; + vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V + default-state = "on"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO69 is used on Codina R0.4 and Codina TMO */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd253_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: this should also be used by the SM5103 Camera power management unit */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + clock-frequency = <400000>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + }; + }; + + spi-gpio-0 { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO201 */ + cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6d27a1"; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&ab8500_ldo_aux6_reg>; + + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd253>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + /* + * GPIO130 will be set to input no pull-up resulting in a resistor + * pulling the reset high and taking the memory out of reset. + */ + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + uart@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + /* FIXME: add a device for the GPS here */ + }; + + /* Debugging console UART connected to AB8505 */ + uart@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + /* This is mostly identical to the Codina v0.4 regulators */ + regulator { + ab8500_ldo_aux1 { + regulator-name = "v-sensors-vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + regulator-name = "v-aux2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + regulator-name = "v-mmc-sd"; + }; + + ab8500_ldo_aux4 { + regulator-name = "v-aux4"; + /* + * Providing some span here makes the touchkey + * LEDs actually dimmable. + */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "v-aux5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + /* 1.8 V to the display */ + regulator-name = "v-aux6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + regulator-name = "v-sensors-vio"; + }; + }; + }; + }; + + /* I2C0 also known as "AGC I2C" */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@39 { + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; + clock-frequency = <400000>; + reg = <0x39>; + + /* IRQ on GPIO146 "PS_INT" */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tmd2672_codina_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + /* Bosch BMA254 accelerometer */ + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* TODO: write bindings and driver for this touchscreen */ + + /* Zinitix BT404 ISP part */ + isp@50 { + compatible = "zinitix,bt404-isp"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + + /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ + touchscreen@20 { + compatible = "zinitix,bt404"; + reg = <0x20>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V + vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V + zinitix,mode = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + sdi2 { + /* + * GPIO130 should be set in GPIO mode and + * pulled down. (Not connected.) + */ + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + codina_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + codina_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIOs for panel control */ + panel { + panel_default_mode: panel_default { + codina_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + codina_cfg2 { + /* ESD IRQ line "LCD detect" */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + codina_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + codina_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Backlight GPIO */ + backlight { + ktd253_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + codina_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Zinitix BT404 touchscreen */ + tsp { + tsp_default: tsp_default { + codina_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for light/proximity sensor TMD2672 */ + tmd2672 { + tmd2672_codina_default: tmd2672_codina { + codina_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for subpmu */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + codina_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + codina_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + codina_cfg2 { + pins = "GPIO225_AG8"; + /* Needs pull down, no pull down resistor on board */ + ste,config = <&gpio_in_pd>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + codina_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + codina_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + codina_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 1c1725d31c7c..b6746ac167bc 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -9,9 +9,13 @@ * the boot loader. * * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). - * The GT-I8160 plain is knonw as the "europe" variant. - * The GT-I8160P appears to not use the ST Microelectronics accelerometer. + * The GT-I8160 plain is known as the "europe" variant. + * The GT-I8160P is the CDMA version and it appears to not use the ST + * Microelectronics accelerometer and reportedly has NFC mounted. * The GT-I8160chn appears to be the same as the europe variant. + * + * There is also the Codina-TMO, Samsung SGH-T599, which has its own device + * tree. */ /dts-v1/; @@ -303,7 +307,22 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO: add the NFC chip here */ + nfc@2b { + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; + /* NFC IRQ on GPIO32 */ + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + /* GPIO 31 */ + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + /* GPIO88 */ + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pn544_codina_default>; + }; }; spi-gpio-0 { @@ -461,10 +480,20 @@ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; - /* CTS/RTS is not used, CTS is repurposed as GPIO */ - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + compatible = "brcm,bcm4751"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + enable-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&bcm4751_codina_default>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -483,6 +512,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ @@ -515,10 +548,9 @@ pinctrl-0 = <&i2c0_a_1_default>; pinctrl-1 = <&i2c0_a_1_sleep>; - /* TODO: write bindings and driver for this proximity sensor */ proximity@39 { - /* Codina has the Mouser TMD2672 */ - compatible = "mouser,tmd2672"; + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; clock-frequency = <400000>; reg = <0x39>; @@ -847,6 +879,34 @@ }; }; }; + nfc { + pn544_codina_default: pn544_codina { + /* Interrupt line */ + codina_cfg1 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_nopull>; + }; + /* Enable and firmware GPIOs */ + codina_cfg2 { + pins = "GPIO31_V3", "GPIO88_C4"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + bcm4751 { + bcm4751_codina_default: bcm4751_codina { + /* Reset line, start out asserted */ + codina_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + codina_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; vibrator { vibrator_default: vibrator_default { codina_cfg1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index fd170974765f..53062d50e455 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -456,6 +456,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <43000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 290ab59e863d..b0dce91aff4b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -304,6 +304,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { regulator-name = "sensor_3v"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 42762bfcd878..e6d4fd0eb5f4 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -485,7 +485,26 @@ /* CTS/RTS is not used, CTS is repurposed as GPIO */ pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + + gnss { + /* + * The Low Noise Amplifier (LNA) power and enablement is controlled + * autonomously by the GSD4t. + * Janice has a SiRFstarIV-based GSD4t + * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R. + */ + compatible = "csr,gsd4t"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO96 */ + sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gsd4t_janice_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -504,6 +523,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <15000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ @@ -941,4 +964,23 @@ }; }; }; + gsd4t { + gsd4t_janice_default: gsd4t_janice { + /* Reset line, start out asserted */ + janice_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + janice_cfg2 { + pins = "GPIO96_D8"; + ste,config = <&gpio_out_lo>; + }; + /* Unused power enablement line, used in R0.0 and R0.1 boards */ + janice_cfg3 { + pins = "GPIO86_C6"; + ste,config = <&gpio_in_pd>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index 2a5bf54137ce..c57676faf181 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -325,6 +325,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index dcb03ce7cbd4..81b341a5ae45 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -281,12 +281,27 @@ }; }; - /* GPF UART */ + /* GPS UART */ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_skomer_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to AB8505 USB */ @@ -305,6 +320,10 @@ pinctrl-1 = <&usb_a_1_sleep>; }; + ab8500_fg { + line-impedance-micro-ohms = <16000>; + }; + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ @@ -649,6 +668,20 @@ }; }; }; + g05ta03 { + g05ta03_skomer_default: g05ta03 { + /* Reset line, start out de-asserted */ + skomer_cfg1 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + skomer_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; &ab8505_gpio { diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 155d9ffacc83..500bcc302d42 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 1cf8a23c2644..8f37aefa7315 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 6e42ca2dada2..91dde07a38ba 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -583,7 +583,7 @@ status = "disabled"; }; - pinctrl: pin-controller@58020000 { + pinctrl: pinctrl@58020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 1708c79b5254..f9ebc47e6421 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -75,6 +75,12 @@ compatible = "fixed-clock"; clock-frequency = <99000000>; }; + + clk_rtc_k: clk-rtc-k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; }; intc: interrupt-controller@a0021000 { @@ -218,6 +224,15 @@ status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>, <&clk_rtc_k>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + bsec: efuse@5c005000 { compatible = "st,stm32mp15-bsec"; reg = <0x5c005000 0x400>; @@ -239,11 +254,13 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; pins-are-numbered; gpioa: gpio@50002000 { diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index ee100d108ea2..09d6226d598f 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -6,6 +6,9 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -23,6 +26,28 @@ reg = <0xc0000000 0x20000000>; }; + gpio-keys { + compatible = "gpio-keys"; + + user-pa13 { + label = "User-PA13"; + linux,code = <BTN_1>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -37,6 +62,10 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f0d66d8c6e3b..6052243ad81c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -379,6 +379,40 @@ }; }; + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -889,6 +923,21 @@ }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -2212,4 +2261,19 @@ bias-disable; }; }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; }; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index f9aa9af31efd..1b2fd3426a81 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -115,6 +115,33 @@ status = "disabled"; }; + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + status = "disabled"; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -122,6 +149,20 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + status = "disabled"; + }; + }; + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -1623,7 +1664,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -1754,7 +1795,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts new file mode 100644 index 000000000000..75874eafde11 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1A"; + compatible = "prt,prtt1a", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; + +&pwm5_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */ + }; +}; + +&pwm5_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */ + }; +}; + +&timers5 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts new file mode 100644 index 000000000000..7ecf31263abc --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1C"; + compatible = "prt,prtt1c", "st,stm32mp151"; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + }; +}; + +ðernet0 { + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", + "", "", "", "", "", "", "", "SPI1_nSS"; +}; + +&gpiod { + gpio-line-names = + "", "", "", "", "", "", "", "", + "WFM_RESET", "", "", "", "", "", "", ""; +}; + +&gpioe { + gpio-line-names = + "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", + "", "", "", "", "WFM_nIRQ", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "PHY3_nINT", + "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", + "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; +}; + +&mdio0 { + /* All this DP83TD510E PHYs can't be probed before switch@0 is + * probed so we need to use compatible with PHYid + */ + /* TI DP83TD510E */ + t1l0_phy: ethernet-phy@6 { + compatible = "ethernet-phy-id2000.0181"; + reg = <6>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.0181"; + reg = <7>; + interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l2_phy: ethernet-phy@10 { + compatible = "ethernet-phy-id2000.0181"; + reg = <10>; + interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* Micrel KSZ9031 */ + rj45_phy: ethernet-phy@2 { + reg = <2>; + interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc2_b4_od_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + }; +}; + +&sdmmc2_b4_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_b4_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_d47_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2_d47_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + non-removable; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmc@1 { + compatible = "prt,prtt1c-wfm200", "silabs,wf200"; + reg = <1>; + }; +}; + +&sdmmc3_b4_od_pins_b { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + }; +}; + +&sdmmc3_b4_pins_b { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + }; +}; + +&sdmmc3_b4_sleep_pins_b { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins_b>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "t1l0"; + phy-mode = "rmii"; + phy-handle = <&t1l0_phy>; + }; + + port@1 { + reg = <1>; + label = "t1l1"; + phy-mode = "rmii"; + phy-handle = <&t1l1_phy>; + }; + + port@2 { + reg = <2>; + label = "t1l2"; + phy-mode = "rmii"; + phy-handle = <&t1l2_phy>; + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rj45_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <ðernet0>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi new file mode 100644 index 000000000000..d865ab5d866b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxad-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + ethernet0 = ðernet0; + mdio-gpio0 = &mdio0; + serial0 = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + status = "okay"; +}; + +ðernet0_rmii_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */ + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK input */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + }; +}; + +ðernet0_rmii_sleep_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; +}; + +&iwdg2 { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&qspi_bk1_pins_a { + pins1 { + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_od_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc1_b4_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart4_idle_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <®_3v3>; +}; + +&usbphyc_port1 { + phy-supply = <®_3v3>; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts new file mode 100644 index 000000000000..ad25929e64e6 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1S"; + compatible = "prt,prtt1s", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + humidity-sensor@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + }; +}; + +&i2c1_pins_a { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */ + }; +}; + +&i2c1_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */ + }; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 000000000000..e3d3f3f30c7d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 000000000000..45dcd299aa9e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts new file mode 100644 index 000000000000..458e0ca3cded --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 000000000000..df9c113edb4b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&optee { + status = "okay"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi { + status = "okay"; +}; + +&scmi_shm { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 83e2c87713f8..238a611192e7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -446,6 +445,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 61e17f44ce81..76c54b006d87 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -141,6 +141,7 @@ compatible = "snps,dwmac-mdio"; reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; reset-delay-us = <1000>; + reset-post-delay-us = <1000>; phy0: ethernet-phy@7 { reg = <7>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 884bda106399..aa2bba75265f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -346,8 +346,6 @@ <0 88 4>, <0 89 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 0eec18678311..8773211df50e 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,17 +1,18 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb @@ -19,29 +20,29 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb @@ -52,15 +53,14 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 561eec21b4de..8b0d586aa84e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -18,7 +18,7 @@ model = "JetHome JetHub J100"; aliases { serial0 = &uart_AO; /* Console */ - serial1 = &uart_AO_B; /* External UART (Wireless Module) */ + serial2 = &uart_AO_B; /* External UART (Wireless Module) */ ethernet0 = ðmac; }; @@ -81,6 +81,15 @@ vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vccq_1v8: regulator-vccq_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCCQ_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&vddao_3v3>; @@ -248,8 +257,7 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; + max-frequency = <50000000>; non-removable; disable-wp; @@ -282,7 +290,7 @@ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; + vqmmc-supply = <&vccq_1v8>; }; /* UART Bluetooth */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 2d7032f41e4b..bcdf55f48a83 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -416,7 +416,7 @@ pinctrl-names = "default"; status = "okay"; - gd25lq128: spi-flash@0 { + gd25lq128: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index 2d769203f671..213a0705ebdc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -298,7 +298,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 6eafb908695f..fcb304c5a40f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -213,6 +213,12 @@ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; }; &uart_C { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 93d8f8aff70d..874f91c348ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -284,7 +284,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - nor_4u1: spi-flash@0 { + nor_4u1: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 86bdc0baf032..f43c45daf7eb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -374,7 +374,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 3cf4ecb6d52e..c9705941e4ab 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -458,7 +458,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q128: spi-flash@0 { + w25q128: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q128fw", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index bf9ae1e1016b..2e45a8ecd9a0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> / { cpus { @@ -60,6 +61,12 @@ #clock-cells = <0>; }; + pwrc: power-controller { + compatible = "amlogic,meson-s4-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -85,6 +92,32 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,meson-s4-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4000 { + reg = <0x0 0x4000 0x0 0x004c>, + <0x0 0x40c0 0x0 0x0220>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 82>; + }; + }; + + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,meson-s4-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index f3f953225bf5..e3486f60645a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -121,7 +121,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 4382b73baef5..d908e96d7ddc 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts new file mode 100644 index 000000000000..26b0f1b3cea6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + }; + + vmmc_v3_3d: fixed_v3_3d { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts new file mode 100644 index 000000000000..e3146747c2d9 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb_host: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <16>; + dr_mode = "host"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi new file mode 100644 index 000000000000..4e46826f883a --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + timer@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <50000000>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1a230000 0x1000>; + }; + }; + + uart0: serial@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + mhu_hse1: mailbox@1b820000 { + compatible = "arm,mhuv2-tx", "arm,primecell"; + reg = <0x1b820000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + + mhu_seh1: mailbox@1b830000 { + compatible = "arm,mhuv2-rx", "arm,primecell"; + reg = <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index fbf13f7c2baf..83e3e7e3984f 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -220,7 +220,7 @@ clock-names = "uartclk", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 269b649934b5..a496e39e6204 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -241,6 +241,7 @@ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 446c8f476eec..065381c1cbf5 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -117,7 +117,7 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { /* etf0 */ + etf_sys0: etf@20010000 { /* etf0 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; @@ -141,7 +141,7 @@ }; }; - tpiu@20030000 { + tpiu_sys: tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; @@ -194,7 +194,7 @@ }; }; - etr@20070000 { + etr_sys: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; iommus = <&smmu_etr 0>; @@ -212,7 +212,7 @@ }; }; - stm@20100000 { + stm_sys: stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x1000000>; @@ -289,6 +289,18 @@ }; }; + cti0: cti@22020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; @@ -349,6 +361,18 @@ }; }; + cti1: cti@22120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm1>; + }; + cpu_debug2: cpu-debug@23010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23010000 0x0 0x1000>; @@ -374,6 +398,18 @@ }; }; + cti2: cti@23020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm2>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; @@ -446,6 +482,18 @@ }; }; + cti3: cti@23120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm3>; + }; + cpu_debug4: cpu-debug@23210000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23210000 0x0 0x1000>; @@ -471,6 +519,18 @@ }; }; + cti4: cti@23220000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23220000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm4>; + }; + cpu_debug5: cpu-debug@23310000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23310000 0x0 0x1000>; @@ -496,6 +556,100 @@ }; }; + cti5: cti@23320000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23320000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm5>; + }; + + cti_sys0: cti@20020000 { /* sys_cti_0 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<2 3>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etr_sys>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<7 6>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<4 5 6 7>; + arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW + STM_TOUT_HETE STM_ASYNCOUT>; + arm,trig-out-sigs=<4 5>; + arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>; + arm,cs-dev-assoc = <&stm_sys>; + }; + + trig-conns@3 { + reg = <3>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&tpiu_sys>; + }; + }; + + cti_sys1: cti@20110000 { /* sys_cti_1 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=<GEN_INTREQ>; + arm,trig-out-sigs=<0>; + arm,trig-out-types=<GEN_HALTREQ>; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-out-sigs=<1 6>; + arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-conn-name = "g_counter"; + }; + }; + gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; @@ -675,8 +829,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index eda3d9e18af6..2e43f4531308 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20140000 0 0x1000>; @@ -82,4 +82,39 @@ }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20160000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys1>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<2 3 4>; + arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_0"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<5 6 7>; + arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_1"; + }; + }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts index 190a0fba4ad6..dd9ea69f086f 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -7,14 +7,18 @@ }; etf@20140000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; funnel@20150000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A57_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 0e24e29eb9b1..f099fb611d4e 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -313,3 +314,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts index dbf13770084f..de2cbac1d1c3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -7,14 +7,18 @@ }; etf@20140000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; funnel@20150000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A72_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index e609420ce3e4..709389582ae3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -319,3 +320,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A72_0>; +}; + +&cti1 { + cpu = <&A72_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index d72dcff9bf06..4135d62e44a2 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -154,6 +154,31 @@ power-domains = <&scmi_devpd 8>; }; +&cti0 { + power-domains = <&scmi_devpd 8>; +}; +&cti1 { + power-domains = <&scmi_devpd 8>; +}; +&cti2 { + power-domains = <&scmi_devpd 8>; +}; +&cti3 { + power-domains = <&scmi_devpd 8>; +}; +&cti4 { + power-domains = <&scmi_devpd 8>; +}; +&cti5 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys0 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys1 { + power-domains = <&scmi_devpd 8>; +}; + &gpu { clocks = <&scmi_dvfs 2>; power-domains = <&scmi_devpd 9>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index f00cffbd032c..dbc22e70b62c 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -9,6 +9,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/arm/coresight-cti-dt.h> #include "juno-base.dtsi" / { @@ -295,3 +296,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 33182d9e5826..ec2d5280a30b 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -10,17 +10,24 @@ arm,v2m-memory-map = "rs2"; iofpga-bus@300000000 { - virtio-p9@140000 { + virtio@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; interrupts = <43>; }; - virtio-net@150000 { + virtio@150000 { compatible = "virtio,mmio"; reg = <0x150000 0x200>; interrupts = <44>; }; + + virtio@200000 { + compatible = "virtio,mmio"; + reg = <0x200000 0x200>; + interrupts = <46>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 5f6cab668aa0..ba8beef3fe99 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -110,7 +110,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 3 0 0x200000>; + ranges = <0 3 0 0x210000>; v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; @@ -222,7 +222,7 @@ clock-names = "timclken1", "timclken2", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index 12a4b1c03390..e34172e3117e 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -203,7 +203,7 @@ &qspi { bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index f00c21e0767e..7bf26f3e36bf 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -146,7 +146,7 @@ }; &qspi { - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index f59fa3979a04..fda97c47f4e9 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -289,8 +289,6 @@ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&iprocslow>; clock-names = "apb_pclk"; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts index 77efa28c4dd5..dfac910a45d6 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -61,7 +61,7 @@ cs-gpios = <&gpio_hsls 34 0>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; @@ -76,7 +76,7 @@ cs-gpios = <&gpio_hsls 96 0>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 7f1b8efd0883..09d4aa8ae1d6 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -556,8 +556,6 @@ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&hsls_div2_clk>; clock-names = "apb_pclk"; iommus = <&smmu 0x6000 0x0000>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 661567d2dd7a..017ccc2f4650 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -806,7 +806,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 7b5a61d22cc5..f52a55f644f7 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -20,6 +20,11 @@ model = "WinLink E850-96 board"; compatible = "winlink,e850-96", "samsung,exynos850"; + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + chosen { stdout-path = &serial_0; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d1700e96fee2..9076afd4bb3e 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -29,22 +29,6 @@ pinctrl3 = &pinctrl_hsi; pinctrl4 = &pinctrl_core; pinctrl5 = &pinctrl_peri; - mmc0 = &mmc_0; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &hsi2c_0; - i2c8 = &hsi2c_1; - i2c9 = &hsi2c_2; - i2c10 = &hsi2c_3; - i2c11 = &hsi2c_4; }; arm-pmu { @@ -181,7 +165,8 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; reg = <0x10040000 0x800>; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8bd6d7e8a474..6b3057a09251 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1045,8 +1045,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0 - 0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 636c8817df7e..3125c3869c69 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -671,8 +671,8 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0 - 0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index c78371703e76..caccb0334ada 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -350,8 +350,6 @@ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; reset-names = "dma", "dma-ocp"; clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 3e5789f37206..bd4e61d5448e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -164,7 +164,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <108000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 1cee26479bfe..d665f742a7d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -211,7 +211,7 @@ assigned-clock-parents = <&tbg 1>; assigned-clock-rates = <20000000>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index 95d46e8d081c..a4de8d00cf46 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index cd326fe224ce..5e5baf6beea4 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -83,7 +83,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -186,7 +186,7 @@ &cp0_spi1 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index f3b0d57a24a3..39a8e5e99d79 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -155,7 +155,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cp0_spi1_pins>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 8729c6467303..871f84b4a6ed 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -589,7 +589,7 @@ pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index f2e8e0df8865..92897bd7e6cf 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -72,7 +72,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -238,7 +238,7 @@ &cp1_spi1 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index adbfecc678b5..779cf167c33e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -360,7 +360,7 @@ pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index dac85fa748de..74bed79e4f5e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -185,7 +185,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index d9f9f2c19740..1acd746284dc 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -175,7 +175,7 @@ <0x2000000 0x1000000>; /* CS0 */ status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index c00b69b88bd2..7e20987253a3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -310,7 +310,7 @@ pinctrl-0 = <&cp0_spi0_pins>; reg = <0x700680 0x50>; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index f995b1bcda01..b7fc241a228c 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -137,7 +137,7 @@ pinctrl-0 = <&cp1_spi0_pins>; reg = <0x700680 0x50>; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi index 03f107e427d7..ce0747fd6444 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi @@ -19,7 +19,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <14>; /* CS14 */ - spi-flash@6 { + flash@6 { compatible = "spi-nand"; pinctrl-0 = <&cs14_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 9baa085d7861..dbf8c1d48a02 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ @@ -59,7 +59,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CS1 */ - spi-flash@9 { + flash@9 { compatible = "spi-nand"; pinctrl-0 = <&cs1_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 33faf1f3264f..699256f1b9d8 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -274,7 +274,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0>; @@ -289,7 +289,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index ef96e6d8c6b3..d10a9172b529 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -89,7 +89,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0>; @@ -104,7 +104,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d000f6b131dc..fa9811251fd7 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb + dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index eb0327c0df48..2a784ee6da49 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -541,6 +541,12 @@ function = "pwm1"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; @@ -630,6 +636,58 @@ }; }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 67231c8576c5..ae688707f8c6 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -600,6 +600,12 @@ function = "pwm5"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -711,6 +717,58 @@ }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 12846125a4c9..faf5bbbb3710 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -283,6 +283,7 @@ compatible = "renesas,r8a774a1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index a4b406a346f9..be998bc40412 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -156,6 +156,7 @@ compatible = "renesas,r8a774b1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index e123c8d1bab9..4f69f90d88cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -145,6 +145,7 @@ compatible = "renesas,r8a774c0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 4e87e8776a2b..884210544ba0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -369,6 +369,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -2731,6 +2732,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7795-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a7795", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 6f79da8cc8c0..0d96b5bb9584 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -334,6 +334,7 @@ compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -2531,6 +2532,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7796-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 68cbbb322acf..58e161e5dae0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -323,6 +323,7 @@ compatible = "renesas,r8a77961-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1222,6 +1223,31 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77961-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77961_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; @@ -2375,6 +2401,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77961-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 9f858af8b762..ecca9582edf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -205,6 +205,7 @@ compatible = "renesas,r8a77965-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -2378,6 +2379,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77965-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a77965", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 517892cf6294..79718234d85f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -108,6 +108,7 @@ compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 347c068ff2c5..148983130adf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -138,6 +138,7 @@ compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 7e0f1aab2135..5d41e46d06f5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -171,6 +171,7 @@ compatible = "renesas,r8a77990-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1837,6 +1838,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77990-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cac1f9467ffa..0eccf81db374 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -94,6 +94,7 @@ compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1237,6 +1238,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77995-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 6af3f4f4f268..53c4a26198e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -192,14 +192,17 @@ clock-frequency = <400000>; bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + compatible = "ti,sn65dsi86"; reg = <0x2c>; clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; vccio-supply = <®_1p8v>; vpll-supply = <®_1p8v>; @@ -271,6 +274,11 @@ function = "i2c6"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_6_18", "GP_6_19", "GP_6_20"; bias-pull-up; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index e46dc9aa0a43..b2e67b82caf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -37,6 +37,20 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &i2c0 { eeprom@51 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -65,4 +79,14 @@ }; }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index c4be288b1912..57d49d27cdca 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -24,6 +24,13 @@ i2c6 = &i2c6; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -81,6 +88,7 @@ compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 907>; @@ -596,6 +604,55 @@ status = "disabled"; }; + canfd: can@e6660000 { + compatible = "renesas,r8a779a0-canfd"; + reg = <0 0xe6660000 0 0x8000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779A0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen3"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 6e07c54148e7..41aa8591b3b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -31,10 +31,30 @@ clock-frequency = <32768>; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + scif3_pins: scif3 { groups = "scif3_data", "scif3_ctrl"; function = "scif3"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi new file mode 100644 index 000000000000..15e8d1ebf575 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Spider Ethernet sub-board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +&i2c4 { + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board"; + reg = <0x52>; + pagesize = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index f286254b41d8..2e3b719cc749 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a779f0-spider-cpu.dtsi" +#include "r8a779f0-spider-ethernet.dtsi" / { model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; @@ -20,3 +21,12 @@ stdout-path = "serial0:115200n8"; }; }; + +&i2c4 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index f4e549867371..df46fb87cffc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -63,6 +63,7 @@ compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 907>; @@ -75,6 +76,66 @@ <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; }; + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6051180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051180 0 0x54>; + interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6051980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051980 0 0x54>; + interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 19>; + interrupt-controller; + #interrupt-cells = <2>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; @@ -96,6 +157,108 @@ #power-domain-cells = <1>; }; + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac0 0x91>, <&dmac0 0x90>, + <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac0 0x93>, <&dmac0 0x92>, + <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac0 0x95>, <&dmac0 0x94>, + <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>, + <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>, + <&dmac1 0x99>, <&dmac1 0x98>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, + <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..c8aadbe55278 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a07g043-cpg.h> + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio-clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssi0: ssi@10049c00 { + reg = <0 0x10049c00 0 0x400>; + #sound-dai-cells = <0>; + /* place holder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + /* place holder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + /* place holder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + /* place holder */ + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058c00 0 0x400>; + /* place holder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + /* place holder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g043-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_DMAC_ARESETN>, + <&cpg R9A07G043_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + /* place holder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + /* place holder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + /* place holder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + /* place holder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + /* place holder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + /* place holder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + /* place holder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + /* place holder */ + }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + /* place holder */ + }; + + wdt2: watchdog@12800400 { + reg = <0 0x12800400 0 0x400>; + /* place holder */ + }; + + ostm0: timer@12801000 { + reg = <0x0 0x12801000 0x0 0x400>; + /* place holder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + /* place holder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + /* place holder */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts new file mode 100644 index 000000000000..08a0404c6f0b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g043.dtsi" +#include "rzg2ul-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043u11"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; +}; + +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&hsusb { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +&ohci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 5a5cea82a5d9..fc34058002e2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -13,79 +13,3 @@ model = "Renesas SMARC EVK based on r9a07g044c2"; compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; - -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c3 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - -&spi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 5d39e765c291..f35aa0311e9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +92,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -74,6 +102,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -83,6 +112,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -96,16 +169,135 @@ ranges; ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; + resets = <&cpg R9A07G054_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; + interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; + resets = <&cpg R9A07G054_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; + resets = <&cpg R9A07G054_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; scif0: serial@1004b800 { @@ -234,43 +426,194 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G054_CANFD_RSTP_N>, + <&cpg R9A07G054_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { + compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G054_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G054_ADC_PRESETN>, + <&cpg R9A07G054_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + + tsu: thermal@10059400 { + compatible = "renesas,r9a07g054-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; + resets = <&cpg R9A07G054_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; }; sbc: spi@10060000 { + compatible = "renesas,r9a07g054-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, + <&cpg CPG_MOD R9A07G054_SPI_CLK>; + resets = <&cpg R9A07G054_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; cpg: clock-controller@11010000 { @@ -346,8 +689,24 @@ }; gpu: gpu@11840000 { + compatible = "renesas,r9a07g054-mali", + "arm,mali-bifrost"; reg = <0x0 0x11840000 0x0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPU_RESETN>, + <&cpg R9A07G054_GPU_AXI_RESETN>, + <&cpg R9A07G054_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; }; gic: interrupt-controller@11900000 { @@ -361,13 +720,35 @@ }; sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; eth0: ethernet@11c20000 { @@ -411,73 +792,226 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g054-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; + resets = <&cpg R9A07G054_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g054", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800C00 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; + resets = <&cpg R9A07G054_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; + resets = <&cpg R9A07G054_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; + resets = <&cpg R9A07G054_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index fc334b4c2aa4..4e07e1a0fb66 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -16,11 +16,3 @@ model = "Renesas SMARC EVK based on r9a07g054l2"; compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; }; - -&pinctrl { - /delete-node/ can0-stb-hog; - /delete-node/ can1-stb-hog; - /delete-node/ gpio-sd0-pwr-en-hog; - /delete-node/ sd0-dev-sel-hog; - /delete-node/ sd1-pwr-en-hog; -}; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 588117aafaca..0e61b85efb43 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -26,7 +26,6 @@ serial0 = &scif0; i2c0 = &i2c0; i2c1 = &i2c1; - i2c3 = &i2c3; }; chosen { @@ -75,7 +74,6 @@ regulator-name = "SDHI1 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; @@ -131,20 +129,6 @@ status = "okay"; }; -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 33ddfd18bd56..aadc41515093 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -14,6 +14,21 @@ / { aliases { serial1 = &scif2; + i2c3 = &i2c3; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; }; }; @@ -33,3 +48,7 @@ status = "okay"; }; #endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 37ff2091582e..a78a8def363e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -12,11 +12,6 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { - pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ - <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ - }; - #if SW_SCIF_CAN /* SW8 should be at position 2->1 */ can1_pins: can1 { @@ -25,13 +20,6 @@ }; #endif - scif1_pins: scif1 { - pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ - <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ - <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ - <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ - }; - #if SW_RSPI_CAN /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ can1-stb-hog { @@ -47,6 +35,33 @@ }; #endif + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */ + <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ + }; + + scif1_pins: scif1 { + pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ + <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ + <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; @@ -90,5 +105,30 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + spi1_pins: spi1 { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ + <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ + <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ + <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ + }; + + ssi0_pins: ssi0 { + pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ + <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ + <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */ + <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */ + }; + + usb0_pins: usb0 { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */ + <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */ + <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */ + <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */ + }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 88a7938017aa..959a0ad1d367 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -41,6 +41,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -84,6 +93,18 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ @@ -110,6 +131,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -175,6 +208,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if (!SW_SD0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_pins>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index df7631fe5fac..74a844ea7537 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -43,6 +43,7 @@ / { aliases { serial1 = &scif1; + i2c2 = &i2c2; }; }; @@ -59,6 +60,20 @@ }; #endif +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated @@ -75,3 +90,15 @@ status = "okay"; }; #endif + +#if (SW_RSPI_CAN) +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..b515748e6a9a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC pincontrol parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ + <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ + }; + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi new file mode 100644 index 000000000000..b0822679a55b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC SOM common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + +#if !(SW_SW0_DEV_SEL) + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; +#endif +}; + +#if (!SW_ET0_EN_N) +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */ + <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */ + <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */ + <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */ + <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */ + <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */ + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; +}; + +#if (SW_SW0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#else +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi new file mode 100644 index 000000000000..056a77369c8d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +#include "rzg2ul-smarc-som.dtsi" +#include "rzg2ul-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 6092dc4531ad..7ad72f377a35 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -866,6 +866,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index b4bdb2d7e4ba..90a4c0629d24 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -426,6 +426,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi deleted file mode 100644 index 4bb5d650df9c..000000000000 --- a/arch/arm64/boot/dts/synaptics/as370.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Synaptics Incorporated - * - * Author: Jisheng Zhang <jszhang@kernel.org> - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "syna,as370"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe80000 0x10000>; - - uart0: serial@c00 { - compatible = "snps,dw-apb-uart"; - reg = <0xc00 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio0: gpio@1800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@2000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x2000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 9a652abcbcac..10c217a57a7d 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -727,7 +727,7 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x0 0x800>; interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 4aab631ef517..d9cf2820c02e 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1661,7 +1661,7 @@ static struct iommu_device *omap_iommu_probe_device(struct device *dev) num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus", sizeof(phandle)); if (num_iommus < 0) - return 0; + return ERR_PTR(-ENODEV); arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL); if (!arch_data) diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h new file mode 100644 index 000000000000..27e232733096 --- /dev/null +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G043 CPG Core Clocks */ +#define R9A07G043_CLK_I 0 +#define R9A07G043_CLK_I2 1 +#define R9A07G043_CLK_S0 2 +#define R9A07G043_CLK_SPI0 3 +#define R9A07G043_CLK_SPI1 4 +#define R9A07G043_CLK_SD0 5 +#define R9A07G043_CLK_SD1 6 +#define R9A07G043_CLK_M0 7 +#define R9A07G043_CLK_M2 8 +#define R9A07G043_CLK_M3 9 +#define R9A07G043_CLK_HP 10 +#define R9A07G043_CLK_TSU 11 +#define R9A07G043_CLK_ZT 12 +#define R9A07G043_CLK_P0 13 +#define R9A07G043_CLK_P1 14 +#define R9A07G043_CLK_P2 15 +#define R9A07G043_CLK_AT 16 +#define R9A07G043_OSCCLK 17 +#define R9A07G043_CLK_P0_DIV2 18 + +/* R9A07G043 Module Clocks */ +#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */ +#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */ +#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */ +#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */ +#define R9A07G043_SYC_CNT_CLK 11 +#define R9A07G043_DMAC_ACLK 12 +#define R9A07G043_DMAC_PCLK 13 +#define R9A07G043_OSTM0_PCLK 14 +#define R9A07G043_OSTM1_PCLK 15 +#define R9A07G043_OSTM2_PCLK 16 +#define R9A07G043_MTU_X_MCK_MTU3 17 +#define R9A07G043_POE3_CLKM_POE 18 +#define R9A07G043_WDT0_PCLK 19 +#define R9A07G043_WDT0_CLK 20 +#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */ +#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */ +#define R9A07G043_SPI_CLK2 23 +#define R9A07G043_SPI_CLK 24 +#define R9A07G043_SDHI0_IMCLK 25 +#define R9A07G043_SDHI0_IMCLK2 26 +#define R9A07G043_SDHI0_CLK_HS 27 +#define R9A07G043_SDHI0_ACLK 28 +#define R9A07G043_SDHI1_IMCLK 29 +#define R9A07G043_SDHI1_IMCLK2 30 +#define R9A07G043_SDHI1_CLK_HS 31 +#define R9A07G043_SDHI1_ACLK 32 +#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */ +#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */ +#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_PCLK2 42 +#define R9A07G043_SSI0_PCLK_SFR 43 +#define R9A07G043_SSI1_PCLK2 44 +#define R9A07G043_SSI1_PCLK_SFR 45 +#define R9A07G043_SSI2_PCLK2 46 +#define R9A07G043_SSI2_PCLK_SFR 47 +#define R9A07G043_SSI3_PCLK2 48 +#define R9A07G043_SSI3_PCLK_SFR 49 +#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HCLK 51 +#define R9A07G043_USB_U2H1_HCLK 52 +#define R9A07G043_USB_U2P_EXR_CPUCLK 53 +#define R9A07G043_USB_PCLK 54 +#define R9A07G043_ETH0_CLK_AXI 55 +#define R9A07G043_ETH0_CLK_CHI 56 +#define R9A07G043_ETH1_CLK_AXI 57 +#define R9A07G043_ETH1_CLK_CHI 58 +#define R9A07G043_I2C0_PCLK 59 +#define R9A07G043_I2C1_PCLK 60 +#define R9A07G043_I2C2_PCLK 61 +#define R9A07G043_I2C3_PCLK 62 +#define R9A07G043_SCIF0_CLK_PCK 63 +#define R9A07G043_SCIF1_CLK_PCK 64 +#define R9A07G043_SCIF2_CLK_PCK 65 +#define R9A07G043_SCIF3_CLK_PCK 66 +#define R9A07G043_SCIF4_CLK_PCK 67 +#define R9A07G043_SCI0_CLKP 68 +#define R9A07G043_SCI1_CLKP 69 +#define R9A07G043_IRDA_CLKP 70 +#define R9A07G043_RSPI0_CLKB 71 +#define R9A07G043_RSPI1_CLKB 72 +#define R9A07G043_RSPI2_CLKB 73 +#define R9A07G043_CANFD_PCLK 74 +#define R9A07G043_GPIO_HCLK 75 +#define R9A07G043_ADC_ADCLK 76 +#define R9A07G043_ADC_PCLK 77 +#define R9A07G043_TSU_PCLK 78 + +/* R9A07G043 Resets */ +#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */ +#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */ +#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */ +#define R9A07G043_DMAC_ARESETN 17 +#define R9A07G043_DMAC_RST_ASYNC 18 +#define R9A07G043_SYC_RESETN 19 +#define R9A07G043_OSTM0_PRESETZ 20 +#define R9A07G043_OSTM1_PRESETZ 21 +#define R9A07G043_OSTM2_PRESETZ 22 +#define R9A07G043_MTU_X_PRESET_MTU3 23 +#define R9A07G043_POE3_RST_M_REG 24 +#define R9A07G043_WDT0_PRESETN 25 +#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */ +#define R9A07G043_SPI_RST 27 +#define R9A07G043_SDHI0_IXRST 28 +#define R9A07G043_SDHI1_IXRST 29 +#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */ +#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_RST_M2_REG 36 +#define R9A07G043_SSI1_RST_M2_REG 37 +#define R9A07G043_SSI2_RST_M2_REG 38 +#define R9A07G043_SSI3_RST_M2_REG 39 +#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HRESETN 41 +#define R9A07G043_USB_U2H1_HRESETN 42 +#define R9A07G043_USB_U2P_EXL_SYSRST 43 +#define R9A07G043_USB_PRESETN 44 +#define R9A07G043_ETH0_RST_HW_N 45 +#define R9A07G043_ETH1_RST_HW_N 46 +#define R9A07G043_I2C0_MRST 47 +#define R9A07G043_I2C1_MRST 48 +#define R9A07G043_I2C2_MRST 49 +#define R9A07G043_I2C3_MRST 50 +#define R9A07G043_SCIF0_RST_SYSTEM_N 51 +#define R9A07G043_SCIF1_RST_SYSTEM_N 52 +#define R9A07G043_SCIF2_RST_SYSTEM_N 53 +#define R9A07G043_SCIF3_RST_SYSTEM_N 54 +#define R9A07G043_SCIF4_RST_SYSTEM_N 55 +#define R9A07G043_SCI0_RST 56 +#define R9A07G043_SCI1_RST 57 +#define R9A07G043_IRDA_RST 58 +#define R9A07G043_RSPI0_RST 59 +#define R9A07G043_RSPI1_RST 60 +#define R9A07G043_RSPI2_RST 61 +#define R9A07G043_CANFD_RSTP_N 62 +#define R9A07G043_CANFD_RSTC_N 63 +#define R9A07G043_GPIO_RSTN 64 +#define R9A07G043_GPIO_PORT_RESETN 65 +#define R9A07G043_GPIO_SPARE_RESETN 66 +#define R9A07G043_ADC_PRESETN 67 +#define R9A07G043_ADC_ADRST_N 68 +#define R9A07G043_TSU_PRESETN 69 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index e02770b98e6c..25e8cfd43459 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -249,30 +249,26 @@ #define STM32MP1_LAST_CLK 232 /* SCMI clock identifiers */ -#define CK_SCMI0_HSE 0 -#define CK_SCMI0_HSI 1 -#define CK_SCMI0_CSI 2 -#define CK_SCMI0_LSE 3 -#define CK_SCMI0_LSI 4 -#define CK_SCMI0_PLL2_Q 5 -#define CK_SCMI0_PLL2_R 6 -#define CK_SCMI0_MPU 7 -#define CK_SCMI0_AXI 8 -#define CK_SCMI0_BSEC 9 -#define CK_SCMI0_CRYP1 10 -#define CK_SCMI0_GPIOZ 11 -#define CK_SCMI0_HASH1 12 -#define CK_SCMI0_I2C4 13 -#define CK_SCMI0_I2C6 14 -#define CK_SCMI0_IWDG1 15 -#define CK_SCMI0_RNG1 16 -#define CK_SCMI0_RTC 17 -#define CK_SCMI0_RTCAPB 18 -#define CK_SCMI0_SPI6 19 -#define CK_SCMI0_USART1 20 - -#define CK_SCMI1_PLL3_Q 0 -#define CK_SCMI1_PLL3_R 1 -#define CK_SCMI1_MCU 2 +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_PLL2_Q 5 +#define CK_SCMI_PLL2_R 6 +#define CK_SCMI_MPU 7 +#define CK_SCMI_AXI 8 +#define CK_SCMI_BSEC 9 +#define CK_SCMI_CRYP1 10 +#define CK_SCMI_GPIOZ 11 +#define CK_SCMI_HASH1 12 +#define CK_SCMI_I2C4 13 +#define CK_SCMI_I2C6 14 +#define CK_SCMI_IWDG1 15 +#define CK_SCMI_RNG1 16 +#define CK_SCMI_RTC 17 +#define CK_SCMI_RTCAPB 18 +#define CK_SCMI_SPI6 19 +#define CK_SCMI_USART1 20 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f3a0ed317835..4ffa7c3612e6 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -107,17 +107,17 @@ #define GPIOK_R 19786 /* SCMI reset domain identifiers */ -#define RST_SCMI0_SPI6 0 -#define RST_SCMI0_I2C4 1 -#define RST_SCMI0_I2C6 2 -#define RST_SCMI0_USART1 3 -#define RST_SCMI0_STGEN 4 -#define RST_SCMI0_GPIOZ 5 -#define RST_SCMI0_CRYP1 6 -#define RST_SCMI0_HASH1 7 -#define RST_SCMI0_RNG1 8 -#define RST_SCMI0_MDMA 9 -#define RST_SCMI0_MCU 10 -#define RST_SCMI0_MCU_HOLD_BOOT 11 +#define RST_SCMI_SPI6 0 +#define RST_SCMI_I2C4 1 +#define RST_SCMI_I2C6 2 +#define RST_SCMI_USART1 3 +#define RST_SCMI_STGEN 4 +#define RST_SCMI_GPIOZ 5 +#define RST_SCMI_CRYP1 6 +#define RST_SCMI_HASH1 7 +#define RST_SCMI_RNG1 8 +#define RST_SCMI_MDMA 9 +#define RST_SCMI_MCU 10 +#define RST_SCMI_MCU_HOLD_BOOT 11 #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ |