diff options
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8976.dtsi | 12 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm4450.dtsi | 11 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8550.dtsi | 19 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 |
6 files changed, 60 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index 668e05185c21..fa36b62156bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -8,8 +8,8 @@ #include "msm8976.dtsi" -&pmu { - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; +&pmu_a72 { + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>; }; &tsens { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 1b158608c49d..861c24cc2556 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -222,11 +222,17 @@ reg = <0x0 0x80000000 0x0 0x0>; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + pmu_a72: pmu-a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 8d75c4f9731c..9c9919e78fbd 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -292,9 +292,14 @@ reg = <0x0 0xa0000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 708107da0ab0..e01b4d4c07f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -301,8 +301,18 @@ reg = <0x0 0x80000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x1 { + compatible = "arm,cortex-x1-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 79311a6bd1ad..9564963fbabf 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -352,8 +352,23 @@ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a510 { + compatible = "arm,cortex-a510-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a710 { + compatible = "arm,cortex-a710-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a715 { + compatible = "arm,cortex-a715-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x3 { + compatible = "arm,cortex-x3-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1774be6c53e5..336c54242778 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -390,8 +390,18 @@ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x4 { + compatible = "arm,cortex-x4-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; |