diff options
Diffstat (limited to 'Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc | 36 |
1 files changed, 26 insertions, 10 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc index ab49b9ac3bcb..96aafa66b4a5 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc @@ -11,21 +11,21 @@ What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Defines the size, in 32-bit words, of the local RAM buffer. +Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer. The value is read directly from HW register RSZ, 0x004. What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC status register. The value +Description: (Read) Shows the value held by the TMC status register. The value is read directly from HW register STS, 0x00C. What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC RAM Read Pointer register +Description: (Read) Shows the value held by the TMC RAM Read Pointer register that is used to read entries from the Trace RAM over the APB interface. The value is read directly from HW register RRP, 0x014. @@ -34,7 +34,7 @@ What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC RAM Write Pointer register +Description: (Read) Shows the value held by the TMC RAM Write Pointer register that is used to sets the write pointer to write entries from the CoreSight bus into the Trace RAM. The value is read directly from HW register RWP, 0x018. @@ -43,21 +43,21 @@ What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Similar to "trigger_cntr" above except that this value is +Description: (Read) Similar to "trigger_cntr" above except that this value is read directly from HW register TRG, 0x01C. What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC Control register. The value +Description: (Read) Shows the value held by the TMC Control register. The value is read directly from HW register CTL, 0x020. What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC Formatter and Flush Status +Description: (Read) Shows the value held by the TMC Formatter and Flush Status register. The value is read directly from HW register FFSR, 0x300. @@ -65,7 +65,7 @@ What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC Formatter and Flush Control +Description: (Read) Shows the value held by the TMC Formatter and Flush Control register. The value is read directly from HW register FFCR, 0x304. @@ -73,7 +73,7 @@ What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Shows the value held by the TMC Mode register, which +Description: (Read) Shows the value held by the TMC Mode register, which indicate the mode the device has been configured to enact. The The value is read directly from the MODE register, 0x028. @@ -81,7 +81,7 @@ What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid Date: March 2016 KernelVersion: 4.7 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> -Description: (R) Indicates the capabilities of the Coresight TMC. +Description: (Read) Indicates the capabilities of the Coresight TMC. The value is read directly from the DEVID register, 0xFC8, What: /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size @@ -91,3 +91,19 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS mode. Writable only for TMC-ETR configurations. The value should be aligned to the kernel pagesize. + +What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available +Date: August 2023 +KernelVersion: 6.7 +Contact: Anshuman Khandual <anshuman.khandual@arm.com> +Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available + for the users to configure explicitly. This file is avaialble only + for TMC ETR devices. + +What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred +Date: August 2023 +KernelVersion: 6.7 +Contact: Anshuman Khandual <anshuman.khandual@arm.com> +Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could + only provide a mode which is supported for a given ETR device. This + file is available only for TMC ETR devices. |