diff options
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/booting.rst | 2 | ||||
| -rw-r--r-- | Documentation/arm64/elf_hwcaps.rst | 2 | ||||
| -rw-r--r-- | Documentation/arm64/sme.rst | 3 | ||||
| -rw-r--r-- | Documentation/arm64/sve.rst | 4 |
4 files changed, 7 insertions, 4 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index f8d0a7288c73..ffeccdd6bdac 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -223,7 +223,7 @@ Before jumping into the kernel, the following conditions must be met: For systems with a GICv3 interrupt controller to be used in v3 mode: - If EL3 is present: - - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. + - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1. - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across all CPUs the kernel is executing on, and must stay constant diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index 8a9d4bf7daf4..83e57e4d38e2 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -14,7 +14,7 @@ Some hardware or software features are only available on some CPU implementations, and/or with certain kernel configurations, but have no architected discovery mechanism available to userspace code at EL0. The kernel exposes the presence of these features to userspace through a set -of flags called hwcaps, exposed in the auxilliary vector. +of flags called hwcaps, exposed in the auxiliary vector. Userspace software can test for features by acquiring the AT_HWCAP or AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant diff --git a/Documentation/arm64/sme.rst b/Documentation/arm64/sme.rst index 68d1efb7d171..1c43ea12eb4f 100644 --- a/Documentation/arm64/sme.rst +++ b/Documentation/arm64/sme.rst @@ -117,6 +117,9 @@ be zeroed. * Signal handlers are invoked with streaming mode and ZA disabled. +* A new signal frame record TPIDR2_MAGIC is added formatted as a struct + tpidr2_context to allow access to TPIDR2_EL0 from signal handlers. + * A new signal frame record za_context encodes the ZA register contents on signal delivery. [1] diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index c7a356bf4e8f..1b90a30382ac 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -175,7 +175,7 @@ the SVE instruction set architecture. When returning from a signal handler: * If there is no sve_context record in the signal frame, or if the record is - present but contains no register data as desribed in the previous section, + present but contains no register data as described in the previous section, then the SVE registers/bits become non-live and take unspecified values. * If sve_context is present in the signal frame and contains full register @@ -223,7 +223,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg) Defer the requested vector length change until the next execve() performed by this thread. - The effect is equivalent to implicit exceution of the following + The effect is equivalent to implicit execution of the following call immediately after the next execve() (if any) by the thread: prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC) |