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-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display Clock & Reset Controller Binding
-
-maintainers:
- - Taniya Das <tdas@codeaurora.org>
-
-description: |
- Qualcomm display clock control module which supports the clocks, resets and
- power domains.
-
-properties:
- compatible:
- enum:
- - qcom,sc7180-dispcc
- - qcom,sdm845-dispcc
-
- clocks:
- minItems: 1
- maxItems: 2
- items:
- - description: Board XO source
- - description: GPLL0 source from GCC
-
- clock-names:
- items:
- - const: xo
- - const: gpll0
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-examples:
- # Example of DISPCC with clock node properties for SDM845:
- - |
- clock-controller@af00000 {
- compatible = "qcom,sdm845-dispcc";
- reg = <0xaf00000 0x10000>;
- clocks = <&rpmhcc 0>, <&gcc 24>;
- clock-names = "xo", "gpll0";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-...