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Diffstat (limited to 'Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 93ae349cf9e9..5cbb34d0b61b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -8,8 +8,6 @@ title: Xilinx Versal clock controller maintainers: - Michal Simek <michal.simek@amd.com> - - Jolly Shah <jolly.shah@xilinx.com> - - Rajan Vaja <rajan.vaja@xilinx.com> description: | The clock controller is a hardware block of Xilinx versal clock tree. It |