diff options
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
450 files changed, 24728 insertions, 7405 deletions
diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml new file mode 100644 index 000000000000..5e942bccf277 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AXI clkgen pcore clock generator + +maintainers: + - Lars-Peter Clausen <lars@metafoo.de> + - Michael Hennerich <michael.hennerich@analog.com> + +description: | + The axi_clkgen IP core is a software programmable clock generator, + that can be synthesized on various FPGA platforms. + + Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen + +properties: + compatible: + enum: + - adi,axi-clkgen-2.00.a + - adi,zynqmp-axi-clkgen-2.00.a + + clocks: + description: + Specifies the reference clock(s) from which the output frequency is + derived. This must either reference one clock if only the first clock + input is connected or two if both clock inputs are connected. + minItems: 1 + maxItems: 2 + + '#clock-cells': + const: 0 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@ff000000 { + compatible = "adi,axi-clkgen-2.00.a"; + #clock-cells = <0>; + reg = <0xff000000 0x1000>; + clocks = <&osc 1>; + }; diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml new file mode 100644 index 000000000000..79b0752faa91 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EN7523 Clock + +maintainers: + - Felix Fietkau <nbd@nbd.name> + - John Crispin <nbd@nbd.name> + +description: | + This node defines the System Control Unit of the EN7523 SoC, + a collection of registers configuring many different aspects of the SoC. + + The clock driver uses it to read and configure settings of the + PLL controller, which provides clocks for the CPU, the bus and + other SoC internal peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify which clock they consume. + + All these identifiers can be found in: + [1]: <include/dt-bindings/clock/en7523-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: airoha,en7523-scu + + reg: + maxItems: 2 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/en7523-clk.h> + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml new file mode 100644 index 000000000000..93587b700476 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AHB Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-ahb-clk + - allwinner,sun6i-a31-ahb1-clk + - allwinner,sun8i-h3-ahb2-clk + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-ahb-clk + + then: + properties: + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-ahb1-clk + + then: + properties: + clocks: + maxItems: 4 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-ahb2-clk + + then: + properties: + clocks: + maxItems: 2 + +examples: + - | + ahb@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>; + clock-output-names = "ahb"; + }; + + - | + ahb1@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + - | + ahb2_clk@1c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6d2>; + clock-output-names = "ahb2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml new file mode 100644 index 000000000000..e14e1aad9fd6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 APB0 Bus Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-apb0-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + apb0@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml new file mode 100644 index 000000000000..8a4747ebe0ba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 APB1 Bus Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-apb1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-axi-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-axi-clk.yaml new file mode 100644 index 000000000000..aa08dd49dd61 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-axi-clk.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 AXI Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-axi-clk + - allwinner,sun8i-a23-axi-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + axi@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + - | + axi_clk@1c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 64938fdaea55..1690b9d99c3d 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -4,11 +4,11 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner Clock Control Unit Device Tree Bindings +title: Allwinner Clock Control Unit maintainers: - Chen-Yu Tsai <wens@csie.org> - - Maxime Ripard <maxime.ripard@bootlin.com> + - Maxime Ripard <mripard@kernel.org> properties: "#clock-cells": @@ -34,11 +34,17 @@ properties: - allwinner,sun8i-v3-ccu - allwinner,sun8i-v3s-ccu - allwinner,sun9i-a80-ccu + - allwinner,sun20i-d1-ccu + - allwinner,sun20i-d1-r-ccu - allwinner,sun50i-a64-ccu - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-a100-ccu + - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu + - allwinner,sun50i-h616-ccu + - allwinner,sun50i-h616-r-ccu - allwinner,suniv-f1c100s-ccu - nextthing,gr8-ccu @@ -47,7 +53,6 @@ properties: clocks: minItems: 2 - maxItems: 4 items: - description: High Frequency Oscillator (usually at 24MHz) - description: Low Frequency Oscillator (usually at 32kHz) @@ -56,7 +61,6 @@ properties: clock-names: minItems: 2 - maxItems: 4 items: - const: hosc - const: losc @@ -77,8 +81,11 @@ if: enum: - allwinner,sun8i-a83t-r-ccu - allwinner,sun8i-h3-r-ccu + - allwinner,sun20i-d1-r-ccu - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h6-r-ccu + - allwinner,sun50i-h616-r-ccu then: properties: @@ -94,7 +101,11 @@ else: if: properties: compatible: - const: allwinner,sun50i-h6-ccu + enum: + - allwinner,sun20i-d1-ccu + - allwinner,sun50i-a100-ccu + - allwinner,sun50i-h6-ccu + - allwinner,sun50i-h616-ccu then: properties: diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml new file mode 100644 index 000000000000..08d073520cfa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 CPU Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-cpu-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + cpu@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-display-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-display-clk.yaml new file mode 100644 index 000000000000..e665e50c1785 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-display-clk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Display Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-display-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml new file mode 100644 index 000000000000..c4714d0fbe07 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Bus Gates Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + compatible: + oneOf: + - const: allwinner,sun4i-a10-gates-clk + - const: allwinner,sun4i-a10-axi-gates-clk + - const: allwinner,sun4i-a10-ahb-gates-clk + - const: allwinner,sun5i-a10s-ahb-gates-clk + - const: allwinner,sun5i-a13-ahb-gates-clk + - const: allwinner,sun7i-a20-ahb-gates-clk + - const: allwinner,sun6i-a31-ahb1-gates-clk + - const: allwinner,sun8i-a23-ahb1-gates-clk + - const: allwinner,sun9i-a80-ahb0-gates-clk + - const: allwinner,sun9i-a80-ahb1-gates-clk + - const: allwinner,sun9i-a80-ahb2-gates-clk + - const: allwinner,sun4i-a10-apb0-gates-clk + - const: allwinner,sun5i-a10s-apb0-gates-clk + - const: allwinner,sun5i-a13-apb0-gates-clk + - const: allwinner,sun7i-a20-apb0-gates-clk + - const: allwinner,sun9i-a80-apb0-gates-clk + - const: allwinner,sun8i-a83t-apb0-gates-clk + - const: allwinner,sun4i-a10-apb1-gates-clk + - const: allwinner,sun5i-a13-apb1-gates-clk + - const: allwinner,sun5i-a10s-apb1-gates-clk + - const: allwinner,sun6i-a31-apb1-gates-clk + - const: allwinner,sun7i-a20-apb1-gates-clk + - const: allwinner,sun8i-a23-apb1-gates-clk + - const: allwinner,sun9i-a80-apb1-gates-clk + - const: allwinner,sun6i-a31-apb2-gates-clk + - const: allwinner,sun8i-a23-apb2-gates-clk + - const: allwinner,sun8i-a83t-bus-gates-clk + - const: allwinner,sun9i-a80-apbs-gates-clk + - const: allwinner,sun4i-a10-dram-gates-clk + + - items: + - const: allwinner,sun5i-a13-dram-gates-clk + - const: allwinner,sun4i-a10-gates-clk + + - items: + - const: allwinner,sun8i-h3-apb0-gates-clk + - const: allwinner,sun4i-a10-gates-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-indices: + minItems: 1 + maxItems: 64 + + clock-output-names: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-indices + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-indices = <0>; + clock-output-names = "axi_dram"; + }; + + - | + clk@1c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <3>, + <4>, <5>, <6>, + <7>, <8>, <9>, + <10>, <11>, <12>, + <13>, <14>, <16>, + <17>, <18>, <20>, + <21>, <22>, <23>, + <24>, <25>, <26>, + <32>, <33>, <34>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <45>, + <46>, <47>, + <50>, <52>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", + "ahb_ohci1", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", + "ahb_nand", "ahb_sdram", "ahb_ace", + "ahb_emac", "ahb_ts", "ahb_spi0", + "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", + "ahb_ve", "ahb_tvd", "ahb_tve0", + "ahb_tve1", "ahb_lcd0", "ahb_lcd1", + "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", + "ahb_de_fe0", "ahb_de_fe1", + "ahb_mp", "ahb_mali400"; + }; + + + - | + clk@1c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-indices = <0>, <1>, + <2>, <3>, + <5>, <6>, + <7>, <10>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis", + "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml new file mode 100644 index 000000000000..e824e33489b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 MBUS Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun5i-a13-mbus-clk + - allwinner,sun8i-a23-mbus-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + + - | + clk@1c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml new file mode 100644 index 000000000000..c612f94befb9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 1 Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + There is three different outputs: the main clock, with the ID 0, + and the output and sample clocks, with the IDs 1 and 2, + respectively. + + compatible: + enum: + - allwinner,sun4i-a10-mmc-clk + - allwinner,sun9i-a80-mmc-clk + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 3 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-mmc-clk + +then: + properties: + clocks: + maxItems: 3 + +else: + properties: + clocks: + maxItems: 2 + +examples: + - | + clk@1c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + - | + clk@6000410 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x06000410 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc0", "mmc0_output", + "mmc0_sample"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml new file mode 100644 index 000000000000..80ae3a7a588c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 0 Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +select: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun9i-a80-mod0-clk + + # The PRCM on the A31 and A23 will have the reg property missing, + # since it's set at the upper level node, and will be validated by + # PRCM's schema. Make sure we only validate standalone nodes. + required: + - compatible + - reg + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-mod0-clk + - allwinner,sun9i-a80-mod0-clk + + reg: + maxItems: 1 + + clocks: + # On the A80, the PRCM mod0 clocks have 2 parents. + minItems: 2 + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + - | + clk@8001454 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x08001454 0x4>; + clocks = <&osc32k>, <&osc24M>; + clock-output-names = "r_ir"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml new file mode 100644 index 000000000000..4f9a8d44d42a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Module 1 Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-mod1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun4i-a10-pll2.h> + + clk@1c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml new file mode 100644 index 000000000000..0052bf1e8a6b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Gateable Oscillator Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-osc-clk + + reg: + maxItems: 1 + + clock-frequency: + description: > + Frequency of the main oscillator. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clock-frequency + - clock-output-names + +additionalProperties: false + +examples: + - | + osc24M: clk@1c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml new file mode 100644 index 000000000000..b13a1f21d5da --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 CPU PLL + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun4i-a10-pll1-clk + - allwinner,sun6i-a31-pll1-clk + - allwinner,sun8i-a23-pll1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "osc24M"; + }; + + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + - | + clk@1c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml new file mode 100644 index 000000000000..418d207d23b8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video PLL + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-pll3-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml new file mode 100644 index 000000000000..76ef3f0c7f2c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 DRAM PLL + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the DRAM clock output, the second is meant + for peripherals on the SoC. + + compatible: + const: allwinner,sun4i-a10-pll5-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 2 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml new file mode 100644 index 000000000000..a94c93c90ece --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Peripheral PLL + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the SATA clock output, the second is the + regular PLL output, the third is a PLL output at twice the rate. + + compatible: + const: allwinner,sun4i-a10-pll6-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 3 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml new file mode 100644 index 000000000000..6646b2a99fc1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 TCON Channel 0 Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-tcon-ch0-clk + - allwinner,sun4i-a10-tcon-ch1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-tcon-ch0-clk + +then: + required: + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clk@1c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + - | + clk@1c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-usb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-usb-clk.yaml new file mode 100644 index 000000000000..5103b675e488 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-usb-clk.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 USB Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-usb-clk + - allwinner,sun5i-a13-usb-clk + - allwinner,sun6i-a31-usb-clk + - allwinner,sun8i-a23-usb-clk + - allwinner,sun8i-h3-usb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + minItems: 2 + maxItems: 8 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-usb-clk + + then: + properties: + clock-output-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: allwinner,sun5i-a13-usb-clk + + then: + properties: + clock-output-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-usb-clk + + then: + properties: + clock-output-names: + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-a23-usb-clk + + then: + properties: + clock-output-names: + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-usb-clk + + then: + properties: + clock-output-names: + maxItems: 8 + +examples: + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", + "usb_ohci0", "usb_ohci1", + "usb_ohci2"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-a23-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", + "usb_hsic_12M", "usb_ohci0"; + }; + + - | + clk@1c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ve-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ve-clk.yaml new file mode 100644 index 000000000000..80337e38d6e5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ve-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ve-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Video Engine Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + "#reset-cells": + const: 0 + + compatible: + const: allwinner,sun4i-a10-ve-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c2013c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-ve-clk"; + reg = <0x01c2013c 0x4>; + clocks = <&pll4>; + clock-output-names = "ve"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml new file mode 100644 index 000000000000..c6a6fbb6863b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A13 AHB Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun5i-a13-ahb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + ahb@1c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml new file mode 100644 index 000000000000..7d6a6a34d20c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Peripheral PLL + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The first output is the regular PLL output, the second is a PLL + output at twice the rate. + + compatible: + const: allwinner,sun6i-a31-pll6-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 2 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml new file mode 100644 index 000000000000..b6202de35707 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A20 GMAC TX Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun7i-a20-gmac-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + description: > + The parent clocks shall be fixed rate dummy clocks at 25 MHz and + 125 MHz, respectively. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-out-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-out-clk.yaml new file mode 100644 index 000000000000..fde7f7dc3d34 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun7i-a20-out-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-out-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A20 Output Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun7i-a20-out-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c201f0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f0 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_a"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml new file mode 100644 index 000000000000..70369bd633e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83t Display Engine 2/3 Clock Controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + oneOf: + - const: allwinner,sun8i-a83t-de2-clk + - const: allwinner,sun8i-h3-de2-clk + - const: allwinner,sun8i-v3s-de2-clk + - const: allwinner,sun50i-a64-de2-clk + - const: allwinner,sun50i-h5-de2-clk + - const: allwinner,sun50i-h6-de3-clk + - items: + - const: allwinner,sun8i-r40-de2-clk + - const: allwinner,sun8i-h3-de2-clk + - items: + - const: allwinner,sun20i-d1-de2-clk + - const: allwinner,sun50i-h5-de2-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun8i-h3-ccu.h> + #include <dt-bindings/reset/sun8i-h3-ccu.h> + + de2_clocks: clock@1000000 { + compatible = "allwinner,sun8i-h3-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml new file mode 100644 index 000000000000..45b9e2c7c1d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Bus Gates Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + compatible: + const: allwinner,sun8i-h3-bus-gates-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-indices: + minItems: 1 + maxItems: 64 + + clock-output-names: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-indices + - clock-names + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, + <116>, <128>, <135>; + clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", + "bus_mmc1", "bus_mmc2", "bus_nand", + "bus_sdram", "bus_gmac", "bus_ts", + "bus_hstimer", "bus_spi0", + "bus_spi1", "bus_otg", + "bus_otg_ehci0", "bus_ehci1", + "bus_ehci2", "bus_ehci3", + "bus_otg_ohci0", "bus_ohci1", + "bus_ohci2", "bus_ohci3", "bus_ve", + "bus_lcd0", "bus_lcd1", "bus_deint", + "bus_csi", "bus_tve", "bus_hdmi", + "bus_de", "bus_gpu", "bus_msgbox", + "bus_spinlock", "bus_codec", + "bus_spdif", "bus_pio", "bus_ths", + "bus_i2s0", "bus_i2s1", "bus_i2s2", + "bus_i2c0", "bus_i2c1", "bus_i2c2", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_scr", "bus_ephy", "bus_dbg"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml new file mode 100644 index 000000000000..f0f65af8ae22 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 AHB Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-ahb-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@6000060 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-ahb-clk"; + reg = <0x06000060 0x4>; + clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "ahb0"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml new file mode 100644 index 000000000000..e9f9bc8f5794 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 APB0 Bus Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - allwinner,sun9i-a80-apb0-clk + - allwinner,sun9i-a80-apb1-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@6000070 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb0-clk"; + reg = <0x06000070 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb0"; + }; + + - | + clk@6000074 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb1-clk"; + reg = <0x06000074 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml new file mode 100644 index 000000000000..c48db2d49340 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 CPUS Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-cpus-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@8001410 { + compatible = "allwinner,sun9i-a80-cpus-clk"; + reg = <0x08001410 0x4>; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; + clock-output-names = "cpus"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml new file mode 100644 index 000000000000..e9f81a343be1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Display Engine Clock Controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-de-clks + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: RAM Bus Clock + - description: Module Clock + + clock-names: + items: + - const: mod + - const: dram + - const: bus + + resets: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun9i-a80-ccu.h> + #include <dt-bindings/reset/sun9i-a80-ccu.h> + + de_clocks: clock@3000000 { + compatible = "allwinner,sun9i-a80-de-clks"; + reg = <0x03000000 0x30>; + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; + clock-names = "mod", "dram", "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml new file mode 100644 index 000000000000..d3ce5eb18d4e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-gt-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 GT Bus Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-gt-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + description: > + The parent order must match the hardware programming order. + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@600005c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-gt-clk"; + reg = <0x0600005c 0x4>; + clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "gt"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml new file mode 100644 index 000000000000..65ee5afe83cc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 MMC Configuration Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +description: > + There is one clock/reset output per mmc controller. The number of + outputs is determined by the size of the address block, which is + related to the overall mmc block. + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-mmc-config-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + clock-output-names: + maxItems: 4 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@1c13000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-config-clk"; + reg = <0x01c13000 0x10>; + clocks = <&ahb0_gates 8>; + resets = <&ahb0_resets 8>; + clock-output-names = "mmc0_config", "mmc1_config", + "mmc2_config", "mmc3_config"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml new file mode 100644 index 000000000000..261264a8aef6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 Peripheral PLL + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 0 + + compatible: + const: allwinner,sun9i-a80-pll4-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@600000c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pll4-clk"; + reg = <0x0600000c 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-clks.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-clks.yaml new file mode 100644 index 000000000000..515c15d5f661 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-clks.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB Clock Controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-clks + + reg: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + + clock-names: + items: + - const: bus + - const: hosc + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun9i-a80-ccu.h> + + usb_clocks: clock@a08000 { + compatible = "allwinner,sun9i-a80-usb-clks"; + reg = <0x00a08000 0x8>; + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; + clock-names = "bus", "hosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml new file mode 100644 index 000000000000..3f7b8d9511f1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-mod-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB Module Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-mod-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 6 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@a08000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-mod-clk"; + reg = <0x00a08000 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb0_ahb", "usb_ohci0", + "usb1_ahb", "usb_ohci1", + "usb2_ahb", "usb_ohci2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml new file mode 100644 index 000000000000..0d49072d47ca --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A80 USB PHY Clock + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +properties: + "#clock-cells": + const: 1 + description: > + The additional ID argument passed to the clock shall refer to + the index of the output. + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun9i-a80-usb-phy-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 6 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-output-names + +additionalProperties: false + +examples: + - | + clk@a08004 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-phy-clk"; + reg = <0x00a08004 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb_phy0", "usb_hsic1_480M", + "usb_phy1", "usb_hsic2_480M", + "usb_phy2", "usb_hsic_12M"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/alphascale,acc.txt b/Documentation/devicetree/bindings/clock/alphascale,acc.txt index b3205b21c9d0..c9fb9324c634 100644 --- a/Documentation/devicetree/bindings/clock/alphascale,acc.txt +++ b/Documentation/devicetree/bindings/clock/alphascale,acc.txt @@ -1,7 +1,7 @@ Alphascale Clock Controller -The ACC (Alphascale Clock Controller) is responsible of choising proper -clock source, setting deviders and clock gates. +The ACC (Alphascale Clock Controller) is responsible for choosing proper +clock source, setting dividers and clock gates. Required properties for the ACC node: - compatible: must be "alphascale,asm9260-clock-controller" diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml new file mode 100644 index 000000000000..6d84cee1bd75 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A1 Peripherals Clock Control Unit + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@jian.hu.com> + - Dmitry Rokosov <ddrokosov@sberdevices.ru> + +properties: + compatible: + const: amlogic,a1-peripherals-clkc + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: input fixed pll div2 + - description: input fixed pll div3 + - description: input fixed pll div5 + - description: input fixed pll div7 + - description: input hifi pll + - description: input oscillator (usually at 24MHz) + + clock-names: + items: + - const: fclk_div2 + - const: fclk_div3 + - const: fclk_div5 + - const: fclk_div7 + - const: hifi_pll + - const: xtal + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@800 { + compatible = "amlogic,a1-peripherals-clkc"; + reg = <0 0x800 0 0x104>; + #clock-cells = <1>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", + "hifi_pll", "xtal"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml new file mode 100644 index 000000000000..a59b188a8bf5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A1 PLL Clock Control Unit + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@jian.hu.com> + - Dmitry Rokosov <ddrokosov@sberdevices.ru> + +properties: + compatible: + const: amlogic,a1-pll-clkc + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: input fixpll_in + - description: input hifipll_in + + clock-names: + items: + - const: fixpll_in + - const: hifipll_in + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@7c80 { + compatible = "amlogic,a1-pll-clkc"; + reg = <0 0x7c80 0 0x18c>; + #clock-cells = <1>; + clocks = <&clkc_periphs CLKID_FIXPLL_IN>, + <&clkc_periphs CLKID_HIFIPLL_IN>; + clock-names = "fixpll_in", "hifipll_in"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt deleted file mode 100644 index c41f0be5d438..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Amlogic GXBB AO Clock and Reset Unit - -The Amlogic GXBB AO clock controller generates and supplies clock to various -controllers within the Always-On part of the SoC. - -Required Properties: - -- compatible: value should be different for each SoC family as : - - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" - - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - - GXM (S912) : "amlogic,meson-gxm-aoclkc" - - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" - - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc" - followed by the common "amlogic,meson-gx-aoclkc" -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "xtal" : the platform xtal - * "mpeg-clk" : the main clock controller mother clock (aka clk81) - * "ext-32k-0" : external 32kHz reference #0 if any (optional) - * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) - * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be -used in device tree sources. - -- #reset-cells: should be 1. - -Each reset is assigned an identifier and client nodes can use this identifier -to specify the reset which they consume. All available resets are defined as -preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be -used in device tree sources. - -Parent node should have the following properties : -- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" -- reg: base address and size of the AO system control register space. - -Example: AO Clock controller node: - -ao_sysctrl: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - -Example: UART controller node that consumes the clock and reset generated - by the clock controller: - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-uart"; - reg = <0x4c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc_AO CLKID_AO_UART1>; - resets = <&clkc_AO RESET_AO_UART1>; - }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml new file mode 100644 index 000000000000..628e5dd33dd4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Always-On Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + oneOf: + - items: + - enum: + - amlogic,meson-gxbb-aoclkc + - amlogic,meson-gxl-aoclkc + - amlogic,meson-gxm-aoclkc + - amlogic,meson-axg-aoclkc + - const: amlogic,meson-gx-aoclkc + - enum: + - amlogic,meson-axg-aoclkc + - amlogic,meson-g12a-aoclkc + + clocks: + minItems: 2 + maxItems: 5 + + clock-names: + minItems: 2 + items: + - const: xtal + - const: mpeg-clk + - const: ext-32k-0 + - const: ext-32k-1 + - const: ext-32k-2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-g12a-aoclkc + + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + - if: + properties: + compatible: + enum: + - amlogic,meson-gxl-aoclkc + - amlogic,meson-gxm-aoclkc + - amlogic,meson-axg-aoclkc + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt deleted file mode 100644 index 7ccecd5c02c1..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Amlogic GXBB Clock and Reset Unit - -The Amlogic GXBB clock controller generates and supplies clock to various -controllers within the SoC. - -Required Properties: - -- compatible: should be: - "amlogic,gxbb-clkc" for GXBB SoC, - "amlogic,gxl-clkc" for GXL and GXM SoC, - "amlogic,axg-clkc" for AXG SoC. - "amlogic,g12a-clkc" for G12A SoC. - "amlogic,g12b-clkc" for G12B SoC. - "amlogic,sm1-clkc" for SM1 SoC. -- clocks : list of clock phandle, one for each entry clock-names. -- clock-names : should contain the following: - * "xtal": the platform xtal - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be -used in device tree sources. - -Parent node should have the following properties : -- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or - "amlogic,meson-axg-hhi-sysctrl" -- reg: base address and size of the HHI system control register space. - -Example: Clock controller node: - -sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - #clock-cells = <1>; - compatible = "amlogic,gxbb-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml new file mode 100644 index 000000000000..63246f1cb539 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + enum: + - amlogic,gxbb-clkc + - amlogic,gxl-clkc + - amlogic,axg-clkc + - amlogic,g12a-clkc + - amlogic,g12b-clkc + - amlogic,sm1-clkc + + clocks: + maxItems: 1 + + clock-names: + const: xtal + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 000000000000..d98d95d8e8c9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller + +maintainers: + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 4d94091c1d2d..cc51e4746b3b 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -11,6 +11,11 @@ Required Properties: - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - #clock-cells: should be 1. - #reset-cells: should be 1. +- clocks: list of clock phandles, one for each entry in clock-names +- clock-names: should contain the following: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) Parent node should have the following properties : - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml new file mode 100644 index 000000000000..c229e4f0c1d9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic S4 Peripherals Clock Controller + +maintainers: + - Yu Tu <yu.tu@amlogic.com> + +properties: + compatible: + const: amlogic,s4-peripherals-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 14 + items: + - description: input fixed pll div2 + - description: input fixed pll div2p5 + - description: input fixed pll div3 + - description: input fixed pll div4 + - description: input fixed pll div5 + - description: input fixed pll div7 + - description: input hifi pll + - description: input gp0 pll + - description: input mpll0 + - description: input mpll1 + - description: input mpll2 + - description: input mpll3 + - description: input hdmi pll + - description: input oscillator (usually at 24MHz) + - description: input external 32kHz reference (optional) + + clock-names: + minItems: 14 + items: + - const: fclk_div2 + - const: fclk_div2p5 + - const: fclk_div3 + - const: fclk_div4 + - const: fclk_div5 + - const: fclk_div7 + - const: hifi_pll + - const: gp0_pll + - const: mpll0 + - const: mpll1 + - const: mpll2 + - const: mpll3 + - const: hdmi_pll + - const: xtal + - const: ext_32k + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> + + clkc_periphs: clock-controller@fe000000 { + compatible = "amlogic,s4-peripherals-clkc"; + reg = <0xfe000000 0x49c>; + clocks = <&clkc_pll 3>, + <&clkc_pll 13>, + <&clkc_pll 5>, + <&clkc_pll 7>, + <&clkc_pll 9>, + <&clkc_pll 11>, + <&clkc_pll 17>, + <&clkc_pll 15>, + <&clkc_pll 25>, + <&clkc_pll 27>, + <&clkc_pll 29>, + <&clkc_pll 31>, + <&clkc_pll 20>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4", + "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll", + "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml new file mode 100644 index 000000000000..d8932ec26ca8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic S4 PLL Clock Controller + +maintainers: + - Yu Tu <yu.tu@amlogic.com> + +properties: + compatible: + const: amlogic,s4-pll-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkc_pll: clock-controller@fe008000 { + compatible = "amlogic,s4-pll-clkc"; + reg = <0xfe008000 0x1e8>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/apple,nco.yaml b/Documentation/devicetree/bindings/clock/apple,nco.yaml new file mode 100644 index 000000000000..8b8411dc42f6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/apple,nco.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/apple,nco.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoCs' NCO block + +maintainers: + - Martin Povišer <povik+lin@cutebit.org> + +description: | + The NCO (Numerically Controlled Oscillator) block found on Apple SoCs + such as the t8103 (M1) is a programmable clock generator performing + fractional division of a high frequency input clock. + + It carries a number of independent channels and is typically used for + generation of audio bitclocks. + +properties: + compatible: + items: + - enum: + - apple,t6000-nco + - apple,t8103-nco + - apple,t8112-nco + - const: apple,nco + + clocks: + description: + Specifies the reference clock from which the output clocks + are derived through fractional division. + maxItems: 1 + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - '#clock-cells' + - reg + +additionalProperties: false + +examples: + - | + nco_clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <900000000>; + clock-output-names = "nco-ref"; + }; + + nco: clock-controller@23b044000 { + compatible = "apple,t8103-nco", "apple,nco"; + reg = <0x3b044000 0x14000>; + #clock-cells = <1>; + clocks = <&nco_clkref>; + }; diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml new file mode 100644 index 000000000000..b5533f81307c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM System Controller ICST Clocks + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: | + The ICS525 and ICS307 oscillators are produced by Integrated + Devices Technology (IDT). ARM integrated these oscillators deeply into their + reference designs by adding special control registers that manage such + oscillators to their system controllers. + + The various ARM system controllers contain logic to serialize and initialize + an ICST clock request after a write to the 32 bit register at an offset + into the system controller. Furthermore, to even be able to alter one of + these frequencies, the system controller must first be unlocked by + writing a special token to another offset in the system controller. + + Some ARM hardware contain special versions of the serial interface that only + connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to + different values and sometimes also hard-wires the output divider. They + therefore have special compatible strings as per this table (the OD value is + the value on the pins, not the resulting output divider). + + In the core modules and logic tiles, the ICST is a configurable clock fed + from a 24 MHz clock on the motherboard (usually the main crystal) used for + generating e.g. video clocks. It is located on the core module and there is + only one of these. This clock node must be a subnode of the core module. + + Hardware variant RDW OD VDW + + Integrator/AP 22 1 Bit 8 0, rest variable + integratorap-cm + + Integrator/AP 46 3 Bit 8 0, rest variable + integratorap-sys + + Integrator/AP 22 or 1 17 or (33 or 25 MHz) + integratorap-pci 14 1 14 + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-core + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-mem + + The ICST oscillator must be provided inside a system controller node. + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - arm,syscon-icst525 + - arm,syscon-icst307 + - arm,syscon-icst525-integratorap-cm + - arm,syscon-icst525-integratorap-sys + - arm,syscon-icst525-integratorap-pci + - arm,syscon-icst525-integratorcp-cm-core + - arm,syscon-icst525-integratorcp-cm-mem + - arm,integrator-cm-auxosc + - arm,versatile-cm-auxosc + - arm,impd1-vco1 + - arm,impd1-vco2 + + reg: + maxItems: 1 + description: The VCO register + + clocks: + description: Parent clock for the ICST VCO + maxItems: 1 + + clock-output-names: + maxItems: 1 + + lock-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset to the unlocking register for the oscillator + + vco-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset to the VCO register for the oscillator + deprecated: true + +required: + - "#clock-cells" + - compatible + - clocks + +additionalProperties: false + +examples: + - | + vco1: clock { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt deleted file mode 100644 index 11f5f95f571b..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ /dev/null @@ -1,34 +0,0 @@ -Clock bindings for ARM Integrator and Versatile Core Module clocks - -Auxiliary Oscillator Clock - -This is a configurable clock fed from a 24 MHz chrystal, -used for generating e.g. video clocks. It is located on the -core module and there is only one of these. - -This clock node *must* be a subnode of the core module, since -it obtains the base address for it's address range from its -parent node. - - -Required properties: -- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -Example: - -core-module@10000000 { - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - auxosc: cm_aux_osc@25M { - #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt deleted file mode 100644 index 4cd81742038f..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM System Controller ICST clocks - -The ICS525 and ICS307 oscillators are produced by Integrated Devices -Technology (IDT). ARM integrated these oscillators deeply into their -reference designs by adding special control registers that manage such -oscillators to their system controllers. - -The various ARM system controllers contain logic to serialize and initialize -an ICST clock request after a write to the 32 bit register at an offset -into the system controller. Furthermore, to even be able to alter one of -these frequencies, the system controller must first be unlocked by -writing a special token to another offset in the system controller. - -Some ARM hardware contain special versions of the serial interface that only -connects the low 8 bits of the VDW (missing one bit), hardwires RDW to -different values and sometimes also hardwire the output divider. They -therefore have special compatible strings as per this table (the OD value is -the value on the pins, not the resulting output divider): - -Hardware variant: RDW OD VDW - -Integrator/AP 22 1 Bit 8 0, rest variable -integratorap-cm - -Integrator/AP 46 3 Bit 8 0, rest variable -integratorap-sys - -Integrator/AP 22 or 1 17 or (33 or 25 MHz) -integratorap-pci 14 1 14 - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-core - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-mem - -The ICST oscillator must be provided inside a system controller node. - -Required properties: -- compatible: must be one of - "arm,syscon-icst525" - "arm,syscon-icst307" - "arm,syscon-icst525-integratorap-cm" - "arm,syscon-icst525-integratorap-sys" - "arm,syscon-icst525-integratorap-pci" - "arm,syscon-icst525-integratorcp-cm-core" - "arm,syscon-icst525-integratorcp-cm-mem" -- lock-offset: the offset address into the system controller where the - unlocking register is located -- vco-offset: the offset address into the system controller where the - ICST control register is located (even 32 bit address) -- #clock-cells: must be <0> -- clocks: parent clock, since the ICST needs a parent clock to derive its - frequency from, this attribute is compulsory. - -Example: - -syscon: syscon@10000000 { - compatible = "syscon"; - reg = <0x10000000 0x1000>; - - oscclk0: osc0@c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0c>; - clocks = <&xtal24mhz>; - }; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt index 0ba1d83ff363..ed1df32c577a 100644 --- a/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt +++ b/Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt @@ -1,6 +1,6 @@ * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs -Marvell Armada 37xx SoCs provde Time Base Generator clocks which are +Marvell Armada 37xx SoCs provide Time Base Generator clocks which are used as parent clocks for the peripheral clocks. The TBG clock consumer should specify the desired clock by having the diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt deleted file mode 100644 index 13f45db3b66d..000000000000 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ /dev/null @@ -1,58 +0,0 @@ -Device Tree Clock bindings for arch-at91 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Slow Clock controller: - -Required properties: -- compatible : shall be one of the following: - "atmel,at91sam9x5-sckc", - "atmel,sama5d3-sckc", - "atmel,sama5d4-sckc" or - "microchip,sam9x60-sckc": - at91 SCKC (Slow Clock Controller) -- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. -- clocks : shall be the input parent clock phandle for the clock. - -Optional properties: -- atmel,osc-bypass : boolean property. Set this when a clock signal is directly - provided on XIN. - -For example: - sckc@fffffe50 { - compatible = "atmel,at91sam9x5-sckc"; - reg = <0xfffffe50 0x4>; - clocks = <&slow_xtal>; - #clock-cells = <0>; - }; - -Power Management Controller (PMC): - -Required properties: -- compatible : shall be "atmel,<chip>-pmc", "syscon" or - "microchip,sam9x60-pmc" - <chip> can be: at91rm9200, at91sam9260, at91sam9261, - at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15, - at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5, - sama5d2, sama5d3 or sama5d4. -- #clock-cells : from common clock binding; shall be set to 2. The first entry - is the type of the clock (core, system, peripheral or generated) and the - second entry its index as provided by the datasheet -- clocks : Must contain an entry for each entry in clock-names. -- clock-names: Must include the following entries: "slow_clk", "main_xtal" - -Optional properties: -- atmel,osc-bypass : boolean property. Set this when a clock signal is directly - provided on XIN. - -For example: - pmc: pmc@f0018000 { - compatible = "atmel,sama5d4-pmc", "syscon"; - reg = <0xf0018000 0x120>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - #clock-cells = <2>; - clocks = <&clk32k>, <&main_xtal>; - clock-names = "slow_clk", "main_xtal"; - }; diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml new file mode 100644 index 000000000000..c1bdcd9058ed --- /dev/null +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/atmel,at91rm9200-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Power Management Controller (PMC) + +maintainers: + - Claudiu Beznea <claudiu.beznea@microchip.com> + +description: + The power management controller optimizes power consumption by controlling all + system and user peripheral clocks. The PMC enables/disables the clock inputs + to many of the peripherals and to the processor. + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91sam9g20-pmc + - const: atmel,at91sam9260-pmc + - const: syscon + - items: + - enum: + - atmel,at91sam9g15-pmc + - atmel,at91sam9g25-pmc + - atmel,at91sam9g35-pmc + - atmel,at91sam9x25-pmc + - atmel,at91sam9x35-pmc + - const: atmel,at91sam9x5-pmc + - const: syscon + - items: + - enum: + - atmel,at91rm9200-pmc + - atmel,at91sam9260-pmc + - atmel,at91sam9g45-pmc + - atmel,at91sam9n12-pmc + - atmel,at91sam9rl-pmc + - atmel,at91sam9x5-pmc + - atmel,sama5d2-pmc + - atmel,sama5d3-pmc + - atmel,sama5d4-pmc + - microchip,sam9x60-pmc + - microchip,sama7g5-pmc + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#clock-cells": + description: | + - 1st cell is the clock type, one of PMC_TYPE_CORE, PMC_TYPE_SYSTEM, + PMC_TYPE_PERIPHERAL, PMC_TYPE_GCK, PMC_TYPE_PROGRAMMABLE (as defined + in <dt-bindings/clock/at91.h>) + - 2nd cell is the clock identifier as defined in <dt-bindings/clock/at91.h + (for core clocks) or as defined in datasheet (for system, peripheral, + gck and programmable clocks). + const: 2 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + atmel,osc-bypass: + description: set when a clock signal is directly provided on XIN + type: boolean + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sam9x60-pmc + - microchip,sama7g5-pmc + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: td_slck + - const: md_slck + - const: main_xtal + + - if: + properties: + compatible: + contains: + enum: + - atmel,at91rm9200-pmc + - atmel,at91sam9260-pmc + - atmel,at91sam9g20-pmc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: slow_xtal + - const: main_xtal + + - if: + properties: + compatible: + contains: + enum: + - atmel,sama5d2-pmc + - atmel,sama5d3-pmc + - atmel,sama5d4-pmc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: slow_clk + - const: main_xtal + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pmc: clock-controller@f0018000 { + compatible = "atmel,sama5d4-pmc", "syscon"; + reg = <0xf0018000 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml new file mode 100644 index 000000000000..7be29877e6d2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/atmel,at91sam9x5-sckc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Slow Clock Controller (SCKC) + +maintainers: + - Claudiu Beznea <claudiu.beznea@microchip.com> + +properties: + compatible: + oneOf: + - enum: + - atmel,at91sam9x5-sckc + - atmel,sama5d3-sckc + - atmel,sama5d4-sckc + - microchip,sam9x60-sckc + - items: + - const: microchip,sama7g5-sckc + - const: microchip,sam9x60-sckc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + enum: [0, 1] + + atmel,osc-bypass: + type: boolean + description: set when a clock signal is directly provided on XIN + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sam9x60-sckc + then: + properties: + "#clock-cells": + const: 1 + else: + properties: + "#clock-cells": + const: 0 + +additionalProperties: false + +examples: + - | + clk32k: clock-controller@fffffe50 { + compatible = "microchip,sam9x60-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt deleted file mode 100644 index aca94fe9416f..000000000000 --- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for the axi-clkgen clock generator - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a". -- #clock-cells : from common clock binding; Should always be set to 0. -- reg : Address and length of the axi-clkgen register set. -- clocks : Phandle and clock specifier for the parent clock(s). This must - either reference one clock if only the first clock input is connected or two - if both clock inputs are connected. For the later case the clock connected - to the first input must be specified first. - -Optional properties: -- clock-output-names : From common clock binding. - -Example: - clock@ff000000 { - compatible = "adi,axi-clkgen"; - #clock-cells = <0>; - reg = <0xff000000 0x1000>; - clocks = <&osc 1>; - }; diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml new file mode 100644 index 000000000000..bd4cefbb1244 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 Clock Control Unit Dividers + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + Clocks Control Unit is the core of Baikal-T1 SoC System Controller + responsible for the chip subsystems clocking and resetting. The CCU is + connected with an external fixed rate oscillator, which signal is transformed + into clocks of various frequencies and then propagated to either individual + IP-blocks or to groups of blocks (clock domains). The transformation is done + by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The + later ones are described in this binding. Each clock domain can be also + individually reset by using the domain clocks divider configuration + registers. Baikal-T1 CCU is logically divided into the next components: + 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but + in general can provide any frequency supported by the CCU PLLs). + 2) PLLs clocks generators (PLLs). + 3) AXI-bus clock dividers (AXI) - described in this binding file. + 4) System devices reference clock dividers (SYS) - described in this binding + file. + which are connected with each other as shown on the next figure: + + +---------------+ + | Baikal-T1 CCU | + | +----+------|- MIPS P5600 cores + | +-|PLLs|------|- DDR controller + | | +----+ | + +----+ | | | | | + |XTAL|--|-+ | | +---+-| + +----+ | | | +-|AXI|-|- AXI-bus + | | | +---+-| + | | | | + | | +----+---+-|- APB-bus + | +-------|SYS|-|- Low-speed Devices + | +---+-|- High-speed Devices + +---------------+ + + Each sub-block is represented as a separate DT node and has an individual + driver to be bound with. + + In order to create signals of wide range frequencies the external oscillator + output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are + then passed over CCU dividers to create signals required for the target clock + domain (like AXI-bus or System Device consumers). The dividers have the + following structure: + + +--------------+ + CLKIN --|->+----+ 1|\ | + SETCLK--|--|/DIV|->| | | + CLKDIV--|--| | | |-|->CLKLOUT + LOCK----|--+----+ | | | + | |/ | + | | | + EN------|-----------+ | + RST-----|--------------|->RSTOUT + +--------------+ + + where CLKIN is the reference clock coming either from CCU PLLs or from an + external clock oscillator, SETCLK - a command to update the output clock in + accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of + the output clock stabilization, EN - enable/disable the divider block, + RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core + peculiarities the dividers may lack of some functionality depicted on the + figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding + clock provider just doesn't expose either switching functions, or the rate + configuration, or both of them. + + The clock dividers, which output clock is then consumed by the SoC individual + devices, are united into a single clocks provider called System Devices CCU. + Similarly the dividers with output clocks utilized as AXI-bus reference clocks + are called AXI-bus CCU. Both of them use the common clock bindings with no + custom properties. The list of exported clocks and reset signals can be found + in the files: 'include/dt-bindings/clock/bt1-ccu.h' and + 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU + are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed + to be a children of later one. + +if: + properties: + compatible: + contains: + const: baikal,bt1-ccu-axi + +then: + properties: + clocks: + items: + - description: CCU SATA PLL output clock + - description: CCU PCIe PLL output clock + - description: CCU Ethernet PLL output clock + + clock-names: + items: + - const: sata_clk + - const: pcie_clk + - const: eth_clk + +else: + properties: + clocks: + items: + - description: External reference clock + - description: CCU SATA PLL output clock + - description: CCU PCIe PLL output clock + - description: CCU Ethernet PLL output clock + + clock-names: + items: + - const: ref_clk + - const: sata_clk + - const: pcie_clk + - const: eth_clk + +properties: + compatible: + enum: + - baikal,bt1-ccu-axi + - baikal,bt1-ccu-sys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: true + + clock-names: true + +additionalProperties: false + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +examples: + # AXI-bus Clock Control Unit node: + - | + #include <dt-bindings/clock/bt1-ccu.h> + + clock-controller@1f04d030 { + compatible = "baikal,bt1-ccu-axi"; + reg = <0x1f04d030 0x030>; + #clock-cells = <1>; + #reset-cells = <1>; + + clocks = <&ccu_pll CCU_SATA_PLL>, + <&ccu_pll CCU_PCIE_PLL>, + <&ccu_pll CCU_ETH_PLL>; + clock-names = "sata_clk", "pcie_clk", "eth_clk"; + }; + # System Devices Clock Control Unit node: + - | + #include <dt-bindings/clock/bt1-ccu.h> + + clock-controller@1f04d060 { + compatible = "baikal,bt1-ccu-sys"; + reg = <0x1f04d060 0x0a0>; + #clock-cells = <1>; + #reset-cells = <1>; + + clocks = <&clk25m>, + <&ccu_pll CCU_SATA_PLL>, + <&ccu_pll CCU_PCIE_PLL>, + <&ccu_pll CCU_ETH_PLL>; + clock-names = "ref_clk", "sata_clk", "pcie_clk", + "eth_clk"; + }; + # Required Clock Control Unit PLL node: + - | + ccu_pll: clock-controller@1f04d000 { + compatible = "baikal,bt1-ccu-pll"; + reg = <0x1f04d000 0x028>; + #clock-cells = <1>; + + clocks = <&clk25m>; + clock-names = "ref_clk"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml new file mode 100644 index 000000000000..7f8d98226437 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 Clock Control Unit PLL + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + Clocks Control Unit is the core of Baikal-T1 SoC System Controller + responsible for the chip subsystems clocking and resetting. The CCU is + connected with an external fixed rate oscillator, which signal is transformed + into clocks of various frequencies and then propagated to either individual + IP-blocks or to groups of blocks (clock domains). The transformation is done + by means of PLLs and gateable/non-gateable dividers embedded into the CCU. + It's logically divided into the next components: + 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but + in general can provide any frequency supported by the CCU PLLs). + 2) PLLs clocks generators (PLLs) - described in this binding file. + 3) AXI-bus clock dividers (AXI). + 4) System devices reference clock dividers (SYS). + which are connected with each other as shown on the next figure: + + +---------------+ + | Baikal-T1 CCU | + | +----+------|- MIPS P5600 cores + | +-|PLLs|------|- DDR controller + | | +----+ | + +----+ | | | | | + |XTAL|--|-+ | | +---+-| + +----+ | | | +-|AXI|-|- AXI-bus + | | | +---+-| + | | | | + | | +----+---+-|- APB-bus + | +-------|SYS|-|- Low-speed Devices + | +---+-|- High-speed Devices + +---------------+ + + Each CCU sub-block is represented as a separate dts-node and has an + individual driver to be bound with. + + In order to create signals of wide range frequencies the external oscillator + output is primarily connected to a set of CCU PLLs. There are five PLLs + to create a clock for the MIPS P5600 cores, the embedded DDR controller, + SATA, Ethernet and PCIe domains. The last three domains though named by the + biggest system interfaces in fact include nearly all of the rest SoC + peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core + with an interface wrapper (so called safe PLL' clocks switcher) to simplify + the PLL configuration procedure. The PLLs work as depicted on the next + diagram: + + +--------------------------+ + | | + +-->+---+ +---+ +---+ | +---+ 0|\ + CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| | + +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT + CLKOD---------C----------------+ 1| | + +--------C--------------------------->|/ + | | ^ + Rclk-+->+---+ | | + CLKR--->|/NR|-+ | + +---+ | + BYPASS--------------------------------------+ + BWADJ---> + + where Rclk is the reference clock coming from XTAL, NR - reference clock + divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT - + output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment + the binding supports the PLL dividers configuration in accordance with a + requested rate, while bypassing and bandwidth adjustment settings can be + added in future if it gets to be necessary. + + The PLLs CLKOUT is then either directly connected with the corresponding + clocks consumer (like P5600 cores or DDR controller) or passed over a CCU + divider to create a signal required for the clock domain. + + The CCU PLL dts-node uses the common clock bindings with no custom + parameters. The list of exported clocks can be found in + 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the + Baikal-T1 SoC System Controller its DT node is supposed to be a child of + later one. + +properties: + compatible: + const: baikal,bt1-ccu-pll + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + description: External reference clock + maxItems: 1 + + clock-names: + const: ref_clk + +additionalProperties: false + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +examples: + # Clock Control Unit PLL node: + - | + clock-controller@1f04d000 { + compatible = "baikal,bt1-ccu-pll"; + reg = <0x1f04d000 0x028>; + #clock-cells = <1>; + + clocks = <&clk25m>; + clock-names = "ref_clk"; + }; + # Required external oscillator: + - | + clk25m: clock-oscillator-25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clk25m"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml index e63827399c1a..f0f9392470a6 100644 --- a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml# +$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Bitmain BM1880 Clock Controller @@ -61,16 +61,4 @@ examples: #clock-cells = <1>; }; - # Example UART controller node that consumes clock generated by the clock controller: - - | - uart0: serial@58018000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x58018000 0x0 0x2000>; - clocks = <&clk 45>, <&clk 46>; - clock-names = "baudclk", "apb_pclk"; - interrupts = <0 9 4>; - reg-shift = <2>; - reg-io-width = <4>; - }; - ... diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml b/Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml new file mode 100644 index 000000000000..2d40df2d34df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm2711-dvp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2711 HDMI DVP + +maintainers: + - Maxime Ripard <mripard@kernel.org> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: brcm,brcm2711-dvp + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + dvp: clock@7ef00000 { + compatible = "brcm,brcm2711-dvp"; + reg = <0x7ef00000 0x10>; + clocks = <&clk_108MHz>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml new file mode 100644 index 000000000000..cd0d763ce2f3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM63268 Timer Clock and Reset + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + +properties: + compatible: + const: brcm,bcm63268-timer-clocks + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + timer_clk: clock-controller@100000ac { + compatible = "brcm,bcm63268-timer-clocks"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt index 3041657e2f96..3e7ca5530775 100644 --- a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt @@ -3,6 +3,8 @@ Gated Clock Controller Bindings for MIPS based BCM63XX SoCs Required properties: - compatible: must be one of: "brcm,bcm3368-clocks" + "brcm,bcm6318-clocks" + "brcm,bcm6318-ubus-clocks" "brcm,bcm6328-clocks" "brcm,bcm6358-clocks" "brcm,bcm6362-clocks" diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt deleted file mode 100644 index ab730ea0a560..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ /dev/null @@ -1,313 +0,0 @@ -Broadcom iProc Family Clocks - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The iProc clock controller manages clocks that are common to the iProc family. -An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL, -LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL -comprises of several leaf clocks - -Required properties for a PLL and its leaf clocks: - -- compatible: - Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on -Cygnus has a compatible string of "brcm,cygnus-genpll" - -- #clock-cells: - Have a value of <1> since there are more than 1 leaf clock of a given PLL - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for the PLL - -- clocks: - The input parent clock phandle for the PLL. For most iProc PLLs, this is an -onboard crystal with a fixed rate - -- clock-output-names: - An ordered list of strings defining the names of the clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - genpll: genpll { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - -Required properties for ASIU clocks: - -ASIU clocks are a special case. These clocks are derived directly from the -reference clock of the onboard crystal - -- compatible: - Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU -clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk" - -- #clock-cells: - Have a value of <1> since there are more than 1 ASIU clocks - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for ASIU clocks - -- clocks: - The input parent clock phandle for the ASIU clock, i.e., the onboard -crystal - -- clock-output-names: - An ordered list of strings defining the names of the ASIU clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - asiu_clks: asiu_clks { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - -Cygnus ------- -PLL and leaf clock compatible strings for Cygnus are: - "brcm,cygnus-armpll" - "brcm,cygnus-genpll" - "brcm,cygnus-lcpll0" - "brcm,cygnus-mipipll" - "brcm,cygnus-asiu-clk" - "brcm,cygnus-audiopll" - -The following table defines the set of PLL/clock index and ID for Cygnus. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-cygnus.h" - - Clock Source (Parent) Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK - adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK - pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK - - genpll crystal 0 BCM_CYGNUS_GENPLL - axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK - 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK - ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK - enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK - audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK - can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK - - lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 - pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK - ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK - sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK - usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK - smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK - ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED - - mipipll crystal 0 BCM_CYGNUS_MIPIPLL - ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED - ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD - ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D - ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED - ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED - ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED - - audiopll crystal 0 BCM_CYGNUS_AUDIOPLL - ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 - ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 - ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 - -Hurricane 2 ------- -PLL and leaf clock compatible strings for Hurricane 2 are: - "brcm,hr2-armpll" - -The following table defines the set of PLL/clock for Hurricane 2: - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - -Northstar and Northstar Plus ------- -PLL and leaf clock compatible strings for Northstar and Northstar Plus are: - "brcm,nsp-armpll" - "brcm,nsp-genpll" - "brcm,nsp-lcpll0" - -The following table defines the set of PLL/clock index and ID for Northstar and -Northstar Plus. These clock IDs are defined in: - "include/dt-bindings/clock/bcm-nsp.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - genpll crystal 0 BCM_NSP_GENPLL - phy genpll 1 BCM_NSP_GENPLL_PHY_CLK - ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK - usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK - iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK - sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK - sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK - - lcpll0 crystal 0 BCM_NSP_LCPLL0 - pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK - sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK - ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK - -Northstar 2 ------------ -PLL and leaf clock compatible strings for Northstar 2 are: - "brcm,ns2-genpll-scr" - "brcm,ns2-genpll-sw" - "brcm,ns2-lcpll-ddr" - "brcm,ns2-lcpll-ports" - -The following table defines the set of PLL/clock index and ID for Northstar 2. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-ns2.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - genpll_scr crystal 0 BCM_NS2_GENPLL_SCR - scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK - fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK - audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK - ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED - ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED - ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED - - genpll_sw crystal 0 BCM_NS2_GENPLL_SW - rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK - 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK - nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK - chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK - port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK - sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK - - lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR - pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK - ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK - ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED - ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED - ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED - ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED - - lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS - wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK - rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK - ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED - ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED - ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED - ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED - -BCM63138 --------- -PLL and leaf clock compatible strings for BCM63138 are: - "brcm,bcm63138-armpll" - -Stingray ------------ -PLL and leaf clock compatible strings for Stingray are: - "brcm,sr-genpll0" - "brcm,sr-genpll1" - "brcm,sr-genpll2" - "brcm,sr-genpll3" - "brcm,sr-genpll4" - "brcm,sr-genpll5" - "brcm,sr-genpll6" - - "brcm,sr-lcpll0" - "brcm,sr-lcpll1" - "brcm,sr-lcpll-pcie" - - -The following table defines the set of PLL/clock index and ID for Stingray. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-sr.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - crmu_ref25m crystal N/A N/A - - genpll0 crystal 0 BCM_SR_GENPLL0 - clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK - clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK - clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK - clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK - clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK - clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK - - genpll1 crystal 0 BCM_SR_GENPLL1 - clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK - clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK - - genpll2 crystal 0 BCM_SR_GENPLL2 - clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK - clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK - clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK - clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK - clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK - clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK - - genpll3 crystal 0 BCM_SR_GENPLL3 - clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK - clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK - - genpll4 crystal 0 BCM_SR_GENPLL4 - clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK - clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK - clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK - clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK - clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - - genpll5 crystal 0 BCM_SR_GENPLL5 - clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK - clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK - clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK - - genpll6 crystal 0 BCM_SR_GENPLL6 - clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK - - lcpll0 crystal 0 BCM_SR_LCPLL0 - clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK - clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK - clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK - clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK - - lcpll1 crystal 0 BCM_SR_LCPLL1 - clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK - clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK - clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK - - lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE - clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml new file mode 100644 index 000000000000..5ad147d265e6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml @@ -0,0 +1,417 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc Family Clocks + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +description: | + The iProc clock controller manages clocks that are common to the iProc family. + An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL, + LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL + comprises of several leaf clocks + + ASIU clocks are a special case. These clocks are derived directly from the + reference clock of the onboard crystal. + +properties: + compatible: + enum: + - brcm,bcm63138-armpll + - brcm,cygnus-armpll + - brcm,cygnus-genpll + - brcm,cygnus-lcpll0 + - brcm,cygnus-mipipll + - brcm,cygnus-asiu-clk + - brcm,cygnus-audiopll + - brcm,hr2-armpll + - brcm,nsp-armpll + - brcm,nsp-genpll + - brcm,nsp-lcpll0 + - brcm,ns2-genpll-scr + - brcm,ns2-genpll-sw + - brcm,ns2-lcpll-ddr + - brcm,ns2-lcpll-ports + - brcm,sr-genpll0 + - brcm,sr-genpll1 + - brcm,sr-genpll2 + - brcm,sr-genpll3 + - brcm,sr-genpll4 + - brcm,sr-genpll5 + - brcm,sr-genpll6 + - brcm,sr-lcpll0 + - brcm,sr-lcpll1 + - brcm,sr-lcpll-pcie + + reg: + minItems: 1 + items: + - description: base register + - description: power register + - description: ASIU or split status register + + clocks: + description: The input parent clock phandle for the PLL / ASIU clock. For + most iProc PLLs, this is an onboard crystal with a fixed rate. + maxItems: 1 + + '#clock-cells': + true + + clock-output-names: + minItems: 1 + maxItems: 45 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,cygnus-armpll + - brcm,nsp-armpll + then: + properties: + '#clock-cells': + const: 0 + else: + properties: + '#clock-cells': + const: 1 + required: + - clock-output-names + - if: + properties: + compatible: + contains: + enum: + - brcm,cygnus-armpll + - brcm,cygnus-genpll + - brcm,cygnus-lcpll0 + - brcm,cygnus-mipipll + - brcm,cygnus-asiu-clk + - brcm,cygnus-audiopll + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Cygnus. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-cygnus.h" + + Clock Source (Parent) Index ID + ----- --------------- ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK + adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK + pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK + + genpll crystal 0 BCM_CYGNUS_GENPLL + axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK + 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK + ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK + enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK + audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK + can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK + + lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 + pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK + ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK + sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK + usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK + smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK + ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED + + mipipll crystal 0 BCM_CYGNUS_MIPIPLL + ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED + ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD + ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D + ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED + ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED + ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED + + audiopll crystal 0 BCM_CYGNUS_AUDIOPLL + ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 + ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 + ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 + - if: + properties: + compatible: + contains: + enum: + - brcm,hr2-armpll + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock for Hurricane 2: + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + - if: + properties: + compatible: + contains: + enum: + - brcm,nsp-armpll + - brcm,nsp-genpll + - brcm,nsp-lcpll0 + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Northstar and + Northstar Plus. These clock IDs are defined in: + "include/dt-bindings/clock/bcm-nsp.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + genpll crystal 0 BCM_NSP_GENPLL + phy genpll 1 BCM_NSP_GENPLL_PHY_CLK + ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK + usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK + iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK + sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK + sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK + + lcpll0 crystal 0 BCM_NSP_LCPLL0 + pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK + sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK + ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK + - if: + properties: + compatible: + contains: + enum: + - brcm,ns2-genpll-scr + - brcm,ns2-genpll-sw + - brcm,ns2-lcpll-ddr + - brcm,ns2-lcpll-ports + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Northstar 2. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-ns2.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + genpll_scr crystal 0 BCM_NS2_GENPLL_SCR + scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK + fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK + audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK + ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED + ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED + ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED + + genpll_sw crystal 0 BCM_NS2_GENPLL_SW + rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK + 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK + nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK + chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK + port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK + sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK + + lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR + pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK + ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK + ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED + ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED + ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED + ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED + + lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS + wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK + rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK + ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED + ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED + ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED + ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + - if: + properties: + compatible: + contains: + enum: + - brcm,sr-genpll0 + - brcm,sr-genpll1 + - brcm,sr-genpll2 + - brcm,sr-genpll3 + - brcm,sr-genpll4 + - brcm,sr-genpll5 + - brcm,sr-genpll6 + - brcm,sr-lcpll0 + - brcm,sr-lcpll1 + - brcm,sr-lcpll-pcie + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Stingray. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-sr.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + crmu_ref25m crystal N/A N/A + + genpll0 crystal 0 BCM_SR_GENPLL0 + clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK + clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK + clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK + clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK + clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK + clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK + + genpll1 crystal 0 BCM_SR_GENPLL1 + clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK + clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK + + genpll2 crystal 0 BCM_SR_GENPLL2 + clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK + clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK + clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK + clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK + clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK + clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK + + genpll3 crystal 0 BCM_SR_GENPLL3 + clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK + clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK + + genpll4 crystal 0 BCM_SR_GENPLL4 + clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK + clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK + clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK + clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK + clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK + + genpll5 crystal 0 BCM_SR_GENPLL5 + clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK + clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK + clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK + + genpll6 crystal 0 BCM_SR_GENPLL6 + clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK + + lcpll0 crystal 0 BCM_SR_LCPLL0 + clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK + clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK + clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK + clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK + + lcpll1 crystal 0 BCM_SR_LCPLL1 + clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK + clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK + clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK + + lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE + clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK + - if: + properties: + compatible: + contains: + const: brcm,cygnus-genpll + then: + properties: + clock-output-names: + items: + - const: genpll + - const: axi21 + - const: 250mhz + - const: ihost_sys + - const: enet_sw + - const: audio_125 + - const: can + - if: + properties: + compatible: + contains: + const: brcm,nsp-lcpll0 + then: + properties: + clock-output-names: + items: + - const: lcpll0 + - const: pcie_phy + - const: sdio + - const: ddr_phy + - if: + properties: + compatible: + contains: + const: brcm,nsp-genpll + then: + properties: + clock-output-names: + items: + - const: genpll + - const: phy + - const: ethernetclk + - const: usbclk + - const: iprocfast + - const: sata1 + - const: sata2 + +required: + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + osc1: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + genpll@301d000 { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x301d000 0x2c>, <0x301c020 0x4>; + clocks = <&os1c>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; + }; + - | + osc2: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + asiu_clks@301d048 { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x301d048 0xc>, <0x180aa024 0x4>; + clocks = <&osc2>; + clock-output-names = "keypad", "adc/touch", "pwm"; + }; + - | + arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x0 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt b/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt deleted file mode 100644 index 8e5a7d868557..000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,kona-ccu.txt +++ /dev/null @@ -1,138 +0,0 @@ -Broadcom Kona Family Clocks - -This binding is associated with Broadcom SoCs having "Kona" style -clock control units (CCUs). A CCU is a clock provider that manages -a set of clock signals. Each CCU is represented by a node in the -device tree. - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible - Shall have a value of the form "brcm,<model>-<which>-ccu", - where <model> is a Broadcom SoC model number and <which> is - the name of a defined CCU. For example: - "brcm,bcm11351-root-ccu" - The compatible strings used for each supported SoC family - are defined below. -- reg - Shall define the base and range of the address space - containing clock control registers -- #clock-cells - Shall have value <1>. The permitted clock-specifier values - are defined below. -- clock-output-names - Shall be an ordered list of strings defining the names of - the clocks provided by the CCU. - -Device tree example: - - slave_ccu: slave_ccu { - compatible = "brcm,bcm11351-slave-ccu"; - reg = <0x3e011000 0x0f00>; - #clock-cells = <1>; - clock-output-names = "uartb", - "uartb2", - "uartb3", - "uartb4"; - }; - - ref_crystal_clk: ref_crystal { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - uart@3e002000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - reg = <0x3e002000 0x1000>; - clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; - -BCM281XX family ---------------- -CCU compatible string values for SoCs in the BCM281XX family are: - "brcm,bcm11351-root-ccu" - "brcm,bcm11351-aon-ccu" - "brcm,bcm11351-hub-ccu" - "brcm,bcm11351-master-ccu" - "brcm,bcm11351-slave-ccu" - -The following table defines the set of CCUs and clock specifiers for -BCM281XX family clocks. When a clock consumer references a clocks, -its symbolic specifier (rather than its numeric index value) should -be used. These specifiers are defined in: - "include/dt-bindings/clock/bcm281xx.h" - - CCU Clock Type Index Specifier - --- ----- ---- ----- --------- - root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M - - aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER - aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC - aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR - - hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M - - master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1 - master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2 - master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3 - master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4 - master dmac peri 4 BCM281XX_MASTER_CCU_DMAC - master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC - master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M - master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M - - slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB - slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2 - slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3 - slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4 - slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0 - slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2 - slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1 - slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2 - slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3 - slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM - - -BCM21664 family ---------------- -CCU compatible string values for SoCs in the BCM21664 family are: - "brcm,bcm21664-root-ccu" - "brcm,bcm21664-aon-ccu" - "brcm,bcm21664-master-ccu" - "brcm,bcm21664-slave-ccu" - -The following table defines the set of CCUs and clock specifiers for -BCM21664 family clocks. When a clock consumer references a clocks, -its symbolic specifier (rather than its numeric index value) should -be used. These specifiers are defined in: - "include/dt-bindings/clock/bcm21664.h" - - CCU Clock Type Index Specifier - --- ----- ---- ----- --------- - root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M - - aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER - - master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1 - master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2 - master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3 - master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4 - master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP - master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP - master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP - master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP - - slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB - slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2 - slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3 - slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4 - slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1 - slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2 - slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3 - slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4 diff --git a/Documentation/devicetree/bindings/clock/brcm,kona-ccu.yaml b/Documentation/devicetree/bindings/clock/brcm,kona-ccu.yaml new file mode 100644 index 000000000000..e5656950b3bd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,kona-ccu.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Kona family clock control units (CCU) + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +description: | + Broadcom "Kona" style clock control unit (CCU) is a clock provider that + manages a set of clock signals. + + All available clock IDs are defined in + - include/dt-bindings/clock/bcm281xx.h for BCM281XX family + - include/dt-bindings/clock/bcm21664.h for BCM21664 family + +properties: + compatible: + enum: + - brcm,bcm11351-aon-ccu + - brcm,bcm11351-hub-ccu + - brcm,bcm11351-master-ccu + - brcm,bcm11351-root-ccu + - brcm,bcm11351-slave-ccu + - brcm,bcm21664-aon-ccu + - brcm,bcm21664-master-ccu + - brcm,bcm21664-root-ccu + - brcm,bcm21664-slave-ccu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-output-names: + minItems: 1 + maxItems: 10 + +required: + - compatible + - reg + - '#clock-cells' + - clock-output-names + +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm11351-aon-ccu + then: + properties: + clock-output-names: + items: + - const: hub_timer + - const: pmu_bsc + - const: pmu_bsc_var + - if: + properties: + compatible: + contains: + const: brcm,bcm11351-hub-ccu + then: + properties: + clock-output-names: + const: tmon_1m + - if: + properties: + compatible: + contains: + const: brcm,bcm11351-master-ccu + then: + properties: + clock-output-names: + items: + - const: sdio1 + - const: sdio2 + - const: sdio3 + - const: sdio4 + - const: usb_ic + - const: hsic2_48m + - const: hsic2_12m + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm11351-root-ccu + - brcm,bcm21664-root-ccu + then: + properties: + clock-output-names: + const: frac_1m + - if: + properties: + compatible: + contains: + const: brcm,bcm11351-slave-ccu + then: + properties: + clock-output-names: + items: + - const: uartb + - const: uartb2 + - const: uartb3 + - const: uartb4 + - const: ssp0 + - const: ssp2 + - const: bsc1 + - const: bsc2 + - const: bsc3 + - const: pwm + - if: + properties: + compatible: + contains: + const: brcm,bcm21664-aon-ccu + then: + properties: + clock-output-names: + const: hub_timer + - if: + properties: + compatible: + contains: + const: brcm,bcm21664-master-ccu + then: + properties: + clock-output-names: + items: + - const: sdio1 + - const: sdio2 + - const: sdio3 + - const: sdio4 + - const: sdio1_sleep + - const: sdio2_sleep + - const: sdio3_sleep + - const: sdio4_sleep + - if: + properties: + compatible: + contains: + const: brcm,bcm21664-slave-ccu + then: + properties: + clock-output-names: + items: + - const: uartb + - const: uartb2 + - const: uartb3 + - const: bsc1 + - const: bsc2 + - const: bsc3 + - const: bsc4 + +additionalProperties: false + +examples: + - | + clock-controller@3e011000 { + compatible = "brcm,bcm11351-slave-ccu"; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "uartb4", + "ssp0", + "ssp2", + "bsc1", + "bsc2", + "bsc3", + "pwm"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt deleted file mode 100644 index 0a6ac1bdcda1..000000000000 --- a/Documentation/devicetree/bindings/clock/calxeda.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree Clock bindings for Calxeda highbank platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "calxeda,hb-pll-clock" - for a PLL clock - "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the - A9 clock. - "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. - "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. -- reg : shall be the control register offset from SYSREGs base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding; shall be set to 0. diff --git a/Documentation/devicetree/bindings/clock/calxeda.yaml b/Documentation/devicetree/bindings/clock/calxeda.yaml new file mode 100644 index 000000000000..a88fbe20fef1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/calxeda.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/calxeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda highbank platform Clock Controller + +description: | + This binding covers the Calxeda SoC internal peripheral and bus clocks + as used by peripherals. The clocks live inside the "system register" + region of the SoC, so are typically presented as children of an + "hb-sregs" node. + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - calxeda,hb-pll-clock + - calxeda,hb-a9periph-clock + - calxeda,hb-a9bus-clock + - calxeda,hb-emmc-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - clocks + - reg + +additionalProperties: false + +examples: + - | + sregs@3fffc000 { + compatible = "calxeda,hb-sregs"; + reg = <0x3fffc000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + + ddrpll: ddrpll@108 { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x108>; + }; + + a9pll: a9pll@100 { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x100>; + }; + + a9periphclk: a9periphclk@104 { + #clock-cells = <0>; + compatible = "calxeda,hb-a9periph-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml new file mode 100644 index 000000000000..380cb6d80025 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K210 Clock + +maintainers: + - Damien Le Moal <dlemoal@kernel.org> + +description: | + Canaan Kendryte K210 SoC clocks driver bindings. The clock + controller node must be defined as a child node of the K210 + system controller node. + + See also: + - dt-bindings/clock/k210-clk.h + +properties: + compatible: + const: canaan,k210-clk + + clocks: + maxItems: 1 + description: + Phandle of the SoC 26MHz fixed-rate oscillator clock. + + '#clock-cells': + const: 1 + +required: + - compatible + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/k210-clk.h> + clocks { + in0: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + /* ... */ + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "canaan,k210-clk"; + clocks = <&in0>; + }; diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml new file mode 100644 index 000000000000..d416c374e853 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier + +maintainers: + - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + +description: | + The CS2000-CP is an extremely versatile system clocking device that + utilizes a programmable phase lock loop. + + Link: https://www.cirrus.com/products/cs2000/ + +properties: + compatible: + enum: + - cirrus,cs2000-cp + + clocks: + description: + Common clock binding for CLK_IN, XTI/REF_CLK + maxItems: 2 + + clock-names: + items: + - const: clk_in + - const: ref_clk + + '#clock-cells': + const: 0 + + reg: + maxItems: 1 + + cirrus,aux-output-source: + description: + Specifies the function of the auxiliary clock output pin + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input + - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input + - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output + - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status + default: 0 + + cirrus,clock-skip: + description: + This mode allows the PLL to maintain lock even when CLK_IN + has missing pulses for up to 20 ms. + $ref: /schemas/types.yaml#/definitions/flag + + cirrus,dynamic-mode: + description: + In dynamic mode, the CLK_IN input is used to drive the + digital PLL of the silicon. + If not given, the static mode shall be used to derive the + output signal directly from the REF_CLK input. + $ref: /schemas/types.yaml#/definitions/flag + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/cirrus,cs2000-cp.h> + + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&rcar_sound 0>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt b/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt deleted file mode 100644 index 52a064c789ee..000000000000 --- a/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt +++ /dev/null @@ -1,94 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -This binding document describes the binding for the clock portion of -the driver. - -Also see these documents for generic binding information: - [1] Clock : ../clock/clock-bindings.txt - -And these for relevant defines: - [2] include/dt-bindings/clock/lochnagar.h - -This binding must be part of the Lochnagar MFD binding: - [3] ../mfd/cirrus,lochnagar.txt - -Required properties: - - - compatible : One of the following strings: - "cirrus,lochnagar1-clk" - "cirrus,lochnagar2-clk" - - - #clock-cells : Must be 1. The first cell indicates the clock - number, see [2] for available clocks and [1]. - -Optional properties: - - - clocks : Must contain an entry for each clock in clock-names. - - clock-names : May contain entries for each of the following - clocks: - - ln-cdc-clkout : Output clock from CODEC card. - - ln-dsp-clkout : Output clock from DSP card. - - ln-gf-mclk1,ln-gf-mclk2,ln-gf-mclk3,ln-gf-mclk4 : Optional - input audio clocks from host system. - - ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from - external connector. - - ln-spdif-mclk : Optional input audio clock from SPDIF. - - ln-spdif-clkout : Optional input audio clock from SPDIF. - - ln-adat-mclk : Optional input audio clock from ADAT. - - ln-pmic-32k : On board fixed clock. - - ln-clk-12m : On board fixed clock. - - ln-clk-11m : On board fixed clock. - - ln-clk-24m : On board fixed clock. - - ln-clk-22m : On board fixed clock. - - ln-clk-8m : On board fixed clock. - - ln-usb-clk-24m : On board fixed clock. - - ln-usb-clk-12m : On board fixed clock. - - - assigned-clocks : A list of Lochnagar clocks to be reparented, see - [2] for available clocks. - - assigned-clock-parents : Parents to be assigned to the clocks - listed in "assigned-clocks". - -Optional nodes: - - - fixed-clock nodes may be registered for the following on board clocks: - - ln-pmic-32k : 32768 Hz - - ln-clk-12m : 12288000 Hz - - ln-clk-11m : 11298600 Hz - - ln-clk-24m : 24576000 Hz - - ln-clk-22m : 22579200 Hz - - ln-clk-8m : 8192000 Hz - - ln-usb-clk-24m : 24576000 Hz - - ln-usb-clk-12m : 12288000 Hz - -Example: - -lochnagar { - lochnagar-clk { - compatible = "cirrus,lochnagar2-clk"; - - #clock-cells = <1>; - - clocks = <&clk-audio>, <&clk_pmic>; - clock-names = "ln-gf-mclk2", "ln-pmic-32k"; - - assigned-clocks = <&lochnagar-clk LOCHNAGAR_CDC_MCLK1>, - <&lochnagar-clk LOCHNAGAR_CDC_MCLK2>; - assigned-clock-parents = <&clk-audio>, - <&clk-pmic>; - }; - - clk-pmic: clk-pmic { - compatible = "fixed-clock"; - clock-cells = <0>; - clock-frequency = <32768>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/cirrus,lochnagar.yaml b/Documentation/devicetree/bindings/clock/cirrus,lochnagar.yaml new file mode 100644 index 000000000000..59de125647ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cirrus,lochnagar.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of various + application processor systems to provide a full evaluation platform. + Audio system topology, clocking and power can all be controlled through + the Lochnagar, allowing the device under test to be used in a variety of + possible use cases. + + This binding document describes the binding for the clock portion of the + driver. + + Also see these documents for generic binding information: + [1] Clock : ../clock/clock-bindings.txt + + And these for relevant defines: + [2] include/dt-bindings/clock/lochnagar.h + + This binding must be part of the Lochnagar MFD binding: + [3] ../mfd/cirrus,lochnagar.yaml + +properties: + compatible: + enum: + - cirrus,lochnagar1-clk + - cirrus,lochnagar2-clk + + '#clock-cells': + description: + The first cell indicates the clock number, see [2] for available + clocks and [1]. + const: 1 + + clock-names: + items: + enum: + - ln-cdc-clkout # Output clock from CODEC card. + - ln-dsp-clkout # Output clock from DSP card. + - ln-gf-mclk1 # Optional input clock from host system. + - ln-gf-mclk2 # Optional input clock from host system. + - ln-gf-mclk3 # Optional input clock from host system. + - ln-gf-mclk4 # Optional input clock from host system. + - ln-psia1-mclk # Optional input clock from external connector. + - ln-psia2-mclk # Optional input clock from external connector. + - ln-spdif-mclk # Optional input clock from SPDIF. + - ln-spdif-clkout # Optional input clock from SPDIF. + - ln-adat-mclk # Optional input clock from ADAT. + - ln-pmic-32k # On board fixed clock. + - ln-clk-12m # On board fixed clock. + - ln-clk-11m # On board fixed clock. + - ln-clk-24m # On board fixed clock. + - ln-clk-22m # On board fixed clock. + - ln-clk-8m # On board fixed clock. + - ln-usb-clk-24m # On board fixed clock. + - ln-usb-clk-12m # On board fixed clock. + minItems: 1 + maxItems: 19 + + clocks: true + assigned-clocks: true + assigned-clock-parents: true + +additionalProperties: false + +required: + - compatible + - '#clock-cells' diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt deleted file mode 100644 index 6030afb10b5c..000000000000 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Samsung Audio Subsystem Clock Controller - -The Samsung Audio Subsystem clock controller generates and supplies clocks -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock -binding described here is applicable to all SoCs in Exynos family. - -Required Properties: - -- compatible: should be one of the following: - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 - SoCs. - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410 - SoCs. - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 - SoCs. -- reg: physical base address and length of the controller's register set. - -- #clock-cells: should be 1. - -- clocks: - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" - is used if not specified. - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" - is used if not specified. - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not - specified. - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if - not specified. - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not - specified. - -- clock-names: Aliases for the above clocks. They should be "pll_ref", - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. - -Optional Properties: - - - power-domains: a phandle to respective power domain node as described by - generic PM domain bindings (see power/power_domain.txt for more - information). - -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. Some of the clocks are available only on a particular -Exynos4 SoC and this is specified where applicable. - -Provided clocks: - -Clock ID SoC (if specific) ------------------------------------------------ - -mout_audss 0 -mout_i2s 1 -dout_srp 2 -dout_aud_bus 3 -dout_i2s 4 -srp_clk 5 -i2s_bus 6 -sclk_i2s 7 -pcm_bus 8 -sclk_pcm 9 -adma 10 Exynos5420 - -Example 1: An example of a clock controller node using the default input - clock names is listed below. - -clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; -}; - -Example 2: An example of a clock controller node with the input clocks - specified. - -clock_audss: audss-clock-controller@3810000 { - compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; - #clock-cells = <1>; - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, - <&ext_i2s_clk>; - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; -}; - -Example 3: I2S controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - -i2s0: i2s@3830000 { - compatible = "samsung,i2s-v5"; - reg = <0x03830000 0x100>; - dmas = <&pdma0 10 - &pdma0 9 - &pdma0 8>; - dma-names = "tx", "rx", "tx-sec"; - clocks = <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_I2S_BUS>, - <&clock_audss EXYNOS_SCLK_I2S>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1", - "mout_audss", "mout_i2s"; -}; diff --git a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt b/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt deleted file mode 100644 index f6272dcd96f4..000000000000 --- a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Samsung Audio Subsystem Clock Controller - -The Samsung Audio Subsystem clock controller generates and supplies clocks -to Audio Subsystem block available in the S5PV210 and compatible SoCs. - -Required Properties: - -- compatible: should be "samsung,s5pv210-audss-clock". -- reg: physical base address and length of the controller's register set. - -- #clock-cells: should be 1. - -- clocks: - - hclk: AHB bus clock of the Audio Subsystem. - - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If - not specified (i.e. xusbxti is used for PLL reference), it is fixed to - a clock named "xxti". - - fout_epll: Input PLL to the AudioSS block, parent of mout_audss. - - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not - specified, it is fixed to a clock named "iiscdclk0". - - sclk_audio0: Audio bus clock, parent of mout_i2s. - -- clock-names: Aliases for the above clocks. They should be "hclk", - "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device -tree sources. - -Example: Clock controller node. - - clk_audss: clock-controller@c0900000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xc0900000 0x1000>; - #clock-cells = <1>; - clock-names = "hclk", "xxti", - "fout_epll", "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>; - }; - -Example: I2S controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - i2s0: i2s@3830000 { - /* ... */ - clock-names = "iis", "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt index b646bbcf7f92..6fe541368889 100644 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -1,186 +1,2 @@ -This binding is a work-in-progress, and are based on some experimental -work by benh[1]. - -Sources of clock signal can be represented by any node in the device -tree. Those nodes are designated as clock providers. Clock consumer -nodes use a phandle and clock specifier pair to connect clock provider -outputs to clock inputs. Similar to the gpio specifiers, a clock -specifier is an array of zero, one or more cells identifying the clock -output on a device. The length of a clock specifier is defined by the -value of a #clock-cells property in the clock provider node. - -[1] http://patchwork.ozlabs.org/patch/31551/ - -==Clock providers== - -Required properties: -#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes - with a single clock output and 1 for nodes with multiple - clock outputs. - -Optional properties: -clock-output-names: Recommended to be a list of strings of clock output signal - names indexed by the first cell in the clock specifier. - However, the meaning of clock-output-names is domain - specific to the clock provider, and is only provided to - encourage using the same meaning for the majority of clock - providers. This format may not work for clock providers - using a complex clock specifier format. In those cases it - is recommended to omit this property and create a binding - specific names property. - - Clock consumer nodes must never directly reference - the provider's clock-output-names property. - -For example: - - oscillator { - #clock-cells = <1>; - clock-output-names = "ckil", "ckih"; - }; - -- this node defines a device with two clock outputs, the first named - "ckil" and the second named "ckih". Consumer nodes always reference - clocks by index. The names should reflect the clock output signal - names for the device. - -clock-indices: If the identifying number for the clocks in the node - is not linear from zero, then this allows the mapping of - identifiers into the clock-output-names array. - -For example, if we have two clocks <&oscillator 1> and <&oscillator 3>: - - oscillator { - compatible = "myclocktype"; - #clock-cells = <1>; - clock-indices = <1>, <3>; - clock-output-names = "clka", "clkb"; - } - - This ensures we do not have any empty strings in clock-output-names - - -==Clock consumers== - -Required properties: -clocks: List of phandle and clock specifier pairs, one pair - for each clock input to the device. Note: if the - clock provider specifies '0' for #clock-cells, then - only the phandle portion of the pair will appear. - -Optional properties: -clock-names: List of clock input name strings sorted in the same - order as the clocks property. Consumers drivers - will use clock-names to match clock input names - with clocks specifiers. -clock-ranges: Empty property indicating that child nodes can inherit named - clocks from this node. Useful for bus nodes to provide a - clock to their children. - -For example: - - device { - clocks = <&osc 1>, <&ref 0>; - clock-names = "baud", "register"; - }; - - -This represents a device with two clock inputs, named "baud" and "register". -The baud clock is connected to output 1 of the &osc device, and the register -clock is connected to output 0 of the &ref. - -==Example== - - /* external oscillator */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <32678>; - clock-output-names = "osc"; - }; - - /* phase-locked-loop device, generates a higher frequency clock - * from the external oscillator reference */ - pll: pll@4c000 { - compatible = "vendor,some-pll-interface" - #clock-cells = <1>; - clocks = <&osc 0>; - clock-names = "ref"; - reg = <0x4c000 0x1000>; - clock-output-names = "pll", "pll-switched"; - }; - - /* UART, using the low frequency oscillator for the baud clock, - * and the high frequency switched PLL output for register - * clocking */ - uart@a000 { - compatible = "fsl,imx-uart"; - reg = <0xa000 0x1000>; - interrupts = <33>; - clocks = <&osc 0>, <&pll 1>; - clock-names = "baud", "register"; - }; - -This DT fragment defines three devices: an external oscillator to provide a -low-frequency reference clock, a PLL device to generate a higher frequency -clock signal, and a UART. - -* The oscillator is fixed-frequency, and provides one clock output, named "osc". -* The PLL is both a clock provider and a clock consumer. It uses the clock - signal generated by the external oscillator, and provides two output signals - ("pll" and "pll-switched"). -* The UART has its baud clock connected the external oscillator and its - register clock connected to the PLL clock (the "pll-switched" signal) - -==Assigned clock parents and rates== - -Some platforms may require initial configuration of default parent clocks -and clock frequencies. Such a configuration can be specified in a device tree -node through assigned-clocks, assigned-clock-parents and assigned-clock-rates -properties. The assigned-clock-parents property should contain a list of parent -clocks in the form of a phandle and clock specifier pair and the -assigned-clock-rates property should contain a list of frequencies in Hz. Both -these properties should correspond to the clocks listed in the assigned-clocks -property. - -To skip setting parent or rate of a clock its corresponding entry should be -set to 0, or can be omitted if it is not followed by any non-zero entry. - - uart@a000 { - compatible = "fsl,imx-uart"; - reg = <0xa000 0x1000>; - ... - clocks = <&osc 0>, <&pll 1>; - clock-names = "baud", "register"; - - assigned-clocks = <&clkcon 0>, <&pll 2>; - assigned-clock-parents = <&pll 2>; - assigned-clock-rates = <0>, <460800>; - }; - -In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and -the <&pll 2> clock is assigned a frequency value of 460800 Hz. - -Configuring a clock's parent and rate through the device node that consumes -the clock can be done only for clocks that have a single user. Specifying -conflicting parent or rate configuration in multiple consumer nodes for -a shared clock is forbidden. - -Configuration of common clocks, which affect multiple consumer devices can -be similarly specified in the clock provider node. - -==Protected clocks== - -Some platforms or firmwares may not fully expose all the clocks to the OS, such -as in situations where those clks are used by drivers running in ARM secure -execution levels. Such a configuration can be specified in device tree with the -protected-clocks property in the form of a clock specifier list. This property should -only be specified in the node that is providing the clocks being protected: - - clock-controller@a000f000 { - compatible = "vendor,clk95; - reg = <0xa000f000 0x1000> - #clocks-cells = <1>; - ... - protected-clocks = <UART3_CLK>, <SPI5_CLK>; - }; +This file has moved to the clock binding schema: +https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml diff --git a/Documentation/devicetree/bindings/clock/cs2000-cp.txt b/Documentation/devicetree/bindings/clock/cs2000-cp.txt deleted file mode 100644 index 54e6df0bee8a..000000000000 --- a/Documentation/devicetree/bindings/clock/cs2000-cp.txt +++ /dev/null @@ -1,22 +0,0 @@ -CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier - -Required properties: - -- compatible: "cirrus,cs2000-cp" -- reg: The chip select number on the I2C bus -- clocks: common clock binding for CLK_IN, XTI/REF_CLK -- clock-names: CLK_IN : clk_in, XTI/REF_CLK : ref_clk -- #clock-cells: must be <0> - -Example: - -&i2c2 { - ... - cs2000: clk_multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&rcar_sound 0>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt b/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt deleted file mode 100644 index 54d6d1358339..000000000000 --- a/Documentation/devicetree/bindings/clock/csr,atlas7-car.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Clock and reset bindings for CSR atlas7 - -Required properties: -- compatible: Should be "sirf,atlas7-car" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- #reset-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. -The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c - -The reset consumer should specify the desired reset by having the reset -ID in its "reset" phandle cell. -The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c - -Examples: Clock and reset controller node: - -car: clock-controller@18620000 { - compatible = "sirf,atlas7-car"; - reg = <0x18620000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Examples: Consumers using clock or reset: - -timer@10dc0000 { - compatible = "sirf,macro-tick"; - reg = <0x10dc0000 0x1000>; - clocks = <&car 54>; - interrupts = <0 0 0>, - <0 1 0>, - <0 2 0>, - <0 49 0>, - <0 50 0>, - <0 51 0>; -}; - -uart1: uart@18020000 { - cell-index = <1>; - compatible = "sirf,macro-uart"; - reg = <0x18020000 0x1000>; - clocks = <&clks 95>; - interrupts = <0 18 0>; - fifosize = <32>; -}; - -vpp@13110000 { - compatible = "sirf,prima2-vpp"; - reg = <0x13110000 0x10000>; - interrupts = <0 31 0>; - clocks = <&car 85>; - resets = <&car 29>; -}; diff --git a/Documentation/devicetree/bindings/clock/efm32-clock.txt b/Documentation/devicetree/bindings/clock/efm32-clock.txt deleted file mode 100644 index 263d293f6a10..000000000000 --- a/Documentation/devicetree/bindings/clock/efm32-clock.txt +++ /dev/null @@ -1,11 +0,0 @@ -* Clock bindings for Energy Micro efm32 Giant Gecko's Clock Management Unit - -Required properties: -- compatible: Should be "efm32gg,cmu" -- reg: Base address and length of the register set -- interrupts: Interrupt used by the CMU -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock ID in -its "clocks" phandle cell. The header efm32-clk.h contains a list of available -IDs. diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt deleted file mode 100644 index 7441ed519f02..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Samsung Exynos3250 Clock Controller - -The Exynos3250 clock controller generates and supplies clock to various -controllers within the Exynos3250 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. - - "samsung,exynos3250-cmu-dmc" - controller compatible with - Exynos3250 SoC for Dynamic Memory Controller domain. - - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible - with Exynos3250 SOC - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos3250.h header and can be used in device -tree sources. - -Example 1: Examples of clock controller nodes are listed below. - - cmu: clock-controller@10030000 { - compatible = "samsung,exynos3250-cmu"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - - cmu_dmc: clock-controller@105c0000 { - compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105C0000 0x2000>; - #clock-cells = <1>; - }; - - cmu_isp: clock-controller@10048000 { - compatible = "samsung,exynos3250-cmu-isp"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 109 0>; - clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt deleted file mode 100644 index 17bb11365354..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ /dev/null @@ -1,86 +0,0 @@ -* Samsung Exynos4 Clock Controller - -The Exynos4 clock controller generates and supplies clock to various controllers -within the Exynos4 SoC. The clock binding described here is applicable to all -SoC's in the Exynos4 family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. - - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos4.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; - -Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP) -subsystem. Registers for those clocks are located in the ISP power domain. -Because those registers are also located in a different memory region than -the main clock controller, a separate clock controller has to be defined for -handling them. - -Required Properties: - -- compatible: should be "samsung,exynos4412-isp-clock". - -- reg: physical base address of the ISP clock controller and length of memory - mapped region. - -- #clock-cells: should be 1. - -- clocks: list of the clock controller input clock identifiers, - from common clock bindings, should point to CLK_ACLK200 and - CLK_ACLK400_MCUISP clocks from the main clock controller. - -- clock-names: list of the clock controller input clock names, - as described in clock-bindings.txt, should be "aclk200" and - "aclk400_mcuisp". - -- power-domains: a phandle to ISP power domain node as described by - generic PM domain bindings. - -Example 3: The clock controllers bindings for Exynos4412 SoCs. - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt deleted file mode 100644 index aff266a12eeb..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Samsung Exynos5250 Clock Controller - -The Exynos5250 clock controller generates and supplies clock to various -controllers within the Exynos5250 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5250.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt deleted file mode 100644 index c79d31f7f66e..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt +++ /dev/null @@ -1,190 +0,0 @@ -* Samsung Exynos5260 Clock Controller - -Exynos5260 has 13 clock controllers which are instantiated -independently from the device-tree. These clock controllers -generate and supply clocks to various hardware blocks within -the SoC. - -Each clock is assigned an identifier and client nodes can use -this identifier to specify the clock which they consume. All -available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5260-clk.h header and can be used in -device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It -is expected that they are defined using standard clock bindings -with following clock-output-names: - - - "fin_pll" - PLL input clock from XXTI - - "xrtcxti" - input clock from XRTCXTI - - "ioclk_pcm_extclk" - pcm external operation clock - - "ioclk_spdif_extclk" - spdif external operation clock - - "ioclk_i2s_cdclk" - i2s0 codec clock - -Phy clocks: - -There are several clocks which are generated by specific PHYs. -These clocks are fed into the clock controller and then routed to -the hardware blocks. These clocks are defined as fixed clocks in the -driver with following names: - - - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 - - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 - - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 - - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 - - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock - - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock - - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link - - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock - - "phyclk_dptx_phy_clk_div2" - - "phyclk_mipi_dphy_4l_m_rxclkesc0" - - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock - - "phyclk_usbhost20_phy_freeclk" - - "phyclk_usbhost20_phy_clk48mohci" - - "phyclk_usbdrd30_udrd30_pipe_pclk" - - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock - -Required Properties for Clock Controller: - - - compatible: should be one of the following. - 1) "samsung,exynos5260-clock-top" - 2) "samsung,exynos5260-clock-peri" - 3) "samsung,exynos5260-clock-egl" - 4) "samsung,exynos5260-clock-kfc" - 5) "samsung,exynos5260-clock-g2d" - 6) "samsung,exynos5260-clock-mif" - 7) "samsung,exynos5260-clock-mfc" - 8) "samsung,exynos5260-clock-g3d" - 9) "samsung,exynos5260-clock-fsys" - 10) "samsung,exynos5260-clock-aud" - 11) "samsung,exynos5260-clock-isp" - 12) "samsung,exynos5260-clock-gscl" - 13) "samsung,exynos5260-clock-disp" - - - reg: physical base address of the controller and the length of - memory mapped region. - - - #clock-cells: should be 1. - - - clocks: list of clock identifiers which are fed as the input to - the given clock controller. Please refer the next section to find - the input clocks for a given controller. - - - clock-names: list of names of clocks which are fed as the input - to the given clock controller. - -Input clocks for top clock controller: - - fin_pll - - dout_mem_pll - - dout_bus_pll - - dout_media_pll - -Input clocks for peri clock controller: - - fin_pll - - ioclk_pcm_extclk - - ioclk_i2s_cdclk - - ioclk_spdif_extclk - - phyclk_hdmi_phy_ref_cko - - dout_aclk_peri_66 - - dout_sclk_peri_uart0 - - dout_sclk_peri_uart1 - - dout_sclk_peri_uart2 - - dout_sclk_peri_spi0_b - - dout_sclk_peri_spi1_b - - dout_sclk_peri_spi2_b - - dout_aclk_peri_aud - - dout_sclk_peri_spi0_b - -Input clocks for egl clock controller: - - fin_pll - - dout_bus_pll - -Input clocks for kfc clock controller: - - fin_pll - - dout_media_pll - -Input clocks for g2d clock controller: - - fin_pll - - dout_aclk_g2d_333 - -Input clocks for mif clock controller: - - fin_pll - -Input clocks for mfc clock controller: - - fin_pll - - dout_aclk_mfc_333 - -Input clocks for g3d clock controller: - - fin_pll - -Input clocks for fsys clock controller: - - fin_pll - - phyclk_usbhost20_phy_phyclock - - phyclk_usbhost20_phy_freeclk - - phyclk_usbhost20_phy_clk48mohci - - phyclk_usbdrd30_udrd30_pipe_pclk - - phyclk_usbdrd30_udrd30_phyclock - - dout_aclk_fsys_200 - -Input clocks for aud clock controller: - - fin_pll - - fout_aud_pll - - ioclk_i2s_cdclk - - ioclk_pcm_extclk - -Input clocks for isp clock controller: - - fin_pll - - dout_aclk_isp1_266 - - dout_aclk_isp1_400 - - mout_aclk_isp1_266 - -Input clocks for gscl clock controller: - - fin_pll - - dout_aclk_gscl_400 - - dout_aclk_gscl_333 - -Input clocks for disp clock controller: - - fin_pll - - phyclk_dptx_phy_ch3_txd_clk - - phyclk_dptx_phy_ch2_txd_clk - - phyclk_dptx_phy_ch1_txd_clk - - phyclk_dptx_phy_ch0_txd_clk - - phyclk_hdmi_phy_tmds_clko - - phyclk_hdmi_phy_ref_clko - - phyclk_hdmi_phy_pixel_clko - - phyclk_hdmi_link_o_tmds_clkhi - - phyclk_mipi_dphy_4l_m_txbyte_clkhs - - phyclk_dptx_phy_o_ref_clk_24m - - phyclk_dptx_phy_clk_div2 - - phyclk_mipi_dphy_4l_m_rxclkesc0 - - phyclk_hdmi_phy_ref_cko - - ioclk_spdif_extclk - - dout_aclk_peri_aud - - dout_aclk_disp_222 - - dout_sclk_disp_pixel - - dout_aclk_disp_333 - -Example 1: An example of a clock controller node is listed below. - - clock_mfc: clock-controller@11090000 { - compatible = "samsung,exynos5260-clock-mfc"; - clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>; - clock-names = "fin_pll", "dout_aclk_mfc_333"; - reg = <0x11090000 0x10000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the - peri clock controller. Refer to the standard clock bindings for - information about 'clocks' and 'clock-names' property. - - serial@12c00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 146 0>; - clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; - diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt deleted file mode 100644 index 217beb27c30e..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Samsung Exynos5410 Clock Controller - -The Exynos5410 clock controller generates and supplies clock to various -controllers within the Exynos5410 SoC. - -Required Properties: - -- compatible: should be "samsung,exynos5410-clock" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -- clocks: should contain an entry specifying the root clock from external - oscillator supplied through XXTI or XusbXTI pin. This clock should be - defined using standard clock bindings with "fin_pll" clock-output-name. - That clock is being passed internally to the 9 PLLs. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5410.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - fin_pll: xxti { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5410-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - clocks = <&fin_pll>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@12c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt deleted file mode 100644 index 717a7b1531c7..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Samsung Exynos5420 Clock Controller - -The Exynos5420 clock controller generates and supplies clock to various -controllers within the Exynos5420 SoC and for the Exynos5800 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. - - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5420.h header and can be used in device -tree sources. - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt deleted file mode 100644 index 183c327a7d6b..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ /dev/null @@ -1,507 +0,0 @@ -* Samsung Exynos5433 CMU (Clock Management Units) - -The Exynos5433 clock controller generates and supplies clock to various -controllers within the Exynos5433 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP - which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - domains and bus clocks. - - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF - which generates clocks for LLI (Low Latency Interface) IP. - - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF - which generates clocks for DRAM Memory Controller domain. - - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC - which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. - - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS - which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. - - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS - which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. - - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D - which generates clocks for G2D/MDMA IPs. - - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP - which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. - - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD - which generates clocks for Cortex-A5/BUS/AUDIO clocks. - - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" - and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS - which generates global data buses clock and global peripheral buses clock. - - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D - which generates clocks for 3D Graphics Engine IP. - - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL - which generates clocks for GSCALER IPs. - - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO - which generates clocks for Cortex-A53 Quad-core processor. - - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS - which generates clocks for Cortex-A57 Quad-core processor, CoreSight and - L2 cache controller. - - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL - which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. - - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC - which generates clocks for MFC(Multi-Format Codec) IP. - - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC - which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. - - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP - which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 - which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} - IPs. - - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 - which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. - - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM - which generates clocks for SSS (Security SubSystem) and SlimSSS IPs. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -- clocks: list of the clock controller input clock identifiers, - from common clock bindings. Please refer the next section - to find the input clocks for a given controller. - -- clock-names: list of the clock controller input clock names, - as described in clock-bindings.txt. - - Input clocks for top clock controller: - - oscclk - - sclk_mphy_pll - - sclk_mfc_pll - - sclk_bus_pll - - Input clocks for cpif clock controller: - - oscclk - - Input clocks for mif clock controller: - - oscclk - - sclk_mphy_pll - - Input clocks for fsys clock controller: - - oscclk - - sclk_ufs_mphy - - aclk_fsys_200 - - sclk_pcie_100_fsys - - sclk_ufsunipro_fsys - - sclk_mmc2_fsys - - sclk_mmc1_fsys - - sclk_mmc0_fsys - - sclk_usbhost30_fsys - - sclk_usbdrd30_fsys - - Input clocks for g2d clock controller: - - oscclk - - aclk_g2d_266 - - aclk_g2d_400 - - Input clocks for disp clock controller: - - oscclk - - sclk_dsim1_disp - - sclk_dsim0_disp - - sclk_dsd_disp - - sclk_decon_tv_eclk_disp - - sclk_decon_vclk_disp - - sclk_decon_eclk_disp - - sclk_decon_tv_vclk_disp - - aclk_disp_333 - - Input clocks for audio clock controller: - - oscclk - - fout_aud_pll - - Input clocks for bus0 clock controller: - - aclk_bus0_400 - - Input clocks for bus1 clock controller: - - aclk_bus1_400 - - Input clocks for bus2 clock controller: - - oscclk - - aclk_bus2_400 - - Input clocks for g3d clock controller: - - oscclk - - aclk_g3d_400 - - Input clocks for gscl clock controller: - - oscclk - - aclk_gscl_111 - - aclk_gscl_333 - - Input clocks for apollo clock controller: - - oscclk - - sclk_bus_pll_apollo - - Input clocks for atlas clock controller: - - oscclk - - sclk_bus_pll_atlas - - Input clocks for mscl clock controller: - - oscclk - - sclk_jpeg_mscl - - aclk_mscl_400 - - Input clocks for mfc clock controller: - - oscclk - - aclk_mfc_400 - - Input clocks for hevc clock controller: - - oscclk - - aclk_hevc_400 - - Input clocks for isp clock controller: - - oscclk - - aclk_isp_dis_400 - - aclk_isp_400 - - Input clocks for cam0 clock controller: - - oscclk - - aclk_cam0_333 - - aclk_cam0_400 - - aclk_cam0_552 - - Input clocks for cam1 clock controller: - - oscclk - - sclk_isp_uart_cam1 - - sclk_isp_spi1_cam1 - - sclk_isp_spi0_cam1 - - aclk_cam1_333 - - aclk_cam1_400 - - aclk_cam1_552 - - Input clocks for imem clock controller: - - oscclk - - aclk_imem_sssx_266 - - aclk_imem_266 - - aclk_imem_200 - -Optional properties: - - power-domains: a phandle to respective power domain node as described by - generic PM domain bindings (see power/power_domain.txt for more - information). - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5433.h header and can be used in device -tree sources. - -Example 1: Examples of 'oscclk' source clock node are listed below. - - xxti: xxti { - compatible = "fixed-clock"; - clock-output-names = "oscclk"; - #clock-cells = <0>; - }; - -Example 2: Examples of clock controller nodes are listed below. - - cmu_top: clock-controller@10030000 { - compatible = "samsung,exynos5433-cmu-top"; - reg = <0x10030000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; - }; - - cmu_cpif: clock-controller@10fc0000 { - compatible = "samsung,exynos5433-cmu-cpif"; - reg = <0x10fc0000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk"; - clocks = <&xxti>; - }; - - cmu_mif: clock-controller@105b0000 { - compatible = "samsung,exynos5433-cmu-mif"; - reg = <0x105b0000 0x100c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; - }; - - cmu_peric: clock-controller@14c80000 { - compatible = "samsung,exynos5433-cmu-peric"; - reg = <0x14c80000 0x0b08>; - #clock-cells = <1>; - }; - - cmu_peris: clock-controller@10040000 { - compatible = "samsung,exynos5433-cmu-peris"; - reg = <0x10040000 0x0b20>; - #clock-cells = <1>; - }; - - cmu_fsys: clock-controller@156e0000 { - compatible = "samsung,exynos5433-cmu-fsys"; - reg = <0x156e0000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; - }; - - cmu_g2d: clock-controller@12460000 { - compatible = "samsung,exynos5433-cmu-g2d"; - reg = <0x12460000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; - power-domains = <&pd_g2d>; - }; - - cmu_disp: clock-controller@13b90000 { - compatible = "samsung,exynos5433-cmu-disp"; - reg = <0x13b90000 0x0c04>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; - clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; - power-domains = <&pd_disp>; - }; - - cmu_aud: clock-controller@114c0000 { - compatible = "samsung,exynos5433-cmu-aud"; - reg = <0x114c0000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", "fout_aud_pll"; - clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; - power-domains = <&pd_aud>; - }; - - cmu_bus0: clock-controller@13600000 { - compatible = "samsung,exynos5433-cmu-bus0"; - reg = <0x13600000 0x0b04>; - #clock-cells = <1>; - - clock-names = "aclk_bus0_400"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - }; - - cmu_bus1: clock-controller@14800000 { - compatible = "samsung,exynos5433-cmu-bus1"; - reg = <0x14800000 0x0b04>; - #clock-cells = <1>; - - clock-names = "aclk_bus1_400"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - }; - - cmu_bus2: clock-controller@13400000 { - compatible = "samsung,exynos5433-cmu-bus2"; - reg = <0x13400000 0x0b04>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_bus2_400"; - clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; - }; - - cmu_g3d: clock-controller@14aa0000 { - compatible = "samsung,exynos5433-cmu-g3d"; - reg = <0x14aa0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_g3d_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; - power-domains = <&pd_g3d>; - }; - - cmu_gscl: clock-controller@13cf0000 { - compatible = "samsung,exynos5433-cmu-gscl"; - reg = <0x13cf0000 0x0b10>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; - power-domains = <&pd_gscl>; - }; - - cmu_apollo: clock-controller@11900000 { - compatible = "samsung,exynos5433-cmu-apollo"; - reg = <0x11900000 0x1088>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_apollo"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; - }; - - cmu_atlas: clock-controller@11800000 { - compatible = "samsung,exynos5433-cmu-atlas"; - reg = <0x11800000 0x1088>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_atlas"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; - }; - - cmu_mscl: clock-controller@105d0000 { - compatible = "samsung,exynos5433-cmu-mscl"; - reg = <0x105d0000 0x0b10>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; - power-domains = <&pd_mscl>; - }; - - cmu_mfc: clock-controller@15280000 { - compatible = "samsung,exynos5433-cmu-mfc"; - reg = <0x15280000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_mfc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; - power-domains = <&pd_mfc>; - }; - - cmu_hevc: clock-controller@14f80000 { - compatible = "samsung,exynos5433-cmu-hevc"; - reg = <0x14f80000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_hevc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; - power-domains = <&pd_hevc>; - }; - - cmu_isp: clock-controller@146d0000 { - compatible = "samsung,exynos5433-cmu-isp"; - reg = <0x146d0000 0x0b0c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; - power-domains = <&pd_isp>; - }; - - cmu_cam0: clock-controller@120d0000 { - compatible = "samsung,exynos5433-cmu-cam0"; - reg = <0x120d0000 0x0b0c>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; - power-domains = <&pd_cam0>; - }; - - cmu_cam1: clock-controller@145d0000 { - compatible = "samsung,exynos5433-cmu-cam1"; - reg = <0x145d0000 0x0b08>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; - power-domains = <&pd_cam1>; - }; - - cmu_imem: clock-controller@11060000 { - compatible = "samsung,exynos5433-cmu-imem"; - reg = <0x11060000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_imem_sssx_266", - "aclk_imem_266", - "aclk_imem_200"; - clocks = <&xxti>, - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_200>; - }; - -Example 3: UART controller node that consumes the clock generated by the clock - controller. - - serial_0: serial@14c10000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14C10000 0x100>; - interrupts = <0 421 0>; - clocks = <&cmu_peric CLK_PCLK_UART0>, - <&cmu_peric CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus>; - }; diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt deleted file mode 100644 index 6bf1e7493f61..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt +++ /dev/null @@ -1,108 +0,0 @@ -* Samsung Exynos7 Clock Controller - -Exynos7 clock controller has various blocks which are instantiated -independently from the device-tree. These clock controllers -generate and supply clocks to various hardware blocks within -the SoC. - -Each clock is assigned an identifier and client nodes can use -this identifier to specify the clock which they consume. All -available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos7-clk.h header and can be used in -device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It -is expected that they are defined using standard clock bindings -with following clock-output-names: - - - "fin_pll" - PLL input clock from XXTI - -Required Properties for Clock Controller: - - - compatible: clock controllers will use one of the following - compatible strings to indicate the clock controller - functionality. - - - "samsung,exynos7-clock-topc" - - "samsung,exynos7-clock-top0" - - "samsung,exynos7-clock-top1" - - "samsung,exynos7-clock-ccore" - - "samsung,exynos7-clock-peric0" - - "samsung,exynos7-clock-peric1" - - "samsung,exynos7-clock-peris" - - "samsung,exynos7-clock-fsys0" - - "samsung,exynos7-clock-fsys1" - - "samsung,exynos7-clock-mscl" - - "samsung,exynos7-clock-aud" - - - reg: physical base address of the controller and the length of - memory mapped region. - - - #clock-cells: should be 1. - - - clocks: list of clock identifiers which are fed as the input to - the given clock controller. Please refer the next section to - find the input clocks for a given controller. - -- clock-names: list of names of clocks which are fed as the input - to the given clock controller. - -Input clocks for top0 clock controller: - - fin_pll - - dout_sclk_bus0_pll - - dout_sclk_bus1_pll - - dout_sclk_cc_pll - - dout_sclk_mfc_pll - - dout_sclk_aud_pll - -Input clocks for top1 clock controller: - - fin_pll - - dout_sclk_bus0_pll - - dout_sclk_bus1_pll - - dout_sclk_cc_pll - - dout_sclk_mfc_pll - -Input clocks for ccore clock controller: - - fin_pll - - dout_aclk_ccore_133 - -Input clocks for peric0 clock controller: - - fin_pll - - dout_aclk_peric0_66 - - sclk_uart0 - -Input clocks for peric1 clock controller: - - fin_pll - - dout_aclk_peric1_66 - - sclk_uart1 - - sclk_uart2 - - sclk_uart3 - - sclk_spi0 - - sclk_spi1 - - sclk_spi2 - - sclk_spi3 - - sclk_spi4 - - sclk_i2s1 - - sclk_pcm1 - - sclk_spdif - -Input clocks for peris clock controller: - - fin_pll - - dout_aclk_peris_66 - -Input clocks for fsys0 clock controller: - - fin_pll - - dout_aclk_fsys0_200 - - dout_sclk_mmc2 - -Input clocks for fsys1 clock controller: - - fin_pll - - dout_aclk_fsys1_200 - - dout_sclk_mmc0 - - dout_sclk_mmc1 - -Input clocks for aud clock controller: - - fin_pll - - fout_aud_pll diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-clock.yaml index b657ecd0ef1c..b0a4fb8256e2 100644 --- a/Documentation/devicetree/bindings/clock/fixed-clock.yaml +++ b/Documentation/devicetree/bindings/clock/fixed-clock.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/fixed-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Binding for simple fixed-rate clock sources +title: Simple fixed-rate clock sources maintainers: - Michael Turquette <mturquette@baylibre.com> diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml index b567f8092f8c..8f71ab300470 100644 --- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml +++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Binding for simple fixed factor rate clock sources +title: Simple fixed factor rate clock sources maintainers: - Michael Turquette <mturquette@baylibre.com> @@ -13,7 +13,6 @@ maintainers: properties: compatible: enum: - - allwinner,sun4i-a10-pll3-2x-clk - fixed-factor-clock "#clock-cells": @@ -24,9 +23,8 @@ properties: clock-div: description: Fixed divider - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 clock-mult: description: Fixed multiplier diff --git a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt deleted file mode 100644 index c359367fd1a9..000000000000 --- a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for simple memory mapped io fixed-rate clock sources. -The driver reads a clock frequency value from a single 32-bit memory mapped -I/O register and registers it as a fixed rate clock. - -It was designed for test systems, like FPGA, not for complete, finished SoCs. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "fixed-mmio-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- reg : Address and length of the clock value register set. - -Optional properties: -- clock-output-names : From common clock binding. - -Example: -sysclock: sysclock@fd020004 { - #clock-cells = <0>; - compatible = "fixed-mmio-clock"; - reg = <0xfd020004 0x4>; -}; diff --git a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml new file mode 100644 index 000000000000..e22fc272d023 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple memory mapped IO fixed-rate clock sources + +description: + This binding describes a fixed-rate clock for which the frequency can + be read from a single 32-bit memory mapped I/O register. + + It was designed for test systems, like FPGA, not for complete, + finished SoCs. + +maintainers: + - Jan Kotas <jank@cadence.com> + +properties: + compatible: + const: fixed-mmio-clock + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + sysclock: sysclock@fd020004 { + compatible = "fixed-mmio-clock"; + #clock-cells = <0>; + reg = <0xfd020004 0x4>; + clock-output-names = "sysclk"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml new file mode 100644 index 000000000000..1fa390ee7b9b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale FlexSPI clock driver for Layerscape SoCs + +maintainers: + - Michael Walle <michael@walle.cc> + +description: + The Freescale Layerscape SoCs have a special FlexSPI clock which is + derived from the platform PLL. + +properties: + compatible: + enum: + - fsl,ls1028a-flexspi-clk + - fsl,lx2160a-flexspi-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + dcfg { + #address-cells = <1>; + #size-cells = <1>; + + fspi_clk: clock-controller@900 { + compatible = "fsl,ls1028a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&parentclk>; + clock-output-names = "fspi_clk"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml new file mode 100644 index 000000000000..07b9d21719c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 Audio Clock Mux + +maintainers: + - Shengjiu Wang <shengjiu.wang@nxp.com> + +description: | + NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP + used to control Audio related clock on the SoC. + +properties: + compatible: + enum: + - fsl,imx8dxl-acm + - fsl,imx8qm-acm + - fsl,imx8qxp-acm + + reg: + maxItems: 1 + + power-domains: + minItems: 13 + maxItems: 21 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h + for the full list of i.MX8 ACM clock IDs. + + clocks: + minItems: 13 + maxItems: 27 + + clock-names: + minItems: 13 + maxItems: 27 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_ASRC_1 + - description: power domain of IMX_SC_R_ESAI_0 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SAI_4 + - description: power domain of IMX_SC_R_SAI_5 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 18 + maxItems: 18 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: esai0_rx_clk + - const: esai0_rx_hf_clk + - const: esai0_tx_clk + - const: esai0_tx_hf_clk + - const: spdif0_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + - const: sai4_rx_bclk + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_ASRC_1 + - description: power domain of IMX_SC_R_ESAI_0 + - description: power domain of IMX_SC_R_ESAI_1 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SAI_4 + - description: power domain of IMX_SC_R_SAI_5 + - description: power domain of IMX_SC_R_SAI_6 + - description: power domain of IMX_SC_R_SAI_7 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_SPDIF_1 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 27 + maxItems: 27 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: mlb_clk + - const: hdmi_rx_mclk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: esai0_rx_clk + - const: esai0_rx_hf_clk + - const: esai0_tx_clk + - const: esai0_tx_hf_clk + - const: esai1_rx_clk + - const: esai1_rx_hf_clk + - const: esai1_tx_clk + - const: esai1_tx_hf_clk + - const: spdif0_rx + - const: spdif1_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + - const: sai4_rx_bclk + - const: sai5_tx_bclk + - const: sai6_rx_bclk + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8dxl-acm + then: + properties: + power-domains: + items: + - description: power domain of IMX_SC_R_AUDIO_CLK_0 + - description: power domain of IMX_SC_R_AUDIO_CLK_1 + - description: power domain of IMX_SC_R_MCLK_OUT_0 + - description: power domain of IMX_SC_R_MCLK_OUT_1 + - description: power domain of IMX_SC_R_AUDIO_PLL_0 + - description: power domain of IMX_SC_R_AUDIO_PLL_1 + - description: power domain of IMX_SC_R_ASRC_0 + - description: power domain of IMX_SC_R_SAI_0 + - description: power domain of IMX_SC_R_SAI_1 + - description: power domain of IMX_SC_R_SAI_2 + - description: power domain of IMX_SC_R_SAI_3 + - description: power domain of IMX_SC_R_SPDIF_0 + - description: power domain of IMX_SC_R_MQS_0 + + clocks: + minItems: 13 + maxItems: 13 + + clock-names: + items: + - const: aud_rec_clk0_lpcg_clk + - const: aud_rec_clk1_lpcg_clk + - const: aud_pll_div_clk0_lpcg_clk + - const: aud_pll_div_clk1_lpcg_clk + - const: ext_aud_mclk0 + - const: ext_aud_mclk1 + - const: spdif0_rx + - const: sai0_rx_bclk + - const: sai0_tx_bclk + - const: sai1_rx_bclk + - const: sai1_tx_bclk + - const: sai2_rx_bclk + - const: sai3_rx_bclk + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + clock-controller@59e00000 { + compatible = "fsl,imx8qxp-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk"; + }; diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml new file mode 100644 index 000000000000..bbd22e95b319 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx8m-anatop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Family Anatop Module + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: | + NXP i.MX8M Family anatop PLL module which generates PLL to CCM root. + +properties: + compatible: + oneOf: + - enum: + - fsl,imx8mm-anatop + - fsl,imx8mq-anatop + - items: + - enum: + - fsl,imx8mn-anatop + - fsl,imx8mp-anatop + - const: fsl,imx8mm-anatop + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; + reg = <0x30360000 0x10000>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/fsl,imx93-anatop.yaml b/Documentation/devicetree/bindings/clock/fsl,imx93-anatop.yaml new file mode 100644 index 000000000000..8a3b2476419a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx93-anatop.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx93-anatop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX93 ANATOP Clock Module + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: | + NXP i.MX93 ANATOP module which contains PLL and OSC to Clock Controller + Module. + +properties: + compatible: + items: + - const: fsl,imx93-anatop + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@44480000 { + compatible = "fsl,imx93-anatop"; + reg = <0x44480000 0x2000>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml new file mode 100644 index 000000000000..88dd9c18db92 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock + +maintainers: + - Wen He <wen.he_1@nxp.com> + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + fsl,vco-hz: + description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency + of this PLL cannot be changed during runtime only at startup. Therefore, + the output frequencies are very limited and might not even closely match + the requested frequency. To work around this restriction the user may specify + its own desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0xf1f0000 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml new file mode 100644 index 000000000000..3bca9d11c148 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SAI bitclock-as-a-clock + +maintainers: + - Michael Walle <michael@walle.cc> + +description: | + It is possible to use the BCLK pin of a SAI module as a generic clock + output. Some SoC are very constrained in their pin multiplexer + configuration. Eg. pins can only be changed groups. For example, on the + LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, + the second pins are wasted. Using this binding it is possible to use the + clock of the second SAI as a MCLK clock for an audio codec, for example. + + This is a composite of a gated clock and a divider clock. + +properties: + compatible: + const: fsl,vf610-sai-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mclk: clock-mclk@f130080 { + compatible = "fsl,vf610-sai-clock"; + reg = <0x0 0xf130080 0x0 0x80>; + #clock-cells = <0>; + clocks = <&parentclk>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml b/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml new file mode 100644 index 000000000000..36d4cfc3c2f8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol + +maintainers: + - Abel Vesa <abel.vesa@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + This binding uses the common clock binding. + (Documentation/devicetree/bindings/clock/clock-bindings.txt) + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See the full list of clock IDs from + include/dt-bindings/clock/imx8qxp-clock.h + +properties: + compatible: + items: + - enum: + - fsl,imx8dxl-clk + - fsl,imx8qm-clk + - fsl,imx8qxp-clk + - const: fsl,scu-clk + + '#clock-cells': + const: 2 + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml new file mode 100644 index 000000000000..3eebc03a309b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 SoC clock controller + +maintainers: + - Peter Griffin <peter.griffin@linaro.org> + +description: | + Google GS101 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that clock tree + is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate + clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/gs101.h' header. + +properties: + compatible: + enum: + - google,gs101-cmu-top + - google,gs101-cmu-apm + - google,gs101-cmu-misc + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-top + - google,gs101-cmu-apm + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-misc + + then: + properties: + clocks: + items: + - description: Misc bus clock (from CMU_TOP) + - description: Misc sss clock (from CMU_TOP) + + clock-names: + items: + - const: dout_cmu_misc_bus + - const: dout_cmu_misc_sss + +additionalProperties: false + +examples: + # Clock controller node for CMU_TOP + - | + #include <dt-bindings/clock/google,gs101.h> + + cmu_top: clock-controller@1e080000 { + compatible = "google,gs101-cmu-top"; + reg = <0x1e080000 0x8000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>; + clock-names = "oscclk"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt deleted file mode 100644 index d3379ff9b84b..000000000000 --- a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt +++ /dev/null @@ -1,21 +0,0 @@ -Binding for simple gpio gated clock. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "gpio-gate-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- enable-gpios : GPIO reference for enabling and disabling the clock. - -Optional properties: -- clocks: Maximum of one parent clock is supported. - -Example: - clock { - compatible = "gpio-gate-clock"; - clocks = <&parentclk>; - #clock-cells = <0>; - enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml new file mode 100644 index 000000000000..d09d0e3f0c6e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple GPIO clock gate + +maintainers: + - Jyri Sarha <jsarha@ti.com> + +properties: + compatible: + const: gpio-gate-clock + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + enable-gpios: + description: GPIO reference for enabling and disabling the clock. + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - enable-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + clock { + compatible = "gpio-gate-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt b/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt deleted file mode 100644 index 2be1e038ca62..000000000000 --- a/Documentation/devicetree/bindings/clock/gpio-mux-clock.txt +++ /dev/null @@ -1,19 +0,0 @@ -Binding for simple gpio clock multiplexer. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "gpio-mux-clock". -- clocks: list of two references to parent clocks. -- #clock-cells : from common clock binding; shall be set to 0. -- select-gpios : GPIO reference for selecting the parent clock. - -Example: - clock { - compatible = "gpio-mux-clock"; - clocks = <&parentclk1>, <&parentclk2>; - #clock-cells = <0>; - select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml new file mode 100644 index 000000000000..1e21f8b3a4ff --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gpio-mux-clock.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple GPIO clock multiplexer + +maintainers: + - Sergej Sawazki <ce3a@gmx.de> + +properties: + compatible: + const: gpio-mux-clock + + clocks: + items: + - description: First parent clock + - description: Second parent clock + + '#clock-cells': + const: 0 + + select-gpios: + description: GPIO reference for selecting the parent clock. + maxItems: 1 + +required: + - compatible + - clocks + - '#clock-cells' + - select-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + clock { + compatible = "gpio-mux-clock"; + clocks = <&parentclk1>, <&parentclk2>; + #clock-cells = <0>; + select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/clock/hi3620-clock.txt b/Documentation/devicetree/bindings/clock/hi3620-clock.txt deleted file mode 100644 index dad6269f52c5..000000000000 --- a/Documentation/devicetree/bindings/clock/hi3620-clock.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Hisilicon Hi3620 Clock Controller - -The Hi3620 clock controller generates and supplies clock to various -controllers within the Hi3620 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC. - - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>. diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt index ef3deb7b86ea..17ac4a3dd26a 100644 --- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt +++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt @@ -4,7 +4,7 @@ Clock control registers reside in different Hi6220 system controllers, please refer the following document to know more about the binding rules for these system controllers: -Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml Required Properties: diff --git a/Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml b/Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml new file mode 100644 index 000000000000..3ceb29cec704 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hisilicon,hi3559av100-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon SOC Clock for HI3559AV100 + +maintainers: + - Dongjiu Geng <gengdongjiu@huawei.com> + +description: | + Hisilicon SOC clock control module which supports the clocks, resets and + power domains on HI3559AV100. + + See also: + dt-bindings/clock/hi3559av100-clock.h + +properties: + compatible: + enum: + - hisilicon,hi3559av100-clock + - hisilicon,hi3559av100-shub-clock + + reg: + minItems: 1 + maxItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 2 + description: | + First cell is reset request register offset. + Second cell is bit offset in reset request register. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@12010000 { + compatible = "hisilicon,hi3559av100-clock"; + #clock-cells = <1>; + #reset-cells = <2>; + reg = <0x0 0x12010000 0x0 0x10000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt deleted file mode 100644 index 4733e58e491b..000000000000 --- a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Hisilicon Hix5hd2 Clock Controller - -The hix5hd2 clock controller generates and supplies clock to various -controllers within the hix5hd2 SoC. - -Required Properties: - -- compatible: should be "hisilicon,hix5hd2-clock" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>. - -Examples: - clock: clock@f8a22000 { - compatible = "hisilicon,hix5hd2-clock"; - reg = <0xf8a22000 0x1000>; - #clock-cells = <1>; - }; - - uart0: uart@f8b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xf8b00000 0x1000>; - interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; - }; diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt deleted file mode 100644 index 05a245c9df08..000000000000 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt +++ /dev/null @@ -1,91 +0,0 @@ -Binding for IDT VersaClock 5,6 programmable i2c clock generators. - -The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock -generators providing from 3 to 12 output clocks. - -==I2C device node== - -Required properties: -- compatible: shall be one of - "idt,5p49v5923" - "idt,5p49v5925" - "idt,5p49v5933" - "idt,5p49v5935" - "idt,5p49v6901" -- reg: i2c device address, shall be 0x68 or 0x6a. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock handles, - - 5p49v5923 and - 5p49v5925 and - 5p49v6901: (required) either or both of XTAL or CLKIN - reference clock. - - 5p49v5933 and - - 5p49v5935: (optional) property not present (internal - Xtal used) or CLKIN reference - clock. -- clock-names: from common clock binding; clock input names, can be - - 5p49v5923 and - 5p49v5925 and - 5p49v6901: (required) either or both of "xin", "clkin". - - 5p49v5933 and - - 5p49v5935: (optional) property not present or "clkin". - -==Mapping between clock specifier and physical pins== - -When referencing the provided clock in the DT using phandle and -clock specifier, the following mapping applies: - -5P49V5923: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT2 - -5P49V5933: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT4 - -5P49V5925 and -5P49V5935: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT2 - 3 -- OUT3 - 4 -- OUT4 - -5P49V6901: - 0 -- OUT0_SEL_I2CB - 1 -- OUT1 - 2 -- OUT2 - 3 -- OUT3 - 4 -- OUT4 - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* IDT 5P49V5923 i2c clock generator */ - vc5: clock-generator@6a { - compatible = "idt,5p49v5923"; - reg = <0x6a>; - #clock-cells = <1>; - - /* Connect XIN input to 25MHz reference */ - clocks = <&ref25m>; - clock-names = "xin"; - }; -}; - -/* Consumer referencing the 5P49V5923 pin OUT1 */ -consumer { - ... - clocks = <&vc5 1>; - ... -} diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml new file mode 100644 index 000000000000..a2c6eea9871d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IDT VersaClock 5 and 6 programmable I2C clock generators + +description: | + The IDT VersaClock 5 and VersaClock 6 are programmable I2C + clock generators providing from 3 to 12 output clocks. + + When referencing the provided clock in the DT using phandle and clock + specifier, the following mapping applies: + + - 5P49V5923: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT2 + + - 5P49V5933: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT4 + + - other parts: + 0 -- OUT0_SEL_I2CB + 1 -- OUT1 + 2 -- OUT2 + 3 -- OUT3 + 4 -- OUT4 + + The idt,shutdown and idt,output-enable-active properties control the + SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown + Register, respectively. Their behavior is summarized by the following + table: + + SH SP Output when the SD/OE pin is Low/High + == == ===================================== + 0 0 Active/Inactive + 0 1 Inactive/Active + 1 0 Active/Shutdown + 1 1 Inactive/Shutdown + + The case where SH and SP are both 1 is likely not very interesting. + +maintainers: + - Luca Ceresoli <luca.ceresoli@bootlin.com> + +properties: + compatible: + enum: + - idt,5p49v5923 + - idt,5p49v5925 + - idt,5p49v5933 + - idt,5p49v5935 + - idt,5p49v60 + - idt,5p49v6901 + - idt,5p49v6965 + - idt,5p49v6975 + + reg: + description: I2C device address + enum: [ 0x68, 0x6a ] + + '#clock-cells': + const: 1 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: [ xin, clkin ] + clocks: + minItems: 1 + maxItems: 2 + + idt,xtal-load-femtofarads: + minimum: 9000 + maximum: 22760 + description: Optional load capacitor for XTAL1 and XTAL2 + + idt,shutdown: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + If 1, this enables the shutdown functionality: the chip will be + shut down if the SD/OE pin is driven high. If 0, this disables the + shutdown functionality: the chip will never be shut down based on + the value of the SD/OE pin. This property corresponds to the SH + bit of the Primary Source and Shutdown Register. + + idt,output-enable-active: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + If 1, this enables output when the SD/OE pin is high, and disables + output when the SD/OE pin is low. If 0, this disables output when + the SD/OE pin is high, and enables output when the SD/OE pin is + low. This corresponds to the SP bit of the Primary Source and + Shutdown Register. + +patternProperties: + "^OUT[1-4]$": + type: object + description: + Description of one of the outputs (OUT1..OUT4). See "Clock1 Output + Configuration" in the Versaclock 5/6/6E Family Register Description + and Programming Guide. + properties: + idt,mode: + description: + The output drive mode. Values defined in dt-bindings/clock/versaclock.h + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + idt,voltage-microvolt: + description: The output drive voltage. + enum: [ 1800000, 2500000, 3300000 ] + idt,slew-percent: + description: The Slew rate control for CMOS single-ended. + enum: [ 80, 85, 90, 100 ] + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - idt,shutdown + - idt,output-enable-active + +allOf: + - if: + properties: + compatible: + enum: + - idt,5p49v5933 + - idt,5p49v5935 + - idt,5p49v6975 + then: + # Devices with builtin crystal + optional external input + properties: + clock-names: + const: clkin + clocks: + maxItems: 1 + else: + # Devices without builtin crystal + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/versaclock.h> + + /* 25MHz reference crystal */ + ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + /* IDT 5P49V5923 I2C clock generator */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + + /* Connect XIN input to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "xin"; + + /* Set the SD/OE pin's settings */ + idt,shutdown = <0>; + idt,output-enable-active = <0>; + + OUT1 { + idt,mode = <VC5_CMOSD>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <80>; + }; + + OUT4 { + idt,mode = <VC5_LVDS>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.txt b/Documentation/devicetree/bindings/clock/imx1-clock.txt deleted file mode 100644 index 9823baf7acb6..000000000000 --- a/Documentation/devicetree/bindings/clock/imx1-clock.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Clock bindings for Freescale i.MX1 CPUs - -Required properties: -- compatible: Should be "fsl,imx1-ccm". -- reg: Address and length of the register set. -- #clock-cells: Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h -for the full list of i.MX1 clock IDs. - -Examples: - clks: ccm@21b000 { - #clock-cells = <1>; - compatible = "fsl,imx1-ccm"; - reg = <0x0021b000 0x1000>; - }; - - pwm: pwm@208000 { - #pwm-cells = <2>; - compatible = "fsl,imx1-pwm"; - reg = <0x00208000 0x1000>; - interrupts = <34>; - clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.yaml b/Documentation/devicetree/bindings/clock/imx1-clock.yaml new file mode 100644 index 000000000000..7ade4c32aff3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx1-clock.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx1-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX1 CPUs Clock Controller + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h + for the full list of i.MX1 clock IDs. + +properties: + compatible: + const: fsl,imx1-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx1-clock.h> + + clock-controller@21b000 { + #clock-cells = <1>; + compatible = "fsl,imx1-ccm"; + reg = <0x0021b000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx21-clock.txt b/Documentation/devicetree/bindings/clock/imx21-clock.txt deleted file mode 100644 index 806f63d628bd..000000000000 --- a/Documentation/devicetree/bindings/clock/imx21-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Clock bindings for Freescale i.MX21 - -Required properties: -- compatible : Should be "fsl,imx21-ccm". -- reg : Address and length of the register set. -- interrupts : Should contain CCM interrupt. -- #clock-cells: Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h -for the full list of i.MX21 clock IDs. - -Examples: - clks: ccm@10027000{ - compatible = "fsl,imx21-ccm"; - reg = <0x10027000 0x800>; - #clock-cells = <1>; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, - <&clks IMX21_CLK_PER1>; - clock-names = "ipg", "per"; - }; diff --git a/Documentation/devicetree/bindings/clock/imx21-clock.yaml b/Documentation/devicetree/bindings/clock/imx21-clock.yaml new file mode 100644 index 000000000000..79cc843703ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx21-clock.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx21-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX21 Clock Controller + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h + for the full list of i.MX21 clock IDs. + +properties: + compatible: + const: fsl,imx21-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx21-clock.h> + + clock-controller@10027000 { + compatible = "fsl,imx21-ccm"; + reg = <0x10027000 0x800>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt deleted file mode 100644 index 8385348d3bd9..000000000000 --- a/Documentation/devicetree/bindings/clock/imx23-clock.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Clock bindings for Freescale i.MX23 - -Required properties: -- compatible: Should be "fsl,imx23-clkctrl" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX23 -clocks and IDs. - - Clock ID - ------------------ - ref_xtal 0 - pll 1 - ref_cpu 2 - ref_emi 3 - ref_pix 4 - ref_io 5 - saif_sel 6 - lcdif_sel 7 - gpmi_sel 8 - ssp_sel 9 - emi_sel 10 - cpu 11 - etm_sel 12 - cpu_pll 13 - cpu_xtal 14 - hbus 15 - xbus 16 - lcdif_div 17 - ssp_div 18 - gpmi_div 19 - emi_pll 20 - emi_xtal 21 - etm_div 22 - saif_div 23 - clk32k_div 24 - rtc 25 - adc 26 - spdif_div 27 - clk32k 28 - dri 29 - pwm 30 - filt 31 - uart 32 - ssp 33 - gpmi 34 - spdif 35 - emi 36 - saif 37 - lcdif 38 - etm 39 - usb 40 - usb_phy 41 - -Examples: - -clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; -}; - -auart0: serial@8006c000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <24 25 23>; - clocks = <&clks 32>; -}; diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.yaml b/Documentation/devicetree/bindings/clock/imx23-clock.yaml new file mode 100644 index 000000000000..5e71c9219500 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx23-clock.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx23-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX23 Clock Controller + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX23 + clocks and IDs. + + Clock ID + ------------------ + ref_xtal 0 + pll 1 + ref_cpu 2 + ref_emi 3 + ref_pix 4 + ref_io 5 + saif_sel 6 + lcdif_sel 7 + gpmi_sel 8 + ssp_sel 9 + emi_sel 10 + cpu 11 + etm_sel 12 + cpu_pll 13 + cpu_xtal 14 + hbus 15 + xbus 16 + lcdif_div 17 + ssp_div 18 + gpmi_div 19 + emi_pll 20 + emi_xtal 21 + etm_div 22 + saif_div 23 + clk32k_div 24 + rtc 25 + adc 26 + spdif_div 27 + clk32k 28 + dri 29 + pwm 30 + filt 31 + uart 32 + ssp 33 + gpmi 34 + spdif 35 + emi 36 + saif 37 + lcdif 38 + etm 39 + usb 40 + usb_phy 41 + +properties: + compatible: + const: fsl,imx23-clkctrl + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@80040000 { + compatible = "fsl,imx23-clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt deleted file mode 100644 index f8135ea9ca4e..000000000000 --- a/Documentation/devicetree/bindings/clock/imx25-clock.txt +++ /dev/null @@ -1,160 +0,0 @@ -* Clock bindings for Freescale i.MX25 - -Required properties: -- compatible: Should be "fsl,imx25-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX25 -clocks and IDs. - - Clock ID - --------------------------- - dummy 0 - osc 1 - mpll 2 - upll 3 - mpll_cpu_3_4 4 - cpu_sel 5 - cpu 6 - ahb 7 - usb_div 8 - ipg 9 - per0_sel 10 - per1_sel 11 - per2_sel 12 - per3_sel 13 - per4_sel 14 - per5_sel 15 - per6_sel 16 - per7_sel 17 - per8_sel 18 - per9_sel 19 - per10_sel 20 - per11_sel 21 - per12_sel 22 - per13_sel 23 - per14_sel 24 - per15_sel 25 - per0 26 - per1 27 - per2 28 - per3 29 - per4 30 - per5 31 - per6 32 - per7 33 - per8 34 - per9 35 - per10 36 - per11 37 - per12 38 - per13 39 - per14 40 - per15 41 - csi_ipg_per 42 - epit_ipg_per 43 - esai_ipg_per 44 - esdhc1_ipg_per 45 - esdhc2_ipg_per 46 - gpt_ipg_per 47 - i2c_ipg_per 48 - lcdc_ipg_per 49 - nfc_ipg_per 50 - owire_ipg_per 51 - pwm_ipg_per 52 - sim1_ipg_per 53 - sim2_ipg_per 54 - ssi1_ipg_per 55 - ssi2_ipg_per 56 - uart_ipg_per 57 - ata_ahb 58 - reserved 59 - csi_ahb 60 - emi_ahb 61 - esai_ahb 62 - esdhc1_ahb 63 - esdhc2_ahb 64 - fec_ahb 65 - lcdc_ahb 66 - rtic_ahb 67 - sdma_ahb 68 - slcdc_ahb 69 - usbotg_ahb 70 - reserved 71 - reserved 72 - reserved 73 - reserved 74 - can1_ipg 75 - can2_ipg 76 - csi_ipg 77 - cspi1_ipg 78 - cspi2_ipg 79 - cspi3_ipg 80 - dryice_ipg 81 - ect_ipg 82 - epit1_ipg 83 - epit2_ipg 84 - reserved 85 - esdhc1_ipg 86 - esdhc2_ipg 87 - fec_ipg 88 - reserved 89 - reserved 90 - reserved 91 - gpt1_ipg 92 - gpt2_ipg 93 - gpt3_ipg 94 - gpt4_ipg 95 - reserved 96 - reserved 97 - reserved 98 - iim_ipg 99 - reserved 100 - reserved 101 - kpp_ipg 102 - lcdc_ipg 103 - reserved 104 - pwm1_ipg 105 - pwm2_ipg 106 - pwm3_ipg 107 - pwm4_ipg 108 - rngb_ipg 109 - reserved 110 - scc_ipg 111 - sdma_ipg 112 - sim1_ipg 113 - sim2_ipg 114 - slcdc_ipg 115 - spba_ipg 116 - ssi1_ipg 117 - ssi2_ipg 118 - tsc_ipg 119 - uart1_ipg 120 - uart2_ipg 121 - uart3_ipg 122 - uart4_ipg 123 - uart5_ipg 124 - reserved 125 - wdt_ipg 126 - cko_div 127 - cko_sel 128 - cko 129 - -Examples: - -clks: ccm@53f80000 { - compatible = "fsl,imx25-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; -}; - -uart1: serial@43f90000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 79>, <&clks 50>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.yaml b/Documentation/devicetree/bindings/clock/imx25-clock.yaml new file mode 100644 index 000000000000..c626a158590e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx25-clock.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx25-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX25 Clock Controller + +maintainers: + - Sascha Hauer <s.hauer@pengutronix.de> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX25 + clocks and IDs. + + Clock ID + -------------------------- + dummy 0 + osc 1 + mpll 2 + upll 3 + mpll_cpu_3_4 4 + cpu_sel 5 + cpu 6 + ahb 7 + usb_div 8 + ipg 9 + per0_sel 10 + per1_sel 11 + per2_sel 12 + per3_sel 13 + per4_sel 14 + per5_sel 15 + per6_sel 16 + per7_sel 17 + per8_sel 18 + per9_sel 19 + per10_sel 20 + per11_sel 21 + per12_sel 22 + per13_sel 23 + per14_sel 24 + per15_sel 25 + per0 26 + per1 27 + per2 28 + per3 29 + per4 30 + per5 31 + per6 32 + per7 33 + per8 34 + per9 35 + per10 36 + per11 37 + per12 38 + per13 39 + per14 40 + per15 41 + csi_ipg_per 42 + epit_ipg_per 43 + esai_ipg_per 44 + esdhc1_ipg_per 45 + esdhc2_ipg_per 46 + gpt_ipg_per 47 + i2c_ipg_per 48 + lcdc_ipg_per 49 + nfc_ipg_per 50 + owire_ipg_per 51 + pwm_ipg_per 52 + sim1_ipg_per 53 + sim2_ipg_per 54 + ssi1_ipg_per 55 + ssi2_ipg_per 56 + uart_ipg_per 57 + ata_ahb 58 + reserved 59 + csi_ahb 60 + emi_ahb 61 + esai_ahb 62 + esdhc1_ahb 63 + esdhc2_ahb 64 + fec_ahb 65 + lcdc_ahb 66 + rtic_ahb 67 + sdma_ahb 68 + slcdc_ahb 69 + usbotg_ahb 70 + reserved 71 + reserved 72 + reserved 73 + reserved 74 + can1_ipg 75 + can2_ipg 76 + csi_ipg 77 + cspi1_ipg 78 + cspi2_ipg 79 + cspi3_ipg 80 + dryice_ipg 81 + ect_ipg 82 + epit1_ipg 83 + epit2_ipg 84 + reserved 85 + esdhc1_ipg 86 + esdhc2_ipg 87 + fec_ipg 88 + reserved 89 + reserved 90 + reserved 91 + gpt1_ipg 92 + gpt2_ipg 93 + gpt3_ipg 94 + gpt4_ipg 95 + reserved 96 + reserved 97 + reserved 98 + iim_ipg 99 + reserved 100 + reserved 101 + kpp_ipg 102 + lcdc_ipg 103 + reserved 104 + pwm1_ipg 105 + pwm2_ipg 106 + pwm3_ipg 107 + pwm4_ipg 108 + rngb_ipg 109 + reserved 110 + scc_ipg 111 + sdma_ipg 112 + sim1_ipg 113 + sim2_ipg 114 + slcdc_ipg 115 + spba_ipg 116 + ssi1_ipg 117 + ssi2_ipg 118 + tsc_ipg 119 + uart1_ipg 120 + uart2_ipg 121 + uart3_ipg 122 + uart4_ipg 123 + uart5_ipg 124 + reserved 125 + wdt_ipg 126 + cko_div 127 + cko_sel 128 + cko 129 + +properties: + compatible: + const: fsl,imx25-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@53f80000 { + compatible = "fsl,imx25-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt deleted file mode 100644 index 4c95c048d3b2..000000000000 --- a/Documentation/devicetree/bindings/clock/imx27-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Clock bindings for Freescale i.MX27 - -Required properties: -- compatible: Should be "fsl,imx27-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h -for the full list of i.MX27 clock IDs. - -Examples: - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.yaml b/Documentation/devicetree/bindings/clock/imx27-clock.yaml new file mode 100644 index 000000000000..71d78a0b551f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx27-clock.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx27-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX27 Clock Controller + +maintainers: + - Fabio Estevam <festevam@gmail.com> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h + for the full list of i.MX27 clock IDs. + +properties: + compatible: + const: fsl,imx27-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx27-clock.h> + + clock-controller@10027000 { + compatible = "fsl,imx27-ccm"; + reg = <0x10027000 0x1000>; + interrupts = <31>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt deleted file mode 100644 index d84a37d2885f..000000000000 --- a/Documentation/devicetree/bindings/clock/imx28-clock.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Clock bindings for Freescale i.MX28 - -Required properties: -- compatible: Should be "fsl,imx28-clkctrl" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX28 -clocks and IDs. - - Clock ID - ------------------ - ref_xtal 0 - pll0 1 - pll1 2 - pll2 3 - ref_cpu 4 - ref_emi 5 - ref_io0 6 - ref_io1 7 - ref_pix 8 - ref_hsadc 9 - ref_gpmi 10 - saif0_sel 11 - saif1_sel 12 - gpmi_sel 13 - ssp0_sel 14 - ssp1_sel 15 - ssp2_sel 16 - ssp3_sel 17 - emi_sel 18 - etm_sel 19 - lcdif_sel 20 - cpu 21 - ptp_sel 22 - cpu_pll 23 - cpu_xtal 24 - hbus 25 - xbus 26 - ssp0_div 27 - ssp1_div 28 - ssp2_div 29 - ssp3_div 30 - gpmi_div 31 - emi_pll 32 - emi_xtal 33 - lcdif_div 34 - etm_div 35 - ptp 36 - saif0_div 37 - saif1_div 38 - clk32k_div 39 - rtc 40 - lradc 41 - spdif_div 42 - clk32k 43 - pwm 44 - uart 45 - ssp0 46 - ssp1 47 - ssp2 48 - ssp3 49 - gpmi 50 - spdif 51 - emi 52 - saif0 53 - saif1 54 - lcdif 55 - etm 56 - fec 57 - can0 58 - can1 59 - usb0 60 - usb1 61 - usb0_phy 62 - usb1_phy 63 - enet_out 64 - -Examples: - -clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; -}; - -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; - clocks = <&clks 45>; -}; diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.yaml b/Documentation/devicetree/bindings/clock/imx28-clock.yaml new file mode 100644 index 000000000000..4aaad7b9c66e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx28-clock.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx28-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX28 Clock Controller + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX28 + clocks and IDs. + + Clock ID + ------------------ + ref_xtal 0 + pll0 1 + pll1 2 + pll2 3 + ref_cpu 4 + ref_emi 5 + ref_io0 6 + ref_io1 7 + ref_pix 8 + ref_hsadc 9 + ref_gpmi 10 + saif0_sel 11 + saif1_sel 12 + gpmi_sel 13 + ssp0_sel 14 + ssp1_sel 15 + ssp2_sel 16 + ssp3_sel 17 + emi_sel 18 + etm_sel 19 + lcdif_sel 20 + cpu 21 + ptp_sel 22 + cpu_pll 23 + cpu_xtal 24 + hbus 25 + xbus 26 + ssp0_div 27 + ssp1_div 28 + ssp2_div 29 + ssp3_div 30 + gpmi_div 31 + emi_pll 32 + emi_xtal 33 + lcdif_div 34 + etm_div 35 + ptp 36 + saif0_div 37 + saif1_div 38 + clk32k_div 39 + rtc 40 + lradc 41 + spdif_div 42 + clk32k 43 + pwm 44 + uart 45 + ssp0 46 + ssp1 47 + ssp2 48 + ssp3 49 + gpmi 50 + spdif 51 + emi 52 + saif0 53 + saif1 54 + lcdif 55 + etm 56 + fec 57 + can0 58 + can1 59 + usb0 60 + usb1 61 + usb0_phy 62 + usb1_phy 63 + enet_out 64 + +properties: + compatible: + const: fsl,imx28-clkctrl + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@80040000 { + compatible = "fsl,imx28-clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx31-clock.txt b/Documentation/devicetree/bindings/clock/imx31-clock.txt deleted file mode 100644 index 0a291090e562..000000000000 --- a/Documentation/devicetree/bindings/clock/imx31-clock.txt +++ /dev/null @@ -1,90 +0,0 @@ -* Clock bindings for Freescale i.MX31 - -Required properties: -- compatible: Should be "fsl,imx31-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX31 -clocks and IDs. - - Clock ID - ----------------------- - dummy 0 - ckih 1 - ckil 2 - mpll 3 - spll 4 - upll 5 - mcu_main 6 - hsp 7 - ahb 8 - nfc 9 - ipg 10 - per_div 11 - per 12 - csi_sel 13 - fir_sel 14 - csi_div 15 - usb_div_pre 16 - usb_div_post 17 - fir_div_pre 18 - fir_div_post 19 - sdhc1_gate 20 - sdhc2_gate 21 - gpt_gate 22 - epit1_gate 23 - epit2_gate 24 - iim_gate 25 - ata_gate 26 - sdma_gate 27 - cspi3_gate 28 - rng_gate 29 - uart1_gate 30 - uart2_gate 31 - ssi1_gate 32 - i2c1_gate 33 - i2c2_gate 34 - i2c3_gate 35 - hantro_gate 36 - mstick1_gate 37 - mstick2_gate 38 - csi_gate 39 - rtc_gate 40 - wdog_gate 41 - pwm_gate 42 - sim_gate 43 - ect_gate 44 - usb_gate 45 - kpp_gate 46 - ipu_gate 47 - uart3_gate 48 - uart4_gate 49 - uart5_gate 50 - owire_gate 51 - ssi2_gate 52 - cspi1_gate 53 - cspi2_gate 54 - gacc_gate 55 - emi_gate 56 - rtic_gate 57 - firi_gate 58 - -Examples: - -clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>, <53>; - #clock-cells = <1>; -}; - -uart1: serial@43f90000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 10>, <&clks 30>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx31-clock.yaml b/Documentation/devicetree/bindings/clock/imx31-clock.yaml new file mode 100644 index 000000000000..50a8498eef8a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx31-clock.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx31-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX31 Clock Controller + +maintainers: + - Fabio Estevam <festevam@gmail.com> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX31 + clocks and IDs. + + Clock ID + ----------------------- + dummy 0 + ckih 1 + ckil 2 + mpll 3 + spll 4 + upll 5 + mcu_main 6 + hsp 7 + ahb 8 + nfc 9 + ipg 10 + per_div 11 + per 12 + csi_sel 13 + fir_sel 14 + csi_div 15 + usb_div_pre 16 + usb_div_post 17 + fir_div_pre 18 + fir_div_post 19 + sdhc1_gate 20 + sdhc2_gate 21 + gpt_gate 22 + epit1_gate 23 + epit2_gate 24 + iim_gate 25 + ata_gate 26 + sdma_gate 27 + cspi3_gate 28 + rng_gate 29 + uart1_gate 30 + uart2_gate 31 + ssi1_gate 32 + i2c1_gate 33 + i2c2_gate 34 + i2c3_gate 35 + hantro_gate 36 + mstick1_gate 37 + mstick2_gate 38 + csi_gate 39 + rtc_gate 40 + wdog_gate 41 + pwm_gate 42 + sim_gate 43 + ect_gate 44 + usb_gate 45 + kpp_gate 46 + ipu_gate 47 + uart3_gate 48 + uart4_gate 49 + uart5_gate 50 + owire_gate 51 + ssi2_gate 52 + cspi1_gate 53 + cspi2_gate 54 + gacc_gate 55 + emi_gate 56 + rtic_gate 57 + firi_gate 58 + +properties: + compatible: + const: fsl,imx31-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for DVFS when a frequency change is requested, request 2 is + to generate interrupt for DPTC when a voltage change is requested. + items: + - description: CCM DVFS interrupt request 1 + - description: CCM DPTC interrupt request 2 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@53f80000 { + compatible = "fsl,imx31-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>, <53>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.txt b/Documentation/devicetree/bindings/clock/imx35-clock.txt deleted file mode 100644 index f49783213c56..000000000000 --- a/Documentation/devicetree/bindings/clock/imx35-clock.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Clock bindings for Freescale i.MX35 - -Required properties: -- compatible: Should be "fsl,imx35-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX35 -clocks and IDs. - - Clock ID - --------------------------- - ckih 0 - mpll 1 - ppll 2 - mpll_075 3 - arm 4 - hsp 5 - hsp_div 6 - hsp_sel 7 - ahb 8 - ipg 9 - arm_per_div 10 - ahb_per_div 11 - ipg_per 12 - uart_sel 13 - uart_div 14 - esdhc_sel 15 - esdhc1_div 16 - esdhc2_div 17 - esdhc3_div 18 - spdif_sel 19 - spdif_div_pre 20 - spdif_div_post 21 - ssi_sel 22 - ssi1_div_pre 23 - ssi1_div_post 24 - ssi2_div_pre 25 - ssi2_div_post 26 - usb_sel 27 - usb_div 28 - nfc_div 29 - asrc_gate 30 - pata_gate 31 - audmux_gate 32 - can1_gate 33 - can2_gate 34 - cspi1_gate 35 - cspi2_gate 36 - ect_gate 37 - edio_gate 38 - emi_gate 39 - epit1_gate 40 - epit2_gate 41 - esai_gate 42 - esdhc1_gate 43 - esdhc2_gate 44 - esdhc3_gate 45 - fec_gate 46 - gpio1_gate 47 - gpio2_gate 48 - gpio3_gate 49 - gpt_gate 50 - i2c1_gate 51 - i2c2_gate 52 - i2c3_gate 53 - iomuxc_gate 54 - ipu_gate 55 - kpp_gate 56 - mlb_gate 57 - mshc_gate 58 - owire_gate 59 - pwm_gate 60 - rngc_gate 61 - rtc_gate 62 - rtic_gate 63 - scc_gate 64 - sdma_gate 65 - spba_gate 66 - spdif_gate 67 - ssi1_gate 68 - ssi2_gate 69 - uart1_gate 70 - uart2_gate 71 - uart3_gate 72 - usbotg_gate 73 - wdog_gate 74 - max_gate 75 - admux_gate 76 - csi_gate 77 - csi_div 78 - csi_sel 79 - iim_gate 80 - gpu2d_gate 81 - ckli_gate 82 - -Examples: - -clks: ccm@53f80000 { - compatible = "fsl,imx35-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; -}; - -esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <7>; - clocks = <&clks 9>, <&clks 8>, <&clks 43>; - clock-names = "ipg", "ahb", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.yaml b/Documentation/devicetree/bindings/clock/imx35-clock.yaml new file mode 100644 index 000000000000..c063369de3ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx35-clock.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx35-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX35 Clock Controller + +maintainers: + - Steffen Trumtrar <s.trumtrar@pengutronix.de> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX35 + clocks and IDs. + + Clock ID + --------------------------- + ckih 0 + mpll 1 + ppll 2 + mpll_075 3 + arm 4 + hsp 5 + hsp_div 6 + hsp_sel 7 + ahb 8 + ipg 9 + arm_per_div 10 + ahb_per_div 11 + ipg_per 12 + uart_sel 13 + uart_div 14 + esdhc_sel 15 + esdhc1_div 16 + esdhc2_div 17 + esdhc3_div 18 + spdif_sel 19 + spdif_div_pre 20 + spdif_div_post 21 + ssi_sel 22 + ssi1_div_pre 23 + ssi1_div_post 24 + ssi2_div_pre 25 + ssi2_div_post 26 + usb_sel 27 + usb_div 28 + nfc_div 29 + asrc_gate 30 + pata_gate 31 + audmux_gate 32 + can1_gate 33 + can2_gate 34 + cspi1_gate 35 + cspi2_gate 36 + ect_gate 37 + edio_gate 38 + emi_gate 39 + epit1_gate 40 + epit2_gate 41 + esai_gate 42 + esdhc1_gate 43 + esdhc2_gate 44 + esdhc3_gate 45 + fec_gate 46 + gpio1_gate 47 + gpio2_gate 48 + gpio3_gate 49 + gpt_gate 50 + i2c1_gate 51 + i2c2_gate 52 + i2c3_gate 53 + iomuxc_gate 54 + ipu_gate 55 + kpp_gate 56 + mlb_gate 57 + mshc_gate 58 + owire_gate 59 + pwm_gate 60 + rngc_gate 61 + rtc_gate 62 + rtic_gate 63 + scc_gate 64 + sdma_gate 65 + spba_gate 66 + spdif_gate 67 + ssi1_gate 68 + ssi2_gate 69 + uart1_gate 70 + uart2_gate 71 + uart3_gate 72 + usbotg_gate 73 + wdog_gate 74 + max_gate 75 + admux_gate 76 + csi_gate 77 + csi_div 78 + csi_sel 79 + iim_gate 80 + gpu2d_gate 81 + ckli_gate 82 + +properties: + compatible: + const: fsl,imx35-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@53f80000 { + compatible = "fsl,imx35-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt deleted file mode 100644 index a24ca9e582d2..000000000000 --- a/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Clock bindings for Freescale i.MX5 - -Required properties: -- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53 -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h -for the full list of i.MX5 clock IDs. - -Examples (for mx53): - -clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; -}; - -can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.yaml b/Documentation/devicetree/bindings/clock/imx5-clock.yaml new file mode 100644 index 000000000000..423c0142c1d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx5-clock.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx5-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX5 Clock Controller + +maintainers: + - Fabio Estevam <festevam@gmail.com> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h + for the full list of i.MX5 clock IDs. + +properties: + compatible: + enum: + - fsl,imx53-ccm + - fsl,imx51-ccm + - fsl,imx50-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx5-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, + <0 72 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt deleted file mode 100644 index 13d36d4c6991..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Clock bindings for Freescale i.MX6 Quad - -Required properties: -- compatible: Should be "fsl,imx6q-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -Optional properties: -- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal - on power off. - Use this property if the SoC should be powered off by external power - management IC (PMIC) triggered via PMIC_STBY_REQ signal. - Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should - be using "syscon-poweroff" driver instead. -- clocks: list of clock specifiers, must contain an entry for each entry - in clock-names -- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h -for the full list of i.MX6 Quad and DualLite clock IDs. - -Examples: - -#include <dt-bindings/clock/imx6qdl-clock.h> - -clks: ccm@20c4000 { - compatible = "fsl,imx6q-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 0x04 0 88 0x04>; - #clock-cells = <1>; -}; - -uart1: serial@2020000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 0x04>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml new file mode 100644 index 000000000000..bae4fcb3aacc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6q-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 Quad Clock Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +properties: + compatible: + const: fsl,imx6q-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 24m osc + - description: 32k osc + - description: ckih1 clock input + - description: anaclk1 clock input + - description: anaclk2 clock input + + clock-names: + items: + - const: osc + - const: ckil + - const: ckih1 + - const: anaclk1 + - const: anaclk2 + + fsl,pmic-stby-poweroff: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Use this property if the SoC should be powered off by external power + management IC (PMIC) triggered via PMIC_STBY_REQ signal. + Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should + be using "syscon-poweroff" driver instead. + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@20c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt deleted file mode 100644 index 15e40bdf147d..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt +++ /dev/null @@ -1,10 +0,0 @@ -* Clock bindings for Freescale i.MX6 SoloLite - -Required properties: -- compatible: Should be "fsl,imx6sl-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h -for the full list of i.MX6 SoloLite clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml new file mode 100644 index 000000000000..c85ff6ea3d24 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6sl-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 SoloLite Clock Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +properties: + compatible: + const: fsl,imx6sl-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@20c4000 { + compatible = "fsl,imx6sl-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt deleted file mode 100644 index fee849d5fdd1..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Clock bindings for Freescale i.MX6 SLL - -Required properties: -- compatible: Should be "fsl,imx6sll-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h -for the full list of i.MX6 SLL clock IDs. - -Examples: - -#include <dt-bindings/clock/imx6sll-clock.h> - -clks: clock-controller@20c4000 { - compatible = "fsl,imx6sll-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; -}; - -uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SLL_CLK_UART1_IPG>, - <&clks IMX6SLL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml new file mode 100644 index 000000000000..6b549ed1493c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 SLL Clock Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +properties: + compatible: + const: fsl,imx6sll-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ipp_di0 clock input + - description: ipp_di1 clock input + + clock-names: + items: + - const: ckil + - const: osc + - const: ipp_di0 + - const: ipp_di1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.txt b/Documentation/devicetree/bindings/clock/imx6sx-clock.txt deleted file mode 100644 index 22362b9b7ba3..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6sx-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX6 SoloX - -Required properties: -- compatible: Should be "fsl,imx6sx-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h -for the full list of i.MX6 SoloX clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml new file mode 100644 index 000000000000..55dcad18b7c6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 SoloX Clock Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +properties: + compatible: + const: fsl,imx6sx-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ipp_di0 clock input + - description: ipp_di1 clock input + - description: anaclk1 clock input + - description: anaclk2 clock input + + clock-names: + items: + - const: ckil + - const: osc + - const: ipp_di0 + - const: ipp_di1 + - const: anaclk1 + - const: anaclk2 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@20c4000 { + compatible = "fsl,imx6sx-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; + }; diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt deleted file mode 100644 index 571d5039f663..000000000000 --- a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX6 UltraLite - -Required properties: -- compatible: Should be "fsl,imx6ul-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h -for the full list of i.MX6 UltraLite clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml new file mode 100644 index 000000000000..be54d4df5afa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 UltraLite Clock Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +properties: + compatible: + const: fsl,imx6ul-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ipp_di0 clock input + - description: ipp_di1 clock input + + clock-names: + items: + - const: ckil + - const: osc + - const: ipp_di0 + - const: ipp_di1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@20c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.txt b/Documentation/devicetree/bindings/clock/imx7d-clock.txt deleted file mode 100644 index 9d3026d81a68..000000000000 --- a/Documentation/devicetree/bindings/clock/imx7d-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX7 Dual - -Required properties: -- compatible: Should be "fsl,imx7d-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h -for the full list of i.MX7 Dual clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.yaml b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml new file mode 100644 index 000000000000..e7d8427e4957 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx7d-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7 Dual Clock Controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + - Anson Huang <Anson.Huang@nxp.com> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h + for the full list of i.MX7 Dual clock IDs. + +properties: + compatible: + const: fsl,imx7d-ccm + + reg: + maxItems: 1 + + interrupts: + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: ckil + - const: osc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt deleted file mode 100644 index 93d89adb7afe..000000000000 --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Clock bindings for Freescale i.MX7ULP - -i.MX7ULP Clock functions are under joint control of the System -Clock Generation (SCG) modules, Peripheral Clock Control (PCC) -modules, and Core Mode Controller (CMC)1 blocks - -The clocking scheme provides clear separation between M4 domain -and A7 domain. Except for a few clock sources shared between two -domains, such as the System Oscillator clock, the Slow IRC (SIRC), -and and the Fast IRC clock (FIRCLK), clock sources and clock -management are separated and contained within each domain. - -M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. -A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. - -Note: this binding doc is only for A7 clock domain. - -System Clock Generation (SCG) modules: ---------------------------------------------------------------------- -The System Clock Generation (SCG) is responsible for clock generation -and distribution across this device. Functions performed by the SCG -include: clock reference selection, generation of clock used to derive -processor, system, peripheral bus and external memory interface clocks, -source selection for peripheral clocks and control of power saving -clock gating mode. - -Required properties: - -- compatible: Should be "fsl,imx7ulp-scg1". -- reg : Should contain registers location and length. -- #clock-cells: Should be <1>. -- clocks: Should contain the fixed input clocks. -- clock-names: Should contain the following clock names: - "rosc", "sosc", "sirc", "firc", "upll", "mpll". - -Peripheral Clock Control (PCC) modules: ---------------------------------------------------------------------- -The Peripheral Clock Control (PCC) is responsible for clock selection, -optional division and clock gating mode for peripherals in their -respected power domain - -Required properties: -- compatible: Should be one of: - "fsl,imx7ulp-pcc2", - "fsl,imx7ulp-pcc3". -- reg : Should contain registers location and length. -- #clock-cells: Should be <1>. -- clocks: Should contain the fixed input clocks. -- clock-names: Should contain the following clock names: - "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", - "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk", - "mpll", "firc_bus_clk", "rosc", "spll_bus_clk"; - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. -See include/dt-bindings/clock/imx7ulp-clock.h -for the full list of i.MX7ULP clock IDs of each module. - -Examples: - -#include <dt-bindings/clock/imx7ulp-clock.h> - -scg1: scg1@403e0000 { - compatible = "fsl,imx7ulp-scg1; - reg = <0x403e0000 0x10000>; - clocks = <&rosc>, <&sosc>, <&sirc>, - <&firc>, <&upll>, <&mpll>; - clock-names = "rosc", "sosc", "sirc", - "firc", "upll", "mpll"; - #clock-cells = <1>; -}; - -pcc2: pcc2@403f0000 { - compatible = "fsl,imx7ulp-pcc2"; - reg = <0x403f0000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", "mpll", - "firc_bus_clk", "rosc", "spll_bus_clk"; -}; - -usdhc1: usdhc@40380000 { - compatible = "fsl,imx7ulp-usdhc"; - reg = <0x40380000 0x10000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC1>; - clock-names ="ipg", "ahb", "per"; - bus-width = <4>; -}; diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml b/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml new file mode 100644 index 000000000000..76842038f52e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller + +maintainers: + - A.s. Dong <aisheng.dong@nxp.com> + +description: | + i.MX7ULP Clock functions are under joint control of the System + Clock Generation (SCG) modules, Peripheral Clock Control (PCC) + modules, and Core Mode Controller (CMC)1 blocks + + The clocking scheme provides clear separation between M4 domain + and A7 domain. Except for a few clock sources shared between two + domains, such as the System Oscillator clock, the Slow IRC (SIRC), + and and the Fast IRC clock (FIRCLK), clock sources and clock + management are separated and contained within each domain. + + M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. + A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. + + Note: this binding doc is only for A7 clock domain. + + The Peripheral Clock Control (PCC) is responsible for clock selection, + optional division and clock gating mode for peripherals in their + respected power domain. + + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/imx7ulp-clock.h for the full list of + i.MX7ULP clock IDs of each module. + +properties: + compatible: + enum: + - fsl,imx7ulp-pcc2 + - fsl,imx7ulp-pcc3 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: nic1 bus clock + - description: nic1 clock + - description: ddr clock + - description: apll pfd2 + - description: apll pfd1 + - description: apll pfd0 + - description: usb pll + - description: system osc bus clock + - description: fast internal reference clock bus + - description: rtc osc + - description: system pll bus clock + + clock-names: + items: + - const: nic1_bus_clk + - const: nic1_clk + - const: ddr_clk + - const: apll_pfd2 + - const: apll_pfd1 + - const: apll_pfd0 + - const: upll + - const: sosc_bus_clk + - const: firc_bus_clk + - const: rosc + - const: spll_bus_clk + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx7ulp-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", "firc_bus_clk", + "rosc", "spll_bus_clk"; + }; diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml b/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml new file mode 100644 index 000000000000..5e25bc6d1372 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller + +maintainers: + - A.s. Dong <aisheng.dong@nxp.com> + +description: | + i.MX7ULP Clock functions are under joint control of the System + Clock Generation (SCG) modules, Peripheral Clock Control (PCC) + modules, and Core Mode Controller (CMC)1 blocks + + The clocking scheme provides clear separation between M4 domain + and A7 domain. Except for a few clock sources shared between two + domains, such as the System Oscillator clock, the Slow IRC (SIRC), + and and the Fast IRC clock (FIRCLK), clock sources and clock + management are separated and contained within each domain. + + M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. + A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. + + Note: this binding doc is only for A7 clock domain. + + The System Clock Generation (SCG) is responsible for clock generation + and distribution across this device. Functions performed by the SCG + include: clock reference selection, generation of clock used to derive + processor, system, peripheral bus and external memory interface clocks, + source selection for peripheral clocks and control of power saving + clock gating mode. + + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/imx7ulp-clock.h for the full list of + i.MX7ULP clock IDs of each module. + +properties: + compatible: + const: fsl,imx7ulp-scg1 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: rtc osc + - description: system osc + - description: slow internal reference clock + - description: fast internal reference clock + - description: usb PLL + + clock-names: + items: + - const: rosc + - const: sosc + - const: sirc + - const: firc + - const: upll + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx7ulp-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + clock-controller@403e0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml new file mode 100644 index 000000000000..80539f88bc27 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Family Clock Control Module + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: | + NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock + controller, which generates and supplies to all modules. + +properties: + compatible: + enum: + - fsl,imx8mm-ccm + - fsl,imx8mn-ccm + - fsl,imx8mp-ccm + - fsl,imx8mq-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + clocks: + minItems: 6 + maxItems: 7 + + clock-names: + minItems: 6 + maxItems: 7 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h + for the full list of i.MX8M clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-ccm + then: + properties: + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + - | + clock-controller@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, + <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", + "clk_ext2", "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt b/Documentation/devicetree/bindings/clock/imx8mm-clock.txt deleted file mode 100644 index 8e4ab9e619a1..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Clock bindings for NXP i.MX8M Mini - -Required properties: -- compatible: Should be "fsl,imx8mm-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include the following entries: - - "osc_32k" - - "osc_24m" - - "clk_ext1" - - "clk_ext2" - - "clk_ext3" - - "clk_ext4" - -clk: clock-controller@30380000 { - compatible = "fsl,imx8mm-ccm"; - reg = <0x0 0x30380000 0x0 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; -}; - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h -for the full list of i.MX8M Mini clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml deleted file mode 100644 index 622f3658bd9f..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml +++ /dev/null @@ -1,112 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP i.MX8M Nano Clock Control Module Binding - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: | - NXP i.MX8M Nano clock control module is an integrated clock controller, which - generates and supplies to all modules. - -properties: - compatible: - const: fsl,imx8mn-ccm - - reg: - maxItems: 1 - - clocks: - items: - - description: 32k osc - - description: 24m osc - - description: ext1 clock input - - description: ext2 clock input - - description: ext3 clock input - - description: ext4 clock input - - clock-names: - items: - - const: osc_32k - - const: osc_24m - - const: clk_ext1 - - const: clk_ext2 - - const: clk_ext3 - - const: clk_ext4 - - '#clock-cells': - const: 1 - description: | - The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h - for the full list of i.MX8M Nano clock IDs. - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - -examples: - # Clock Control Module node: - - | - clk: clock-controller@30380000 { - compatible = "fsl,imx8mn-ccm"; - reg = <0x0 0x30380000 0x0 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, - <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", - "clk_ext2", "clk_ext3", "clk_ext4"; - }; - - # Required external clocks for Clock Control Module node: - - | - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - -... diff --git a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml new file mode 100644 index 000000000000..0a6dc1a6e122 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP AudioMIX Block Control + +maintainers: + - Marek Vasut <marex@denx.de> + +description: | + NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP + used to control Audio related clock on the SoC. + +properties: + compatible: + const: fsl,imx8mp-audio-blk-ctrl + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + minItems: 7 + maxItems: 7 + + clock-names: + items: + - const: ahb + - const: sai1 + - const: sai2 + - const: sai3 + - const: sai5 + - const: sai6 + - const: sai7 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h + for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + + clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl"; + reg = <0x30e20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_SAI1>, + <&clk IMX8MP_CLK_SAI2>, + <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_CLK_SAI5>, + <&clk IMX8MP_CLK_SAI6>, + <&clk IMX8MP_CLK_SAI7>; + clock-names = "ahb", + "sai1", "sai2", "sai3", + "sai5", "sai6", "sai7"; + power-domains = <&pgc_audio>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt deleted file mode 100644 index 52de8263e012..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Clock bindings for NXP i.MX8M Quad - -Required properties: -- compatible: Should be "fsl,imx8mq-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include the following entries: - - "ckil" - - "osc_25m" - - "osc_27m" - - "clk_ext1" - - "clk_ext2" - - "clk_ext3" - - "clk_ext4" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h -for the full list of i.MX8M Quad clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt deleted file mode 100644 index 965cfa42e025..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ /dev/null @@ -1,51 +0,0 @@ -* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings - -The Low-Power Clock Gate (LPCG) modules contain a local programming -model to control the clock gates for the peripherals. An LPCG module -is used to locally gate the clocks for the associated peripheral. - -Note: -This level of clock gating is provided after the clocks are generated -by the SCU resources and clock controls. Thus even if the clock is -enabled by these control bits, it might still not be running based -on the base resource. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qxp-lpcg-adma", - "fsl,imx8qxp-lpcg-conn", - "fsl,imx8qxp-lpcg-dc", - "fsl,imx8qxp-lpcg-dsp", - "fsl,imx8qxp-lpcg-gpu", - "fsl,imx8qxp-lpcg-hsio", - "fsl,imx8qxp-lpcg-img", - "fsl,imx8qxp-lpcg-lsio", - "fsl,imx8qxp-lpcg-vpu" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h - -Examples: - -#include <dt-bindings/clock/imx8qxp-clock.h> - -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; -}; - -usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; -}; diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml new file mode 100644 index 000000000000..b207f95361b2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock + +maintainers: + - Aisheng Dong <aisheng.dong@nxp.com> + +description: | + The Low-Power Clock Gate (LPCG) modules contain a local programming + model to control the clock gates for the peripherals. An LPCG module + is used to locally gate the clocks for the associated peripheral. + + This level of clock gating is provided after the clocks are generated + by the SCU resources and clock controls. Thus even if the clock is + enabled by these control bits, it might still not be running based + on the base resource. + + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See the full list of clock IDs from: + include/dt-bindings/clock/imx8-lpcg.h + +properties: + compatible: + oneOf: + - const: fsl,imx8qxp-lpcg + - items: + - enum: + - fsl,imx8qm-lpcg + - const: fsl,imx8qxp-lpcg + - enum: + - fsl,imx8qxp-lpcg-adma + - fsl,imx8qxp-lpcg-conn + - fsl,imx8qxp-lpcg-dc + - fsl,imx8qxp-lpcg-dsp + - fsl,imx8qxp-lpcg-gpu + - fsl,imx8qxp-lpcg-hsio + - fsl,imx8qxp-lpcg-img + - fsl,imx8qxp-lpcg-lsio + - fsl,imx8qxp-lpcg-vpu + deprecated: true + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + description: | + Input parent clocks phandle array for each clock + minItems: 1 + maxItems: 8 + + clock-indices: + description: | + An integer array indicating the bit offset for each clock. + Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the + supported LPCG clock indices. + minItems: 1 + maxItems: 8 + + clock-output-names: + description: | + Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock-indices property. + minItems: 1 + maxItems: 8 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, + <&conn_axi_clk>; + clock-indices = <IMX_LPCG_CLK_0>, + <IMX_LPCG_CLK_4>, + <IMX_LPCG_CLK_5>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-cgc-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-cgc-clock.yaml new file mode 100644 index 000000000000..68a60cdc19af --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8ulp-cgc-clock.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Clock Generation & Control(CGC) Module + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: | + On i.MX8ULP, The clock sources generation, distribution and management is + under the control of several CGCs & PCCs modules. The CGC modules generate + and distribute clocks on the device. + +properties: + compatible: + enum: + - fsl,imx8ulp-cgc1 + - fsl,imx8ulp-cgc2 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Generation & Control Module node: + - | + clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx8ulp-pcc-clock.yaml b/Documentation/devicetree/bindings/clock/imx8ulp-pcc-clock.yaml new file mode 100644 index 000000000000..d0b0792fe7ba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8ulp-pcc-clock.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: | + On i.MX8ULP, The clock sources generation, distribution and management is + under the control of several CGCs & PCCs modules. The PCC modules control + software reset, clock selection, optional division and clock gating mode + for peripherals. + +properties: + compatible: + enum: + - fsl,imx8ulp-pcc3 + - fsl,imx8ulp-pcc4 + - fsl,imx8ulp-pcc5 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + # Peripheral Clock Control Module node: + - | + clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/imx93-clock.yaml b/Documentation/devicetree/bindings/clock/imx93-clock.yaml new file mode 100644 index 000000000000..ccb53c6b96c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx93-clock.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx93-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX93 Clock Control Module + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: | + i.MX93 clock control module is an integrated clock controller, which + includes clock generator, clock gate and supplies to all modules. + +properties: + compatible: + enum: + - fsl,imx93-ccm + + reg: + maxItems: 1 + + clocks: + description: + specify the external clocks used by the CCM module. + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + + clock-names: + description: + specify the external clocks names used by the CCM module. + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + + '#clock-cells': + const: 1 + description: + See include/dt-bindings/clock/imx93-clock.h for the full list of + i.MX93 clock IDs. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml b/Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml new file mode 100644 index 000000000000..777af4aad4b2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imxrt1050-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MXRT Clock Controller + +maintainers: + - Giulio Benetti <giulio.benetti@benettiengineering.com> + - Jesse Taube <Mr.Bossman075@gmail.com> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imxrt*-clock.h + for the full list of i.MXRT clock IDs. + +properties: + compatible: + const: fsl,imxrt1050-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + clocks: + description: 24m osc + maxItems: 1 + + clock-names: + const: osc + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imxrt1050-clock.h> + + clks: clock-controller@400fc000 { + compatible = "fsl,imxrt1050-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt deleted file mode 100644 index 75598e655067..000000000000 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ /dev/null @@ -1,57 +0,0 @@ -Ingenic SoC CGU binding - -The CGU in an Ingenic SoC provides all the clocks generated on-chip. It -typically includes a variety of PLLs, multiplexers, dividers & gates in order -to provide many different clock signals derived from only 2 external source -clocks. - -Required properties: -- compatible : Should be one of: - * ingenic,jz4740-cgu - * ingenic,jz4725b-cgu - * ingenic,jz4770-cgu - * ingenic,jz4780-cgu - * ingenic,x1000-cgu -- reg : The address & length of the CGU registers. -- clocks : List of phandle & clock specifiers for clocks external to the CGU. - Two such external clocks should be specified - first the external crystal - "ext" and second the RTC clock source "rtc". -- clock-names : List of name strings for the external clocks. -- #clock-cells: Should be 1. - Clock consumers specify this argument to identify a clock. The valid values - may be found in <dt-bindings/clock/<soctype>-cgu.h>. - -Example SoC include file: - -/ { - cgu: jz4740-cgu { - compatible = "ingenic,jz4740-cgu"; - reg = <0x10000000 0x100>; - #clock-cells = <1>; - }; - - uart0: serial@10030000 { - clocks = <&cgu JZ4740_CLK_UART0>; - }; -}; - -Example board file: - -/ { - ext: clock@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - rtc: clock@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - &cgu { - clocks = <&ext> <&rtc>; - clock-names: "ext", "rtc"; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml new file mode 100644 index 000000000000..509df06b9c9d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs CGU + +description: | + The CGU in an Ingenic SoC provides all the clocks generated on-chip. It + typically includes a variety of PLLs, multiplexers, dividers & gates in order + to provide many different clock signals derived from only 2 external source + clocks. + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +select: + properties: + compatible: + contains: + enum: + - ingenic,jz4740-cgu + - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu + - ingenic,jz4760-cgu + - ingenic,jz4760b-cgu + - ingenic,jz4770-cgu + - ingenic,jz4780-cgu + - ingenic,x1000-cgu + - ingenic,x1830-cgu + required: + - compatible + +properties: + $nodename: + pattern: "^clock-controller@[0-9a-f]+$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#clock-cells": + const: 1 + + ranges: true + + compatible: + items: + - enum: + - ingenic,jz4740-cgu + - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu + - ingenic,jz4760-cgu + - ingenic,jz4760b-cgu + - ingenic,jz4770-cgu + - ingenic,jz4780-cgu + - ingenic,x1000-cgu + - ingenic,x1830-cgu + - const: simple-mfd + minItems: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: External oscillator clock + - description: Internal 32 kHz RTC clock + + clock-names: + items: + - const: ext + - enum: + - rtc + - osc32k # Different name, same clock + + assigned-clocks: + minItems: 1 + maxItems: 64 + + assigned-clock-parents: + minItems: 1 + maxItems: 64 + + assigned-clock-rates: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + +patternProperties: + "^usb-phy@[a-f0-9]+$": + $ref: /schemas/phy/ingenic,phy-usb.yaml# + "^mac-phy-ctrl@[a-f0-9]+$": + $ref: /schemas/net/ingenic,mac.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> + cgu: clock-controller@10000000 { + compatible = "ingenic,jz4770-cgu", "simple-mfd"; + reg = <0x10000000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x100>; + + clocks = <&ext>, <&osc32k>; + clock-names = "ext", "osc32k"; + + #clock-cells = <1>; + + otg_phy: usb-phy@3c { + compatible = "ingenic,jz4770-phy"; + reg = <0x3c 0x10>; + + clocks = <&cgu JZ4770_CLK_OTG_PHY>; + + vcc-supply = <&ldo5>; + + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt deleted file mode 100644 index 9f4ec5cb5c6b..000000000000 --- a/Documentation/devicetree/bindings/clock/intc_stratix10.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be - "intel,stratix10-clkmgr" - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - -- #clock-cells : from common clock binding, shall be set to 1. - -Example: - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/intel,agilex.yaml b/Documentation/devicetree/bindings/clock/intel,agilex.yaml new file mode 100644 index 000000000000..3745ba8dbd76 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,agilex.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex platform clock controller + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +description: + The Intel Agilex Clock controller is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: intel,agilex-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + clocks = <&osc1>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml new file mode 100644 index 000000000000..d120b0da7f3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex5 clock manager + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +description: + The Intel Agilex5 Clock Manager is an integrated clock controller, which + generates and supplies clock to all the modules. + +properties: + compatible: + const: intel,agilex5-clkmgr + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml new file mode 100644 index 000000000000..76609a390429 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain SoC's Clock Controller(CGU) + +maintainers: + - Rahul Tanwar <rahul.tanwar@linux.intel.com> + +description: | + Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides + all means to access the CGU hardware module in order to generate a series + of clocks for the whole system and individual peripherals. + + Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it + defines all available clocks as macros. These macros can be used in device + tree sources. + +properties: + compatible: + const: intel,cgu-lgm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + cgu: clock-controller@e0200000 { + compatible = "intel,cgu-lgm"; + reg = <0xe0200000 0x33c>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml b/Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml new file mode 100644 index 000000000000..e000116a51a4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA eASIC N5X platform clock controller + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +description: + The Intel eASIC N5X Clock controller is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: intel,easic-n5x-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clkmgr: clock-controller@ffd10000 { + compatible = "intel,easic-n5x-clkmgr"; + reg = <0xffd10000 0x1000>; + clocks = <&osc1>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/intel,stratix10.yaml b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml new file mode 100644 index 000000000000..b4a8be213400 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Stratix10 platform clock controller + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + compatible: + const: intel,stratix10-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@ffd10000 { + compatible = "intel,stratix10-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt index 47570d207215..9a3fbc665606 100644 --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt @@ -14,7 +14,7 @@ Required properties: - #clock-cells : from common clock binding; shall be set to 0. - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" - clocks : parent clock phandle -- reg - pll control0 and pll multipler registers +- reg - pll control0 and pll multiplier registers - reg-names : control, multiplier and post-divider. The multiplier and post-divider registers are applicable only for main pll clock - fixed-postdiv : fixed post divider value. If absent, use clkod register bits diff --git a/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml new file mode 100644 index 000000000000..01561a0f35d5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 Clock Controller + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +properties: + compatible: + enum: + - loongson,ls1b-clk + - loongson,ls1c-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkc: clock-controller@1fe78030 { + compatible = "loongson,ls1b-clk"; + reg = <0x1fe78030 0x8>; + + clocks = <&xtal>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml new file mode 100644 index 000000000000..63a59015987e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2 SoC Clock Control Module + +maintainers: + - Yinbo Zhu <zhuyinbo@loongson.cn> + +description: | + Loongson-2 SoC clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + enum: + - loongson,ls2k-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: 100m ref + + clock-names: + items: + - const: ref_100m + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h + for the full list of Loongson-2 SoC clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ref_100m: clock-ref-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ref_100m"; + }; + + clk: clock-controller@1fe00480 { + compatible = "loongson,ls2k-clk"; + reg = <0x1fe00480 0x58>; + #clock-cells = <1>; + clocks = <&ref_100m>; + clock-names = "ref_100m"; + }; diff --git a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt index fa97c12014ac..8cf8f0ecdd16 100644 --- a/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt +++ b/Documentation/devicetree/bindings/clock/lpc1850-ccu.txt @@ -68,7 +68,7 @@ soc { "base_ssp0_clk", "base_sdio_clk"; }; - /* A user of CCU brach clocks */ + /* A user of CCU branch clocks */ uart1: serial@40082000 { ... clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; diff --git a/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt b/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt index 6f1c7b4e4d2c..b6b2547a3d17 100644 --- a/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt +++ b/Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt @@ -5,8 +5,8 @@ control registers for two low speed clocks. One of the clocks is a 32 kHz oscillator driver with power up/down and clock gating. Next is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. -These clocks are used by the RTC and the Event Router peripherials. -The 32 kHz can also be routed to other peripherials to enable low +These clocks are used by the RTC and the Event Router peripherals. +The 32 kHz can also be routed to other peripherals to enable low power modes. This binding uses the common clock binding: diff --git a/Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml new file mode 100644 index 000000000000..175f5c8f2bc5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,armada-3700-uart-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Marvell Armada 3720 UART clocks + +maintainers: + - Pali Rohár <pali@kernel.org> + +properties: + compatible: + const: marvell,armada-3700-uart-clock + + reg: + items: + - description: UART Clock Control Register + - description: UART 2 Baud Rate Divisor Register + + clocks: + description: | + List of parent clocks suitable for UART from following set: + "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal" + UART clock can use one from this set and when more are provided + then kernel would choose and configure the most suitable one. + It is suggest to specify at least one TBG clock to achieve + baudrates above 230400 and also to specify clock which bootloader + used for UART (most probably xtal) for smooth boot log on UART. + + clock-names: + items: + - const: TBG-A-P + - const: TBG-B-P + - const: TBG-A-S + - const: TBG-B-S + - const: xtal + minItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + uartclk: clock-controller@12010 { + compatible = "marvell,armada-3700-uart-clock"; + reg = <0x12010 0x4>, <0x12210 0x4>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>; + clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-audio-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-audio-clock.yaml new file mode 100644 index 000000000000..dffa73402da9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-audio-clock.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 Audio Clock Controller + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +description: | + The audio clock controller generates and supplies the clocks to the audio + codec. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in + <dt-bindings/clock/marvell,mmp2-audio.h>. + +properties: + compatible: + enum: + - marvell,mmp2-audio-clock + + reg: + maxItems: 1 + + clocks: + items: + - description: Audio subsystem clock + - description: The crystal oscillator clock + - description: First I2S clock + - description: Second I2S clock + + clock-names: + items: + - const: audio + - const: vctcxo + - const: i2s0 + - const: i2s1 + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/marvell,mmp2-audio.h> + #include <dt-bindings/clock/marvell,mmp2.h> + #include <dt-bindings/power/marvell,mmp2.h> + + clock-controller@d42a0c30 { + compatible = "marvell,mmp2-audio-clock"; + reg = <0xd42a0c30 0x10>; + clock-names = "audio", "vctcxo", "i2s0", "i2s1"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&soc_clocks MMP2_CLK_VCTCXO>, + <&soc_clocks MMP2_CLK_I2S0>, + <&soc_clocks MMP2_CLK_I2S1>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml new file mode 100644 index 000000000000..d68f0d196e7d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 and MMP3 Clock Controller + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +description: | + The clock subsystem on MMP2 or MMP3 generates and supplies clock to various + controllers within the SoC. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. + +properties: + compatible: + enum: + - marvell,mmp2-clock # controller compatible with MMP2 SoC + - marvell,mmp3-clock # controller compatible with MMP3 SoC + + reg: + items: + - description: MPMU register region + - description: APMU register region + - description: APBC register region + + reg-names: + items: + - const: mpmu + - const: apmu + - const: apbc + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + clock-controller@d4050000 { + compatible = "marvell,mmp2-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt deleted file mode 100644 index 23b52dc02266..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell MMP2 Clock Controller - -The MMP2 clock subsystem generates and supplies clock to various -controllers within the MMP2 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,mmp2-clock" - controller compatible with MMP2 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 3 places in SOC has clock control logic: - "mpmu", "apmu", "apbc". So three reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt index 3472b461ca93..c10849efb444 100644 --- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt +++ b/Documentation/devicetree/bindings/clock/maxim,max77686.txt @@ -49,7 +49,7 @@ Example: max77686: max77686@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; #clock-cells = <1>; @@ -74,7 +74,7 @@ Example: max77802: max77802@9 { compatible = "maxim,max77802"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/maxim,max9485.txt b/Documentation/devicetree/bindings/clock/maxim,max9485.txt index 61bec1100a94..b8f5c3bbf12b 100644 --- a/Documentation/devicetree/bindings/clock/maxim,max9485.txt +++ b/Documentation/devicetree/bindings/clock/maxim,max9485.txt @@ -12,7 +12,7 @@ requests. Required properties: - compatible: "maxim,max9485" -- clocks: Input clock, must provice 27.000 MHz +- clocks: Input clock, must provide 27.000 MHz - clock-names: Must be set to "xclk" - #clock-cells: From common clock binding; shall be set to 1 diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml new file mode 100644 index 000000000000..685535846cbb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AP Mixedsys Controller + +maintainers: + - Michael Turquette <mturquette@baylibre.com> + - Stephen Boyd <sboyd@kernel.org> + +description: + The Mediatek apmixedsys controller provides PLLs to the system. + The clock values can be found in <dt-bindings/clock/mt*-clk.h>. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt6797-apmixedsys + - mediatek,mt7622-apmixedsys + - mediatek,mt7981-apmixedsys + - mediatek,mt7986-apmixedsys + - mediatek,mt7988-apmixedsys + - mediatek,mt8135-apmixedsys + - mediatek,mt8173-apmixedsys + - mediatek,mt8516-apmixedsys + - items: + - const: mediatek,mt7623-apmixedsys + - const: mediatek,mt2701-apmixedsys + - const: syscon + - items: + - enum: + - mediatek,mt2701-apmixedsys + - mediatek,mt2712-apmixedsys + - mediatek,mt6765-apmixedsys + - mediatek,mt6779-apmixedsys + - mediatek,mt6795-apmixedsys + - mediatek,mt7629-apmixedsys + - mediatek,mt8167-apmixedsys + - mediatek,mt8183-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml new file mode 100644 index 000000000000..f9cddacc2eae --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek ethsys controller + +description: + The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +maintainers: + - James Liao <jamesjj.liao@mediatek.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-ethsys + - mediatek,mt7622-ethsys + - mediatek,mt7629-ethsys + - mediatek,mt7981-ethsys + - mediatek,mt7986-ethsys + - mediatek,mt7988-ethsys + - const: syscon + - items: + - const: mediatek,mt7623-ethsys + - const: mediatek,mt2701-ethsys + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1b000000 { + compatible = "mediatek,mt2701-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml new file mode 100644 index 000000000000..04469eabc8fa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + enum: + - mediatek,mt6795-mfgcfg + - mediatek,mt6795-vdecsys + - mediatek,mt6795-vencsys + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mfgcfg: clock-controller@13000000 { + compatible = "mediatek,mt6795-mfgcfg"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt6795-vencsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml new file mode 100644 index 000000000000..378b761237d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: + The Mediatek system clock controller provides various clocks and system + configuration like reset and bus protection on MT6795. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-apmixedsys + - mediatek,mt6795-infracfg + - mediatek,mt6795-pericfg + - mediatek,mt6795-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml new file mode 100644 index 000000000000..b42f0f5c11b7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mt7621-clk.h>. + + The clocks are provided inside a system controller node. + + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: <include/dt-bindings/reset/mt7621-reset.h>. + +properties: + compatible: + items: + - const: mediatek,mt7621-sysc + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + + ralink,memctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control memory registers + + clock-output-names: + maxItems: 8 + +required: + - compatible + - reg + - '#clock-cells' + - ralink,memctl + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + + sysc: sysc@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml new file mode 100644 index 000000000000..e32a0251ff6a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7988 ethwarp Controller + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +description: + The Mediatek MT7988 ethwarp controller provides clocks and resets for the + Ethernet related subsystems found the MT7988 SoC. + The clock values can be found in <dt-bindings/clock/mt*-clk.h>. + +properties: + compatible: + items: + - const: mediatek,mt7988-ethwarp + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/ti-syscon.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml new file mode 100644 index 000000000000..192f1451f0af --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7988 XFI PLL Clock Controller + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +description: + The MediaTek XFI PLL controller provides the 156.25MHz clock for the + Ethernet SerDes PHY from the 40MHz top_xtal clock. + +properties: + compatible: + const: mediatek,mt7988-xfi-pll + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - resets + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog 16>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml new file mode 100644 index 000000000000..d00327d12e1e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek frequency hopping and spread spectrum clocking control + +maintainers: + - Edward-JW Yang <edward-jw.yang@mediatek.com> + +description: | + Frequency hopping control (FHCTL) is a piece of hardware that control + some PLLs to adopt "hopping" mechanism to adjust their frequency. + Spread spectrum clocking (SSC) is another function provided by this hardware. + +properties: + compatible: + enum: + - mediatek,mt6795-fhctl + - mediatek,mt8173-fhctl + - mediatek,mt8186-fhctl + - mediatek,mt8192-fhctl + - mediatek,mt8195-fhctl + + reg: + maxItems: 1 + + clocks: + description: Phandles of the PLL with FHCTL hardware capability. + minItems: 1 + maxItems: 30 + + mediatek,hopping-ssc-percent: + description: The percentage of spread spectrum clocking for one PLL. + minItems: 1 + maxItems: 30 + items: + default: 0 + minimum: 0 + maximum: 8 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8186-clk.h> + fhctl: fhctl@1000ce00 { + compatible = "mediatek,mt8186-fhctl"; + reg = <0x1000ce00 0x200>; + clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; + mediatek,hopping-ssc-percent = <3>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml new file mode 100644 index 000000000000..860570320545 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT8188 + +maintainers: + - Garmin Chang <garmin.chang@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + enum: + - mediatek,mt8188-adsp-audio26m + - mediatek,mt8188-camsys + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-ccusys + - mediatek,mt8188-imgsys + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-imp-iic-wrap-c + - mediatek,mt8188-imp-iic-wrap-en + - mediatek,mt8188-imp-iic-wrap-w + - mediatek,mt8188-ipesys + - mediatek,mt8188-mfgcfg + - mediatek,mt8188-vdecsys + - mediatek,mt8188-vdecsys-soc + - mediatek,mt8188-vencsys + - mediatek,mt8188-wpesys + - mediatek,mt8188-wpesys-vpp0 + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11283000 { + compatible = "mediatek,mt8188-imp-iic-wrap-c"; + reg = <0x11283000 0x1000>; + #clock-cells = <1>; + }; + diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml new file mode 100644 index 000000000000..4cf8d3af9803 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT8188 + +maintainers: + - Garmin Chang <garmin.chang@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. + The mcusys provides mux control to select the clock source in AP MCU. + The device nodes also provide the system control capacity for configuration. + +properties: + compatible: + items: + - enum: + - mediatek,mt8188-apmixedsys + - mediatek,mt8188-infracfg-ao + - mediatek,mt8188-pericfg-ao + - mediatek,mt8188-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "mediatek,mt8188-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml new file mode 100644 index 000000000000..b327ecb4e524 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT8365 + +maintainers: + - Markus Schneider-Pargmann <msp@baylibre.com> + +properties: + compatible: + items: + - enum: + - mediatek,mt8365-apu + - mediatek,mt8365-imgsys + - mediatek,mt8365-mfgcfg + - mediatek,mt8365-vdecsys + - mediatek,mt8365-vencsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apu: clock-controller@19020000 { + compatible = "mediatek,mt8365-apu", "syscon"; + reg = <0x19020000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml new file mode 100644 index 000000000000..643f84660c8e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT8365 + +maintainers: + - Markus Schneider-Pargmann <msp@baylibre.com> + +description: + The apmixedsys module provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provides the clock source to other IP blocks. + The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8365-topckgen + - mediatek,mt8365-infracfg + - mediatek,mt8365-apmixedsys + - mediatek,mt8365-pericfg + - mediatek,mt8365-mcucfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml new file mode 100644 index 000000000000..ba7ffc5b16a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MTMIPS SoCs System Controller + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + MediaTek MIPS and Ralink SoCs provides a system controller to allow + to access to system control registers. These registers include clock + and reset related ones so this node is both clock and reset provider + for the rest of the world. + + These SoCs have an XTAL from where the cpu clock is + provided as well as derived clocks for the bus and the peripherals. + +properties: + compatible: + items: + - enum: + - ralink,mt7620-sysc + - ralink,mt7628-sysc + - ralink,mt7688-sysc + - ralink,rt2880-sysc + - ralink,rt3050-sysc + - ralink,rt3052-sysc + - ralink,rt3352-sysc + - ralink,rt3883-sysc + - ralink,rt5350-sysc + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + description: + The first cell indicates the clock number. + const: 1 + + '#reset-cells': + description: + The first cell indicates the reset bit within the register. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + syscon@0 { + compatible = "ralink,rt5350-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml new file mode 100644 index 000000000000..bdf3b55bd56f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Top Clock Generator Controller + +maintainers: + - Michael Turquette <mturquette@baylibre.com> + - Stephen Boyd <sboyd@kernel.org> + +description: + The Mediatek topckgen controller provides various clocks to the system. + The clock values can be found in <dt-bindings/clock/mt*-clk.h>. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt6797-topckgen + - mediatek,mt7622-topckgen + - mediatek,mt8135-topckgen + - mediatek,mt8173-topckgen + - mediatek,mt8516-topckgen + - items: + - const: mediatek,mt7623-topckgen + - const: mediatek,mt2701-topckgen + - const: syscon + - items: + - enum: + - mediatek,mt2701-topckgen + - mediatek,mt2712-topckgen + - mediatek,mt6765-topckgen + - mediatek,mt6779-topckgen + - mediatek,mt6795-topckgen + - mediatek,mt7629-topckgen + - mediatek,mt7981-topckgen + - mediatek,mt7986-topckgen + - mediatek,mt7988-mcusys + - mediatek,mt7988-topckgen + - mediatek,mt8167-topckgen + - mediatek,mt8183-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml new file mode 100644 index 000000000000..df2bec188706 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN966X Generic Clock Controller + +maintainers: + - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> + +description: | + The LAN966X Generic clock controller contains 3 PLLs - cpu_clk, + ddr_clk and sys_clk. This clock controller generates and supplies + clock to various peripherals within the SoC. + +properties: + compatible: + const: microchip,lan966x-gck + + reg: + minItems: 1 + items: + - description: Generic clock registers + - description: Optional gate clock registers + + clocks: + items: + - description: CPU clock source + - description: DDR clock source + - description: System clock source + + clock-names: + items: + - const: cpu + - const: ddr + - const: sys + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml new file mode 100644 index 000000000000..f1770360798f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: | + Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of + these blocks contains two PLLs and 2 DLLs & are located in the four corners of + the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: + https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html + +properties: + compatible: + const: microchip,mpfs-ccc + + reg: + items: + - description: PLL0's control registers + - description: PLL1's control registers + - description: DLL0's control registers + - description: DLL1's control registers + + clocks: + description: + The CCC PLL's have two input clocks. It is required that even if the input + clocks are identical that both are provided. + minItems: 2 + items: + - description: PLL0's refclk0 + - description: PLL0's refclk1 + - description: PLL1's refclk0 + - description: PLL1's refclk1 + - description: DLL0's refclk + - description: DLL1's refclk + + clock-names: + minItems: 2 + items: + - const: pll0_ref0 + - const: pll0_ref1 + - const: pll1_ref0 + - const: pll1_ref1 + - const: dll0_ref + - const: dll1_ref + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x38010000 0x1000>, <0x38020000 0x1000>, + <0x39010000 0x1000>, <0x39020000 0x1000>; + #clock-cells = <1>; + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + }; diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml new file mode 100644 index 000000000000..e4e1c31267d2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Clock Control Module + +maintainers: + - Daire McNamara <daire.mcnamara@microchip.com> + +description: | + Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, + which gates and enables all peripheral clocks. + + This device tree binding describes 33 gate clocks. Clocks are referenced by + user nodes by the CLKCFG node phandle and the clock index in the group, from + 0 to 32. + +properties: + compatible: + const: microchip,mpfs-clkcfg + + reg: + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Config node: + - | + #include <dt-bindings/clock/microchip,mpfs-clock.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + clkcfg: clock-controller@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + clocks = <&ref>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml new file mode 100644 index 000000000000..39559a0a598a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 DPLL Clock + +maintainers: + - Lars Povlsen <lars.povlsen@microchip.com> + +description: | + The Sparx5 DPLL clock controller generates and supplies clock to + various peripherals within the SoC. + +properties: + compatible: + const: microchip,sparx5-dpll + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock provider for eMMC: + - | + lcpll_clk: lcpll-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000000>; + }; + clks: clock-controller@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + clocks = <&lcpll_clk>; + reg = <0x1110000c 0x24>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml index 5cf0b811821e..0af1c569eb32 100644 --- a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml# +$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Milbeaut SoCs Clock Controller Binding +title: Milbeaut SoCs Clock Controller maintainers: - Taichi Sugaya <sugaya.taichi@socionext.com> @@ -18,10 +18,12 @@ description: | properties: compatible: - oneOf: - - items: - - enum: - - socionext,milbeaut-m10v-ccu + enum: + - socionext,milbeaut-m10v-ccu + + reg: + maxItems: 1 + clocks: maxItems: 1 description: external clock @@ -35,11 +37,13 @@ required: - clocks - '#clock-cells' +additionalProperties: false + examples: # Clock controller node: - | m10v-clk-ctrl@1d021000 { - compatible = "socionext,milbeaut-m10v-clk-ccu"; + compatible = "socionext,milbeaut-m10v-ccu"; reg = <0x1d021000 0x4000>; #clock-cells = <1>; clocks = <&clki40mhz>; diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file mode 100644 index 000000000000..a9ad7ab5230c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 CPU PLL + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable + PLL that can be used as the clock source for the CPU(s). + +properties: + compatible: + const: mstar,msc313-cpupll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mstar-msc313-mpll.h> + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <1>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml new file mode 100644 index 000000000000..0df5d75d4ebc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 MPLL + +maintainers: + - Daniel Palmer <daniel@thingy.jp> + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that + takes the external xtal input and multiplies it to create a high + frequency clock and divides that down into a number of clocks that + peripherals use. + +properties: + compatible: + const: mstar,msc313-mpll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + mpll@206000 { + compatible = "mstar,msc313-mpll"; + reg = <0x206000 0x200>; + #clock-cells = <1>; + clocks = <&xtal>; + }; diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..8f0c43683729 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Controller Module + +maintainers: + - Chi-Fang Li <cfli0@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + items: + - const: nuvoton,ma35d1-clk + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. + maxItems: 5 + items: + enum: + - integer + - fractional + - spread-spectrum + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + + clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x40460200 0x100>; + #clock-cells = <1>; + clocks = <&clk_hxt>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml new file mode 100644 index 000000000000..b901ca13cd25 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM8XX Clock Controller + +maintainers: + - Tomer Maimon <tmaimon77@gmail.com> + +description: | + Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which + generates and supplies clocks to all modules within the BMC. + +properties: + compatible: + enum: + - nuvoton,npcm845-clk + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full + list of NPCM8XX clock IDs. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ahb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@f0801000 { + compatible = "nuvoton,npcm845-clk"; + reg = <0x0 0xf0801000 0x0 0x1000>; + #clock-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index 9acea9d93160..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra114-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA114_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt deleted file mode 100644 index 7f02fb4ca4ad..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra124 and Tegra132 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in the header files - <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common - to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h> - (for Tegra124-specific clocks). -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. -- nvidia,external-memory-controller : phandle of the EMC driver. - -The node should contain a "emc-timings" subnode for each supported RAM type (see -field RAM_CODE in register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set - is used for. - -Each "emc-timings" node should contain a "timing" subnode for every supported -EMC clock rate. - -Required properties for "timing" nodes : -- clock-frequency : Should contain the memory clock rate to which this timing -relates. -- nvidia,parent-clock-frequency : Should contain the rate at which the current -parent of the EMC clock should be running at this timing. -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - emc-parent : the clock that should be the parent of the EMC clock at this -timing. - -Example SoC include file: - -/ { - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA124_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <112400000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; - - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml new file mode 100644 index 000000000000..a9ba21144a56 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + enum: + - nvidia,tegra124-car + - nvidia,tegra132-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + + nvidia,external-memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the external memory controller node + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that + this timing set is used for + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + external memory clock rate in Hz + minimum: 1000000 + maximum: 1000000000 + + nvidia,parent-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + rate of parent clock in Hz + minimum: 1000000 + maximum: 1000000000 + + clocks: + items: + - description: parent clock of EMC + + clock-names: + items: + - const: emc-parent + + required: + - clock-frequency + - nvidia,parent-clock-frequency + - clocks + - clock-names + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra124-car.h> + + car: clock-controller@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 958e0ad78c52..f7d347385b57 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -136,7 +136,7 @@ clock@70110000 { }; /* pinmux nodes added for completeness. Binding doc can be found in: - * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml */ pinmux: pinmux@700008d4 { diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted file mode 100644 index 6c5901b503d0..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra20 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra20-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra20-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA20_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml new file mode 100644 index 000000000000..bee2dd4b29bf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + enum: + - nvidia,tegra20-car + - nvidia,tegra30-car + - nvidia,tegra114-car + - nvidia,tegra210-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + +patternProperties: + "^(sclk)|(pll-[cem])$": + type: object + properties: + compatible: + enum: + - nvidia,tegra20-sclk + - nvidia,tegra30-sclk + - nvidia,tegra30-pllc + - nvidia,tegra30-plle + - nvidia,tegra30-pllm + + operating-points-v2: true + + clocks: + items: + - description: node's clock + + power-domains: + maxItems: 1 + description: phandle to the core SoC power domain + + required: + - compatible + - operating-points-v2 + - clocks + - power-domains + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + + car: clock-controller@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + operating-points-v2 = <&opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&domain>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt deleted file mode 100644 index 26f237f641b7..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt +++ /dev/null @@ -1,56 +0,0 @@ -NVIDIA Tegra210 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra210-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra210-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra210-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA210_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt deleted file mode 100644 index 63618cde12df..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra30 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra30-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra30-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA30_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt b/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt deleted file mode 100644 index b652f3fb7796..000000000000 --- a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt +++ /dev/null @@ -1,28 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family Standard Clocks -================================================ - -Please also refer to clock-bindings.txt in this directory for common clock -bindings usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk" - For OX820, should be "oxsemi,ox820-stdclk" -- #clock-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - stdclk: stdclk { - compatible = "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/prima2-clock.txt b/Documentation/devicetree/bindings/clock/prima2-clock.txt deleted file mode 100644 index 5016979c0f78..000000000000 --- a/Documentation/devicetree/bindings/clock/prima2-clock.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Clock bindings for CSR SiRFprimaII - -Required properties: -- compatible: Should be "sirf,prima2-clkc" -- reg: Address and length of the register set -- interrupts: Should contain clock controller interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of prima2 -clocks and IDs. - - Clock ID - --------------------------- - rtc 0 - osc 1 - pll1 2 - pll2 3 - pll3 4 - mem 5 - sys 6 - security 7 - dsp 8 - gps 9 - mf 10 - io 11 - cpu 12 - uart0 13 - uart1 14 - uart2 15 - tsc 16 - i2c0 17 - i2c1 18 - spi0 19 - spi1 20 - pwmc 21 - efuse 22 - pulse 23 - dmac0 24 - dmac1 25 - nand 26 - audio 27 - usp0 28 - usp1 29 - usp2 30 - vip 31 - gfx 32 - mm 33 - lcd 34 - vpp 35 - mmc01 36 - mmc23 37 - mmc45 38 - usbpll 39 - usb0 40 - usb1 41 - -Examples: - -clks: clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; -}; - -i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - clocks = <&clks 17>; -}; diff --git a/Documentation/devicetree/bindings/clock/pwm-clock.txt b/Documentation/devicetree/bindings/clock/pwm-clock.txt deleted file mode 100644 index 83db876b3b90..000000000000 --- a/Documentation/devicetree/bindings/clock/pwm-clock.txt +++ /dev/null @@ -1,26 +0,0 @@ -Binding for an external clock signal driven by a PWM pin. - -This binding uses the common clock binding[1] and the common PWM binding[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/pwm/pwm.txt - -Required properties: -- compatible : shall be "pwm-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- pwms : from common PWM binding; this determines the clock frequency - via the period given in the PWM specifier. - -Optional properties: -- clock-output-names : From common clock binding. -- clock-frequency : Exact output frequency, in case the PWM period - is not exact but was rounded to nanoseconds. - -Example: - clock { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "mipi_mclk"; - pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */ - }; diff --git a/Documentation/devicetree/bindings/clock/pwm-clock.yaml b/Documentation/devicetree/bindings/clock/pwm-clock.yaml new file mode 100644 index 000000000000..f88ecb2995e0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/pwm-clock.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/pwm-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: An external clock signal driven by a PWM pin. + +maintainers: + - Philipp Zabel <p.zabel@pengutronix.de> + +properties: + compatible: + const: pwm-clock + + '#clock-cells': + const: 0 + + clock-frequency: + description: Exact output frequency, in case the PWM period is not exact + but was rounded to nanoseconds. + + clock-output-names: + maxItems: 1 + + pwms: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - pwms + +additionalProperties: false + +examples: + - | + clock { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "mipi_mclk"; + pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */ + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt deleted file mode 100644 index e3fa8118eaee..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt +++ /dev/null @@ -1,22 +0,0 @@ -Qualcomm MSM8916 A53 PLL Binding --------------------------------- -The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies -above 1GHz. - -Required properties : -- compatible : Shall contain only one of the following: - - "qcom,msm8916-a53pll" - -- reg : shall contain base register location and length - -- #clock-cells : must be set to <0> - -Example: - - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0xb016000 0x40>; - #clock-cells = <0>; - }; - diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml new file mode 100644 index 000000000000..5ca927a8b1d5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm A53 PLL clock + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for + frequencies above 1GHz. + +properties: + compatible: + enum: + - qcom,ipq5018-a53pll + - qcom,ipq5332-a53pll + - qcom,ipq6018-a53pll + - qcom,ipq8074-a53pll + - qcom,ipq9574-a73pll + - qcom,msm8916-a53pll + - qcom,msm8939-a53pll + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + clocks: + items: + - description: board XO clock + + clock-names: + items: + - const: xo + + operating-points-v2: true + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Example 1 - A53 PLL found on MSM8916 devices + - | + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + # Example 2 - A53 PLL found on IPQ6018 devices + - | + a53pll_ipq: clock-controller@b116000 { + compatible = "qcom,ipq6018-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo>; + clock-names = "xo"; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml new file mode 100644 index 000000000000..809c34eb7d5a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm A7 PLL clock + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high + frequency clock to the CPU. + +properties: + compatible: + enum: + - qcom,sdx55-a7pll + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + clocks: + items: + - description: board XO clock + + clock-names: + items: + - const: bi_tcxo + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,aoncc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,aoncc-sm8250.yaml new file mode 100644 index 000000000000..8b8932bd5a92 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,aoncc-sm8250.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPASS Always ON Clock Controller on SM8250 SoCs + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h for the full list + of Audio Clock controller clock IDs. + +properties: + compatible: + const: qcom,sm8250-lpass-aoncc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio codec voting clock + - description: Glitch Free Mux register clock + + clock-names: + items: + - const: core + - const: audio + - const: bus + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> + #include <dt-bindings/sound/qcom,q6afe.h> + clock-controller@3800000 { + #clock-cells = <1>; + compatible = "qcom,sm8250-lpass-aoncc"; + reg = <0x03380000 0x40000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,audiocc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,audiocc-sm8250.yaml new file mode 100644 index 000000000000..cfca888f6014 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,audiocc-sm8250.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPASS Audio Clock Controller on SM8250 SoCs + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h for the full list + of Audio Clock controller clock IDs. + +properties: + compatible: + const: qcom,sm8250-lpass-audiocc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio codec voting clock + - description: Glitch Free Mux register clock + + clock-names: + items: + - const: core + - const: audio + - const: bus + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> + #include <dt-bindings/sound/qcom,q6afe.h> + clock-controller@3300000 { + #clock-cells = <1>; + compatible = "qcom,sm8250-lpass-audiocc"; + reg = <0x03300000 0x30000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml new file mode 100644 index 000000000000..3fd3dc1069fb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM8250 + +maintainers: + - Jonathan Marek <jonathan@marek.ca> + +description: | + Qualcomm camera clock control module provides the clocks, resets and + power domains on SM8250. + + See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sm8250-camcc + + clocks: + items: + - description: AHB + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + power-domains: + items: + - description: MMCX power domain + + reg: + maxItems: 1 + + required-opps: + maxItems: 1 + description: + OPP node describing required MMCX performance point. + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8250.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc.txt b/Documentation/devicetree/bindings/clock/qcom,camcc.txt deleted file mode 100644 index c5eb6694fda9..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,camcc.txt +++ /dev/null @@ -1,18 +0,0 @@ -Qualcomm Camera Clock & Reset Controller Binding ------------------------------------------------- - -Required properties : -- compatible : shall contain "qcom,sdm845-camcc". -- reg : shall contain base register location and length. -- #clock-cells : from common clock binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Example: - camcc: clock-controller@ad00000 { - compatible = "qcom,sdm845-camcc"; - reg = <0xad00000 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml new file mode 100644 index 000000000000..3cb996b2c9d5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SC8280XP + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains for the two MDSS instances on SC8280XP. + + See also: + include/dt-bindings/clock/qcom,dispcc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-dispcc0 + - qcom,sc8280xp-dispcc1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: SoC sleep clock + - description: DisplayPort 0 link clock + - description: DisplayPort 0 VCO div clock + - description: DisplayPort 1 link clock + - description: DisplayPort 1 VCO div clock + - description: DisplayPort 2 link clock + - description: DisplayPort 2 VCO div clock + - description: DisplayPort 3 link clock + - description: DisplayPort 3 VCO div clock + - description: DSI 0 PLL byte clock + - description: DSI 0 PLL DSI clock + - description: DSI 1 PLL byte clock + - description: DSI 1 PLL DSI clock + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + items: + - description: MMCX power domain + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@af00000 { + compatible = "qcom,sc8280xp-dispcc0"; + reg = <0x0af00000 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&mdss0_dp_phy0 0>, + <&mdss0_dp_phy0 1>, + <&mdss0_dp_phy1 0>, + <&mdss0_dp_phy1 1>, + <&mdss0_dp_phy2 0>, + <&mdss0_dp_phy2 1>, + <&mdss0_dp_phy3 0>, + <&mdss0_dp_phy3 1>, + <&mdss0_dsi0_phy 0>, + <&mdss0_dsi0_phy 1>, + <&mdss0_dsi1_phy 0>, + <&mdss0_dsi1_phy 1>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml new file mode 100644 index 000000000000..0a3ef7fd03fa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock Controller on SM6125 + +maintainers: + - Martin Botka <martin.botka@somainline.org> + +description: | + Qualcomm display clock control module provides the clocks and power domains + on SM6125. + + See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h + +properties: + compatible: + enum: + - qcom,sm6125-dispcc + + clocks: + items: + - description: Board XO source + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + - description: AHB config clock from GCC + - description: GPLL0 div source from GCC + + clock-names: + items: + - const: bi_tcxo + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dsi1_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + - const: cfg_ahb_clk + - const: gcc_disp_gpll0_div_clk_src + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing the power domain's performance point. + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6125.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@5f00000 { + compatible = "qcom,sm6125-dispcc"; + reg = <0x5f00000 0x20000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "cfg_ahb_clk", + "gcc_disp_gpll0_div_clk_src"; + + required-opps = <&rpmhpd_opp_ret>; + power-domains = <&rpmpd SM6125_VDDCX>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml new file mode 100644 index 000000000000..8efac3fb159f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SM6350 + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM6350. + + See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h + +properties: + compatible: + const: qcom,sm6350-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm6350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@af00000 { + compatible = "qcom,sm6350-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK>, + <&dsi_phy 0>, + <&dsi_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml new file mode 100644 index 000000000000..59cc88a52f6b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350 + +maintainers: + - Jonathan Marek <jonathan@marek.ca> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM8150/SM8250/SM8350. + + See also:: + include/dt-bindings/clock/qcom,dispcc-sm8150.h + include/dt-bindings/clock/qcom,dispcc-sm8250.h + include/dt-bindings/clock/qcom,dispcc-sm8350.h + +properties: + compatible: + enum: + - qcom,sc8180x-dispcc + - qcom,sm8150-dispcc + - qcom,sm8250-dispcc + - qcom,sm8350-dispcc + + clocks: + items: + - description: Board XO source + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dsi1_phy_pll_out_byteclk + - const: dsi1_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@af00000 { + compatible = "qcom,sm8250-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt deleted file mode 100644 index d639e18d0b85..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt +++ /dev/null @@ -1,19 +0,0 @@ -Qualcomm Technologies, Inc. Display Clock Controller Binding ------------------------------------------------------------- - -Required properties : - -- compatible : shall contain "qcom,sdm845-dispcc" -- reg : shall contain base register location and length. -- #clock-cells : from common clock binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. - -Example: - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x100000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml new file mode 100644 index 000000000000..19211176ee0b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on APQ8064. + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8960.h + include/dt-bindings/reset/qcom,gcc-msm8960.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,gcc-apq8064 + - qcom,gcc-msm8960 + - const: syscon + - enum: + - qcom,gcc-apq8064 + - qcom,gcc-msm8960 + deprecated: true + + thermal-sensor: + description: child tsens device + $ref: /schemas/thermal/qcom-tsens.yaml# + + clocks: + maxItems: 3 + + clock-names: + items: + - const: cxo + - const: pxo + - const: pll4 + + nvmem-cells: + minItems: 1 + maxItems: 2 + deprecated: true + description: + Qualcomm TSENS (thermal sensor device) on some devices can + be part of GCC and hence the TSENS properties can also be part + of the GCC/clock-controller node. + For more details on the TSENS properties please refer + Documentation/devicetree/bindings/thermal/qcom-tsens.yaml + + nvmem-cell-names: + minItems: 1 + deprecated: true + items: + - const: calib + - const: calib_backup + + '#thermal-sensor-cells': + const: 1 + deprecated: true + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-apq8064", "syscon"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <0 178 4>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml new file mode 100644 index 000000000000..d84608269080 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on APQ8084 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on APQ8084. + + See also:: + include/dt-bindings/clock/qcom,gcc-apq8084.h + include/dt-bindings/reset/qcom,gcc-apq8084.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-apq8084 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: UFS RX symbol 0 clock + - description: UFS RX symbol 1 clock + - description: UFS TX symbol 0 clock + - description: UFS TX symbol 1 clock + - description: SATA ASIC0 clock + - description: SATA RX clock + - description: PCIe PIPE clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: ufs_rx_symbol_0_clk_src + - const: ufs_rx_symbol_1_clk_src + - const: ufs_tx_symbol_0_clk_src + - const: ufs_tx_symbol_1_clk_src + - const: sata_asic0_clk + - const: sata_rx_clk + - const: pcie_pipe + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */ + clock-controller@fc400000 { + compatible = "qcom,gcc-apq8084"; + reg = <0xfc400000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&ufsphy 0>, + <&ufsphy 1>, + <&ufsphy 2>, + <&ufsphy 3>, + <&sata 0>, + <&sata 1>, + <&pcie_phy>; + clock-names = "xo", + "sleep_clk", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src", + "ufs_tx_symbol_1_clk_src", + "sata_asic0_clk", + "sata_rx_clk", + "pcie_pipe"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml new file mode 100644 index 000000000000..fb3957d485f9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ4019 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + - Robert Marko <robert.markoo@sartura.hr> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ4019. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-ipq4019 + + clocks: + items: + - description: board XO clock + - description: sleep clock + + clock-names: + items: + - const: xo + - const: sleep_clk + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq4019"; + reg = <0x1800000 0x60000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&xo>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml new file mode 100644 index 000000000000..af5d883cfdc8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ6018 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + - Robert Marko <robimarko@gmail.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ6018. + + See also:: + include/dt-bindings/clock/qcom,gcc-ipq6018.h + include/dt-bindings/reset/qcom,gcc-ipq6018.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-ipq6018 + + clocks: + items: + - description: board XO clock + - description: sleep clock + + clock-names: + items: + - const: xo + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq6018"; + reg = <0x01800000 0x80000>; + clocks = <&xo>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file mode 100644 index 000000000000..93f3084b97c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ8064 + +maintainers: + - Ansuel Smith <ansuelsmth@gmail.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ8064. + + See also:: + include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + items: + - const: qcom,gcc-ipq8064 + - const: syscon + + clocks: + minItems: 2 + items: + - description: PXO source + - description: CXO source + - description: PLL4 from LCC + + clock-names: + minItems: 2 + items: + - const: pxo + - const: cxo + - const: pll4 + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,lcc-ipq806x.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; + clock-names = "pxo", "cxo", "pll4"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml new file mode 100644 index 000000000000..2d44ddc45aab --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ8074 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ8074. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-ipq8074 + + clocks: + items: + - description: board XO clock + - description: sleep clock + - description: Gen3 QMP PCIe PHY PIPE clock + - description: Gen2 QMP PCIe PHY PIPE clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: pcie0_pipe + - const: pcie1_pipe + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml new file mode 100644 index 000000000000..c9e985548621 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8660 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks and resets on + MSM8660 + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8660.h + include/dt-bindings/reset/qcom,gcc-msm8660.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-msm8660 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pxo + - const: cxo + +required: + - compatible + +unevaluatedProperties: false + +examples: + # Example for GCC for MSM8974: + - | + clock-controller@900000 { + compatible = "qcom,gcc-msm8660"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml new file mode 100644 index 000000000000..b91462587df5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215 + +maintainers: + - Stephan Gerhold <stephan@gerhold.net> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8909, MSM8917 or QM215. + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8909.h + include/dt-bindings/clock/qcom,gcc-msm8917.h + +properties: + compatible: + enum: + - qcom,gcc-msm8909 + - qcom,gcc-msm8917 + - qcom,gcc-qm215 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: dsi0pll + - const: dsi0pllbyte + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8909"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>; + clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml new file mode 100644 index 000000000000..ad84c0f7680b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8916 or MSM8939. + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8916.h + include/dt-bindings/clock/qcom,gcc-msm8939.h + include/dt-bindings/reset/qcom,gcc-msm8916.h + include/dt-bindings/reset/qcom,gcc-msm8939.h + +properties: + compatible: + enum: + - qcom,gcc-msm8916 + - qcom,gcc-msm8939 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: External MCLK clock + - description: External Primary I2S clock + - description: External Secondary I2S clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: dsi0pll + - const: dsi0pllbyte + - const: ext_mclk + - const: ext_pri_i2s + - const: ext_sec_i2s + +required: + - compatible + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8916"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x300000 0x90000>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml new file mode 100644 index 000000000000..fe9fd4cb185f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8953 + +maintainers: + - Adam Skladowski <a_skl39@protonmail.com> + - Sireesh Kodali <sireeshkodali@protonmail.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8953. + + See also: include/dt-bindings/clock/qcom,gcc-msm8953.h + +properties: + compatible: + const: qcom,gcc-msm8953 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + + clock-names: + items: + - const: xo + - const: sleep + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + + clock-controller@1800000 { + compatible = "qcom,gcc-msm8953"; + reg = <0x01800000 0x80000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml new file mode 100644 index 000000000000..1927aecc86bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226 + Controller + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8974 (all variants) and MSM8226. + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + +$ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-msm8226 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + + clocks: + items: + - description: XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep_clk + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974"; + reg = <0x00100000 0x94000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, + <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml new file mode 100644 index 000000000000..62d6f1fe1228 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8976 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8976. + + See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h + +properties: + compatible: + enum: + - qcom,gcc-msm8976 + - qcom,gcc-msm8976-v1.1 + + clocks: + items: + - description: XO source + - description: Always-on XO source + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Byte clock from DSI PHY1 + + clock-names: + items: + - const: xo + - const: xo_a + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + + vdd_gfx-supply: + description: + Phandle to voltage regulator providing power to the GX domain. + +required: + - compatible + - clocks + - clock-names + - vdd_gfx-supply + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-msm8976"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x1800000 0x80000>; + + clocks = <&xo_board>, + <&xo_board>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; + + clock-names = "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + + vdd_gfx-supply = <&pm8004_s5>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml new file mode 100644 index 000000000000..8f0f20c1442a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8994 + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8994 and MSM8992. + + See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h + +properties: + compatible: + enum: + - qcom,gcc-msm8992 + - qcom,gcc-msm8994 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8994"; + reg = <0x00300000 0x90000>; + clocks = <&xo_board>, <&sleep_clk>; + clock-names = "xo", "sleep"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml new file mode 100644 index 000000000000..97523cc1ecfb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8996 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module which provides the clocks, resets and + power domains on MSM8996. + + See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h + +properties: + compatible: + const: qcom,gcc-msm8996 + + clocks: + minItems: 3 + items: + - description: XO source + - description: Second XO source + - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: PCIe 1 PIPE clock (optional) + - description: PCIe 2 PIPE clock (optional) + - description: USB3 PIPE clock (optional) + - description: UFS RX symbol 0 clock (optional) + - description: UFS RX symbol 1 clock (optional) + - description: UFS TX symbol 0 clock (optional) + + clock-names: + minItems: 3 + items: + - const: cxo + - const: cxo2 + - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: pcie_1_pipe_clk_src + - const: pcie_2_pipe_clk_src + - const: usb3_phy_pipe_clk_src + - const: ufs_rx_symbol_0_clk_src + - const: ufs_rx_symbol_1_clk_src + - const: ufs_tx_symbol_0_clk_src + +required: + - compatible + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x300000 0x90000>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml new file mode 100644 index 000000000000..58f7fb22c5c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8998 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8998. + + See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h + +properties: + compatible: + const: qcom,gcc-msm8998 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Audio reference clock (Optional clock) + minItems: 2 + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: aud_ref_clk # Optional clock + minItems: 2 + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@100000 { + compatible = "qcom,gcc-msm8998"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x00100000 0xb0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep>, + <0>; + clock-names = "xo", + "sleep_clk", + "aud_ref_clk"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml new file mode 100644 index 000000000000..7d05f0f63cef --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains. + + See also:: + include/dt-bindings/clock/qcom,gcc-msm8953.h + include/dt-bindings/clock/qcom,gcc-mdm9607.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-mdm9607 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-mdm9607"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml new file mode 100644 index 000000000000..c9bec4656f6e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on QCM2290 + +maintainers: + - Shawn Guo <shawn.guo@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on QCM2290. + + See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h + +properties: + compatible: + const: qcom,gcc-qcm2290 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@1400000 { + compatible = "qcom,gcc-qcm2290"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml new file mode 100644 index 000000000000..7bc6c57e4d11 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on QCS404 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on QCS404. + + See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h + +properties: + compatible: + const: qcom,gcc-qcs404 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: cxo + - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: hdmi_pll + +required: + - compatible + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml new file mode 100644 index 000000000000..7aae21a76690 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SC7180 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SC7180. + + See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h + +properties: + compatible: + const: qcom,gcc-sc7180 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + power-domains: + items: + - description: CX domain + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SC7180_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml new file mode 100644 index 000000000000..c4ca08d9ad5a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SC7280 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SC7280. + + See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h + +properties: + compatible: + const: qcom,gcc-sc7280 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE-0 pipe clock source + - description: PCIE-1 pipe clock source + - description: USF phy rx symbol 0 clock source + - description: USF phy rx symbol 1 clock source + - description: USF phy tx symbol 0 clock source + - description: USB30 phy wrapper pipe clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_0_pipe_clk + - const: pcie_1_pipe_clk + - const: ufs_phy_rx_symbol_0_clk + - const: ufs_phy_rx_symbol_1_clk + - const: ufs_phy_tx_symbol_0_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + + power-domains: + items: + - description: CX domain + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + clock-controller@100000 { + compatible = "qcom,gcc-sc7280"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, + <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", + "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + power-domains = <&rpmhpd SC7280_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml new file mode 100644 index 000000000000..6c4846b34e4b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SC8180x + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SC8180x. + + See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h + +properties: + compatible: + const: qcom,gcc-sc8180x + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sc8180x"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml new file mode 100644 index 000000000000..5681e535fede --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SC8280xp + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on SC8280xp. + + See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h + +properties: + compatible: + const: qcom,gcc-sc8280xp + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: UFS memory first RX symbol clock + - description: UFS memory second RX symbol clock + - description: UFS memory first TX symbol clock + - description: UFS card first RX symbol clock + - description: UFS card second RX symbol clock + - description: UFS card first TX symbol clock + - description: Primary USB SuperSpeed pipe clock + - description: USB4 PHY pipegmux clock source + - description: USB4 PHY DP gmux clock source + - description: USB4 PHY sys pipegmux clock source + - description: USB4 PHY PCIe pipe clock + - description: USB4 PHY router max pipe clock + - description: Primary USB4 RX0 clock + - description: Primary USB4 RX1 clock + - description: Secondary USB SuperSpeed pipe clock + - description: Second USB4 PHY pipegmux clock source + - description: Second USB4 PHY DP gmux clock source + - description: Second USB4 PHY sys pipegmux clock source + - description: Second USB4 PHY PCIe pipe clock + - description: Second USB4 PHY router max pipe clock + - description: Secondary USB4 RX0 clock + - description: Secondary USB4 RX1 clock + - description: Multiport USB first SuperSpeed pipe clock + - description: Multiport USB second SuperSpeed pipe clock + - description: PCIe 2a pipe clock + - description: PCIe 2b pipe clock + - description: PCIe 3a pipe clock + - description: PCIe 3b pipe clock + - description: PCIe 4 pipe clock + - description: First EMAC controller reference clock + - description: Second EMAC controller reference clock + + power-domains: + items: + - description: CX domain + + protected-clocks: + maxItems: 389 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + clock-controller@100000 { + compatible = "qcom,gcc-sc8280xp"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&ufs_card_rx_symbol_0_clk>, + <&ufs_card_rx_symbol_1_clk>, + <&ufs_card_tx_symbol_0_clk>, + <&usb_0_ssphy>, + <&gcc_usb4_phy_pipegmux_clk_src>, + <&gcc_usb4_phy_dp_gmux_clk_src>, + <&gcc_usb4_phy_sys_pipegmux_clk_src>, + <&usb4_phy_gcc_usb4_pcie_pipe_clk>, + <&usb4_phy_gcc_usb4rtr_max_pipe_clk>, + <&qusb4phy_gcc_usb4_rx0_clk>, + <&qusb4phy_gcc_usb4_rx1_clk>, + <&usb_1_ssphy>, + <&gcc_usb4_1_phy_pipegmux_clk_src>, + <&gcc_usb4_1_phy_dp_gmux_clk_src>, + <&gcc_usb4_1_phy_sys_pipegmux_clk_src>, + <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>, + <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>, + <&qusb4phy_1_gcc_usb4_rx0_clk>, + <&qusb4phy_1_gcc_usb4_rx1_clk>, + <&usb_2_ssphy>, + <&usb_3_ssphy>, + <&pcie2a_lane>, + <&pcie2b_lane>, + <&pcie3a_lane>, + <&pcie3b_lane>, + <&pcie4_lane>, + <&rxc0_ref_clk>, + <&rxc1_ref_clk>; + power-domains = <&rpmhpd SC8280XP_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml new file mode 100644 index 000000000000..52e7412aace5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660/SDM630/SDM636 Global Clock & Reset Controller + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDM630, SDM636 and SDM660 + + See also:: + include/dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) + +$ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + + clocks: + items: + - description: XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep_clk + + power-domains: + maxItems: 1 + +required: + - compatible + +unevaluatedProperties: false + +examples: + # Example for GCC for SDM660: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sdm660"; + reg = <0x00100000 0x94000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, + <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml new file mode 100644 index 000000000000..0595da0e8a42 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDM670 and SDM845 + + See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h + +properties: + compatible: + enum: + - qcom,gcc-sdm670 + - qcom,gcc-sdm845 + + clocks: + minItems: 3 + maxItems: 5 + + clock-names: + minItems: 3 + maxItems: 5 + + power-domains: + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,gcc-sdm670 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + - if: + properties: + compatible: + contains: + const: qcom,gcc-sdm845 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_0_pipe_clk + - const: pcie_1_pipe_clk + +unevaluatedProperties: false + +examples: + # Example for GCC for SDM845: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_lane>, + <&pcie1_lane>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml new file mode 100644 index 000000000000..428e954d7638 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX55 + +maintainers: + - Vinod Koul <vkoul@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on SDX55 + + See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h + +properties: + compatible: + const: qcom,gcc-sdx55 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sdx55"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml new file mode 100644 index 000000000000..523e18d7f150 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX65 + +maintainers: + - Vamsi krishna Lanka <quic_vamslank@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDX65 + + See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h + +properties: + compatible: + const: qcom,gcc-sdx65 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_pipe_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x100000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml new file mode 100644 index 000000000000..a5ad0a3da397 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM6115 and SM4250 + +maintainers: + - Iskren Chernev <iskren.chernev@gmail.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM4250/6115. + + See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h + +properties: + compatible: + const: qcom,gcc-sm6115 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml new file mode 100644 index 000000000000..8e37623788bd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM6125. + + See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h + +properties: + compatible: + const: qcom,gcc-sm6125 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@1400000 { + compatible = "qcom,gcc-sm6125"; + reg = <0x01400000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml new file mode 100644 index 000000000000..d1b26ab48eaf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM6350 + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM6350. + + See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h + +properties: + compatible: + const: qcom,gcc-sm6350 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm6350"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml new file mode 100644 index 000000000000..58ccb7df847c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8150 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8150. + + See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h + +properties: + compatible: + const: qcom,gcc-sm8150 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8150"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml new file mode 100644 index 000000000000..5d77c092be5b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8250 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8250. + + See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h + +properties: + compatible: + const: qcom,gcc-sm8250 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8250"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml new file mode 100644 index 000000000000..b4fdde71ef18 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8350 + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8350. + + See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h + +properties: + compatible: + const: qcom,gcc-sm8350 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: UFS card Rx symbol 0 clock source (Optional clock) + - description: UFS card Rx symbol 1 clock source (Optional clock) + - description: UFS card Tx symbol 0 clock source (Optional clock) + - description: UFS phy Rx symbol 0 clock source (Optional clock) + - description: UFS phy Rx symbol 1 clock source (Optional clock) + - description: UFS phy Tx symbol 0 clock source (Optional clock) + - description: USB3 phy wrapper pipe clock source (Optional clock) + - description: USB3 phy sec pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: ufs_card_rx_symbol_0_clk # Optional clock + - const: ufs_card_rx_symbol_1_clk # Optional clock + - const: ufs_card_tx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8350"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml new file mode 100644 index 000000000000..75259f468d54 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8450 + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8450 + + See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h + +properties: + compatible: + const: qcom,gcc-sm8450 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: PCIE 1 Phy Auxiliary clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: pcie_1_phy_aux_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index e73a56fb60ca..788825105f24 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -1,60 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/qcom,gcc.yaml# +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller Binding +title: Qualcomm Global Clock & Reset Controller Common Properties maintainers: - Stephen Boyd <sboyd@kernel.org> - - Taniya Das <tdas@codeaurora.org> + - Taniya Das <quic_tdas@quicinc.com> description: | - Qualcomm global clock control module which supports the clocks, resets and - power domains. + Common bindings for Qualcomm global clock control module providing the + clocks, resets and power domains. properties: - compatible : - enum: - - qcom,gcc-apq8064 - - qcom,gcc-apq8084 - - qcom,gcc-ipq8064 - - qcom,gcc-ipq4019 - - qcom,gcc-ipq8074 - - qcom,gcc-msm8660 - - qcom,gcc-msm8916 - - qcom,gcc-msm8960 - - qcom,gcc-msm8974 - - qcom,gcc-msm8974pro - - qcom,gcc-msm8974pro-ac - - qcom,gcc-msm8994 - - qcom,gcc-msm8996 - - qcom,gcc-msm8998 - - qcom,gcc-mdm9615 - - qcom,gcc-qcs404 - - qcom,gcc-sc7180 - - qcom,gcc-sdm630 - - qcom,gcc-sdm660 - - qcom,gcc-sdm845 - - qcom,gcc-sm8150 - - clocks: - minItems: 1 - maxItems: 3 - items: - - description: Board XO source - - description: Board active XO source - - description: Sleep clock source - - clock-names: - minItems: 1 - maxItems: 3 - items: - - const: bi_tcxo - - const: bi_tcxo_ao - - const: sleep_clk - '#clock-cells': const: 1 @@ -67,122 +27,16 @@ properties: reg: maxItems: 1 - nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Qualcomm TSENS (thermal sensor device) on some devices can - be part of GCC and hence the TSENS properties can also be part - of the GCC/clock-controller node. - For more details on the TSENS properties please refer - Documentation/devicetree/bindings/thermal/qcom-tsens.txt - - nvmem-cell-names: - minItems: 1 - maxItems: 2 - description: - Names for each nvmem-cells specified. - items: - - const: calib - - const: calib_backup - - 'thermal-sensor-cells': - const: 1 - protected-clocks: description: - Protected clock specifier list as per common clock binding + Protected clock specifier list as per common clock binding. required: - - compatible - reg - '#clock-cells' - '#reset-cells' - '#power-domain-cells' -if: - properties: - compatible: - contains: - const: qcom,gcc-apq8064 - -then: - required: - - nvmem-cells - - nvmem-cell-names - - '#thermal-sensor-cells' - -else: - if: - properties: - compatible: - contains: - enum: - - qcom,gcc-sm8150 - - qcom,gcc-sc7180 - then: - required: - - clocks - - clock-names - - -examples: - # Example for GCC for MSM8960: - - | - clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - reg = <0x900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - - # Example of GCC with TSENS properties: - - | - clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - #thermal-sensor-cells = <1>; - }; - - # Example of GCC with protected-clocks properties: - - | - clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; - protected-clocks = <187>, <188>, <189>, <190>, <191>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - # Example of GCC with clock node properties for SM8150: - - | - clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x00100000 0x1f0000>; - clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; +additionalProperties: true - # Example of GCC with clock nodes properties for SC7180: - - | - clock-controller@100000 { - compatible = "qcom,gcc-sc7180"; - reg = <0x100000 0x1f0000>; - clocks = <&rpmhcc 0>, <&rpmhcc 1>; - clock-names = "bi_tcxo", "bi_tcxo_ao"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml new file mode 100644 index 000000000000..0518ea963cdd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM660 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and + power domains on SDM630 and SDM660. + + See also dt-bindings/clock/qcom,gpucc-sdm660.h. + +properties: + compatible: + enum: + - qcom,gpucc-sdm630 + - qcom,gpucc-sdm660 + + clocks: + items: + - description: Board XO source + - description: GPLL0 main gpu branch + - description: GPLL0 divider gpu branch + + clock-names: + items: + - const: xo + - const: gcc_gpu_gpll0_clk + - const: gcc_gpu_gpll0_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm660.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + + clock-controller@5065000 { + compatible = "qcom,gpucc-sdm660"; + reg = <0x05065000 0x9038>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "xo", "gcc_gpu_gpll0_clk", + "gcc_gpu_gpll0_div_clk"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt deleted file mode 100644 index 269afe8a757e..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ /dev/null @@ -1,24 +0,0 @@ -Qualcomm Graphics Clock & Reset Controller Binding --------------------------------------------------- - -Required properties : -- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1 -- #reset-cells : from common reset binding, shall contain 1 -- #power-domain-cells : from generic power domain binding, shall contain 1 -- clocks : shall contain the XO clock - shall contain the gpll0 out main clock (msm8998) -- clock-names : shall be "xo" - shall be "gpll0" (msm8998) - -Example: - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml new file mode 100644 index 000000000000..f369fa34e00c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,gpucc-sdm845.h + include/dt-bindings/clock/qcom,gpucc-sa8775p.h + include/dt-bindings/clock/qcom,gpucc-sc7180.h + include/dt-bindings/clock/qcom,gpucc-sc7280.h + include/dt-bindings/clock/qcom,gpucc-sc8280xp.h + include/dt-bindings/clock/qcom,gpucc-sm6350.h + include/dt-bindings/clock/qcom,gpucc-sm8150.h + include/dt-bindings/clock/qcom,gpucc-sm8250.h + include/dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sdm845-gpucc + - qcom,sa8775p-gpucc + - qcom,sc7180-gpucc + - qcom,sc7280-gpucc + - qcom,sc8180x-gpucc + - qcom,sc8280xp-gpucc + - qcom,sm6350-gpucc + - qcom,sm8150-gpucc + - qcom,sm8250-gpucc + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk_src + - const: gcc_gpu_gpll0_div_clk_src + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x05090000 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt index ec02a024424c..5769cbbe76be 100644 --- a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt @@ -12,6 +12,9 @@ PROPERTIES "qcom,hfpll-apq8064", "qcom,hfpll" "qcom,hfpll-msm8974", "qcom,hfpll" "qcom,hfpll-msm8960", "qcom,hfpll" + "qcom,msm8976-hfpll-a53", "qcom,hfpll" + "qcom,msm8976-hfpll-a72", "qcom,hfpll" + "qcom,msm8976-hfpll-cci", "qcom,hfpll" - reg: Usage: required diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml new file mode 100644 index 000000000000..ef84a0c95f7e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5018 + +maintainers: + - Sricharan Ramabadhran <quic_srichara@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5018 + + See also:: + include/dt-bindings/clock/qcom,ipq5018-gcc.h + include/dt-bindings/reset/qcom,ipq5018-gcc.h + +properties: + compatible: + const: qcom,gcc-ipq5018 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE20 PHY0 pipe clock source + - description: PCIE20 PHY1 pipe clock source + - description: USB3 PHY pipe clock source + - description: GEPHY RX clock source + - description: GEPHY TX clock source + - description: UNIPHY RX clock source + - description: UNIPHY TX clk source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq5018"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie20_phy0_pipe_clk>, + <&pcie20_phy1_pipe_clk>, + <&usb3_phy0_pipe_clk>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, + <&uniphy_rx_clk>, + <&uniphy_tx_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml new file mode 100644 index 000000000000..718fe0625424 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5332 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5332. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-gcc + + clocks: + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: USB PCIE wrapper pipe clock source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_2lane_phy_pipe_clk>, + <&pcie_2lane_phy_pipe_clk_x1>, + <&usb_pcie_wrapper_pipe_clk>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml new file mode 100644 index 000000000000..944a0ea79cd6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9574 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Anusha Rao <quic_anusha@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-gcc.h + include/dt-bindings/reset/qcom,ipq9574-gcc.h + +properties: + compatible: + const: qcom,ipq9574-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Bias PLL ubi clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: USB3 PHY pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9574-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&bias_pll_ubi_nc_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml new file mode 100644 index 000000000000..57632757d4e6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1 + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. ACC v1 is currently used as a + clock-controller for enabling the cpu and handling the aux clocks. + +properties: + compatible: + const: qcom,kpss-acc-v1 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + minItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..88b7672123a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation) and provide access + to the kpss-gcc registers. + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - qcom,kpss-gcc-msm8660 + - qcom,kpss-gcc-mdm9615 + - const: qcom,kpss-gcc + - const: syscon + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pll8_vote + - const: pxo + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 +then: + required: + - clocks + - clock-names + - '#clock-cells' +else: + properties: + clock: false + clock-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + - | + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt deleted file mode 100644 index a3c78aa88038..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,lcc.txt +++ /dev/null @@ -1,22 +0,0 @@ -Qualcomm LPASS Clock & Reset Controller Binding ------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,lcc-msm8960" - "qcom,lcc-apq8064" - "qcom,lcc-ipq8064" - "qcom,lcc-mdm9615" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Example: - clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml new file mode 100644 index 000000000000..55985e562a34 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,lcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Clock & Reset Controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + enum: + - qcom,lcc-apq8064 + - qcom,lcc-ipq8064 + - qcom,lcc-mdm9615 + - qcom,lcc-msm8960 + + clocks: + maxItems: 8 + + clock-names: + maxItems: 8 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,lcc-apq8064 + - qcom,lcc-msm8960 + then: + properties: + clocks: + items: + - description: Board PXO source + - description: PLL 4 Vote clock + - description: MI2S codec clock + - description: Mic I2S codec clock + - description: Mic I2S spare clock + - description: Speaker I2S codec clock + - description: Speaker I2S spare clock + - description: PCM codec clock + + clock-names: + items: + - const: pxo + - const: pll4_vote + - const: mi2s_codec_clk + - const: codec_i2s_mic_codec_clk + - const: spare_i2s_mic_codec_clk + - const: codec_i2s_spkr_codec_clk + - const: spare_i2s_spkr_codec_clk + - const: pcm_codec_clk + + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + enum: + - qcom,lcc-mdm9615 + then: + properties: + clocks: + items: + - description: Board CXO source + - description: PLL 4 Vote clock + - description: MI2S codec clock + - description: Mic I2S codec clock + - description: Mic I2S spare clock + - description: Speaker I2S codec clock + - description: Speaker I2S spare clock + - description: PCM codec clock + + clock-names: + items: + - const: cxo + - const: pll4_vote + - const: mi2s_codec_clk + - const: codec_i2s_mic_codec_clk + - const: spare_i2s_mic_codec_clk + - const: codec_i2s_spkr_codec_clk + - const: spare_i2s_spkr_codec_clk + - const: pcm_codec_clk + + required: + - clocks + - clock-names + +examples: + - | + clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt deleted file mode 100644 index b9e9787045b9..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt +++ /dev/null @@ -1,26 +0,0 @@ -Qualcomm LPASS Clock Controller Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain "qcom,sdm845-lpasscc" -- #clock-cells : from common clock binding, shall contain 1. -- reg : shall contain base register address and size, - in the order - Index-0 maps to LPASS_CC register region - Index-1 maps to LPASS_QDSP6SS register region - -Optional properties : -- reg-names : register names of LPASS domain - "cc", "qdsp6ss". - -Example: - -The below node has to be defined in the cases where the LPASS peripheral loader -would bring the subsystem out of reset. - - lpasscc: clock-controller@17014000 { - compatible = "qcom,sdm845-lpasscc"; - reg = <0x17014000 0x1f004>, <0x17300000 0x200>; - reg-names = "cc", "qdsp6ss"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt deleted file mode 100644 index 8b0f7841af8d..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Qualcomm Multimedia Clock & Reset Controller Binding ----------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,mmcc-apq8064" - "qcom,mmcc-apq8084" - "qcom,mmcc-msm8660" - "qcom,mmcc-msm8960" - "qcom,mmcc-msm8974" - "qcom,mmcc-msm8996" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Optional properties : -- #power-domain-cells : shall contain 1 - -Example: - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml new file mode 100644 index 000000000000..aa35a40648ba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -0,0 +1,360 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multimedia Clock & Reset Controller + +maintainers: + - Jeffrey Hugo <quic_jhugo@quicinc.com> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm multimedia clock control module provides the clocks, resets and + power domains. + +properties: + compatible: + enum: + - qcom,mmcc-apq8064 + - qcom,mmcc-apq8084 + - qcom,mmcc-msm8226 + - qcom,mmcc-msm8660 + - qcom,mmcc-msm8960 + - qcom,mmcc-msm8974 + - qcom,mmcc-msm8992 + - qcom,mmcc-msm8994 + - qcom,mmcc-msm8996 + - qcom,mmcc-msm8998 + - qcom,mmcc-sdm630 + - qcom,mmcc-sdm660 + + clocks: + minItems: 7 + maxItems: 13 + + clock-names: + minItems: 7 + maxItems: 13 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + + vdd-gfx-supply: + description: + Regulator supply for the GPU_GX GDSC + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-apq8064 + - qcom,mmcc-msm8960 + then: + properties: + clocks: + items: + - description: Board PXO source + - description: PLL 3 clock + - description: PLL 3 Vote clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: DSI phy instance 2 dsi clock + - description: DSI phy instance 2 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: pxo + - const: pll3 + - const: pll8_vote + - const: dsi1pll + - const: dsi1pllbyte + - const: dsi2pll + - const: dsi2pllbyte + - const: hdmipll + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-msm8226 + then: + properties: + clocks: + items: + - description: Board XO source + - description: MMSS GPLL0 voted clock + - description: GPLL0 voted clock + - description: GPLL1 voted clock + - description: GFX3D clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + clock-names: + items: + - const: xo + - const: mmss_gpll0_vote + - const: gpll0_vote + - const: gpll1_vote + - const: gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-msm8974 + then: + properties: + clocks: + items: + - description: Board XO source + - description: MMSS GPLL0 voted clock + - description: GPLL0 voted clock + - description: GPLL1 voted clock + - description: GFX3D clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: eDP phy PLL link clock + - description: eDP phy PLL vco clock + + clock-names: + items: + - const: xo + - const: mmss_gpll0_vote + - const: gpll0_vote + - const: gpll1_vote + - const: gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + - const: edp_link_clk + - const: edp_vco_div + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-apq8084 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: MMSS GPLL0 voted clock + - description: GPLL0 clock + - description: GPLL0 voted clock + - description: GPLL1 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: eDP phy PLL link clock + - description: eDP phy PLL vco clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: mmss_gpll0_vote + - const: gpll0 + - const: gpll0_vote + - const: gpll1 + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + - const: edp_link_clk + - const: edp_vco_div + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-msm8994 + - qcom,mmcc-msm8998 + - qcom,mmcc-sdm630 + - qcom,mmcc-sdm660 + then: + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8994 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Global PLL 0 clock + - description: MMSS NoC AHB clock + - description: GFX3D clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: xo + - const: gpll0 + - const: mmssnoc_ahb + - const: oxili_gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + + - if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8996 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Global PLL 0 clock + - description: MMSS NoC AHB clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: xo + - const: gpll0 + - const: gcc_mmss_noc_cfg_ahb_clk + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + + - if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8998 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Global PLL 0 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: DisplayPort phy PLL link clock + - description: DisplayPort phy PLL vco clock + - description: Global PLL 0 DIV clock + + clock-names: + items: + - const: xo + - const: gpll0 + - const: dsi0dsi + - const: dsi0byte + - const: dsi1dsi + - const: dsi1byte + - const: hdmipll + - const: dplink + - const: dpvco + - const: gpll0_div + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-sdm630 + - qcom,mmcc-sdm660 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: Global PLL 0 clock + - description: Global PLL 0 DIV clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: DisplayPort phy PLL link clock + - description: DisplayPort phy PLL vco clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: gpll0 + - const: gpll0_div + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: dp_link_2x_clk_divsel_five + - const: dp_vco_divided_clk_src_mux + +examples: + # Example for MMCC for MSM8960: + - | + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml new file mode 100644 index 000000000000..fcace96c72eb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,msm8996-apcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm clock controller for MSM8996 CPUs + +maintainers: + - Loic Poulain <loic.poulain@linaro.org> + +description: | + Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster + and clock 1 is for Perf cluster. + +properties: + compatible: + enum: + - qcom,msm8996-apcc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: XO source + - description: SYS APCS AUX clock + + clock-names: + items: + - const: xo + - const: sys_apcs_aux + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + kryocc: clock-controller@6400000 { + compatible = "qcom,msm8996-apcc"; + reg = <0x6400000 0x90000>; + #clock-cells = <1>; + + clocks = <&xo_board>, <&apcs_glb>; + clock-names = "xo", "sys_apcs_aux"; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml new file mode 100644 index 000000000000..0dfbd8c4d465 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,msm8996-cbf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8996 Core Bus Fabric (CBF) clock controller + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: > + The clock controller for the Qualcomm MSM8996 CBF clock, which drives the + interconnect between two CPU clusters. + +properties: + compatible: + enum: + - qcom,msm8996-cbf + - qcom,msm8996pro-cbf + + reg: + maxItems: 1 + + clocks: + items: + - description: XO source + - description: SYS APCS AUX clock + + '#clock-cells': + const: 0 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@9a11000 { + compatible = "qcom,msm8996-cbf"; + reg = <0x09a11000 0x10000>; + clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&apcs_glb>; + #clock-cells = <0>; + #interconnect-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml new file mode 100644 index 000000000000..7b271ae210a3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on MSM8998 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on MSM8998. + + See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h + +properties: + compatible: + const: qcom,msm8998-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) + + clock-names: + items: + - const: xo + - const: gpll0 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@5065000 { + compatible = "qcom,msm8998-gpucc"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x05065000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>; + clock-names = "xo", "gpll0"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml index bbaaf1e2a203..03fa30fe9253 100644 --- a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml @@ -11,7 +11,7 @@ maintainers: properties: compatible: - const: "qcom,qcs404-q6sstopcc" + const: qcom,qcs404-q6sstopcc reg: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml new file mode 100644 index 000000000000..4a00f2d41684 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on QCM2290 + +maintainers: + - Loic Poulain <loic.poulain@linaro.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on qcm2290. + + See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h + +properties: + compatible: + const: qcom,qcm2290-dispcc + + clocks: + items: + - description: Board XO source + - description: Board active-only XO source + - description: GPLL0 source from GCC + - description: GPLL0 div source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: gcc_disp_gpll0_clk_src + - const: gcc_disp_gpll0_div_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@5f00000 { + compatible = "qcom,qcm2290-dispcc"; + reg = <0x5f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml new file mode 100644 index 000000000000..fd21df0e7697 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + - Imran Shaik <quic_imrashai@quicinc.com> + +description: | + Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control + module which supports the clocks, resets on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h + +properties: + compatible: + enum: + - qcom,qdu1000-ecpricc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: GPLL1 source from GCC + - description: GPLL2 source from GCC + - description: GPLL3 source from GCC + - description: GPLL4 source from GCC + - description: GPLL5 source from GCC + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,qdu1000-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@280000 { + compatible = "qcom,qdu1000-ecpricc"; + reg = <0x00280000 0x31c00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml new file mode 100644 index 000000000000..d712b1a87e25 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + - Imran Shaik <quic_imrashai@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h + +properties: + compatible: + const: qcom,qdu1000-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 0 Phy Auxiliary clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,qdu1000-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, + <&usb3_phy_wrapper_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt deleted file mode 100644 index 944719bd586f..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ /dev/null @@ -1,51 +0,0 @@ -Qualcomm RPM Clock Controller Binding ------------------------------------------------- -The RPM is a dedicated hardware engine for managing the shared -SoC resources in order to keep the lowest power profile. It -communicates with other hardware subsystems via shared memory -and accepts clock requests, aggregates the requests and turns -the clocks on/off or scales them on demand. - -Required properties : -- compatible : shall contain only one of the following. The generic - compatible "qcom,rpmcc" should be also included. - - "qcom,rpmcc-msm8660", "qcom,rpmcc" - "qcom,rpmcc-apq8060", "qcom,rpmcc" - "qcom,rpmcc-msm8916", "qcom,rpmcc" - "qcom,rpmcc-msm8974", "qcom,rpmcc" - "qcom,rpmcc-apq8064", "qcom,rpmcc" - "qcom,rpmcc-msm8996", "qcom,rpmcc" - "qcom,rpmcc-msm8998", "qcom,rpmcc" - "qcom,rpmcc-qcs404", "qcom,rpmcc" - -- #clock-cells : shall contain 1 - -The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> -and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock -is an "active" clock, which means that the consumer only care that the -clock is available when the apps CPU subsystem is active, i.e. not -suspended or in deep idle. If it is important that the clock keeps running -during system suspend, you need to specify the non-active clock, the one -not containing *_A_* in the enumerator name. - -Example: - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; - #clock-cells = <1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml new file mode 100644 index 000000000000..3665dd30604a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPM Clock Controller + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: | + The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and + come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is + an "active" clock, which means that the consumer only care that the clock is + available when the apps CPU subsystem is active, i.e. not suspended or in + deep idle. If it is important that the clock keeps running during system + suspend, you need to specify the non-active clock, the one not containing + *_A_* in the enumerator name. + +properties: + compatible: + items: + - enum: + - qcom,rpmcc-apq8060 + - qcom,rpmcc-apq8064 + - qcom,rpmcc-ipq806x + - qcom,rpmcc-mdm9607 + - qcom,rpmcc-msm8226 + - qcom,rpmcc-msm8660 + - qcom,rpmcc-msm8909 + - qcom,rpmcc-msm8916 + - qcom,rpmcc-msm8917 + - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8974 + - qcom,rpmcc-msm8976 + - qcom,rpmcc-msm8992 + - qcom,rpmcc-msm8994 + - qcom,rpmcc-msm8996 + - qcom,rpmcc-msm8998 + - qcom,rpmcc-qcm2290 + - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm660 + - qcom,rpmcc-sm6115 + - qcom,rpmcc-sm6125 + - qcom,rpmcc-sm6375 + - const: qcom,rpmcc + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + +required: + - compatible + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,rpmcc-apq8060 + - qcom,rpmcc-ipq806x + - qcom,rpmcc-msm8660 + + then: + properties: + clocks: + items: + - description: pxo clock + + clock-names: + items: + - const: pxo + + - if: + properties: + compatible: + contains: + const: qcom,rpmcc-apq8064 + then: + properties: + clocks: + items: + - description: pxo clock + - description: cxo clock + + clock-names: + items: + - const: pxo + - const: cxo + + - if: + properties: + compatible: + contains: + enum: + - qcom,rpmcc-mdm9607 + - qcom,rpmcc-msm8226 + - qcom,rpmcc-msm8916 + - qcom,rpmcc-msm8917 + - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8974 + - qcom,rpmcc-msm8976 + - qcom,rpmcc-msm8992 + - qcom,rpmcc-msm8994 + - qcom,rpmcc-msm8996 + - qcom,rpmcc-msm8998 + - qcom,rpmcc-qcm2290 + - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm660 + - qcom,rpmcc-sm6115 + - qcom,rpmcc-sm6125 + + then: + properties: + clocks: + items: + - description: xo clock + + clock-names: + items: + - const: xo + +additionalProperties: false + +examples: + - | + rpm { + rpm-requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + clock-controller { + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + }; + + - | + rpm { + clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 94e2f14eb967..ca857942ed6c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/qcom,rpmhcc.yaml# +$id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. RPMh Clocks Bindings +title: Qualcomm Technologies, Inc. RPMh Clocks maintainers: - - Taniya Das <tdas@codeaurora.org> + - Taniya Das <quic_tdas@quicinc.com> description: | Resource Power Manager Hardened (RPMh) manages shared resources on @@ -17,9 +17,26 @@ description: | properties: compatible: enum: + - qcom,qdu1000-rpmh-clk + - qcom,sa8775p-rpmh-clk - qcom,sc7180-rpmh-clk + - qcom,sc7280-rpmh-clk + - qcom,sc8180x-rpmh-clk + - qcom,sc8280xp-rpmh-clk + - qcom,sdm670-rpmh-clk - qcom,sdm845-rpmh-clk + - qcom,sdx55-rpmh-clk + - qcom,sdx65-rpmh-clk + - qcom,sdx75-rpmh-clk + - qcom,sm4450-rpmh-clk + - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk + - qcom,sm8250-rpmh-clk + - qcom,sm8350-rpmh-clk + - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk + - qcom,sm8650-rpmh-clk + - qcom,x1e80100-rpmh-clk clocks: maxItems: 1 @@ -35,6 +52,8 @@ required: - compatible - '#clock-cells' +additionalProperties: false + examples: # Example for GCC for SDM845: The below node should be defined inside # &apps_rsc node. diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml new file mode 100644 index 000000000000..0f641c235b13 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on sa8775p + +maintainers: + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on sa8775p. + + See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h + +properties: + compatible: + const: qcom,sa8775p-gcc + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: UFS memory first RX symbol clock + - description: UFS memory second RX symbol clock + - description: UFS memory first TX symbol clock + - description: UFS card first RX symbol clock + - description: UFS card second RX symbol clock + - description: UFS card first TX symbol clock + - description: Primary USB3 PHY wrapper pipe clock + - description: Secondary USB3 PHY wrapper pipe clock + - description: PCIe 0 pipe clock + - description: PCIe 1 pipe clock + - description: PCIe PHY clock + - description: First EMAC controller reference clock + - description: Second EMAC controller reference clock + + protected-clocks: + maxItems: 240 + + power-domains: + maxItems: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + gcc: clock-controller@100000 { + compatible = "qcom,sa8775p-gcc"; + reg = <0x100000 0xc7018>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&ufs_card_rx_symbol_0_clk>, + <&ufs_card_rx_symbol_1_clk>, + <&ufs_card_tx_symbol_0_clk>, + <&usb_0_ssphy>, + <&usb_1_ssphy>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&pcie_phy_pipe_clk>, + <&rxc0_ref_clk>, + <&rxc1_ref_clk>; + power-domains = <&rpmhpd SA8775P_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file mode 100644 index 000000000000..c7fe6400ea13 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SC7180 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SC7180. + + See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sc7180-camcc + + clocks: + items: + - description: Board XO source + - description: Camera_ahb clock from GCC + - description: Camera XO clock from GCC + + clock-names: + items: + - const: bi_tcxo + - const: iface + - const: xo + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sc7180-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_XO_CLK>; + clock-names = "bi_tcxo", "iface", "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml new file mode 100644 index 000000000000..1c9ce300a435 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SC7180 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SC7180. + + See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h + +properties: + compatible: + const: qcom,sc7180-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0x0af00000 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi_phy 0>, + <&dsi_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file mode 100644 index 000000000000..fdfb389083c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller on SC7180 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm LPASS core clock control module provides the clocks and power + domains on SC7180. + + See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h + +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC + - description: Board XO source + + clock-names: + items: + - const: iface + - const: bi_tcxo + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + minItems: 1 + items: + - description: lpass core cc register + - description: lpass audio cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_cc + +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + maxItems: 1 + +else: + properties: + reg: + minItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0x63000000 0x28>; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0x62d00000 0x50000>, <0x62780000 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml new file mode 100644 index 000000000000..873a2f918bac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Modem Clock Controller on SC7180 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm modem clock control module provides the clocks on SC7180. + + See also:: include/dt-bindings/clock/qcom,mss-sc7180.h + +properties: + compatible: + const: qcom,sc7180-mss + + clocks: + items: + - description: gcc_mss_mfab_axi clock from GCC + - description: gcc_mss_nav_axi clock from GCC + - description: gcc_mss_cfg_ahb clock from GCC + + clock-names: + items: + - const: gcc_mss_mfab_axis + - const: gcc_mss_nav_axi + - const: cfg_ahb + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + clock-controller@41a8000 { + compatible = "qcom,sc7180-mss"; + reg = <0x041a8000 0x8000>; + clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>; + clock-names = "gcc_mss_mfab_axis", + "gcc_mss_nav_axi", + "cfg_ahb"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml new file mode 100644 index 000000000000..dcef8de3a905 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SC7280 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm camera clock control module provides the clocks, resets and + power domains on SC7280. + + See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sc7280-camcc + + clocks: + items: + - description: Board XO source + - description: Board XO active source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sc7280-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml new file mode 100644 index 000000000000..c42b0ef61385 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SC7280 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SC7280. + + See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h + +properties: + compatible: + const: qcom,sc7280-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + - description: Link clock from EDP PHY + - description: VCO DIV clock from EDP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@af00000 { + compatible = "qcom,sc7280-dispcc"; + reg = <0x0af00000 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi_phy 0>, + <&dsi_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml new file mode 100644 index 000000000000..f44c5c130d2d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller on SC7280 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm LPASS core clock control module provides the clocks and power + domains on SC7280. + + See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-lpasscc + + clocks: + items: + - description: gcc_cfg_noc_lpass_clk from GCC + + clock-names: + items: + - const: iface + + '#clock-cells': + const: 1 + + reg: + items: + - description: LPASS qdsp6ss register + - description: LPASS top-cc register + + reg-names: + items: + - const: qdsp6ss + - const: top_cc + + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + remoteproc peripheral loader. + type: boolean + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> + clock-controller@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0x03000000 0x40>, <0x03c04000 0x4>; + reg-names = "qdsp6ss", "top_cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + qcom,adsp-pil-mode; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml new file mode 100644 index 000000000000..deee5423d66e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC7280 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks and + power domains on SC7280. + + See also:: + include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h + include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h + +properties: + clocks: true + + clock-names: true + + reg: true + + compatible: + enum: + - qcom,sc7280-lpassaoncc + - qcom,sc7280-lpassaudiocc + - qcom,sc7280-lpasscorecc + - qcom,sc7280-lpasshm + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + '#reset-cells': + const: 1 + + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + peripheral loader. + type: boolean + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,sc7280-lpassaudiocc + + then: + properties: + clocks: + items: + - description: Board XO source + - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC + + clock-names: + items: + - const: bi_tcxo + - const: lpass_aon_cc_main_rcg_clk_src + + reg: + items: + - description: lpass core cc register + - description: lpass audio csr register + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-lpassaoncc + + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board XO active only source + - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: iface + + reg: + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-lpasshm + - qcom,sc7280-lpasscorecc + + then: + properties: + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + + reg: + maxItems: 1 +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0x3300000 0x30000>, + <0x32a9000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> + lpass_hm: clock-controller@3c00000 { + compatible = "qcom,sc7280-lpasshm"; + reg = <0x3c00000 0x28>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0x3900000 0x50000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0x3380000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscore LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao","iface"; + qcom,adsp-pil-mode; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..3326dcd6766c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpassaudiocc + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + - | + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml new file mode 100644 index 000000000000..810b852ae371 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SDM845 + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SDM845. + + See also:: include/dt-bindings/clock/qcom,camcc-sm845.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sdm845-camcc + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml new file mode 100644 index 000000000000..719844d7ea11 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SDM845 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SDM845. + + See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h + +properties: + compatible: + const: qcom,sdm845-dispcc + + # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. + # The code had to use hardcoded mechanisms to find the input clocks. + # New dts files should have these clocks. + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: GPLL0 div source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: bi_tcxo + - const: gcc_disp_gpll0_clk_src + - const: gcc_disp_gpll0_div_clk_src + - const: dsi0_phy_pll_out_byteclk + - const: dsi0_phy_pll_out_dsiclk + - const: dsi1_phy_pll_out_byteclk + - const: dsi1_phy_pll_out_dsiclk + - const: dp_link_clk_divsel_ten + - const: dp_vco_divided_clk_src_mux + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.yaml new file mode 100644 index 000000000000..a96fd837c70a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdm845-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM845 LPASS Clock Controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller. + + See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h + +properties: + compatible: + const: qcom,sdm845-lpasscc + + '#clock-cells': + const: 1 + + reg: + maxItems: 2 + + reg-names: + items: + - const: cc + - const: qdsp6ss + +required: + - compatible + - '#clock-cells' + - reg + - reg-names + +additionalProperties: false + +examples: + - | + clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml new file mode 100644 index 000000000000..98921fa236b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX75 + +maintainers: + - Imran Shaik <quic_imrashai@quicinc.com> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDX75 + + See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h + +properties: + compatible: + const: qcom,sdx75-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC0 sgmiiphy rclk source + - description: EMAC0 sgmiiphy tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy rclk source + - description: EMAC1 sgmiiphy tclk source + - description: PCIE20 phy aux clock source + - description: PCIE_1 Pipe clock source + - description: PCIE_2 Pipe clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x80000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml new file mode 100644 index 000000000000..5953c8d92436 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM4450 + +maintainers: + - Ajit Pandey <quic_ajipan@quicinc.com> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM4450 + + See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h + +properties: + compatible: + const: qcom,sm4450-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,sm4450-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml new file mode 100644 index 000000000000..f802a2e7f818 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock Controller for SM6115 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm display clock control module provides the clocks and power domains + on SM6115. + + See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h + +properties: + compatible: + enum: + - qcom,sm6115-dispcc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: GPLL0 DISP DIV clock from GCC + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + clock-controller@5f00000 { + compatible = "qcom,sm6115-dispcc"; + reg = <0x5f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..cf19f44af774 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm6125.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml new file mode 100644 index 000000000000..fd6658cb793d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM6350 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM6350. + + See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h + +properties: + compatible: + const: qcom,sm6350-camcc + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sm6350-camcc"; + reg = <0x0ad00000 0x16000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml new file mode 100644 index 000000000000..183b1c75dbdf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM6375. + + See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sm6375-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6375-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + clock-controller@5f00000 { + compatible = "qcom,sm6375-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi_phy 0>, + <&dsi_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml new file mode 100644 index 000000000000..295d4bb1a966 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM6375 + + See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sm6375-gcc + + clocks: + items: + - description: Board XO source + - description: Board XO Active-Only source + - description: Sleep clock source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@1400000 { + compatible = "qcom,sm6375-gcc"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..cf4cad76f6c9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + + power-domains: + description: + A phandle and PM domain specifier for the VDD_GX power rail + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required VDD_GX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6375-gcc.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + power-domains = <&rpmpd SM6375_VDDGX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml new file mode 100644 index 000000000000..0eb76d9d51c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM7150 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Danila Tikhonov <danila@jiaxyga.com> + - David Wronek <davidwronek@gmail.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM7150 + + See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h + +properties: + compatible: + const: qcom,sm7150-gcc + + clocks: + items: + - description: Board XO source + - description: Board XO Active-Only source + - description: Sleep clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,sm7150-gcc"; + reg = <0x00100000 0x001f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml new file mode 100644 index 000000000000..46d1d91e3a01 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Video Clock & Reset Controller + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,videocc-sm8350.h + include/dt-bindings/reset/qcom,videocc-sm8350.h + +properties: + compatible: + enum: + - qcom,sc8280xp-videocc + - qcom,sm8350-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Board sleep clock + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + clock-controller@abf0000 { + compatible = "qcom,sm8350-videocc"; + reg = <0x0abf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml new file mode 100644 index 000000000000..48986460f994 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM8450 + +maintainers: + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: + include/dt-bindings/clock/qcom,sm8450-camcc.h + include/dt-bindings/clock/qcom,sm8550-camcc.h + include/dt-bindings/clock/qcom,sc8280xp-camcc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,sc8280xp-camcc + - qcom,sm8450-camcc + - qcom,sm8550-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: + A phandle and PM domain specifier for the MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml new file mode 100644 index 000000000000..2f22310b08a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM8450 + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h + +properties: + compatible: + enum: + - qcom,sm8450-dispcc + + clocks: + minItems: 3 + items: + - description: Board XO source + - description: Board Always On XO source + - description: Display's AHB clock + - description: sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + - description: Link clock from DP PHY1 + - description: VCO DIV clock from DP PHY1 + - description: Link clock from DP PHY2 + - description: VCO DIV clock from DP PHY2 + - description: Link clock from DP PHY3 + - description: VCO DIV clock from DP PHY3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@af00000 { + compatible = "qcom,sm8450-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml new file mode 100644 index 000000000000..1a384e8532a5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8450 + +maintainers: + - Konrad Dybcio <konrad.dybcio@linaro.org> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/clock/qcom,sm8550-gpucc.h + include/dt-bindings/reset/qcom,sm8450-gpucc.h + include/dt-bindings/reset/qcom,sm8650-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8450-gpucc + - qcom,sm8550-gpucc + - qcom,sm8650-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml new file mode 100644 index 000000000000..bad8f019a8d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8450 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + +properties: + compatible: + enum: + - qcom,sm8450-videocc + - qcom,sm8550-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml new file mode 100644 index 000000000000..c129f8c16b50 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM8550 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h + +properties: + compatible: + enum: + - qcom,sm8550-dispcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Display's AHB clock + - description: sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + - description: Link clock from DP PHY1 + - description: VCO DIV clock from DP PHY1 + - description: Link clock from DP PHY2 + - description: VCO DIV clock from DP PHY2 + - description: Link clock from DP PHY3 + - description: VCO DIV clock from DP PHY3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp1_phy 0>, + <&dp1_phy 1>, + <&dp2_phy 0>, + <&dp2_phy 1>, + <&dp3_phy 0>, + <&dp3_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml new file mode 100644 index 000000000000..0c706de31cf1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8550 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h + +properties: + compatible: + const: qcom,sm8550-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: PCIE 1 Phy Auxiliary clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,sm8550-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie_1_phy_aux_clk>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..af16b05eac96 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also: + - include/dt-bindings/clock/qcom,sm8550-tcsr.h + - include/dt-bindings/clock/qcom,sm8650-tcsr.h + +properties: + compatible: + items: + - enum: + - qcom,sm8550-tcsr + - qcom,sm8650-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml new file mode 100644 index 000000000000..5e0c45c380f5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM8650 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Neil Armstrong <neil.armstrong@linaro.org> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM8650. + + See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h + +properties: + compatible: + enum: + - qcom,sm8650-dispcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Display's AHB clock + - description: sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + - description: Link clock from DP PHY1 + - description: VCO DIV clock from DP PHY1 + - description: Link clock from DP PHY2 + - description: VCO DIV clock from DP PHY2 + - description: Link clock from DP PHY3 + - description: VCO DIV clock from DP PHY3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8650-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@af00000 { + compatible = "qcom,sm8650-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp1_phy 0>, + <&dp1_phy 1>, + <&dp2_phy 0>, + <&dp2_phy 1>, + <&dp3_phy 0>, + <&dp3_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml new file mode 100644 index 000000000000..b54761cc8674 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8650 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8650 + + See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h + +properties: + compatible: + const: qcom,sm8650-gcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: PCIE 1 Phy Auxiliary clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,sm8650-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie_1_phy_aux_clk>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt deleted file mode 100644 index 7474aba36607..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt +++ /dev/null @@ -1,59 +0,0 @@ -Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv) - -clkdiv configures the clock frequency of a set of outputs on the PMIC. -These clocks are typically wired through alternate functions on -gpio pins. - -======================= -Properties -======================= - -- compatible - Usage: required - Value type: <string> - Definition: must be "qcom,spmi-clkdiv". - -- reg - Usage: required - Value type: <prop-encoded-array> - Definition: base address of CLKDIV peripherals. - -- qcom,num-clkdivs - Usage: required - Value type: <u32> - Definition: number of CLKDIV peripherals. - -- clocks: - Usage: required - Value type: <prop-encoded-array> - Definition: reference to the xo clock. - -- clock-names: - Usage: required - Value type: <stringlist> - Definition: must be "xo". - -- #clock-cells: - Usage: required - Value type: <u32> - Definition: shall contain 1. - -======= -Example -======= - -pm8998_clk_divs: clock-controller@5b00 { - compatible = "qcom,spmi-clkdiv"; - reg = <0x5b00>; - #clock-cells = <1>; - qcom,num-clkdivs = <3>; - clocks = <&xo_board>; - clock-names = "xo"; - - assigned-clocks = <&pm8998_clk_divs 1>, - <&pm8998_clk_divs 2>, - <&pm8998_clk_divs 3>; - assigned-clock-rates = <9600000>, - <9600000>, - <9600000>; -}; diff --git a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.yaml b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.yaml new file mode 100644 index 000000000000..16c95ad6c9d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC clock divider + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Stephen Boyd <sboyd@kernel.org> + +description: | + Qualcomm SPMI PMIC clock divider configures the clock frequency of a set of + outputs on the PMIC. These clocks are typically wired through alternate + functions on GPIO pins. + +properties: + compatible: + const: qcom,spmi-clkdiv + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: xo + + "#clock-cells": + const: 1 + + qcom,num-clkdivs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of CLKDIV peripherals. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - qcom,num-clkdivs + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + qcom,num-clkdivs = <3>; + + assigned-clocks = <&pm8998_clk_divs 1>, + <&pm8998_clk_divs 2>, + <&pm8998_clk_divs 3>; + assigned-clock-rates = <9600000>, + <9600000>, + <9600000>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt deleted file mode 100644 index 8a8622c65c5a..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ /dev/null @@ -1,18 +0,0 @@ -Qualcomm Video Clock & Reset Controller Binding ------------------------------------------------ - -Required properties : -- compatible : shall contain "qcom,sdm845-videocc" -- reg : shall contain base register location and length -- #clock-cells : from common clock binding, shall contain 1. -- #power-domain-cells : from generic power domain binding, shall contain 1. -- #reset-cells : from common reset binding, shall contain 1. - -Example: - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml new file mode 100644 index 000000000000..6999e36ace1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,videocc-sc7180.h + include/dt-bindings/clock/qcom,videocc-sc7280.h + include/dt-bindings/clock/qcom,videocc-sdm845.h + include/dt-bindings/clock/qcom,videocc-sm8150.h + include/dt-bindings/clock/qcom,videocc-sm8250.h + +properties: + compatible: + enum: + - qcom,sc7180-videocc + - qcom,sc7280-videocc + - qcom,sdm845-videocc + - qcom,sm8150-videocc + - qcom,sm8250-videocc + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +allOf: + - if: + properties: + compatible: + enum: + - qcom,sc7180-videocc + - qcom,sdm845-videocc + - qcom,sm8150-videocc + then: + properties: + clocks: + items: + - description: Board XO source + clock-names: + items: + - const: bi_tcxo + + - if: + properties: + compatible: + enum: + - qcom,sc7280-videocc + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + + - if: + properties: + compatible: + enum: + - qcom,sm8250-videocc + then: + properties: + clocks: + items: + - description: AHB + - description: Board XO source + - description: Board active XO source + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: bi_tcxo_ao + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0x0ab00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml new file mode 100644 index 000000000000..14a796dbf8bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on X1E80100 + +maintainers: + - Rajendra Nayak <quic_rjendra@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on X1E80100 + + See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h + +properties: + compatible: + const: qcom,x1e80100-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIe 3 pipe clock + - description: PCIe 4 pipe clock + - description: PCIe 5 pipe clock + - description: PCIe 6a pipe clock + - description: PCIe 6b pipe clock + - description: USB QMP Phy 0 clock source + - description: USB QMP Phy 1 clock source + - description: USB QMP Phy 2 clock source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@100000 { + compatible = "qcom,x1e80100-gcc"; + reg = <0x00100000 0x200000>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <&pcie3_phy>, + <&pcie4_phy>, + <&pcie5_phy>, + <&pcie6a_phy>, + <&pcie6b_phy>, + <&usb_1_ss0_qmpphy 0>, + <&usb_1_ss1_qmpphy 1>, + <&usb_1_ss2_qmpphy 2>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index f7d48f23da44..10119d9ef4b1 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -44,6 +44,7 @@ Required properties: * "fsl,ls1046a-clockgen" * "fsl,ls1088a-clockgen" * "fsl,ls2080a-clockgen" + * "fsl,lx2160a-clockgen" Chassis-version clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml new file mode 100644 index 000000000000..42b6f80613f3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + The 5P35023 is a VersaClock programmable clock generator and + is designed for low-power, consumer, and high-performance PCI + express applications. The 5P35023 device is a three PLL + architecture design, and each PLL is individually programmable + and allowing for up to 6 unique frequency outputs. + + An internal OTP memory allows the user to store the configuration + in the device. After power up, the user can change the device register + settings through the I2C interface when I2C mode is selected. + + The driver can read a full register map from the DT, and will use that + register map to initialize the attached part (via I2C) when the system + boots. Any configuration not supported by the common clock framework + must be done via the full register map, including optimized settings. + + Link to datasheet: + https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator + +properties: + compatible: + enum: + - renesas,5p35023 + + reg: + maxItems: 1 + + '#clock-cells': + description: + The index in the assigned-clocks is mapped to the output clock as below + 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2. + const: 1 + + clocks: + maxItems: 1 + + renesas,settings: + description: Optional, complete register map of the device. + Optimized settings for the device must be provided in full + and are written during initialization. + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 37 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,9series.yaml b/Documentation/devicetree/bindings/clock/renesas,9series.yaml new file mode 100644 index 000000000000..af6319697b1c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,9series.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,9series.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas 9-series I2C PCIe clock generators + +description: | + The Renesas 9-series are I2C PCIe clock generators providing + from 1 to 20 output clocks. + + When referencing the provided clock in the DT using phandle + and clock specifier, the following mapping applies: + + - 9FGV0241: + 0 -- DIF0 + 1 -- DIF1 + - 9FGV0441: + 0 -- DIF0 + 1 -- DIF1 + 2 -- DIF2 + 3 -- DIF3 + - 9FGV0841: + 0 -- DIF0 + 1 -- DIF1 + 2 -- DIF2 + 3 -- DIF3 + 4 -- DIF4 + 5 -- DIF5 + 6 -- DIF6 + 7 -- DIF7 + +maintainers: + - Marek Vasut <marex@denx.de> + +properties: + compatible: + enum: + - renesas,9fgv0241 + - renesas,9fgv0441 + - renesas,9fgv0841 + + reg: + description: I2C device address + enum: [ 0x68, 0x6a ] + + '#clock-cells': + const: 1 + + clocks: + items: + - description: XTal input clock + + renesas,out-amplitude-microvolt: + enum: [ 600000, 700000, 800000, 900000 ] + description: Output clock signal amplitude + + renesas,out-spread-spectrum: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 100000, 99750, 99500 ] + description: Output clock down spread in pcm (1/1000 of percent) + +patternProperties: + "^DIF[0-19]$": + type: object + description: + Description of one of the outputs (DIF0..DIF19). + + properties: + renesas,slew-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2000000, 3000000 ] + description: Output clock slew rate select in V/ns + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + /* 25MHz reference crystal */ + ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + rs9: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + #clock-cells = <1>; + + clocks = <&ref25m>; + + DIF0 { + renesas,slew-rate = <3000000>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml new file mode 100644 index 000000000000..9185d101737e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -0,0 +1,241 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Clock Pulse Generator (CPG) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and fixed and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + oneOf: + - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6 + - const: renesas,r8a7740-cpg-clocks # R-Mobile A1 + - const: renesas,r8a7778-cpg-clocks # R-Car M1 + - const: renesas,r8a7779-cpg-clocks # R-Car H1 + - items: + - enum: + - renesas,r7s72100-cpg-clocks # RZ/A1H + - const: renesas,rz-cpg-clocks # RZ/A1 + - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5 + + reg: + maxItems: 1 + + clocks: true + + '#clock-cells': + const: 1 + + clock-output-names: true + + renesas,mode: + description: Board-specific settings of the MD_CK* bits on R-Mobile A1 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-output-names + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r8a73a4-cpg-clocks + then: + properties: + clocks: + items: + - description: extal1 + - description: extal2 + + clock-output-names: + items: + - const: main + - const: pll0 + - const: pll1 + - const: pll2 + - const: pll2s + - const: pll2h + - const: z + - const: z2 + - const: i + - const: m3 + - const: b + - const: m1 + - const: m2 + - const: zx + - const: zs + - const: hp + + - if: + properties: + compatible: + contains: + const: renesas,r8a7740-cpg-clocks + then: + properties: + clocks: + items: + - description: extal1 + - description: extal2 + - description: extalr + + clock-output-names: + items: + - const: system + - const: pllc0 + - const: pllc1 + - const: pllc2 + - const: r + - const: usb24s + - const: i + - const: zg + - const: b + - const: m1 + - const: hp + - const: hpp + - const: usbp + - const: s + - const: zb + - const: m3 + - const: cp + + required: + - renesas,mode + + - if: + properties: + compatible: + contains: + const: renesas,r8a7778-cpg-clocks + then: + properties: + clocks: + maxItems: 1 + + clock-output-names: + items: + - const: plla + - const: pllb + - const: b + - const: out + - const: p + - const: s + - const: s1 + + - if: + properties: + compatible: + contains: + const: renesas,r8a7779-cpg-clocks + then: + properties: + clocks: + maxItems: 1 + + clock-output-names: + items: + - const: plla + - const: z + - const: zs + - const: s + - const: s1 + - const: p + - const: b + - const: out + + - if: + properties: + compatible: + contains: + const: renesas,r7s72100-cpg-clocks + then: + properties: + clocks: + items: + - description: extal1 + - description: usb_x1 + + clock-output-names: + items: + - const: pll + - const: i + - const: g + + - if: + properties: + compatible: + contains: + const: renesas,sh73a0-cpg-clocks + then: + properties: + clocks: + items: + - description: extal1 + - description: extal2 + + clock-output-names: + items: + - const: main + - const: pll0 + - const: pll1 + - const: pll2 + - const: pll3 + - const: dsi0phy + - const: dsi1phy + - const: zg + - const: m3 + - const: b + - const: m1 + - const: m2 + - const: z + - const: zx + - const: hp + + - if: + properties: + compatible: + contains: + enum: + - renesas,r8a7778-cpg-clocks + - renesas,r8a7779-cpg-clocks + - renesas,rz-cpg-clocks + then: + required: + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7740-clock.h> + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7740-cpg-clocks"; + reg = <0xe6150000 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; + #clock-cells = <1>; + clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", + "usb24s", "i", "zg", "b", "m1", "hp", "hpp", + "usbp", "s", "zb", "m3", "cp"; + renesas,mode = <0x05>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml new file mode 100644 index 000000000000..2197c952e21d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas CPG DIV6 Clock + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse + Generator (CPG). Their clock input is divided by a configurable factor from 1 + to 64. + +properties: + compatible: + items: + - enum: + - renesas,r8a73a4-div6-clock # R-Mobile APE6 + - renesas,r8a7740-div6-clock # R-Mobile A1 + - renesas,sh73a0-div6-clock # SH-Mobile AG5 + - const: renesas,cpg-div6-clock + + reg: + maxItems: 1 + + clocks: + oneOf: + - maxItems: 1 + - maxItems: 4 + - maxItems: 8 + description: + For clocks with multiple parents, invalid settings must be specified as + "<0>". + + '#clock-cells': + const: 0 + + clock-output-names: true + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a73a4-clock.h> + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a73a4-cpg-clocks"; + reg = <0xe6150000 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll2s", "pll2h", "z", "z2", + "i", "m3", "b", "m1", "m2", + "zx", "zs", "hp"; + }; + + sdhi2_clk: sdhi2_clk@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615007c 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, + <&extal2_clk>; + #clock-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt deleted file mode 100644 index ae36ab842919..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Renesas CPG DIV6 Clock - -The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse -Generator (CPG). Their clock input is divided by a configurable factor from 1 -to 64. - -Required Properties: - - - compatible: Must be one of the following - - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks - - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks - - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks - - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks - - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - and "renesas,cpg-div6-clock" as a fallback. - - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock(s); either one, four, or eight - clocks must be specified. For clocks with multiple parents, invalid - settings must be specified as "<0>". - - #clock-cells: Must be 0 - - -Optional Properties: - - - clock-output-names: The name of the clock as a free-form string - - -Example -------- - - sdhi2_clk: sdhi2_clk@e615007c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - clock-output-names = "sdhi2ck"; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt deleted file mode 100644 index c7674d0267a3..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ /dev/null @@ -1,100 +0,0 @@ -* Renesas Clock Pulse Generator / Module Standby and Software Reset - -On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) -and MSSR (Module Standby and Software Reset) blocks are intimately connected, -and share the same register block. - -They provide the following functionalities: - - The CPG block generates various core clocks, - - The MSSR block provides two functions: - 1. Module Standby, providing a Clock Domain to control the clock supply - to individual SoC devices, - 2. Reset Control, to perform a software reset of individual SoC devices. - -Required Properties: - - compatible: Must be one of: - - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2) - - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) - - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N) - - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N) - - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) - - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) - - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) - - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W) - - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+) - - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) - - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3) - - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - - - reg: Base address and length of the memory resource used by the CPG/MSSR - block - - - clocks: References to external parent clocks, one entry for each entry in - clock-names - - clock-names: List of external parent clock names. Valid names are: - - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, - r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, - r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970, - r8a77980, r8a77990, r8a77995) - - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965, - r8a77970, r8a77980) - - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, - r8a7793, r8a7794) - - - #clock-cells: Must be 2 - - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" - and a core clock reference, as defined in - <dt-bindings/clock/*-cpg-mssr.h>. - - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the datasheet. - - - #power-domain-cells: Must be 0 - - SoC devices that are part of the CPG/MSSR Clock Domain and can be - power-managed through Module Standby should refer to the CPG device - node in their "power-domains" property, as documented by the generic PM - Domain bindings in - Documentation/devicetree/bindings/power/power-domain.yaml. - - - #reset-cells: Must be 1 - - The single reset specifier cell must be the module number, as defined - in the datasheet. - - -Examples --------- - - - CPG device node: - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - - - CPG/MSSR Clock Domain member device node: - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 310>; - clock-names = "fck"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - resets = <&cpg 310>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml new file mode 100644 index 000000000000..9c3dc6c4fa94 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Clock Pulse Generator / Module Standby and Software Reset + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: | + On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) + and MSSR (Module Standby and Software Reset) blocks are intimately connected, + and share the same register block. + + They provide the following functionalities: + - The CPG block generates various core clocks, + - The MSSR block provides two functions: + 1. Module Standby, providing a Clock Domain to control the clock supply + to individual SoC devices, + 2. Reset Control, to perform a software reset of individual SoC devices. + +properties: + compatible: + enum: + - renesas,r7s9210-cpg-mssr # RZ/A2 + - renesas,r8a7742-cpg-mssr # RZ/G1H + - renesas,r8a7743-cpg-mssr # RZ/G1M + - renesas,r8a7744-cpg-mssr # RZ/G1N + - renesas,r8a7745-cpg-mssr # RZ/G1E + - renesas,r8a77470-cpg-mssr # RZ/G1C + - renesas,r8a774a1-cpg-mssr # RZ/G2M + - renesas,r8a774b1-cpg-mssr # RZ/G2N + - renesas,r8a774c0-cpg-mssr # RZ/G2E + - renesas,r8a774e1-cpg-mssr # RZ/G2H + - renesas,r8a7790-cpg-mssr # R-Car H2 + - renesas,r8a7791-cpg-mssr # R-Car M2-W + - renesas,r8a7792-cpg-mssr # R-Car V2H + - renesas,r8a7793-cpg-mssr # R-Car M2-N + - renesas,r8a7794-cpg-mssr # R-Car E2 + - renesas,r8a7795-cpg-mssr # R-Car H3 + - renesas,r8a7796-cpg-mssr # R-Car M3-W + - renesas,r8a77961-cpg-mssr # R-Car M3-W+ + - renesas,r8a77965-cpg-mssr # R-Car M3-N + - renesas,r8a77970-cpg-mssr # R-Car V3M + - renesas,r8a77980-cpg-mssr # R-Car V3H + - renesas,r8a77990-cpg-mssr # R-Car E3 + - renesas,r8a77995-cpg-mssr # R-Car D3 + - renesas,r8a779a0-cpg-mssr # R-Car V3U + - renesas,r8a779f0-cpg-mssr # R-Car S4-8 + - renesas,r8a779g0-cpg-mssr # R-Car V4H + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - extal # All + - extalr # Most R-Car Gen3 and RZ/G2 + - usb_extal # Most R-Car Gen2 and RZ/G1 + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + <dt-bindings/clock/*-cpg-mssr.h> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, as defined in the datasheet. + const: 2 + + '#power-domain-cells': + description: + SoC devices that are part of the CPG/MSSR Clock Domain and can be + power-managed through Module Standby should refer to the CPG device node + in their "power-domains" property, as documented by the generic PM Domain + bindings in Documentation/devicetree/bindings/power/power-domain.yaml. + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the module number, as defined in + the datasheet. + const: 1 + +if: + not: + properties: + compatible: + items: + enum: + - renesas,r7s9210-cpg-mssr +then: + required: + - '#reset-cells' + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0xe6150000 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt deleted file mode 100644 index da578ebdda28..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Renesas CPG Module Stop (MSTP) Clocks - -The CPG can gate SoC device clocks. The gates are organized in groups of up to -32 gates. - -This device tree binding describes a single 32 gate clocks group per node. -Clocks are referenced by user nodes by the MSTP node phandle and the clock -index in the group, from 0 to 31. - -Required Properties: - - - compatible: Must be one of the following - - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks - - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks - - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks - - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks - - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks - - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - and "renesas,cpg-mstp-clocks" as a fallback. - - reg: Base address and length of the I/O mapped registers used by the MSTP - clocks. The first register is the clock control register and is mandatory. - The second register is the clock status register and is optional when not - implemented in hardware. - - clocks: Reference to the parent clocks, one per output clock. The parents - must appear in the same order as the output clocks. - - #clock-cells: Must be 1 - - clock-output-names: The name of the clocks as free-form strings - - clock-indices: Indices of the gate clocks into the group (0 to 31) - -The clocks, clock-output-names and clock-indices properties contain one entry -per gate clock. The MSTP groups are sparsely populated. Unimplemented gate -clocks must not be declared. - - -Example -------- - - #include <dt-bindings/clock/r8a7790-clock.h> - - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, - <&mmc0_clk>; - #clock-cells = <1>; - clock-output-names = - "tpu0", "mmcif1", "sdhi3", "sdhi2", - "sdhi1", "sdhi0", "mmcif0"; - clock-indices = < - R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 - R8A7790_CLK_MMCIF0 - >; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.yaml new file mode 100644 index 000000000000..9752ac63288b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are + organized in groups of up to 32 gates. + + This device tree binding describes a single 32 gate clocks group per node. + Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle + and the clock index in the group, from 0 to 31. + +properties: + compatible: + items: + - enum: + - renesas,r7s72100-mstp-clocks # RZ/A1 + - renesas,r8a73a4-mstp-clocks # R-Mobile APE6 + - renesas,r8a7740-mstp-clocks # R-Mobile A1 + - renesas,r8a7778-mstp-clocks # R-Car M1 + - renesas,r8a7779-mstp-clocks # R-Car H1 + - renesas,sh73a0-mstp-clocks # SH-Mobile AG5 + - const: renesas,cpg-mstp-clocks + + reg: + minItems: 1 + items: + - description: Module Stop Control Register (MSTPCR) + - description: Module Stop Status Register (MSTPSR) + + clocks: + minItems: 1 + maxItems: 32 + + '#clock-cells': + const: 1 + + clock-indices: + minItems: 1 + maxItems: 32 + + clock-output-names: + minItems: 1 + maxItems: 32 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-indices + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a73a4-clock.h> + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a73a4-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xe6150138 4>, <0xe6150040 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 + R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 + R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 + R8A73A4_CLK_DMAC + >; + clock-output-names = + "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3", + "dmac"; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt deleted file mode 100644 index 268ca615459e..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt +++ /dev/null @@ -1,98 +0,0 @@ -Device tree Clock bindings for Renesas EMMA Mobile EV2 - -This binding uses the common clock binding. - -* SMU -System Management Unit described in user's manual R19UH0037EJ1000_SMU. -This is not a clock provider, but clocks under SMU depend on it. - -Required properties: -- compatible: Should be "renesas,emev2-smu" -- reg: Address and Size of SMU registers - -* SMU_CLKDIV -Function block with an input mux and a divider, which corresponds to -"Serial clock generator" in fig."Clock System Overview" of the manual, -and "xxx frequency division setting register" (XXXCLKDIV) registers. -This makes internal (neither input nor output) clock that is provided -to input of xxxGCLK block. - -Required properties: -- compatible: Should be "renesas,emev2-smu-clkdiv" -- reg: Byte offset from SMU base and Bit position in the register -- clocks: Parent clocks. Input clocks as described in clock-bindings.txt -- #clock-cells: Should be <0> - -* SMU_GCLK -Clock gating node shown as "Clock stop processing block" in the -fig."Clock System Overview" of the manual. -Registers are "xxx clock gate control register" (XXXGCLKCTRL). - -Required properties: -- compatible: Should be "renesas,emev2-smu-gclk" -- reg: Byte offset from SMU base and Bit position in the register -- clocks: Input clock as described in clock-bindings.txt -- #clock-cells: Should be <0> - -Example of provider: - -usia_u0_sclkdiv: usia_u0_sclkdiv { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>; - #clock-cells = <0>; -}; - -usia_u0_sclk: usia_u0_sclk { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; -}; - -Example of consumer: - -serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = <0 8 0>; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; -}; - -Example of clock-tree description: - - This describes a clock path in the clock tree - c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk - -smu@e0110000 { - compatible = "renesas,emev2-smu"; - reg = <0xe0110000 0x10000>; - #address-cells = <2>; - #size-cells = <0>; - - c32ki: c32ki { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - pll3_fo: pll3_fo { - compatible = "fixed-factor-clock"; - clocks = <&c32ki>; - clock-div = <1>; - clock-mult = <7000>; - #clock-cells = <0>; - }; - usia_u0_sclkdiv: usia_u0_sclkdiv { - compatible = "renesas,emev2-smu-clkdiv"; - reg = <0x610 0>; - clocks = <&pll3_fo>; - #clock-cells = <0>; - }; - usia_u0_sclk: usia_u0_sclk { - compatible = "renesas,emev2-smu-gclk"; - reg = <0x4a0 1>; - clocks = <&usia_u0_sclkdiv>; - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml new file mode 100644 index 000000000000..4d9a64800481 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile EV2 System Management Unit + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: | + The System Management Unit is described in user's manual R19UH0037EJ1000_SMU. + This is not a clock provider, but clocks under SMU depend on it. + +properties: + compatible: + const: renesas,emev2-smu + + reg: + maxItems: 1 + + '#address-cells': + const: 2 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +patternProperties: + ".*sclkdiv@.*": + type: object + + description: | + Function block with an input mux and a divider, which corresponds to + "Serial clock generator" in fig. "Clock System Overview" of the manual, + and "xxx frequency division setting register" (XXXCLKDIV) registers. + This makes internal (neither input nor output) clock that is provided + to input of xxxGCLK block. + + properties: + compatible: + const: renesas,emev2-smu-clkdiv + + reg: + maxItems: 1 + description: + Byte offset from SMU base and Bit position in the register. + + clocks: + minItems: 1 + maxItems: 4 + + '#clock-cells': + const: 0 + + required: + - compatible + - reg + - clocks + - '#clock-cells' + + additionalProperties: false + + ".*sclk@.*": + type: object + + description: | + Clock gating node shown as "Clock stop processing block" in the + fig. "Clock System Overview" of the manual. + Registers are "xxx clock gate control register" (XXXGCLKCTRL). + + properties: + compatible: + const: renesas,emev2-smu-gclk + + reg: + maxItems: 1 + description: + Byte offset from SMU base and Bit position in the register. + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + required: + - compatible + - reg + - clocks + - '#clock-cells' + + additionalProperties: false + +additionalProperties: true + +examples: + - | + // Example of clock-tree description: + // + // This describes a clock path in the clock tree + // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk + clocks@e0110000 { + compatible = "renesas,emev2-smu"; + reg = <0xe0110000 0x10000>; + #address-cells = <2>; + #size-cells = <0>; + + c32ki: c32ki { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + pll3_fo: pll3_fo { + compatible = "fixed-factor-clock"; + clocks = <&c32ki>; + clock-div = <1>; + clock-mult = <7000>; + #clock-cells = <0>; + }; + usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x610 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usia_u0_sclk: usia_u0_sclk@4a0,1 { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4a0 1>; + clocks = <&usia_u0_sclkdiv>; + #clock-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt deleted file mode 100644 index 399e0da22348..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Renesas H8/300 divider clock - -Required Properties: - - - compatible: Must be "renesas,h8300-div-clock" - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - reg: Base address and length of the divide rate selector - - - renesas,width: bit width of selector - -Example -------- - - cclk: cclk { - compatible = "renesas,h8300-div-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee01b 2>; - renesas,width = <2>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt deleted file mode 100644 index 500cdadbceb7..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,h8s2678-pll-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -Renesas H8S2678 PLL clock - -This device is Clock multiplyer - -Required Properties: - - - compatible: Must be "renesas,h8s2678-pll-clock" - - - clocks: Reference to the parent clocks - - - #clock-cells: Must be 0 - - - reg: Two rate selector (Multiply / Divide) register address - -Example -------- - - pllclk: pllclk { - compatible = "renesas,h8s2678-pll-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee03b 2>, <0xfee045 2>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt deleted file mode 100644 index ece92393e80d..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Renesas R8A73A4 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs -and several fixed ratio dividers. - -Required Properties: - - - compatible: Must be "renesas,r8a73a4-cpg-clocks" - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", - "m1", "m2", "zx", "zs", and "hp". - - -Example -------- - - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a73a4-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll2s", "pll2h", "z", "z2", - "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt deleted file mode 100644 index 2c03302f86ed..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt +++ /dev/null @@ -1,41 +0,0 @@ -These bindings should be considered EXPERIMENTAL for now. - -* Renesas R8A7740 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs -and several fixed ratio and variable ratio dividers. - -Required Properties: - - - compatible: Must be "renesas,r8a7740-cpg-clocks" - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the three parent clocks - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are - "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", - "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp". - - - renesas,mode: board-specific settings of the MD_CK* bits - - -Example -------- - -cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7740-cpg-clocks"; - reg = <0xe6150000 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; - #clock-cells = <1>; - clock-output-names = "system", "pllc0", "pllc1", - "pllc2", "r", - "usb24s", - "i", "zg", "b", "m1", "hp", - "hpp", "usbp", "s", "zb", "m3", - "cp"; -}; - -&cpg_clocks { - renesas,mode = <0x05>; -}; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt deleted file mode 100644 index 7cc4c0330b53..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Renesas R8A7778 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A7778. It includes two PLLs and -several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be "renesas,r8a7778-cpg-clocks" - - reg: Base address and length of the memory resource used by the CPG - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are - "plla", "pllb", "b", "out", "p", "s", and "s1". - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7778-cpg-clocks"; - reg = <0xffc80000 0x80>; - #clock-cells = <1>; - clocks = <&extal_clk>; - clock-output-names = "plla", "pllb", "b", - "out", "p", "s", "s1"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - sdhi0: sd@ffe4c000 { - compatible = "renesas,sdhi-r8a7778"; - reg = <0xffe4c000 0x100>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt deleted file mode 100644 index 8c81547c29f5..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Renesas R8A7779 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R8A7779. It includes one PLL and -several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be "renesas,r8a7779-cpg-clocks" - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the parent clock - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are "plla", - "z", "zs", "s", "s1", "p", "b", "out". - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@ffc80000 { - compatible = "renesas,r8a7779-cpg-clocks"; - reg = <0xffc80000 0x30>; - clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "plla", "z", "zs", "s", "s1", "p", - "b", "out"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; - reg = <0xfc600000 0x2000>; - interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7779_CLK_SATA>; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt deleted file mode 100644 index aed713cf0831..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt +++ /dev/null @@ -1,46 +0,0 @@ -* Renesas R9A06G032 SYSCTRL - -Required Properties: - - - compatible: Must be: - - "renesas,r9a06g032-sysctrl" - - reg: Base address and length of the SYSCTRL IO block. - - #clock-cells: Must be 1 - - clocks: References to the parent clocks: - - external 40mhz crystal. - - external (optional) 32.768khz - - external (optional) jtag input - - external (optional) RGMII_REFCLK - - clock-names: Must be: - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - - #power-domain-cells: Must be 0 - -Examples --------- - - - SYSCTRL node: - - sysctrl: system-controller@4000c000 { - compatible = "renesas,r9a06g032-sysctrl"; - reg = <0x4000c000 0x1000>; - #clock-cells = <1>; - - clocks = <&ext_mclk>, <&ext_rtc_clk>, - <&ext_jtag_clk>, <&ext_rgmii_ref>; - clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; - #power-domain-cells = <0>; - }; - - - Other nodes can use the clocks provided by SYSCTRL as in: - - #include <dt-bindings/clock/r9a06g032-sysctrl.h> - uart0: serial@40060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x40060000 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - power-domains = <&sysctrl>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml new file mode 100644 index 000000000000..26d94cedc871 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1D (R9A06G032) System Controller + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +properties: + compatible: + const: renesas,r9a06g032-sysctrl + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: External 40 MHz crystal + - description: Optional external 32.768 kHz crystal + - description: Optional external JTAG input + - description: Optional external RGMII_REFCLK + + clock-names: + minItems: 1 + items: + - const: mclk + - const: rtc + - const: jtag + - const: rgmii_ref_ext + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 0 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^dma-router@[a-f0-9]+$": + type: object + $ref: /schemas/dma/renesas,rzn1-dmamux.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, + <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt deleted file mode 100644 index 83f6c6a7c41c..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Renesas R-Car USB 2.0 clock selector - -This file provides information on what the device node for the R-Car USB 2.0 -clock selector. - -If you connect an external clock to the USB_EXTAL pin only, you should set -the clock rate to "usb_extal" node only. -If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module -is not needed because this is default setting. (Of course, you can set the -clock rates to both "usb_extal" and "usb_xtal" nodes. - -Case 1: An external clock connects to R-Car SoC - +----------+ +--- R-Car ---------------------+ - |External |---|USB_EXTAL ---> all usb channels| - |clock | |USB_XTAL | - +----------+ +-------------------------------+ -In this case, we need this driver with "usb_extal" clock. - -Case 2: An oscillator connects to R-Car SoC - +----------+ +--- R-Car ---------------------+ - |Oscillator|---|USB_EXTAL -+-> all usb channels| - | |---|USB_XTAL --+ | - +----------+ +-------------------------------+ -In this case, we don't need this selector. - -Required properties: -- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of - an R8A7795 SoC. - "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of - an R8A7796 SoC. - "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3 - compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the USB 2.0 clock selector register block. -- clocks: A list of phandles and specifier pairs. -- clock-names: Name of the clocks. - - The functional clock must be "ehci_ohci" - - The USB_EXTAL clock pin must be "usb_extal" - - The USB_XTAL clock pin must be "usb_xtal" -- #clock-cells: Must be 0 - -Example (R-Car H3): - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a7795-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>; - clock-names = "ehci_ohci", "usb_extal", "usb_xtal"; - #clock-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml new file mode 100644 index 000000000000..c84f29f1810f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car USB 2.0 clock selector + +maintainers: + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +description: | + If you connect an external clock to the USB_EXTAL pin only, you should set + the clock rate to "usb_extal" node only. + If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module + is not needed because this is default setting. (Of course, you can set the + clock rates to both "usb_extal" and "usb_xtal" nodes. + + Case 1: An external clock connects to R-Car SoC + +----------+ +--- R-Car ---------------------+ + |External |---|USB_EXTAL ---> all usb channels| + |clock | |USB_XTAL | + +----------+ +-------------------------------+ + + In this case, we need this driver with "usb_extal" clock. + + Case 2: An oscillator connects to R-Car SoC + +----------+ +--- R-Car ---------------------+ + |Oscillator|---|USB_EXTAL -+-> all usb channels| + | |---|USB_XTAL --+ | + +----------+ +-------------------------------+ + In this case, we don't need this selector. + +properties: + compatible: + items: + - enum: + - renesas,r8a774a1-rcar-usb2-clock-sel # RZ/G2M + - renesas,r8a774b1-rcar-usb2-clock-sel # RZ/G2N + - renesas,r8a774e1-rcar-usb2-clock-sel # RZ/G2H + - renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3 + - renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W + - renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+ + - const: renesas,rcar-gen3-usb2-clock-sel + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: ehci_ohci + - const: hs-usb-if + - const: usb_extal + - const: usb_xtal + + '#clock-cells': + const: 0 + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: ehci_ohci + - const: hs-usb-if + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7795-cpg-mssr.h> + #include <dt-bindings/power/r8a7795-sysc.h> + + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a7795-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0xe6590630 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal>, <&usb_xtal>; + clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt deleted file mode 100644 index 8ff3e2774ed8..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Renesas RZ/A1 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable -CPU and GPU clocks, and several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be one of - - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG - and "renesas,rz-cpg-clocks" as a fallback. - - reg: Base address and length of the memory resource used by the CPG - - clocks: References to possible parent clocks. Order must match clock modes - in the datasheet. For the r7s72100, this is extal, usb_x1. - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are "pll", - "i", and "g" - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml new file mode 100644 index 000000000000..80a8c7114c31 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: | + On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module + Standby Mode share the same register block. On RZ/V2M, the functionality is + similar, but does not have Clock Monitor Registers. + + They provide the following functionalities: + - The CPG block generates various core clocks, + - The Module Standby Mode block provides two functions: + 1. Module Standby, providing a Clock Domain to control the clock supply + to individual SoC devices, + 2. Reset Control, to perform a software reset of individual SoC devices. + +properties: + compatible: + enum: + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five + - renesas,r9a07g044-cpg # RZ/G2{L,LC} + - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a08g045-cpg # RZ/G3S + - renesas,r9a09g011-cpg # RZ/V2M + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: + Clock source to CPG can be either from external clock input (EXCLK) or + crystal oscillator (XIN/XOUT). + const: extal + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + <dt-bindings/clock/r9a0*-cpg.h>, + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>. + const: 2 + + '#power-domain-cells': + description: + SoC devices that are part of the CPG/Module Standby Mode Clock Domain and + can be power-managed through Module Standby should refer to the CPG device + node in their "power-domains" property, as documented by the generic PM + Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the module number, as defined in + <dt-bindings/clock/r9a0*-cpg.h>. + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g044-cpg"; + reg = <0x11010000 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt deleted file mode 100644 index a8978ec94831..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt +++ /dev/null @@ -1,35 +0,0 @@ -These bindings should be considered EXPERIMENTAL for now. - -* Renesas SH73A0 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs -and several fixed ratio dividers. - -Required Properties: - - - compatible: Must be "renesas,sh73a0-cpg-clocks" - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b", - "m1", "m2", "z", "zx", and "hp". - - -Example -------- - - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,sh73a0-cpg-clocks"; - reg = <0 0xe6150000 0 0x10000>; - clocks = <&extal1_clk>, <&extal2_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll2", - "pll3", "dsi0phy", "dsi1phy", - "zg", "m3", "b", "m1", "m2", - "z", "zx", "hp"; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml new file mode 100644 index 000000000000..b339f1f9f072 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Versaclock7 Programmable Clock + +maintainers: + - Alex Helms <alexander.helms.jy@renesas.com> + +description: | + Renesas Versaclock7 is a family of configurable clock generator and + jitter attenuator ICs with fractional and integer dividers. + +properties: + '#clock-cells': + const: 1 + + compatible: + enum: + - renesas,rc21008a + + reg: + maxItems: 1 + + clocks: + items: + - description: External crystal or oscillator + + clock-names: + items: + - const: xin + +required: + - '#clock-cells' + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + vc7_xin: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49152000>; + }; + + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + vc7: clock-controller@9 { + compatible = "renesas,rc21008a"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt deleted file mode 100644 index 55e78cddec8c..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Rockchip PX30 Clock and Reset Unit - -The PX30 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" -- compatible: CRU should be "rockchip,px30-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names -- clock-names: Should contain the following: - - "xin24m" for both PMUCRU and CRU - - "gpll" for CRU (sourced from PMUCRU) -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "i2sx_clkin" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml new file mode 100644 index 000000000000..0f0f64b6f8cb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The PX30 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "i2sx_clkin" - external I2S clock - optional + - "gmac_clkin" - external GMAC clock - optional + +properties: + compatible: + enum: + - rockchip,px30-cru + - rockchip,px30-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + items: + - description: Clock for both PMUCRU and CRU + - description: Clock for CRU (sourced from PMUCRU) + + clock-names: + minItems: 1 + items: + - const: xin24m + - const: gpll + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-cru + + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/px30-cru.h> + + pmucru: clock-controller@ff2bc000 { + compatible = "rockchip,px30-pmucru"; + reg = <0xff2bc000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0xff2b0000 0x1000>; + clocks = <&xin24m>, <&pmucru PLL_GPLL>; + clock-names = "xin24m", "gpll"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt deleted file mode 100644 index 20df350b9ef3..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Rockchip RK3036 Clock and Reset Unit - -The RK3036 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3036-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "rmii_clkin" - external EMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@20060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml new file mode 100644 index 000000000000..ba5b45464315 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3036 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3036 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "ext_i2s" - external I2S clock - optional + - "rmii_clkin" - external EMAC clock - optional + +properties: + compatible: + enum: + - rockchip,rk3036-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt deleted file mode 100644 index 6f8744fd301b..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3126/RK3128 Clock and Reset Unit - -The RK3126/RK3128 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru" - "rockchip,rk3126-cru" - controller compatible with RK3126 SoC. - "rockchip,rk3128-cru" - controller compatible with RK3128 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart2: serial@20068000 { - compatible = "rockchip,serial"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "sclk_uart", "pclk_uart"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml new file mode 100644 index 000000000000..b3d9c8eca989 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3126/RK3128 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + +properties: + compatible: + enum: + - rockchip,rk3126-cru + - rockchip,rk3128-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + items: + - const: xin24m + - enum: + - ext_i2s + - gmac_clkin + - enum: + - ext_i2s + - gmac_clkin + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 7f368530a2e4..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml new file mode 100644 index 000000000000..ddd7e46af0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3188/RK3066 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3188-cru.h and + dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. + Similar macros exist for the reset sources in these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - RTC clock - optional + - "xin27m" - 27mhz crystal input on RK3066 - optional + - "ext_hsadc" - external HSADC clock - optional + - "ext_cif0" - external camera clock - optional + - "ext_rmii" - external RMII clock - optional + - "ext_jtag" - external JTAG clock - optional + +properties: + compatible: + enum: + - rockchip,rk3066a-cru + - rockchip,rk3188-cru + - rockchip,rk3188a-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt deleted file mode 100644 index f323048127eb..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3228 Clock and Reset Unit - -The RK3228 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3228-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10110000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10110000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml new file mode 100644 index 000000000000..1050fff72ade --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3228 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3228 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + +properties: + compatible: + enum: + - rockchip,rk3228-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index 8cb47c39ba53..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml new file mode 100644 index 000000000000..6655e97d52e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3288 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3288 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + + A revision of this SoC is available: rk3288w. The clock tree is a bit + different so another dt-compatible is available. Noticed that it is only + setting the difference but there is no automatic revision detection. This + should be performed by boot loaders. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_hsadc" - external HSADC clock - optional, + - "ext_edp_24m" - external display port clock - optional, + - "ext_vip" - external VIP clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + +properties: + compatible: + enum: + - rockchip,rk3288-cru + - rockchip,rk3288w-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt deleted file mode 100644 index 9b151c5b0c90..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Rockchip RK3308 Clock and Reset Unit - -The RK3308 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: CRU should be "rockchip,rk3308-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in", - "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in", - "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional, - - "mac_clkin" - external MAC clock - optional - -Example: Clock controller node: - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml new file mode 100644 index 000000000000..fec37f5b80f6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3308 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3308 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", + "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in", + "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or + SPDIF clock - optional + - "mac_clkin" - external MAC clock - optional + +properties: + compatible: + enum: + - rockchip,rk3308-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0xff500000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt deleted file mode 100644 index 7c8bbcfed8d2..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3368 Clock and Reset Unit - -The RK3368 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3368-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - - "ext_vip" - external VIP clock - optional, - - "usbotg_out" - output clock of the pll in the otg phy - -Example: Clock controller node: - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3368-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml new file mode 100644 index 000000000000..90af242b41c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3368 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3368 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "ext_isp" - external ISP clock - optional + - "ext_jtag" - external JTAG clock - optional + - "ext_vip" - external VIP clock - optional + - "usbotg_out" - output clock of the pll in the otg phy + +properties: + compatible: + enum: + - rockchip,rk3368-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt deleted file mode 100644 index 3bc56fae90ac..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Rockchip RK3399 Clock and Reset Unit - -The RK3399 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" -- compatible: CRU should be "rockchip,rk3399-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files". - It is used for GRF muxes, if missing any muxes present in the GRF will not - be available. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "clkin_gmac" - external GMAC clock - optional, - - "clkin_i2s" - external I2S clock - optional, - - "pclkin_cif" - external ISP clock - optional, - - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 - -Example: Clock controller node: - - pmucru: pmu-clock-controller@ff750000 { - compatible = "rockchip,rk3399-pmucru"; - reg = <0x0 0xff750000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3399-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff1a0000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml new file mode 100644 index 000000000000..0b758e015ee3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3399 Clock and Reset Unit + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3399 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "clkin_gmac" - external GMAC clock - optional, + - "clkin_i2s" - external I2S clock - optional, + - "pclkin_cif" - external ISP clock - optional, + - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 + - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 + +properties: + compatible: + enum: + - rockchip,rk3399-pmucru + - rockchip,rk3399-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files". It is used + for GRF muxes, if missing any muxes present in the GRF will not be + available. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + pmucru: clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0xff750000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0xff760000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml new file mode 100644 index 000000000000..f809c289445e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROCKCHIP rk3568 Family Clock Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3568 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module) + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be + used in device tree sources. + +properties: + compatible: + enum: + - rockchip,rk3568-cru + - rockchip,rk3568-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0xfdd00000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0xfdd20000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml new file mode 100644 index 000000000000..74cd3f3f229a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3588 Family Clock and Reset Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3588 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clock and reset IDs + are defined as preprocessor macros in dt-binding headers. + +properties: + compatible: + enum: + - rockchip,rk3588-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + + assigned-clocks: true + + assigned-clock-rates: true + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + phandle to the syscon managing the "general register files". It is used + for GRF muxes, if missing any muxes present in the GRF will not be + available. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0xfd7c0000 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt deleted file mode 100644 index 161326a4f9c1..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Rockchip RV1108 Clock and Reset Unit - -The RV1108 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rv1108-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_vip" - external VIP clock - optional - - "ext_i2s" - external I2S clock - optional - - "ext_gmac" - external GMAC clock - optional - - "hdmiphy" - external clock input derived from HDMI PHY - optional - - "usbphy" - external clock input derived from USB PHY - optional - -Example: Clock controller node: - - cru: cru@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml new file mode 100644 index 000000000000..4611d920b8df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1108 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RV1108 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "ext_vip" - external VIP clock - optional + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "hdmiphy" - external clock input derived from HDMI PHY - optional + - "usbphy" - external clock input derived from USB PHY - optional + +properties: + compatible: + enum: + - rockchip,rv1108-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml new file mode 100644 index 000000000000..0998f8b922bd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1126 Clock and Reset Unit + +maintainers: + - Jagan Teki <jagan@edgeble.ai> + - Finley Xiao <finley.xiao@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RV1126 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126-cru + - rockchip,rv1126-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml new file mode 100644 index 000000000000..d819dfaafff9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Audio SubSystem clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos-audss-clk.h header. + +properties: + compatible: + enum: + - samsung,exynos4210-audss-clock + - samsung,exynos5250-audss-clock + - samsung,exynos5410-audss-clock + - samsung,exynos5420-audss-clock + + clocks: + minItems: 2 + items: + - description: + Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is + used if not specified. + - description: + Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is + used if not specified. + - description: + Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not + specified. + - description: + PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified. + - description: + External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + + clock-names: + minItems: 2 + items: + - const: pll_ref + - const: pll_in + - const: sclk_audio + - const: sclk_pcm_in + - const: cdclk + + "#clock-cells": + const: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0c>; + #clock-cells = <1>; + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml new file mode 100644 index 000000000000..a36781a455b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + All available clocks are defined as preprocessor macros in + dt-bindings/clock/ headers. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos3250-cmu + - samsung,exynos3250-cmu-dmc + - samsung,exynos3250-cmu-isp + - samsung,exynos4210-clock + - samsung,exynos4212-clock + - samsung,exynos4412-clock + - samsung,exynos5250-clock + - items: + - enum: + - samsung,exynos5420-clock + - samsung,exynos5800-clock + - const: syscon + + clocks: + minItems: 1 + maxItems: 4 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5250.h> + clock: clock-controller@10010000 { + compatible = "samsung,exynos5250-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-ext-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-ext-clock.yaml new file mode 100644 index 000000000000..c98eff64f2b5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-ext-clock.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC external/osc/XXTI/XusbXTI clock + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins. + +properties: + compatible: + enum: + - samsung,clock-xxti + - samsung,clock-xusbxti + - samsung,exynos5420-oscclk + + "#clock-cells": + const: 0 + + clock-frequency: true + + clock-output-names: + maxItems: 1 + +required: + - compatible + - clock-frequency + +additionalProperties: false + +examples: + - | + fixed-rate-clocks { + clock { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos4412-isp-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos4412-isp-clock.yaml new file mode 100644 index 000000000000..bee13436d1ea --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos4412-isp-clock.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos4412 SoC ISP clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP) + All available clocks are defined as preprocessor macros in + dt-bindings/clock/ headers. + +properties: + compatible: + const: samsung,exynos4412-isp-clock + + clocks: + items: + - description: CLK_ACLK200 from the main clock controller + - description: CLK_ACLK400_MCUISP from the main clock controller + + clock-names: + items: + - const: aclk200 + - const: aclk400_mcuisp + + "#clock-cells": + const: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - power-domains + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos4.h> + clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml new file mode 100644 index 000000000000..b05f83533e3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml @@ -0,0 +1,382 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5260 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "fin_pll" - PLL input clock from XXTI + - "xrtcxti" - input clock from XRTCXTI + - "ioclk_pcm_extclk" - pcm external operation clock + - "ioclk_spdif_extclk" - spdif external operation clock + - "ioclk_i2s_cdclk" - i2s0 codec clock + + Phy clocks:: + There are several clocks which are generated by specific PHYs. These clocks + are fed into the clock controller and then routed to the hardware blocks. + These clocks are defined as fixed clocks in the driver with following names:: + - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 + - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 + - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 + - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 + - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock + - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock + - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link + - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock + - "phyclk_dptx_phy_clk_div2" + - "phyclk_mipi_dphy_4l_m_rxclkesc0" + - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock + - "phyclk_usbhost20_phy_freeclk" + - "phyclk_usbhost20_phy_clk48mohci" + - "phyclk_usbdrd30_udrd30_pipe_pclk" + - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos5260-clk.h header. + +properties: + compatible: + enum: + - samsung,exynos5260-clock-top + - samsung,exynos5260-clock-peri + - samsung,exynos5260-clock-egl + - samsung,exynos5260-clock-kfc + - samsung,exynos5260-clock-g2d + - samsung,exynos5260-clock-mif + - samsung,exynos5260-clock-mfc + - samsung,exynos5260-clock-g3d + - samsung,exynos5260-clock-fsys + - samsung,exynos5260-clock-aud + - samsung,exynos5260-clock-isp + - samsung,exynos5260-clock-gscl + - samsung,exynos5260-clock-disp + + clocks: + minItems: 1 + maxItems: 19 + + clock-names: + minItems: 1 + maxItems: 19 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-top + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: fin_pll + - const: dout_mem_pll + - const: dout_bus_pll + - const: dout_media_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-peri + then: + properties: + clocks: + minItems: 13 + maxItems: 13 + clock-names: + items: + - const: fin_pll + - const: ioclk_pcm_extclk + - const: ioclk_i2s_cdclk + - const: ioclk_spdif_extclk + - const: phyclk_hdmi_phy_ref_cko + - const: dout_aclk_peri_66 + - const: dout_sclk_peri_uart0 + - const: dout_sclk_peri_uart1 + - const: dout_sclk_peri_uart2 + - const: dout_sclk_peri_spi0_b + - const: dout_sclk_peri_spi1_b + - const: dout_sclk_peri_spi2_b + - const: dout_aclk_peri_aud + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-egl + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_bus_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-kfc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_media_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-g2d + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_g2d_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-mif + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: fin_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-mfc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_mfc_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-g3d + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: fin_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-fsys + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: fin_pll + - const: phyclk_usbhost20_phy_phyclock + - const: phyclk_usbhost20_phy_freeclk + - const: phyclk_usbhost20_phy_clk48mohci + - const: phyclk_usbdrd30_udrd30_pipe_pclk + - const: phyclk_usbdrd30_udrd30_phyclock + - const: dout_aclk_fsys_200 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-aud + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: fin_pll + - const: fout_aud_pll + - const: ioclk_i2s_cdclk + - const: ioclk_pcm_extclk + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-isp + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_isp1_266 + - const: dout_aclk_isp1_400 + - const: mout_aclk_isp1_266 + + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-gscl + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_gscl_400 + - const: dout_aclk_gscl_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5260-clock-disp + then: + properties: + clocks: + minItems: 19 + maxItems: 19 + clock-names: + items: + - const: fin_pll + - const: phyclk_dptx_phy_ch3_txd_clk + - const: phyclk_dptx_phy_ch2_txd_clk + - const: phyclk_dptx_phy_ch1_txd_clk + - const: phyclk_dptx_phy_ch0_txd_clk + - const: phyclk_hdmi_phy_tmds_clko + - const: phyclk_hdmi_phy_ref_clko + - const: phyclk_hdmi_phy_pixel_clko + - const: phyclk_hdmi_link_o_tmds_clkhi + - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs + - const: phyclk_dptx_phy_o_ref_clk_24m + - const: phyclk_dptx_phy_clk_div2 + - const: phyclk_mipi_dphy_4l_m_rxclkesc0 + - const: phyclk_hdmi_phy_ref_cko + - const: ioclk_spdif_extclk + - const: dout_aclk_peri_aud + - const: dout_aclk_disp_222 + - const: dout_sclk_disp_pixel + - const: dout_aclk_disp_333 + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5260-clk.h> + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + clock-controller@10010000 { + compatible = "samsung,exynos5260-clock-top"; + reg = <0x10010000 0x10000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEM_PLL>, + <&clock_mif MIF_DOUT_BUS_PLL>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_mem_pll", + "dout_bus_pll", + "dout_media_pll"; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml new file mode 100644 index 000000000000..b737c9d35a1c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5410 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "fin_pll" - PLL input clock from XXTI + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos5410.h header. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos5410-clock + + clocks: + description: + Should contain an entry specifying the root clock from external + oscillator supplied through XXTI or XusbXTI pin. This clock should be + defined using standard clock bindings with "fin_pll" clock-output-name. + That clock is being passed internally to the 9 PLLs. + maxItems: 1 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5410.h> + + fin_pll: osc-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + clock-controller@10010000 { + compatible = "samsung,exynos5410-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml new file mode 100644 index 000000000000..3f9326e09f79 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml @@ -0,0 +1,524 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5433 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "oscclk" - PLL input clock from XXTI + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos5433.h header. + +properties: + compatible: + enum: + # CMU_TOP which generates clocks for + # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus + # clocks + - samsung,exynos5433-cmu-top + # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP + - samsung,exynos5433-cmu-cpif + # CMU_MIF which generates clocks for DRAM Memory Controller domain + - samsung,exynos5433-cmu-mif + # CMU_PERIC which generates clocks for + # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs + - samsung,exynos5433-cmu-peric + # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs + - samsung,exynos5433-cmu-peris + # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs + - samsung,exynos5433-cmu-fsys + - samsung,exynos5433-cmu-g2d + # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs + - samsung,exynos5433-cmu-disp + - samsung,exynos5433-cmu-aud + - samsung,exynos5433-cmu-bus0 + - samsung,exynos5433-cmu-bus1 + - samsung,exynos5433-cmu-bus2 + - samsung,exynos5433-cmu-g3d + - samsung,exynos5433-cmu-gscl + - samsung,exynos5433-cmu-apollo + # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor, + # CoreSight and L2 cache controller + - samsung,exynos5433-cmu-atlas + # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and + # JPEG IPs + - samsung,exynos5433-cmu-mscl + - samsung,exynos5433-cmu-mfc + - samsung,exynos5433-cmu-hevc + # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs + - samsung,exynos5433-cmu-isp + # CMU_CAM0 which generates clocks for + # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs + - samsung,exynos5433-cmu-cam0 + # CMU_CAM1 which generates clocks for + # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs + - samsung,exynos5433-cmu-cam1 + # CMU_IMEM which generates clocks for SSS (Security SubSystem) and + # SlimSSS IPs + - samsung,exynos5433-cmu-imem + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-top + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: oscclk + - const: sclk_mphy_pll + - const: sclk_mfc_pll + - const: sclk_bus_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-cpif + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: oscclk + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-mif + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: sclk_mphy_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-fsys + then: + properties: + clocks: + minItems: 10 + maxItems: 10 + clock-names: + items: + - const: oscclk + - const: sclk_ufs_mphy + - const: aclk_fsys_200 + - const: sclk_pcie_100_fsys + - const: sclk_ufsunipro_fsys + - const: sclk_mmc2_fsys + - const: sclk_mmc1_fsys + - const: sclk_mmc0_fsys + - const: sclk_usbhost30_fsys + - const: sclk_usbdrd30_fsys + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-g2d + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: aclk_g2d_266 + - const: aclk_g2d_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-disp + then: + properties: + clocks: + minItems: 9 + maxItems: 9 + clock-names: + items: + - const: oscclk + - const: sclk_dsim1_disp + - const: sclk_dsim0_disp + - const: sclk_dsd_disp + - const: sclk_decon_tv_eclk_disp + - const: sclk_decon_vclk_disp + - const: sclk_decon_eclk_disp + - const: sclk_decon_tv_vclk_disp + - const: aclk_disp_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-aud + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: fout_aud_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-bus0 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: aclk_bus0_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-bus1 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: aclk_bus1_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-bus2 + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_bus2_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-g3d + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_g3d_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-gscl + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: aclk_gscl_111 + - const: aclk_gscl_333 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-apollo + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: sclk_bus_pll_apollo + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-atlas + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: sclk_bus_pll_atlas + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-mscl + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: sclk_jpeg_mscl + - const: aclk_mscl_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-mfc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_mfc_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-hevc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: oscclk + - const: aclk_hevc_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-isp + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: oscclk + - const: aclk_isp_dis_400 + - const: aclk_isp_400 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-cam0 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: oscclk + - const: aclk_cam0_333 + - const: aclk_cam0_400 + - const: aclk_cam0_552 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-cam1 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: oscclk + - const: sclk_isp_uart_cam1 + - const: sclk_isp_spi1_cam1 + - const: sclk_isp_spi0_cam1 + - const: aclk_cam1_333 + - const: aclk_cam1_400 + - const: aclk_cam1_552 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-cmu-imem + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: oscclk + - const: aclk_imem_sssx_266 + - const: aclk_imem_266 + - const: aclk_imem_200 + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5433.h> + xxti: clock { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + clock-controller@10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml new file mode 100644 index 000000000000..c137c6744ef9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml @@ -0,0 +1,272 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "fin_pll" - PLL input clock from XXTI + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/exynos7-clk.h header. + +properties: + compatible: + enum: + - samsung,exynos7-clock-topc + - samsung,exynos7-clock-top0 + - samsung,exynos7-clock-top1 + - samsung,exynos7-clock-ccore + - samsung,exynos7-clock-peric0 + - samsung,exynos7-clock-peric1 + - samsung,exynos7-clock-peris + - samsung,exynos7-clock-fsys0 + - samsung,exynos7-clock-fsys1 + - samsung,exynos7-clock-mscl + - samsung,exynos7-clock-aud + + clocks: + minItems: 1 + maxItems: 13 + + clock-names: + minItems: 1 + maxItems: 13 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-top0 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: fin_pll + - const: dout_sclk_bus0_pll + - const: dout_sclk_bus1_pll + - const: dout_sclk_cc_pll + - const: dout_sclk_mfc_pll + - const: dout_sclk_aud_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-top1 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: fin_pll + - const: dout_sclk_bus0_pll + - const: dout_sclk_bus1_pll + - const: dout_sclk_cc_pll + - const: dout_sclk_mfc_pll + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-ccore + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_ccore_133 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-peric0 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_peric0_66 + - const: sclk_uart0 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-peric1 + then: + properties: + clocks: + minItems: 13 + maxItems: 13 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_peric1_66 + - const: sclk_uart1 + - const: sclk_uart2 + - const: sclk_uart3 + - const: sclk_spi0 + - const: sclk_spi1 + - const: sclk_spi2 + - const: sclk_spi3 + - const: sclk_spi4 + - const: sclk_i2s1 + - const: sclk_pcm1 + - const: sclk_spdif + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-peris + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_peris_66 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-fsys0 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_fsys0_200 + - const: dout_sclk_mmc2 + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-fsys1 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: fin_pll + - const: dout_aclk_fsys1_200 + - const: dout_sclk_mmc0 + - const: dout_sclk_mmc1 + - const: dout_sclk_ufsunipro20 + - const: dout_sclk_phy_fsys1 + - const: dout_sclk_phy_fsys1_26m + required: + - clock-names + - clocks + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-clock-aud + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: fin_pll + - const: fout_aud_pll + required: + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos7-clk.h> + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + clock-controller@105e0000 { + compatible = "samsung,exynos7-clock-top1"; + reg = <0x105e0000 0xb000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_topc DOUT_SCLK_BUS0_PLL>, + <&clock_topc DOUT_SCLK_BUS1_PLL>, + <&clock_topc DOUT_SCLK_CC_PLL>, + <&clock_topc DOUT_SCLK_MFC_PLL>; + clock-names = "fin_pll", + "dout_sclk_bus0_pll", + "dout_sclk_bus1_pll", + "dout_sclk_cc_pll", + "dout_sclk_mfc_pll"; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml new file mode 100644 index 000000000000..006d33a9e0f1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7885 SoC clock controller + +maintainers: + - Dávid Virág <virag.david003@gmail.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Exynos7885 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos7885.h' header. + +properties: + compatible: + enum: + - samsung,exynos7885-cmu-top + - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-fsys + - samsung,exynos7885-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_g3d + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_TOP) + - description: MMC_CARD clock (from CMU_TOP) + - description: MMC_EMBD clock (from CMU_TOP) + - description: MMC_SDIO clock (from CMU_TOP) + - description: USB30DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_fsys_bus + - const: dout_fsys_mmc_card + - const: dout_fsys_mmc_embd + - const: dout_fsys_mmc_sdio + - const: dout_fsys_usb30drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: SPI0 clock (from CMU_TOP) + - description: SPI1 clock (from CMU_TOP) + - description: UART0 clock (from CMU_TOP) + - description: UART1 clock (from CMU_TOP) + - description: UART2 clock (from CMU_TOP) + - description: USI0 clock (from CMU_TOP) + - description: USI1 clock (from CMU_TOP) + - description: USI2 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_spi0 + - const: dout_peri_spi1 + - const: dout_peri_uart0 + - const: dout_peri_uart1 + - const: dout_peri_uart2 + - const: dout_peri_usi0 + - const: dout_peri_usi1 + - const: dout_peri_usi2 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include <dt-bindings/clock/exynos7885.h> + + cmu_peri: clock-controller@10010000 { + compatible = "samsung,exynos7885-cmu-peri"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_SPI0>, + <&cmu_top CLK_DOUT_PERI_SPI1>, + <&cmu_top CLK_DOUT_PERI_UART0>, + <&cmu_top CLK_DOUT_PERI_UART1>, + <&cmu_top CLK_DOUT_PERI_UART2>, + <&cmu_top CLK_DOUT_PERI_USI0>, + <&cmu_top CLK_DOUT_PERI_USI1>, + <&cmu_top CLK_DOUT_PERI_USI2>; + clock-names = "oscclk", + "dout_peri_bus", + "dout_peri_spi0", + "dout_peri_spi1", + "dout_peri_uart0", + "dout_peri_uart1", + "dout_peri_uart2", + "dout_peri_usi0", + "dout_peri_usi1", + "dout_peri_usi2"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml new file mode 100644 index 000000000000..c752c8985a53 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -0,0 +1,311 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos850 SoC clock controller + +maintainers: + - Sam Protsenko <semen.protsenko@linaro.org> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Exynos850 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + clocks must be defined as fixed-rate clocks in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos850.h' header. + +properties: + compatible: + enum: + - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-aud + - samsung,exynos850-cmu-cmgp + - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d + - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-is + - samsung,exynos850-cmu-mfcmscl + - samsung,exynos850-cmu-peri + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_APM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_apm_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-aud + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: AUD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_aud + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CMGP bus clock (from CMU_APM) + + clock-names: + items: + - const: oscclk + - const: gout_clkcmu_cmgp_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: eMMC clock (from CMU_TOP) + - description: SSS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_mmc_embd + - const: dout_core_sss + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: DPU clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_dpu + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-hsi + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI bus clock (from CMU_TOP) + - description: SD card clock (from CMU_TOP) + - description: USB 2.0 DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: dout_hsi_bus + - const: dout_hsi_mmc_card + - const: dout_hsi_usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-is + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_IS bus clock (from CMU_TOP) + - description: Image Texture Processing core clock (from CMU_TOP) + - description: Visual Recognition Accelerator clock (from CMU_TOP) + - description: Geometric Distortion Correction clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_is_bus + - const: dout_is_itp + - const: dout_is_vra + - const: dout_is_gdc + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-mfcmscl + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Multi-Format Codec clock (from CMU_TOP) + - description: Memory to Memory Scaler clock (from CMU_TOP) + - description: Multi-Channel Scaler clock (from CMU_TOP) + - description: JPEG codec clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_mfcmscl_mfc + - const: dout_mfcmscl_m2m + - const: dout_mfcmscl_mcsc + - const: dout_mfcmscl_jpeg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: UART clock (from CMU_TOP) + - description: Parent clock for HSI2C and SPI (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_uart + - const: dout_peri_ip + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include <dt-bindings/clock/exynos850.h> + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml new file mode 100644 index 000000000000..55c4f94a14d1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -0,0 +1,263 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Auto v9 SoC clock controller + +maintainers: + - Chanho Park <chanho61.park@samsung.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Exynos Auto v9 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). + The external OSCCLK must be defined as fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynosautov9.h' header. + +properties: + compatible: + enum: + - samsung,exynosautov9-cmu-top + - samsung,exynosautov9-cmu-busmc + - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-fsys0 + - samsung,exynosautov9-cmu-fsys1 + - samsung,exynosautov9-cmu-fsys2 + - samsung,exynosautov9-cmu-peric0 + - samsung,exynosautov9-cmu-peric1 + - samsung,exynosautov9-cmu-peris + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-busmc + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_BUSMC bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_busmc_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_core_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS0 bus clock (from CMU_TOP) + - description: CMU_FSYS0 pcie clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys0_bus + - const: dout_clkcmu_fsys0_pcie + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS1 bus clock (from CMU_TOP) + - description: CMU_FSYS1 mmc card clock (from CMU_TOP) + - description: CMU_FSYS1 usb clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys1_bus + - const: gout_clkcmu_fsys1_mmc_card + - const: dout_clkcmu_fsys1_usbdrd + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys2 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS2 bus clock (from CMU_TOP) + - description: UFS clock (from CMU_TOP) + - description: Ethernet clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys2_bus + - const: dout_fsys2_clkcmu_ufs_embd + - const: dout_fsys2_clkcmu_ethernet + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC0 bus clock (from CMU_TOP) + - description: PERIC0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric0_bus + - const: dout_clkcmu_peric0_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC1 bus clock (from CMU_TOP) + - description: PERIC1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric1_bus + - const: dout_clkcmu_peric1_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peris_bus + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS2 + - | + #include <dt-bindings/clock/samsung,exynosautov9.h> + + cmu_fsys2: clock-controller@17c00000 { + compatible = "samsung,exynosautov9-cmu-fsys2"; + reg = <0x17c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, + <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; + clock-names = "oscclk", + "dout_clkcmu_fsys2_bus", + "dout_fsys2_clkcmu_ufs_embd", + "dout_fsys2_clkcmu_ethernet"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,s2mps11.txt b/Documentation/devicetree/bindings/clock/samsung,s2mps11.txt deleted file mode 100644 index 2726c1d58a79..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s2mps11.txt +++ /dev/null @@ -1,49 +0,0 @@ -Binding for Samsung S2M and S5M family clock generator block -============================================================ - -This is a part of device tree bindings for S2M and S5M family multi-function -devices. -More information can be found in bindings/mfd/sec-core.txt file. - -The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz -outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs. - -To register these as clocks with common clock framework instantiate under -main device node a sub-node named "clocks". - -It uses the common clock binding documented in: - - Documentation/devicetree/bindings/clock/clock-bindings.txt - - -Required properties of the "clocks" sub-node: - - #clock-cells: should be 1. - - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", - "samsung,s2mps14-clk", "samsung,s5m8767-clk" - The S2MPS15 uses the same compatible as S2MPS13, as both provides similar - clocks. - - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - Clock ID Devices - ---------------------------------------------------------- - 32KhzAP 0 S2MPS11/13/14/15, S5M8767 - 32KhzCP 1 S2MPS11/13/15, S5M8767 - 32KhzBT 2 S2MPS11/13/14/15, S5M8767 - -Include dt-bindings/clock/samsung,s2mps11.h file to use preprocessor defines -in device tree sources. - - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2m_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "xx", "yy", "zz"; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml b/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml new file mode 100644 index 000000000000..d5296e6053a1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,s2mps11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2M and S5M family clock generator block + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz + outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs. + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/samsung,s2mps11.h header. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mps11-clk + - samsung,s2mps13-clk # S2MPS13 and S2MPS15 + - samsung,s2mps14-clk + - samsung,s5m8767-clk + + "#clock-cells": + const: 1 + + clock-output-names: + maxItems: 3 + description: Names for AP, CP and BT clocks. + +required: + - compatible + - "#clock-cells" + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt deleted file mode 100644 index 2632d3f13004..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2410 Clock Controller - -The S3C2410 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2410, -s3c2440 and s3c2442 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC. - - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC. - - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2410.h header and can be used in device -tree sources. - -External clocks: - -The xti clock used as input for the plls is generated outside the SoC. It is -expected that is are defined using standard clock bindings with a -clock-output-names value of "xti". - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2410-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt deleted file mode 100644 index 21a8c23e658f..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2412 Clock Controller - -The S3C2412 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2412 -and s3c2413 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be "samsung,s3c2412-clock" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2412.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2412-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2412-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt deleted file mode 100644 index 985c0f574e9a..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Samsung S3C2443 Clock Controller - -The S3C2443 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to all SoCs in -the s3c24x family starting with the s3c2443. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC. - - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC. - - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2443.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_uart" - external uart clock - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-audss-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,s5pv210-audss-clock.yaml new file mode 100644 index 000000000000..2659854ea1c0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-audss-clock.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5Pv210 SoC Audio SubSystem clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/s5pv210-audss.h header. + +properties: + compatible: + const: samsung,s5pv210-audss-clock + + clocks: + minItems: 4 + items: + - description: + AHB bus clock of the Audio Subsystem. + - description: + Optional fixed rate PLL reference clock, parent of mout_audss. If not + specified (i.e. xusbxti is used for PLL reference), it is fixed to a + clock named "xxti". + - description: + Input PLL to the AudioSS block, parent of mout_audss. + - description: + Audio bus clock, parent of mout_i2s. + - description: + Optional external i2s clock, parent of mout_i2s. If not specified, it + is fixed to a clock named "iiscdclk0". + + clock-names: + minItems: 4 + items: + - const: hclk + - const: xxti + - const: fout_epll + - const: sclk_audio0 + - const: iiscdclk0 + + "#clock-cells": + const: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/s5pv210.h> + + clock-controller@c0900000 { + compatible = "samsung,s5pv210-audss-clock"; + reg = <0xc0900000 0x1000>; + #clock-cells = <1>; + clock-names = "hclk", "xxti", "fout_epll", "sclk_audio0"; + clocks = <&clocks DOUT_HCLKP>, <&xxti>, <&clocks FOUT_EPLL>, + <&clocks SCLK_AUDIO0>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt deleted file mode 100644 index a86c83bf9d4e..000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Samsung S5P6442/S5PC110/S5PV210 Clock Controller - -Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock -controller, which generates and supplies clock to various controllers -within the SoC. - -Required Properties: - -- compatible: should be one of following: - - "samsung,s5pv210-clock" : for clock controller of Samsung - S5PC110/S5PV210 SoCs, - - "samsung,s5p6442-clock" : for clock controller of Samsung - S5P6442 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s5pv210.h header and can be used in device tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xxti": external crystal oscillator connected to XXTI and XXTO pins of -the SoC, - - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO -pins of the SoC, - -A subset of above clocks available on given board shall be specified in -board device tree, including the system base clock, as selected by XOM[0] -pin of the SoC. Refer to generic fixed rate clock bindings -documentation[1] for more information how to specify these clocks. - -[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml - -Example: Clock controller node: - - clock: clock-controller@7e00f000 { - compatible = "samsung,s5pv210-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - -Example: Required external clocks: - - xxti: clock-xxti { - compatible = "fixed-clock"; - clock-output-names = "xxti"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - xusbxti: clock-xusbxti { - compatible = "fixed-clock"; - clock-output-names = "xusbxti"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - uart0: serial@e2900000 { - compatible = "samsung,s5pv210-uart"; - reg = <0xe2900000 0x400>; - interrupt-parent = <&vic1>; - interrupts = <10>; - clock-names = "uart", "clk_uart_baud0", - "clk_uart_baud1"; - clocks = <&clocks UART0>, <&clocks UART0>, - <&clocks SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml new file mode 100644 index 000000000000..67a33665cf00 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller + +maintainers: + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + Expected external clocks, defined in DTS as fixed-rate clocks with a matching + name:: + - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of + the SoC, + - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO + pins of the SoC, + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/s5pv210.h header. + +properties: + compatible: + enum: + - samsung,s5pv210-clock + - samsung,s5p6442-clock + + clocks: + items: + - description: xxti clock + - description: xusbxti clock + + clock-names: + items: + - const: xxti + - const: xusbxti + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/s5pv210.h> + + xxti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xxti"; + #clock-cells = <0>; + }; + + xusbxti: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xusbxti"; + #clock-cells = <0>; + }; + + clock-controller@e0100000 { + compatible = "samsung,s5pv210-clock"; + reg = <0xe0100000 0x10000>; + clock-names = "xxti", "xusbxti"; + clocks = <&xxti>, <&xusbxti>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt deleted file mode 100644 index 349808f4fb8c..000000000000 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt +++ /dev/null @@ -1,46 +0,0 @@ -SiFive FU540 PRCI bindings - -On the FU540 family of SoCs, most system-wide clock and reset integration -is via the PRCI IP block. - -Required properties: -- compatible: Should be "sifive,<chip>-prci". Only one value is - supported: "sifive,fu540-c000-prci" -- reg: Should describe the PRCI's register target physical address region -- clocks: Should point to the hfclk device tree node and the rtcclk - device tree node. The RTC clock here is not a time-of-day clock, - but is instead a high-stability clock source for system timers - and cycle counters. -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock via the clock ID -macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. -These macros begin with PRCI_CLK_. - -The hfclk and rtcclk nodes are required, and represent physical -crystals or resonators located on the PCB. These nodes should be present -underneath /, rather than /soc. - -Examples: - -/* under /, in PCB-specific DT data */ -hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; -}; -rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; -}; - -/* under /soc, in SoC-specific DT data */ -prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml new file mode 100644 index 000000000000..c79e752283aa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + On the FU540 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + const: sifive,fu540-c000-prci + + reg: + maxItems: 1 + + clocks: + items: + - description: high frequency clock. + - description: RTL clock. + + clock-names: + items: + - const: hfclk + - const: rtcclk + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml new file mode 100644 index 000000000000..252085a0cf65 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Zong Li <zong.li@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + On the FU740 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu740-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + const: sifive,fu740-c000-prci + + reg: + maxItems: 1 + + clocks: + items: + - description: high frequency clock. + - description: RTL clock. + + clock-names: + items: + - const: hfclk + - const: rtcclk + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + prci: clock-controller@10000000 { + compatible = "sifive,fu740-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si514.txt b/Documentation/devicetree/bindings/clock/silabs,si514.txt index ea1a9dbc63b6..a4f28ec86f35 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si514.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si514.txt @@ -6,7 +6,7 @@ found in the datasheet[2]. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Si514 datasheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf + https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf Required properties: - compatible: Shall be "silabs,si514" diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.txt b/Documentation/devicetree/bindings/clock/silabs,si5341.txt index a70c333e4cd4..ce55aba0ce22 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5341.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si5341.txt @@ -1,15 +1,21 @@ -Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator. +Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable +i2c clock generator. Reference [1] Si5341 Data Sheet https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf [2] Si5341 Reference Manual https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf +[3] Si5345 Reference Manual + https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which in turn can be directed to any of the 10 (or 4) outputs through a divider. The internal structure of the clock generators can be found in [2]. +The Si5345 is similar to the Si5341 with the addition of fractional input +dividers and automatic input selection, as described in [3]. +The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs. The driver can be used in "as is" mode, reading the current settings from the chip at boot, in case you have a (pre-)programmed device. If the PLL is not @@ -18,9 +24,8 @@ it. The device type, speed grade and revision are determined runtime by probing. -The driver currently only supports XTAL input mode, and does not support any -fancy input configurations. They can still be programmed into the chip and -the driver will leave them "as is". +The driver currently does not support any fancy input configurations. They can +still be programmed into the chip and the driver will leave them "as is". ==I2C device node== @@ -28,6 +33,9 @@ Required properties: - compatible: shall be one of the following: "silabs,si5340" - Si5340 A/B/C/D "silabs,si5341" - Si5341 A/B/C/D + "silabs,si5342" - Si5342 A/B/C/D + "silabs,si5344" - Si5344 A/B/C/D + "silabs,si5345" - Si5345 A/B/C/D - reg: i2c device address, usually 0x74 - #clock-cells: from common clock binding; shall be set to 2. The first value is "0" for outputs, "1" for synthesizers. @@ -36,9 +44,9 @@ Required properties: corresponding to inputs. Use a fixed clock for the "xtal" input. At least one must be present. - clock-names: One of: "xtal", "in0", "in1", "in2" -- vdd-supply: Regulator node for VDD Optional properties: +- vdd-supply: Regulator node for VDD - vdda-supply: Regulator node for VDDA - vdds-supply: Regulator node for VDDS - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL @@ -51,7 +59,14 @@ Optional properties: be initialized, and always performs the soft-reset routine. Since this will temporarily stop all output clocks, don't do this if the chip is generating the CPU clock for example. +- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used + in EXTCLK (external reference clock) rather than XTAL (crystal) mode. - interrupts: Interrupt for INTRb pin. +- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V + rather than 1.8V thresholds. +- vddoX-supply (where X is an output index): Regulator node for VDDO for the + specified output. The driver selects the output VDD_SEL setting based on this + voltage. - #address-cells: shall be set to 1. - #size-cells: shall be set to 0. @@ -68,8 +83,6 @@ Required child node properties: - reg: number of clock output. Optional child node properties: -- vdd-supply: Regulator node for VDD for this output. The driver selects default - values for common-mode and amplitude based on the voltage. - silabs,format: Output format, one of: 1 = differential (defaults to LVDS levels) 2 = low-power (defaults to HCSL levels) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt deleted file mode 100644 index f00191cad8cd..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ /dev/null @@ -1,126 +0,0 @@ -Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. - -Reference -[1] Si5351A/B/C Data Sheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf - -The Si5351a/b/c are programmable i2c clock generators with up to 8 output -clocks. Si5351a also has a reduced pin-count package (MSOP10) where only -3 output clocks are accessible. The internal structure of the clock -generators can be found in [1]. - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5351a" - Si5351a, QFN20 package - "silabs,si5351a-msop" - Si5351a, MSOP10 package - "silabs,si5351b" - Si5351b, QFN20 package - "silabs,si5351c" - Si5351c, QFN20 package -- reg: i2c device address, shall be 0x60 or 0x61. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be xtal reference clock or xtal and clkin for - si5351c only. Corresponding clock input names are "xtal" and - "clkin" respectively. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - -Optional properties: -- silabs,pll-source: pair of (number, source) for each pll. Allows - to overwrite clock source of pll A (number=0) or B (number=1). - -==Child nodes== - -Each of the clock outputs can be overwritten individually by -using a child node to the I2C device node. If a child node for a clock -output is not set, the eeprom configuration is not overwritten. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,clock-source: source clock of the output divider stage N, shall be - 0 = multisynth N - 1 = multisynth 0 for output clocks 0-3, else multisynth4 - 2 = xtal - 3 = clkin (si5351c only) -- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. -- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth - divider. -- silabs,pll-master: boolean, multisynth can change pll frequency. -- silabs,pll-reset: boolean, clock output can reset its pll. -- silabs,disable-state : clock output disable state, shall be - 0 = clock output is driven LOW when disabled - 1 = clock output is driven HIGH when disabled - 2 = clock output is FLOATING (HIGH-Z) when disabled - 3 = clock output is NEVER disabled - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* Si5351a msop10 i2c clock generator */ - si5351a: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - /* - * overwrite clkout0 configuration with: - * - 8mA output drive strength - * - pll0 as clock source of multisynth0 - * - multisynth0 as clock source of output divider - * - multisynth0 can change pll0 - * - set initial clock frequency of 74.25MHz - */ - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - clock-frequency = <74250000>; - }; - - /* - * overwrite clkout1 configuration with: - * - 4mA output drive strength - * - pll1 as clock source of multisynth1 - * - multisynth1 as clock source of output divider - * - multisynth1 can change pll1 - */ - clkout1 { - reg = <1>; - silabs,drive-strength = <4>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - pll-master; - }; - - /* - * overwrite clkout2 configuration with: - * - xtal as clock source of output divider - */ - clkout2 { - reg = <2>; - silabs,clock-source = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml new file mode 100644 index 000000000000..d3e0ec29993b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -0,0 +1,265 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si5351A/B/C programmable I2C clock generators + +description: | + The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to + 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 + output clocks are accessible. The internal structure of the clock generators + can be found in [1]. + + [1] Si5351A/B/C Data Sheet + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf + +maintainers: + - Alvin Šipraga <alsi@bang-olufsen.dk> + +properties: + compatible: + enum: + - silabs,si5351a # Si5351A, 20-QFN package + - silabs,si5351a-msop # Si5351A, 10-MSOP package + - silabs,si5351b # Si5351B, 20-QFN package + - silabs,si5351c # Si5351C, 20-QFN package + + reg: + enum: + - 0x60 + - 0x61 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#clock-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: xtal + - const: clkin + + silabs,pll-source: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of cell pairs containing a PLL index and its source. Allows to + overwrite clock source of the internal PLLs. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). + enum: [ 0, 1 ] + + silabs,pll-reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 2 + description: A list of cell pairs containing a PLL index and its reset mode. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: | + Reset mode for the PLL. Mode can be one of: + + 0 - reset whenever PLL rate is adjusted (default mode) + 1 - do not reset when PLL rate is adjusted + + In mode 1, the PLL is only reset if the silabs,pll-reset is + specified in one of the clock output child nodes that also sources + the PLL. This mode may be preferable if output clocks are expected + to be adjusted without glitches. + enum: [ 0, 1 ] + +patternProperties: + "^clkout@[0-7]$": + type: object + + additionalProperties: false + + properties: + reg: + description: Clock output number. + + clock-frequency: true + + silabs,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Source clock of the this output's divider stage. + + 0 - use multisynth N for this output, where N is the output number + 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4 + (otherwise) for this output + 2 - use XTAL for this output + 3 - use CLKIN for this output (Si5351C only) + + silabs,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2, 4, 6, 8 ] + description: Output drive strength in mA. + + silabs,multisynth-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Source PLL A (0) or B (1) for the corresponding multisynth divider. + + silabs,pll-master: + type: boolean + description: | + The frequency of the source PLL is allowed to be changed by the + multisynth when setting the rate of this clock output. + + silabs,pll-reset: + type: boolean + description: Reset the source PLL when enabling this clock output. + + silabs,disable-state: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + Clock output disable state. The state can be one of: + + 0 - clock output is driven LOW when disabled + 1 - clock output is driven HIGH when disabled + 2 - clock output is FLOATING (HIGH-Z) when disabled + 3 - clock output is never disabled + + allOf: + - if: + properties: + compatible: + contains: + const: silabs,si5351a-msop + then: + properties: + reg: + maximum: 2 + else: + properties: + reg: + maximum: 7 + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + silabs,clock-source: + enum: [ 0, 1, 2, 3 ] + else: + properties: + silabs,clock-source: + enum: [ 0, 1, 2 ] + + required: + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - silabs,si5351a + - silabs,si5351a-msop + - silabs,si5351b + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +required: + - reg + - "#address-cells" + - "#size-cells" + - "#clock-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* Connect XTAL input to 25MHz reference */ + clocks = <&ref25>; + clock-names = "xtal"; + + /* Use XTAL input as source of PLL0 and PLL1 */ + silabs,pll-source = <0 0>, <1 0>; + + /* Don't reset PLL1 on rate adjustment */ + silabs,pll-reset-mode = <1 1>; + + /* + * Overwrite CLK0 configuration with: + * - 8 mA output drive strength + * - PLL0 as clock source of multisynth 0 + * - Multisynth 0 as clock source of output divider + * - Multisynth 0 can change PLL0 + * - Set initial clock frequency of 74.25MHz + */ + clkout@0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + clock-frequency = <74250000>; + }; + + /* + * Overwrite CLK1 configuration with: + * - 4 mA output drive strength + * - PLL1 as clock source of multisynth 1 + * - Multisynth 1 as clock source of output divider + * - Multisynth 1 can change PLL1 + * - Reset PLL1 when enabling this clock output + */ + clkout@1 { + reg = <1>; + silabs,drive-strength = <4>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + silabs,pll-reset; + }; + + /* + * Overwrite CLK2 configuration with: + * - XTAL as clock source of output divider + */ + clkout@2 { + reg = <2>; + silabs,clock-source = <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si570.txt b/Documentation/devicetree/bindings/clock/silabs,si570.txt index c09f21e1d98f..5dda17df1ac5 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si570.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si570.txt @@ -7,9 +7,9 @@ found in the data sheets[2][3]. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Si570/571 Data Sheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf + https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf [3] Si598/599 Data Sheet - http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf + https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf Required properties: - compatible: Shall be one of "silabs,si570", "silabs,si571", @@ -28,6 +28,8 @@ Optional properties: - clock-frequency: Output frequency to generate. This defines the output frequency set during boot. It can be reprogrammed during runtime through the common clock framework. + - silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely + on hardware loading of RAM from NVM at power on. Example: si570: clock-generator@5d { diff --git a/Documentation/devicetree/bindings/clock/skyworks,si521xx.yaml b/Documentation/devicetree/bindings/clock/skyworks,si521xx.yaml new file mode 100644 index 000000000000..9e35e0e51ce8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/skyworks,si521xx.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/skyworks,si521xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Skyworks Si521xx I2C PCIe clock generators + +description: | + The Skyworks Si521xx are I2C PCIe clock generators providing + from 4 to 9 output clocks. + +maintainers: + - Marek Vasut <marex@denx.de> + +properties: + compatible: + enum: + - skyworks,si52144 + - skyworks,si52146 + - skyworks,si52147 + + reg: + const: 0x6b + + '#clock-cells': + const: 1 + + clocks: + items: + - description: XTal input clock + + skyworks,out-amplitude-microvolt: + enum: [ 300000, 400000, 500000, 600000, 700000, 800000, 900000, 1000000 ] + description: Output clock signal amplitude + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@6b { + compatible = "skyworks,si52144"; + reg = <0x6b>; + #clock-cells = <1>; + clocks = <&ref25m>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml new file mode 100644 index 000000000000..4e82582fb2f3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier clock controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + oneOf: + - description: System clock + enum: + - socionext,uniphier-ld4-clock + - socionext,uniphier-pro4-clock + - socionext,uniphier-sld8-clock + - socionext,uniphier-pro5-clock + - socionext,uniphier-pxs2-clock + - socionext,uniphier-ld6b-clock + - socionext,uniphier-ld11-clock + - socionext,uniphier-ld20-clock + - socionext,uniphier-pxs3-clock + - socionext,uniphier-nx1-clock + - description: Media I/O (MIO) clock, SD clock + enum: + - socionext,uniphier-ld4-mio-clock + - socionext,uniphier-pro4-mio-clock + - socionext,uniphier-sld8-mio-clock + - socionext,uniphier-pro5-sd-clock + - socionext,uniphier-pxs2-sd-clock + - socionext,uniphier-ld11-mio-clock + - socionext,uniphier-ld20-sd-clock + - socionext,uniphier-pxs3-sd-clock + - socionext,uniphier-nx1-sd-clock + - description: Peripheral clock + enum: + - socionext,uniphier-ld4-peri-clock + - socionext,uniphier-pro4-peri-clock + - socionext,uniphier-sld8-peri-clock + - socionext,uniphier-pro5-peri-clock + - socionext,uniphier-pxs2-peri-clock + - socionext,uniphier-ld11-peri-clock + - socionext,uniphier-ld20-peri-clock + - socionext,uniphier-pxs3-peri-clock + - socionext,uniphier-nx1-peri-clock + - description: SoC-glue clock + enum: + - socionext,uniphier-pro4-sg-clock + + "#clock-cells": + const: 1 + +additionalProperties: false + +required: + - compatible + - "#clock-cells" + +examples: + - | + clock-controller { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml b/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml new file mode 100644 index 000000000000..c1dc24673c0d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,cv1800-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800 Series Clock Controller + +maintainers: + - Inochi Amaoto <inochiama@outlook.com> + +properties: + compatible: + enum: + - sophgo,cv1800-clk + - sophgo,cv1810-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + description: + See <dt-bindings/clock/sophgo,cv1800.h> for valid indices. + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@3002000 { + compatible = "sophgo,cv1800-clk"; + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt index e9d179e882d9..aaaf02ca2a6a 100644 --- a/Documentation/devicetree/bindings/clock/sprd.txt +++ b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt @@ -1,4 +1,4 @@ -Spreadtrum Clock Binding +Spreadtrum SC9860 Clock Binding ------------------------ Required properties: diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml new file mode 100644 index 000000000000..a0658056c330 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SC9863A Clock Control Unit + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + "#clock-cells": + const: 1 + + compatible: + enum: + - sprd,sc9863a-ap-clk + - sprd,sc9863a-aon-clk + - sprd,sc9863a-apahb-gate + - sprd,sc9863a-pmu-gate + - sprd,sc9863a-aonapb-gate + - sprd,sc9863a-pll + - sprd,sc9863a-mpll + - sprd,sc9863a-rpll + - sprd,sc9863a-dpll + - sprd,sc9863a-mm-gate + - sprd,sc9863a-mm-clk + - sprd,sc9863a-apapb-gate + + clocks: + minItems: 1 + maxItems: 4 + description: | + The input parent clock(s) phandle for this clock, only list fixed + clocks which are declared in devicetree. + + clock-names: + minItems: 1 + items: + - const: ext-26m + - const: ext-32k + - const: ext-4m + - const: rco-100m + + reg: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + +if: + properties: + compatible: + enum: + - sprd,sc9863a-ap-clk + - sprd,sc9863a-aon-clk +then: + required: + - reg + +else: + description: | + Other SC9863a clock nodes should be the child of a syscon node in + which compatible string should be: + "sprd,sc9863a-glbregs", "syscon", "simple-mfd" + + The 'reg' property for the clock node is also required if there is a sub + range of registers for the clocks. + +additionalProperties: false + +examples: + - | + ap_clk: clock-controller@21500000 { + compatible = "sprd,sc9863a-ap-clk"; + reg = <0x21500000 0x1000>; + clocks = <&ext_26m>, <&ext_32k>; + clock-names = "ext-26m", "ext-32k"; + #clock-cells = <1>; + }; + + - | + syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; + reg = <0x20e00000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x20e00000 0x4000>; + + apahb_gate: apahb-gate@0 { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml new file mode 100644 index 000000000000..43d2b6c31357 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UMS512 Soc clock controller + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + compatible: + enum: + - sprd,ums512-apahb-gate + - sprd,ums512-ap-clk + - sprd,ums512-aonapb-clk + - sprd,ums512-pmu-gate + - sprd,ums512-g0-pll + - sprd,ums512-g2-pll + - sprd,ums512-g3-pll + - sprd,ums512-gc-pll + - sprd,ums512-aon-gate + - sprd,ums512-audcpapb-gate + - sprd,ums512-audcpahb-gate + - sprd,ums512-gpu-clk + - sprd,ums512-mm-clk + - sprd,ums512-mm-gate-clk + - sprd,ums512-apapb-gate + + "#clock-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 4 + description: | + The input parent clock(s) phandle for the clock, only list + fixed clocks which are declared in devicetree. + + clock-names: + minItems: 1 + items: + - const: ext-26m + - const: ext-32k + - const: ext-4m + - const: rco-100m + + reg: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - reg + +additionalProperties: false + +examples: + - | + ap_clk: clock-controller@20200000 { + compatible = "sprd,ums512-ap-clk"; + reg = <0x20200000 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt deleted file mode 100644 index fb9495ea582c..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt +++ /dev/null @@ -1,60 +0,0 @@ -STMicroelectronics STM32 Peripheral Reset Clock Controller -========================================================== - -The RCC IP is both a reset and a clock controller. - -RCC makes also power management (resume/supend and wakeup interrupt). - -Please also refer to reset.txt for common reset controller binding usage. - -Please also refer to clock-bindings.txt for common clock controller -binding usage. - - -Required properties: -- compatible: "st,stm32mp1-rcc", "syscon" -- reg: should be register base and length as documented in the datasheet -- #clock-cells: 1, device nodes should specify the clock in their - "clocks" property, containing a phandle to the clock device node, - an index specifying the clock to use. -- #reset-cells: Shall be 1 -- interrupts: Should contain a general interrupt line and a interrupt line - to the wake-up of processor (CSTOP). - -Example: - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>, - <GIC_SPI 145 IRQ_TYPE_NONE>; - }; - -Specifying clocks -================= - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/stm32mp1-clks.h header and can be used in device -tree sources. - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. - -For example on STM32MP1, for LTDC reset: - ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset - = 0x180 / 4 * 32 + 0 = 3072 - -The list of valid indices for STM32MP1 is available in: -include/dt-bindings/reset-controller/stm32mp1-resets.h - -This file implements defines like: -#define LTDC_R 3072 diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml new file mode 100644 index 000000000000..5194be0b410e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP1 Reset Clock Controller + +maintainers: + - Gabriel Fernandez <gabriel.fernandez@foss.st.com> + +description: | + The RCC IP is both a reset and a clock controller. + RCC makes also power management (resume/supend and wakeup interrupt). + Please also refer to reset.txt for common reset controller binding usage. + + This binding uses common clock bindings + Documentation/devicetree/bindings/clock/clock-bindings.txt + + Specifying clocks + ================= + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/stm32mp1-clks.h header and can be used in device + tree sources. + + Specifying softreset control of devices + ======================================= + + Device nodes should specify the reset channel required in their "resets" + property, containing a phandle to the reset device node and an index specifying + which channel to use. + The index is the bit number within the RCC registers bank, starting from RCC + base address. + It is calculated as: index = register_offset / 4 * 32 + bit_offset. + Where bit_offset is the bit offset within the register. + + For example on STM32MP1, for LTDC reset: + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset + = 0x180 / 4 * 32 + 0 = 3072 + + The list of valid indices for STM32MP1 is available in: + include/dt-bindings/reset-controller/stm32mp1-resets.h + include/dt-bindings/reset-controller/stm32mp13-resets.h + + This file implements defines like: + #define LTDC_R 3072 + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + items: + - enum: + - st,stm32mp1-rcc-secure + - st,stm32mp1-rcc + - st,stm32mp13-rcc + - const: syscon + clocks: true + clock-names: true + + reg: + maxItems: 1 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-rcc-secure + - st,stm32mp13-rcc +then: + properties: + clocks: + description: Specifies oscillators. + maxItems: 5 + + clock-names: + items: + - const: hse + - const: hsi + - const: csi + - const: lse + - const: lsi + required: + - clocks + - clock-names +else: + properties: + clocks: + description: + Specifies the external RX clock for ethernet MAC. + maxItems: 1 + + clock-names: + const: ETH_RX_CLK/ETH_REF_CLK + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml new file mode 100644 index 000000000000..7732e79a42b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 Reset Clock Controller + +maintainers: + - Gabriel Fernandez <gabriel.fernandez@foss.st.com> + +description: | + The RCC hardware block is both a reset and a clock controller. + RCC makes also power management (resume/supend). + + See also:: + include/dt-bindings/clock/st,stm32mp25-rcc.h + include/dt-bindings/reset/st,stm32mp25-rcc.h + +properties: + compatible: + enum: + - st,stm32mp25-rcc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + clocks: + items: + - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz) + - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz) + - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz) + - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz) + - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz) + + clock-names: + items: + - const: hse + - const: hsi + - const: msi + - const: lse + - const: lsi + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/st,stm32mp25-rcc.h> + + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "hse", "hsi", "msi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..c918075405ba 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,11 +64,21 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- clocks : must be set to the parent's phandle. it's could be output clocks of +- clocks : must be set to the parent's phandle. it could be output clocks of a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks) - clock-output-names : List of strings used to name the clock outputs. diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml new file mode 100644 index 000000000000..8f49a1ae03f1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Audio Clock Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7100-audclk + + reg: + maxItems: 1 + + clocks: + items: + - description: Audio source clock + - description: External 12.288MHz clock + - description: Domain 7 AHB bus clock + + clock-names: + items: + - const: audio_src + - const: audio_12288 + - const: dom7ahb_bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive-jh7100.h> + + clock-controller@10480000 { + compatible = "starfive,jh7100-audclk"; + reg = <0x10480000 0x10000>; + clocks = <&clkgen JH7100_CLK_AUDIO_SRC>, + <&clkgen JH7100_CLK_AUDIO_12288>, + <&clkgen JH7100_CLK_DOM7AHB_BUS>; + clock-names = "audio_src", "audio_12288", "dom7ahb_bus"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml new file mode 100644 index 000000000000..12f17b60ecbe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Clock Generator + +maintainers: + - Geert Uytterhoeven <geert@linux-m68k.org> + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7100-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main clock source (25 MHz) + - description: Application-specific clock source (12-27 MHz) + - description: RMII reference clock (50 MHz) + - description: RGMII RX clock (125 MHz) + + clock-names: + items: + - const: osc_sys + - const: osc_aud + - const: gmac_rmii_ref + - const: gmac_gr_mii_rxclk + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive-jh7100.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x11800000 0x10000>; + clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; + clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..923680a44aef --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB or GMAC0 RGMII RX + - description: APB Bus or STG AXI/AHB + - description: GMAC0 GTX or APB Bus + - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference + - description: GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + - description: RTC Oscillator (32.768 kHz) + + clock-names: + oneOf: + - minItems: 5 + items: + - const: osc + - enum: + - gmac0_rmii_refin + - gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + - minItems: 6 + items: + - const: osc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml new file mode 100644 index 000000000000..3b8b85be5cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-ispcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: ISP Top core + - description: ISP Top Axi + - description: NOC ISP Bus + - description: external DVP + + clock-names: + items: + - const: isp_top_core + - const: isp_top_axi + - const: noc_bus_isp_axi + - const: dvp_clk + + resets: + items: + - description: ISP Top core + - description: ISP Top Axi + - description: NOC ISP Bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + + power-domains: + maxItems: 1 + description: + ISP domain power + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - '#clock-cells' + - '#reset-cells' + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/power/starfive,jh7110-pmu.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x19810000 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..be8300ce86d0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + These PLLs are high speed, low jitter frequency synthesizers in the JH7110. + Each PLL works in integer mode or fraction mode, with configuration + registers in the sys syscon. So the PLLs node should be a child of + SYS-SYSCON node. + The formula for calculating frequency is + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml new file mode 100644 index 000000000000..b64ccd84200a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System-Top-Group Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-stgcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: HIFI4 core + - description: STG AXI/AHB + - description: USB (125 MHz) + - description: CPU Bus + - description: HIFI4 Axi + - description: NOC STG Bus + - description: APB Bus + + clock-names: + items: + - const: osc + - const: hifi4_core + - const: stg_axiahb + - const: usb_125m + - const: cpu_bus + - const: hifi4_axi + - const: nocstg_bus + - const: apb_bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x10230000 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml new file mode 100644 index 000000000000..5ba0a885aa80 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System Clock and Reset Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + const: starfive,jh7110-syscrg + + reg: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC1 RMII reference or GMAC1 RGMII RX + - description: External I2S TX bit clock + - description: External I2S TX left/right channel clock + - description: External I2S RX bit clock + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC1 RMII reference + - description: GMAC1 RGMII RX + - description: External I2S TX bit clock + - description: External I2S TX left/right channel clock + - description: External I2S RX bit clock + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 + + clock-names: + oneOf: + - items: + - const: osc + - enum: + - gmac1_rmii_refin + - gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out + + - items: + - const: osc + - const: gmac1_rmii_refin + - const: gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x13020000 0x10000>; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>, + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml new file mode 100644 index 000000000000..af77bd8c86b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Video-Output Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-voutcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Vout Top core + - description: Vout Top Ahb + - description: Vout Top Axi + - description: Vout Top HDMI MCLK + - description: I2STX0 BCLK + - description: external HDMI pixel + + clock-names: + items: + - const: vout_src + - const: vout_top_ahb + - const: vout_top_axi + - const: vout_top_hdmitx0_mclk + - const: i2stx0_bclk + - const: hdmitx0_pixelclk + + resets: + maxItems: 1 + description: Vout Top core + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + + power-domains: + maxItems: 1 + description: + Vout domain power + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - '#clock-cells' + - '#reset-cells' + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/power/starfive,jh7110-pmu.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + + voutcrg: clock-controller@295C0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x295C0000 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt deleted file mode 100644 index 7cafcb98ead7..000000000000 --- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt +++ /dev/null @@ -1,80 +0,0 @@ -Clock bindings for ST-Ericsson U300 System Controller Clocks - -Bindings for the gated system controller clocks: - -Required properties: -- compatible: must be "stericsson,u300-syscon-clk" -- #clock-cells: must be <0> -- clock-type: specifies the type of clock: - 0 = slow clock - 1 = fast clock - 2 = rest/remaining clock -- clock-id: specifies the clock in the type range - -Optional properties: -- clocks: parent clock(s) - -The available clocks per type are as follows: - -Type: ID: Clock: -------------------- -0 0 Slow peripheral bridge clock -0 1 UART0 clock -0 4 GPIO clock -0 6 RTC clock -0 7 Application timer clock -0 8 Access timer clock - -1 0 Fast peripheral bridge clock -1 1 I2C bus 0 clock -1 2 I2C bus 1 clock -1 5 MMC interface peripheral (silicon) clock -1 6 SPI clock - -2 3 CPU clock -2 4 DMA controller clock -2 5 External Memory Interface (EMIF) clock -2 6 NAND flask interface clock -2 8 XGAM graphics engine clock -2 9 Shared External Memory Interface (SEMI) clock -2 10 AHB Subsystem Bridge clock -2 12 Interrupt controller clock - -Example: - -gpio_clk: gpio_clk@13M { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-clk"; - clock-type = <0>; /* Slow */ - clock-id = <4>; - clocks = <&slow_clk>; -}; - -gpio: gpio@c0016000 { - compatible = "stericsson,gpio-coh901"; - (...) - clocks = <&gpio_clk>; -}; - - -Bindings for the MMC/SD card clock: - -Required properties: -- compatible: must be "stericsson,u300-syscon-mclk" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -mmc_mclk: mmc_mclk { - #clock-cells = <0>; - compatible = "stericsson,u300-syscon-mclk"; - clocks = <&mmc_pclk>; -}; - -mmcsd: mmcsd@c0001000 { - compatible = "arm,pl18x", "arm,primecell"; - clocks = <&mmc_pclk>, <&mmc_mclk>; - clock-names = "apb_pclk", "mclk"; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml new file mode 100644 index 000000000000..2150307219a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST-Ericsson DB8500 (U8500) clocks + +maintainers: + - Ulf Hansson <ulf.hansson@linaro.org> + - Linus Walleij <linus.walleij@linaro.org> + +description: While named "U8500 clocks" these clocks are inside the + DB8500 digital baseband system-on-chip and its siblings such as + DB8520. These bindings consider the clocks present in the SoC + itself, not off-chip clocks. There are four different on-chip + clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and + control management unit) clocks and PRCC (peripheral reset and + clock controller) clocks. For some reason PRCC 4 does not exist so + the itemization can be a bit unintuitive. + +properties: + compatible: + enum: + - stericsson,u8500-clks + - stericsson,u8540-clks + - stericsson,u9540-clks + + reg: + items: + - description: PRCC 1 register area + - description: PRCC 2 register area + - description: PRCC 3 register area + - description: PRCC 5 register area + - description: PRCC 6 register area + + prcmu-clock: + description: A subnode with one clock cell for PRCMU (power, reset, control + management unit) clocks. The cell indicates which PRCMU clock in the + prcmu-clock node the consumer wants to use. + type: object + + properties: + '#clock-cells': + const: 1 + + additionalProperties: false + + prcc-periph-clock: + description: A subnode with two clock cells for PRCC (peripheral + reset and clock controller) peripheral clocks. The first cell indicates + which PRCC block the consumer wants to use, possible values are 1, 2, 3, + 5, 6. The second cell indicates which clock inside the PRCC block it + wants, possible values are 0 thru 31. + type: object + + properties: + '#clock-cells': + const: 2 + + additionalProperties: false + + prcc-kernel-clock: + description: A subnode with two clock cells for PRCC (peripheral reset + and clock controller) kernel clocks. The first cell indicates which PRCC + block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The + second cell indicates which clock inside the PRCC block it wants, possible + values are 0 thru 31. + type: object + + properties: + '#clock-cells': + const: 2 + + additionalProperties: false + + prcc-reset-controller: + description: A subnode with two reset cells for the reset portions of the + PRCC (peripheral reset and clock controller). The first cell indicates + which PRCC block the consumer wants to use, possible values are 1, 2, 3 + 5 and 6. The second cell indicates which reset line inside the PRCC block + it wants to control, possible values are 0 thru 31. + type: object + + properties: + '#reset-cells': + const: 2 + + additionalProperties: false + + rtc32k-clock: + description: A subnode with zero clock cells for the 32kHz RTC clock. + type: object + + properties: + '#clock-cells': + const: 0 + + additionalProperties: false + + smp-twd-clock: + description: A subnode for the ARM SMP Timer Watchdog cluster with zero + clock cells. + type: object + + properties: + '#clock-cells': + const: 0 + + additionalProperties: false + + clkout-clock: + description: A subnode with three clock cells for externally routed clocks, + output clocks. These are two PRCMU-internal clocks that can be divided and + muxed out on the pads of the DB8500 SoC. + type: object + + properties: + '#clock-cells': + description: + The first cell indicates which output clock we are using, + possible values are 0 (CLKOUT1) and 1 (CLKOUT2). + The second cell indicates which clock we want to use as source, + possible values are 0 thru 7, see the defines for the different + source clocks. + The third cell is a divider, legal values are 1 thru 63. + const: 3 + + additionalProperties: false + +required: + - compatible + - reg + - prcmu-clock + - prcc-periph-clock + - prcc-kernel-clock + - rtc32k-clock + - smp-twd-clock + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ste-db8500-clkout.h> + clocks@8012 { + compatible = "stericsson,u8500-clks"; + reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, + <0x8000f000 0x1000>, <0xa03ff000 0x1000>, + <0xa03cf000 0x1000>; + + prcmu_clk: prcmu-clock { + #clock-cells = <1>; + }; + + prcc_pclk: prcc-periph-clock { + #clock-cells = <2>; + }; + + prcc_kclk: prcc-kernel-clock { + #clock-cells = <2>; + }; + + prcc_reset: prcc-reset-controller { + #reset-cells = <2>; + }; + + rtc_clk: rtc32k-clock { + #clock-cells = <0>; + }; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + + clkout_clk: clkout-clock { + #clock-cells = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt deleted file mode 100644 index 41a52c2acffd..000000000000 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ /dev/null @@ -1,34 +0,0 @@ -Allwinner Display Engine 2.0/3.0 Clock Control Binding ------------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun8i-a83t-de2-clk" - - "allwinner,sun8i-h3-de2-clk" - - "allwinner,sun8i-v3s-de2-clk" - - "allwinner,sun50i-a64-de2-clk" - - "allwinner,sun50i-h5-de2-clk" - - "allwinner,sun50i-h6-de3-clk" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock (on A83T it's the DE PLL) - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de2_clocks: clock@1000000 { - compatible = "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt deleted file mode 100644 index fb18f327b97a..000000000000 --- a/Documentation/devicetree/bindings/clock/sun9i-de.txt +++ /dev/null @@ -1,28 +0,0 @@ -Allwinner A80 Display Engine Clock Control Binding --------------------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-de-clks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the display engine subsystem. - Three are needed: - - "mod": the display engine module clock - - "dram": the DRAM bus clock for the system - - "bus": the bus clock for the whole display engine subsystem -- clock-names: Must contain the clock names described just above -- resets: phandle to the reset control for the display engine subsystem. -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; - clock-names = "mod", "dram", "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt deleted file mode 100644 index 3564bd4f2a20..000000000000 --- a/Documentation/devicetree/bindings/clock/sun9i-usb.txt +++ /dev/null @@ -1,24 +0,0 @@ -Allwinner A80 USB Clock Control Binding ---------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun9i-a80-usb-clocks" - -- reg: Must contain the registers base address and length -- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: - - "bus": the bus clock for the whole USB subsystem - - "hosc": the high frequency oscillator (usually at 24MHz) -- clock-names: Must contain the clock names described just above -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -Example: -usb_clocks: clock@a08000 { - compatible = "allwinner,sun9i-a80-usb-clks"; - reg = <0x00a08000 0x8>; - clocks = <&ccu CLK_BUS_USB>, <&osc24M>; - clock-names = "bus", "hosc"; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file mode 100644 index 000000000000..bcc14088220a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller + +maintainers: + - Qin Jian <qinjian@cqplus1.com> + +properties: + compatible: + const: sunplus,sp7021-clkc + + reg: + maxItems: 3 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + extclk: osc0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "extclk"; + }; + + clkc: clock-controller@9c000004 { + compatible = "sunplus,sp7021-clkc"; + reg = <0x9c000004 0x28>, + <0x9c000200 0x44>, + <0x9c000268 0x08>; + clocks = <&extclk>; + #clock-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt deleted file mode 100644 index 1a042e20b115..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ /dev/null @@ -1,225 +0,0 @@ -Device Tree Clock bindings for arch-sunxi - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator - "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 - "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 - "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 - "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10 - "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 - "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock - "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock - "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 - "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 - "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock - "allwinner,sun4i-a10-axi-clk" - for the AXI clock - "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 - "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs - "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates - "allwinner,sun4i-a10-ahb-clk" - for the AHB clock - "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 - "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 - "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 - "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 - "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s - "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 - "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 - "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 - "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 - "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 - "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 - "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 - "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 - "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 - "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 - "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock - "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 - "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 - "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 - "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T - "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 - "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 - "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s - "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 - "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 - "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 - "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3 - "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 - "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock - "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 - "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 - "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 - "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s - "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 - "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 - "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 - "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 - "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 - "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 - "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T - "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 - "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 - "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10 - "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 - "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13 - "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 - "allwinner,sun4i-a10-mmc-clk" - for the MMC clock - "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 - "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 - "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks - "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 - "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 - "allwinner,sun7i-a20-out-clk" - for the external output clocks - "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 - "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10 - "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10 - "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 - "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 - "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 - "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 - "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 - "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 - "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 - "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock - "allwinner,sun6i-a31-display-clk" - for the display clocks - -Required properties for all clocks: -- reg : shall be the control register address for the clock. -- clocks : shall be the input parent clock(s) phandle for the clock. For - multiplexed clocks, the list order must match the hardware - programming order. -- #clock-cells : from common clock binding; shall be set to 0 except for - the following compatibles where it shall be set to 1: - "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", - "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", - "allwinner,*-usb-clk", "allwinner,*-mmc-clk", - "allwinner,*-mmc-config-clk" -- clock-output-names : shall be the corresponding names of the outputs. - If the clock module only has one output, the name shall be the - module name. - -And "allwinner,*-usb-clk" clocks also require: -- reset-cells : shall be set to 1 - -The "allwinner,sun4i-a10-ve-clk" clock also requires: -- reset-cells : shall be set to 0 - -The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: -- #reset-cells : shall be set to 1 -- resets : shall be the reset control phandle for the mmc block. - -For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate -dummy clocks at 25 MHz and 125 MHz, respectively. See example. - -Clock consumers should specify the desired clocks they use with a -"clocks" phandle cell. Consumers that are using a gated clock should -provide an additional ID in their clock property. This ID is the -offset of the bit controlling this particular gate in the register. -For the other clocks with "#clock-cells" = 1, the additional ID shall -refer to the index of the output. - -For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output -is the normal PLL6 output, or "pll6". The second output is rate doubled -PLL6, or "pll6x2". - -The "allwinner,*-mmc-clk" clocks have three different outputs: the -main clock, with the ID 0, and the output and sample clocks, with the -IDs 1 and 2, respectively. - -The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output -per mmc controller. The number of outputs is determined by the size of -the address block, which is related to the overall mmc block. - -For example: - -osc24M: clk@1c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-osc-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M_fixed>; - clock-output-names = "osc24M"; -}; - -pll1: clk@1c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; -}; - -pll5: clk@1c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; - reg = <0x01c20020 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll5_ddr", "pll5_other"; -}; - -pll6: clk@1c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; -}; - -cpu: cpu@1c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>; - clock-output-names = "cpu"; -}; - -mmc0_clk: clk@1c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; - clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; -}; - -mii_phy_tx_clk: clk@2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; -}; - -gmac_int_tx_clk: clk@3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; -}; - -gmac_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - /* - * The first clock must be fixed at 25MHz; - * the second clock must be fixed at 125MHz - */ - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac"; -}; - -mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ahb0_gates 8>; - clock-names = "ahb"; - resets = <&ahb0_resets 8>; - reset-names = "ahb"; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; -}; diff --git a/Documentation/devicetree/bindings/clock/tango4-clock.txt b/Documentation/devicetree/bindings/clock/tango4-clock.txt deleted file mode 100644 index 19c580a7bda2..000000000000 --- a/Documentation/devicetree/bindings/clock/tango4-clock.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Sigma Designs Tango4 Clock Generator - -The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used -for RAM and various peripheral devices). The clock binding described here -is applicable to all Tango4 SoCs. - -Required Properties: - -- compatible: should be "sigma,tango4-clkgen". -- reg: physical base address of the device and length of memory mapped region. -- clocks: phandle of the input clock (crystal oscillator). -- clock-output-names: should be "cpuclk" and "sysclk". -- #clock-cells: should be set to 1. - -Example: - - clkgen: clkgen@10000 { - compatible = "sigma,tango4-clkgen"; - reg = <0x10000 0x40>; - clocks = <&xtal>; - clock-output-names = "cpuclk", "sysclk"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml new file mode 100644 index 000000000000..dc808e2f8327 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD (Full Self-Driving) SoC clock controller + +maintainers: + - Alim Akhtar <alim.akhtar@samsung.com> + - linux-fsd@tesla.com + +description: | + FSD clock controller consist of several clock management unit + (CMU), which generates clocks for various inteernal SoC blocks. + The root clock comes from external OSC clock (24 MHz). + + All available clocks are defined as preprocessor macros in + 'dt-bindings/clock/fsd-clk.h' header. + +properties: + compatible: + enum: + - tesla,fsd-clock-cmu + - tesla,fsd-clock-imem + - tesla,fsd-clock-peric + - tesla,fsd-clock-fsys0 + - tesla,fsd-clock-fsys1 + - tesla,fsd-clock-mfc + - tesla,fsd-clock-cam_csi + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-cmu + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-imem + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: IMEM TCU clock (from CMU_CMU) + - description: IMEM bus clock (from CMU_CMU) + - description: IMEM DMA clock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_imem_tcuclk + - const: dout_cmu_imem_aclk + - const: dout_cmu_imem_dmaclk + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-peric + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: Shared0 PLL div4 clock (from CMU_CMU) + - description: PERIC shared1 div36 clock (from CMU_CMU) + - description: PERIC shared0 div3 TBU clock (from CMU_CMU) + - description: PERIC shared0 div20 clock (from CMU_CMU) + - description: PERIC shared1 div4 DMAclock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_pll_shared0_div4 + - const: dout_cmu_peric_shared1div36 + - const: dout_cmu_peric_shared0div3_tbuclk + - const: dout_cmu_peric_shared0div20 + - const: dout_cmu_peric_shared1div4_dmaclk + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-fsys0 + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: Shared0 PLL div6 clock (from CMU_CMU) + - description: FSYS0 shared1 div4 clock (from CMU_CMU) + - description: FSYS0 shared0 div4 clock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_pll_shared0_div6 + - const: dout_cmu_fsys0_shared1div4 + - const: dout_cmu_fsys0_shared0div4 + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-fsys1 + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: FSYS1 shared0 div8 clock (from CMU_CMU) + - description: FSYS1 shared0 div4 clock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_fsys1_shared0div8 + - const: dout_cmu_fsys1_shared0div4 + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-mfc + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-cam_csi + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + clock-names: + items: + - const: fin_pll + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS1 + - | + #include <dt-bindings/clock/fsd-clk.h> + + clock_fsys1: clock-controller@16810000 { + compatible = "tesla,fsd-clock-fsys1"; + reg = <0x16810000 0x3000>; + #clock-cells = <1>; + + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml b/Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml new file mode 100644 index 000000000000..b2e40bd39a3a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am62-audio-refclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Audio Reference Clock + +maintainers: + - Jai Luthra <j-luthra@ti.com> + +properties: + compatible: + items: + - const: ti,am62-audio-refclk + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + audio_refclk0: clock@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file mode 100644 index 000000000000..64b8bce5962c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI EHRPWM Time Base Clock + +maintainers: + - Vignesh Raghavendra <vigneshr@ti.com> + +properties: + compatible: + items: + - enum: + - ti,am654-ehrpwm-tbclk + - ti,am64-epwm-tbclk + - ti,am62-epwm-tbclk + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + ehrpwm_tbclk: clock@4140 { + compatible = "ti,am654-ehrpwm-tbclk"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,cdce706.txt b/Documentation/devicetree/bindings/clock/ti,cdce706.txt index 959d96632f5d..21c3ff764788 100644 --- a/Documentation/devicetree/bindings/clock/ti,cdce706.txt +++ b/Documentation/devicetree/bindings/clock/ti,cdce706.txt @@ -1,7 +1,7 @@ Bindings for Texas Instruments CDCE706 programmable 3-PLL clock synthesizer/multiplier/divider. -Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf +Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf I2C device node required properties: - compatible: shall be "ti,cdce706". diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt deleted file mode 100644 index 26544c85202a..000000000000 --- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt +++ /dev/null @@ -1,53 +0,0 @@ -Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers. - -Reference -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] http://www.ti.com/product/cdce913 -[3] http://www.ti.com/product/cdce925 -[4] http://www.ti.com/product/cdce937 -[5] http://www.ti.com/product/cdce949 - -The driver provides clock sources for each output Y1 through Y5. - -Required properties: - - compatible: Shall be one of the following: - - "ti,cdce913": 1-PLL, 3 Outputs - - "ti,cdce925": 2-PLL, 5 Outputs - - "ti,cdce937": 3-PLL, 7 Outputs - - "ti,cdce949": 4-PLL, 9 Outputs - - reg: I2C device address. - - clocks: Points to a fixed parent clock that provides the input frequency. - - #clock-cells: From common clock bindings: Shall be 1. - -Optional properties: - - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a - board, or to compensate for external influences. -- vdd-supply: A regulator node for Vdd -- vddout-supply: A regulator node for Vddout - -For all PLL1, PLL2, ... an optional child node can be used to specify spread -spectrum clocking parameters for a board. - - spread-spectrum: SSC mode as defined in the data sheet. - - spread-spectrum-center: Use "centered" mode instead of "max" mode. When - present, the clock runs at the requested frequency on average. Otherwise - the requested frequency is the maximum value of the SCC range. - - -Example: - - clockgen: cdce925pw@64 { - compatible = "cdce925"; - reg = <0x64>; - clocks = <&xtal_27Mhz>; - #clock-cells = <1>; - xtal-load-pf = <5>; - vdd-supply = <&1v8-reg>; - vddout-supply = <&3v3-reg>; - /* PLL options to get SSC 1% centered */ - PLL2 { - spread-spectrum = <4>; - spread-spectrum-center; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.yaml b/Documentation/devicetree/bindings/clock/ti,cdce925.yaml new file mode 100644 index 000000000000..95c1c6f8b755 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,cdce925.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI CDCE913/925/937/949 programmable I2C clock synthesizers + +maintainers: + - Alexander Stein <alexander.stein@ew.tq-group.com> + +description: | + Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction + + - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913 + - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925 + - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937 + - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949 + +properties: + compatible: + enum: + - ti,cdce913 + - ti,cdce925 + - ti,cdce937 + - ti,cdce949 + + reg: + maxItems: 1 + + clocks: + items: + - description: fixed parent clock + + "#clock-cells": + const: 1 + + vdd-supply: + description: Regulator that provides 1.8V Vdd power supply + + vddout-supply: + description: | + Regulator that provides Vddout power supply. + non-L variant: 2.5V or 3.3V for + L variant: 1.8V for + + xtal-load-pf: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Crystal load-capacitor value to fine-tune performance on a + board, or to compensate for external influences. + +patternProperties: + "^PLL[1-4]$": + type: object + description: | + optional child node can be used to specify spread + spectrum clocking parameters for a board + + additionalProperties: false + + properties: + spread-spectrum: + $ref: /schemas/types.yaml#/definitions/uint32 + description: SSC mode as defined in the data sheet + + spread-spectrum-center: + type: boolean + description: | + Use "centered" mode instead of "max" mode. When + present, the clock runs at the requested frequency on average. + Otherwise the requested frequency is the maximum value of the + SCC range. + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cdce925: clock-controller@64 { + compatible = "ti,cdce925"; + reg = <0x64>; + clocks = <&xtal_27Mhz>; + #clock-cells = <1>; + xtal-load-pf = <5>; + vdd-supply = <®_1v8>; + vddout-supply = <®_3v3>; + /* PLL options to get SSC 1% centered */ + PLL2 { + spread-spectrum = <4>; + spread-spectrum-center; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml b/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml new file mode 100644 index 000000000000..13d7b3d03d84 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml @@ -0,0 +1,209 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments LMK04832 Clock Controller + +maintainers: + - Liam Beguin <liambeguin@gmail.com> + +description: | + Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B + support. The LMK04832 is pin compatible with the LMK0482x family. + + Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf + +properties: + compatible: + enum: + - ti,lmk04832 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#clock-cells': + const: 1 + + spi-max-frequency: + maximum: 5000000 + + clocks: + items: + - description: PLL2 reference clock. + + clock-names: + items: + - const: oscin + + reset-gpios: + maxItems: 1 + + ti,spi-4wire-rdbk: + description: | + Select SPI 4wire readback pin configuration. + Available readback pins are, + CLKin_SEL0 0 + CLKin_SEL1 1 + RESET 2 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + + ti,vco-hz: + description: Optional to set VCO frequency of the PLL in Hertz. + + ti,sysref-ddly: + description: SYSREF digital delay value. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8 + maximum: 8191 + default: 8 + + ti,sysref-mux: + description: | + SYSREF Mux configuration. + Available options are, + Normal SYNC 0 + Re-clocked 1 + SYSREF Pulser 2 + SYSREF Continuous 3 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 3 + + ti,sync-mode: + description: SYNC pin configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + + ti,sysref-pulse-count: + description: + Number of SYSREF pulses to send when SYSREF is not in continuous mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + default: 4 + +patternProperties: + "@[0-9a-d]+$": + type: object + description: + Child nodes used to configure output clocks. + + properties: + reg: + description: + clock output identifier. + minimum: 0 + maximum: 13 + + ti,clkout-fmt: + description: + Clock output format. + Available options are, + Powerdown 0x00 + LVDS 0x01 + HSDS 6 mA 0x02 + HSDS 8 mA 0x03 + LVPECL 1600 mV 0x04 + LVPECL 2000 mV 0x05 + LCPECL 0x06 + CML 16 mA 0x07 + CML 24 mA 0x08 + CML 32 mA 0x09 + CMOS (Off/Inverted) 0x0a + CMOS (Normal/Off) 0x0b + CMOS (Inverted/Inverted) 0x0c + CMOS (Inverted/Normal) 0x0d + CMOS (Normal/Inverted) 0x0e + CMOS (Normal/Normal) 0x0f + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + ti,clkout-sysref: + description: + Select SYSREF clock path for output clock. + type: boolean + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clocks { + lmk04832_oscin: oscin { + compatible = "fixed-clock"; + + #clock-cells = <0>; + clock-frequency = <122880000>; + clock-output-names = "lmk04832-oscin"; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + lmk04832: clock-controller@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + compatible = "ti,lmk04832"; + spi-max-frequency = <781250>; + + reset-gpios = <&gpio_lmk 0 0 0>; + + #clock-cells = <1>; + clocks = <&lmk04832_oscin>; + clock-names = "oscin"; + + ti,spi-4wire-rdbk = <0>; + ti,vco-hz = <2457600000>; + + assigned-clocks = + <&lmk04832 0>, <&lmk04832 1>, + <&lmk04832 2>, <&lmk04832 3>, + <&lmk04832 4>, + <&lmk04832 6>, <&lmk04832 7>, + <&lmk04832 10>, <&lmk04832 11>; + assigned-clock-rates = + <122880000>, <384000>, + <122880000>, <384000>, + <122880000>, + <153600000>, <384000>, + <614400000>, <384000>; + + clkout0@0 { + reg = <0>; + ti,clkout-fmt = <0x01>; // LVDS + }; + + clkout1@1 { + reg = <1>; + ti,clkout-fmt = <0x01>; // LVDS + ti,clkout-sysref; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt deleted file mode 100644 index 4e59dc6b1778..000000000000 --- a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt +++ /dev/null @@ -1,36 +0,0 @@ -Texas Instruments TI-SCI Clocks -=============================== - -All clocks on Texas Instruments' SoCs that contain a System Controller, -are only controlled by this entity. Communication between a host processor -running an OS and the System Controller happens through a protocol known -as TI-SCI[1]. This clock implementation plugs into the common clock -framework and makes use of the TI-SCI protocol on clock API requests. - -[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -Required properties: -------------------- -- compatible: Must be "ti,k2g-sci-clk" -- #clock-cells: Shall be 2. - In clock consumers, this cell represents the device ID and clock ID - exposed by the PM firmware. The list of valid values for the device IDs - and clocks IDs for 66AK2G SoC are documented at - http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data - -Examples: --------- - -pmmc: pmmc { - compatible = "ti,k2g-sci"; - - k2g_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; -}; - -uart0: serial@2530c00 { - compatible = "ns16550a"; - clocks = <&k2g_clks 0x2c 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml new file mode 100644 index 000000000000..0a9d6a4c4b66 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-SCI clock controller + +maintainers: + - Nishanth Menon <nm@ti.com> + +description: | + Some TI SoCs contain a system controller (like the Power Management Micro + Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling + the state of the various hardware modules present on the SoC. Communication + between the host processor running an OS and the system controller happens + through a protocol called TI System Control Interface (TI-SCI protocol). + + This clock controller node uses the TI SCI protocol to perform various clock + management of various hardware modules (devices) present on the SoC. This + node must be a child node of the associated TI-SCI system controller node. + +properties: + $nodename: + pattern: "^clock-controller$" + + compatible: + const: ti,k2g-sci-clk + + "#clock-cells": + const: 2 + description: + The two cells represent values that the TI-SCI controller defines. + + The first cell should contain the device ID. + + The second cell should contain the clock ID. + + Please see http://processors.wiki.ti.com/index.php/TISCI for + protocol documentation for the values to be used for different devices. + +additionalProperties: false + +examples: + - | + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt index 48ee6991f2cc..d20db7974a38 100644 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt @@ -16,18 +16,25 @@ For more information, please see the Linux clock framework binding at Documentation/devicetree/bindings/clock/clock-bindings.txt. Required properties : -- compatible : shall be "ti,clkctrl" +- compatible : shall be "ti,clkctrl" or a clock domain specific name: + "ti,clkctrl-l4-cfg" + "ti,clkctrl-l4-per" + "ti,clkctrl-l4-secure" + "ti,clkctrl-l4-wkup" +- clock-output-names : from common clock binding - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index +- reg : clock registers Example: Clock controller node on omap 4430: &cm2 { l4per: cm@1400 { cm_l4per@0 { - cm_l4per_clkctrl: clk@20 { + cm_l4per_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt index cb76b3f2b341..9c6199249ce5 100644 --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt @@ -17,6 +17,9 @@ Required properties: - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of clocks within this domain +Optional properties: +- clock-output-names : from common clock binding. + Examples: dss_clkdm: dss_clkdm { compatible = "ti,clockdomain"; diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt index 5f43c4706b09..33ac7c9ad053 100644 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -27,6 +27,9 @@ Required properties: - clocks : link phandles of component clocks - #clock-cells : from common clock binding; shall be set to 0. +Optional properties: +- clock-output-names : from common clock binding. + Examples: usb_l4_gate_ick: usb_l4_gate_ick { diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt index 36998e184821..c9894538315b 100644 --- a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt +++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt @@ -15,7 +15,7 @@ Required properties: - for "ti,da850-pll1", shall be "clksrc" Optional properties: -- ti,clkmode-square-wave: Indicates that the the board is supplying a square +- ti,clkmode-square-wave: Indicates that the board is supplying a square wave input on the OSCIN pin instead of using a crystal oscillator. This property is only valid when compatible = "ti,da850-pll0". diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index df57009ff8e7..37a7cb6ad07d 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -42,6 +42,11 @@ Required properties: "idlest" - contains the idle status register base address "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) + "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains + the frequency spreading register base address (optional) + "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains + the modulation frequency register base address + (optional) ti,am3-* dpll types do not have autoidle register ti,omap2-* dpll type does not support idlest / autoidle registers @@ -51,6 +56,14 @@ Optional properties: - ti,low-power-stop : DPLL supports low power stop mode, gating output - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - ti,lock : DPLL locks in programmed rate + - ti,min-div : the minimum divisor to start from to round the DPLL + target rate + - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency + spreading in permille (10th of a percent) + - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread + spectrum modulation frequency + - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean + to enable the downspread feature Examples: dpll_core_ck: dpll_core_ck@44e00490 { @@ -83,3 +96,10 @@ Examples: clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt index 10f7047755f3..68504079f99f 100644 --- a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt +++ b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt @@ -6,7 +6,7 @@ functional clock but can be configured to provide different clocks. ATL can maintain a clock averages to some desired frequency based on the bws/aws signals - can compensate the drift between the two ws signal. -In order to provide the support for ATL and it's output clocks (which can be used +In order to provide the support for ATL and its output clocks (which can be used internally within the SoC or external components) two sets of bindings is needed: Clock tree binding: @@ -43,7 +43,7 @@ Configuration of ATL instances: - aws : Audio word select signal selection }; -For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include +For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include file. Examples: @@ -83,7 +83,7 @@ atl: atl@4843c000 { clock-names = "fck"; }; -#include <dt-bindings/clk/ti-dra7-atl.h> +#include <dt-bindings/clock/ti-dra7-atl.h> &atl { diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt index 662b36d53bf0..518e3c142276 100644 --- a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt +++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt @@ -16,6 +16,7 @@ Required properties: - clocks: parent clock. Optional properties: +- clock-output-names : from common clock binding. - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, see [2] - reg: offset for the autoidle register of this clock, see [2] diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt index 56d603c1f716..4982615c01b9 100644 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt @@ -10,7 +10,7 @@ will be controlled instead and the corresponding hw-ops for that is used. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt +[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt Required properties: @@ -36,6 +36,7 @@ Required properties: ti,clkdm-gate-clock type Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for programming the clock gate, invalid for ti,clkdm-gate-clock type - ti,set-bit-to-disable : inverts default gate programming. Setting the bit diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt index 3f4704040140..d3eb5ca92a7f 100644 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt @@ -9,7 +9,7 @@ companion clock finding (match corresponding functional gate clock) and hardware autoidle enable / disable. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt +[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml Required properties: - compatible : shall be one of: @@ -28,6 +28,7 @@ Required properties: - reg : base address for the control register Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) Examples: diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt index eec8994b9be8..b33f641f1043 100644 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -8,7 +8,7 @@ parents, one of which can be selected as output. This clock does not gate or adjust the parent rate via a divider or multiplier. By default the "clocks" property lists the parents in the same order -as they are programmed into the regster. E.g: +as they are programmed into the register. E.g: clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; @@ -42,6 +42,7 @@ Required properties: - reg : register offset for register controlling adjustable mux Optional properties: +- clock-output-names : from common clock binding. - ti,bit-shift : number of bits to shift the bit-mask, defaults to 0 if not present - ti,index-starts-at-one : valid input select programming starts at 1, not diff --git a/Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml b/Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml new file mode 100644 index 000000000000..d525f96cf244 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI clksel clock + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: | + The TI CLKSEL clocks consist of consist of input clock mux bits, and in some + cases also has divider, multiplier and gate bits. + +properties: + compatible: + const: ti,clksel + + reg: + maxItems: 1 + description: The CLKSEL register range + + '#address-cells': + enum: [ 0, 1, 2 ] + + '#size-cells': + enum: [ 0, 1, 2 ] + + ranges: true + + "#clock-cells": + const: 2 + description: The CLKSEL register and bit offset + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: + type: object + +examples: + - | + clksel_gfx_fclk: clock@52c { + compatible = "ti,clksel"; + reg = <0x25c 0x4>; + #clock-cells = <2>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml new file mode 100644 index 000000000000..d36558aa39f3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 TMPV770X PLL Controller + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X. + +properties: + compatible: + const: toshiba,tmpv7708-pipllct + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + description: External reference clock (OSC2) + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + + osc2_clk: osc2-clk { + compatible = "fixed-clock"; + clock-frequency = <20000000>; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pipllct: clock-controller@24220000 { + compatible = "toshiba,tmpv7708-pipllct"; + reg = <0 0x24220000 0 0x820>; + #clock-cells = <1>; + clocks = <&osc2_clk>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml new file mode 100644 index 000000000000..081f85b1eb88 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 TMPV770x SMU controller + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshia Visconti5 SMU (System Management Unit) which supports the clock + and resets on TMPV770x. + +properties: + compatible: + items: + - const: toshiba,tmpv7708-pismu + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pismu: syscon@24200000 { + compatible = "toshiba,tmpv7708-pismu", "syscon"; + reg = <0 0x24200000 0 0x2140>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt deleted file mode 100644 index 7b5f602765fe..000000000000 --- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt +++ /dev/null @@ -1,132 +0,0 @@ -UniPhier clock controller - - -System clock ------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-clock" - for LD4 SoC. - "socionext,uniphier-pro4-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-clock" - for LD11 SoC. - "socionext,uniphier-ld20-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 8: ST DMAC -12: GIO (Giga bit stream I/O) -14: USB3 ch0 host -15: USB3 ch1 host -16: USB3 ch0 PHY0 -17: USB3 ch0 PHY1 -20: USB3 ch1 PHY0 -21: USB3 ch1 PHY1 - - -Media I/O (MIO) clock, SD clock -------------------------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-mio-clock" - for LD4 SoC. - "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-mio-clock" - for LD11 SoC. - "socionext,uniphier-ld20-sd-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 0: SD ch0 host - 1: eMMC host - 2: SD ch1 host - 7: MIO DMAC - 8: USB2 ch0 host - 9: USB2 ch1 host -10: USB2 ch2 host -12: USB2 ch0 PHY -13: USB2 ch1 PHY -14: USB2 ch2 PHY - - -Peripheral clock ----------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-peri-clock" - for LD4 SoC. - "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC. - "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC. - "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC. - "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-peri-clock" - for LD11 SoC. - "socionext,uniphier-ld20-peri-clock" - for LD20 SoC. - "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC -- #clock-cells: should be 1. - -Example: - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - other nodes ... - }; - -Provided clocks: - - 0: UART ch0 - 1: UART ch1 - 2: UART ch2 - 3: UART ch3 - 4: I2C ch0 - 5: I2C ch1 - 6: I2C ch2 - 7: I2C ch3 - 8: I2C ch4 - 9: I2C ch5 -10: I2C ch6 diff --git a/Documentation/devicetree/bindings/clock/ux500.txt b/Documentation/devicetree/bindings/clock/ux500.txt deleted file mode 100644 index e52bd4b72348..000000000000 --- a/Documentation/devicetree/bindings/clock/ux500.txt +++ /dev/null @@ -1,64 +0,0 @@ -Clock bindings for ST-Ericsson Ux500 clocks - -Required properties : -- compatible : shall contain only one of the following: - "stericsson,u8500-clks" - "stericsson,u8540-clks" - "stericsson,u9540-clks" -- reg : shall contain base register location and length for - CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of - CLKRST4, which does not exist. - -Required subnodes: -- prcmu-clock: a subnode with one clock cell for PRCMU (power, - reset, control unit) clocks. The cell indicates which PRCMU - clock in the prcmu-clock node the consumer wants to use. -- prcc-periph-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) peripheral clocks. - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- prcc-kernel-clock: a subnode with two clock cells for - PRCC (programmable reset- and clock controller) kernel clocks - The first cell indicates which PRCC block the consumer - wants to use, possible values are 1, 2, 3, 5, 6. The second - cell indicates which clock inside the PRCC block it wants, - possible values are 0 thru 31. -- rtc32k-clock: a subnode with zero clock cells for the 32kHz - RTC clock. -- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster - with zero clock cells. - -Example: - -clocks { - compatible = "stericsson,u8500-clks"; - /* - * Registers for the CLKRST block on peripheral - * groups 1, 2, 3, 5, 6, - */ - reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, - <0x8000f000 0x1000>, <0xa03ff000 0x1000>, - <0xa03cf000 0x1000>; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt index 63f9f1ac3439..109ffa3a5b66 100644 --- a/Documentation/devicetree/bindings/clock/vf610-clock.txt +++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt @@ -9,7 +9,7 @@ Optional properties: - clocks: list of clock identifiers which are external input clocks to the given clock controller. Please refer the next section to find the input clocks for a given controller. -- clock-names: list of names of clocks which are exteral input clocks to the +- clock-names: list of names of clocks which are external input clocks to the given clock controller. Input clocks for top clock controller: diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 000000000000..9d5324dc1027 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + enum: + - xlnx,clocking-wizard + - xlnx,clocking-wizard-v5.2 + - xlnx,clocking-wizard-v6.0 + - xlnx,versal-clk-wizard + + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. Higher the speed grade faster is the FPGA device. + + xlnx,nr-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + description: + Number of outputs. + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - xlnx,speed-grade + - xlnx,nr-outputs + +additionalProperties: false + +examples: + - | + clock-controller@b0000000 { + compatible = "xlnx,clocking-wizard"; + reg = <0xb0000000 0x10000>; + #clock-cells = <1>; + xlnx,speed-grade = <1>; + xlnx,nr-outputs = <6>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml new file mode 100644 index 000000000000..bef109d163a8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal clock controller + +maintainers: + - Michal Simek <michal.simek@amd.com> + +description: | + The clock controller is a hardware block of Xilinx versal clock tree. It + reads required input clock frequencies from the devicetree and acts as clock + provider for all clock consumers of PS clocks. + +properties: + compatible: + oneOf: + - enum: + - xlnx,versal-clk + - xlnx,zynqmp-clk + - items: + - enum: + - xlnx,versal-net-clk + - const: xlnx,versal-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + minItems: 2 + maxItems: 8 + + clock-names: + minItems: 2 + maxItems: 8 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-clk + + then: + properties: + clocks: + items: + - description: reference clock + - description: alternate reference clock for programmable logic + + clock-names: + items: + - const: ref + - const: pl_alt_ref + + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-net-clk + + then: + properties: + clocks: + items: + - description: reference clock + - description: alternate reference clock for programmable logic + - description: alternate reference clock + + clock-names: + items: + - const: ref + - const: pl_alt_ref + - const: alt_ref + + - if: + properties: + compatible: + contains: + enum: + - xlnx,zynqmp-clk + + then: + properties: + clocks: + minItems: 5 + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + - description: (E)MIO clock source (Optional clock) + - description: GEM emio clock (Optional clock) + - description: Watchdog external clock (Optional clock) + + clock-names: + minItems: 5 + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + - pattern: "^mio_clk[00-77]+.*$" + - pattern: "gem[0-3]+_emio_clk.*$" + - pattern: "swdt[0-1]+_ext_clk.*$" + +examples: + - | + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + versal_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,versal-clk"; + clocks = <&ref>, <&pl_alt_ref>; + clock-names = "ref", "pl_alt_ref"; + }; + }; + }; + + clock-controller { + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt deleted file mode 100644 index 391ee1a60bed..000000000000 --- a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt +++ /dev/null @@ -1,63 +0,0 @@ --------------------------------------------------------------------------- -Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using -Zynq MPSoC firmware interface --------------------------------------------------------------------------- -The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock -tree. It reads required input clock frequencies from the devicetree and acts -as clock provider for all clock consumers of PS clocks. - -See clock_bindings.txt for more information on the generic clock bindings. - -Required properties: - - #clock-cells: Must be 1 - - compatible: Must contain: "xlnx,zynqmp-clk" - - clocks: List of clock specifiers which are external input - clocks to the given clock controller. Please refer - the next section to find the input clocks for a - given controller. - - clock-names: List of clock names which are exteral input clocks - to the given clock controller. Please refer to the - clock bindings for more details. - -Input clocks for zynqmp Ultrascale+ clock controller: - -The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock -inputs. These required clock inputs are: - - pss_ref_clk (PS reference clock) - - video_clk (reference clock for video system ) - - pss_alt_ref_clk (alternative PS reference clock) - - aux_ref_clk - - gt_crx_ref_clk (transceiver reference clock) - -The following strings are optional parameters to the 'clock-names' property in -order to provide an optional (E)MIO clock source: - - swdt0_ext_clk - - swdt1_ext_clk - - gem0_emio_clk - - gem1_emio_clk - - gem2_emio_clk - - gem3_emio_clk - - mio_clk_XX # with XX = 00..77 - - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51 - - -Output clocks are registered based on clock information received -from firmware. Output clocks indexes are mentioned in -include/dt-bindings/clock/xlnx-zynqmp-clk.h. - -------- -Example -------- - -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - zynqmp_clk: clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/zx296702-clk.txt b/Documentation/devicetree/bindings/clock/zx296702-clk.txt deleted file mode 100644 index 5c91c9e4f1be..000000000000 --- a/Documentation/devicetree/bindings/clock/zx296702-clk.txt +++ /dev/null @@ -1,34 +0,0 @@ -Device Tree Clock bindings for ZTE zx296702 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "zte,zx296702-topcrm-clk": - zx296702 top clock selection, divider and gating - - "zte,zx296702-lsp0crpm-clk" and - "zte,zx296702-lsp1crpm-clk": - zx296702 device level clock selection and gating - -- reg: Address and length of the register set - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h -for the full list of zx296702 clock IDs. - - -topclk: topcrm@09800000 { - compatible = "zte,zx296702-topcrm-clk"; - reg = <0x09800000 0x1000>; - #clock-cells = <1>; -}; - -uart0: serial@09405000 { - compatible = "zte,zx296702-uart"; - reg = <0x09405000 0x1000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&lsp1clk ZX296702_UART0_PCLK>; -}; diff --git a/Documentation/devicetree/bindings/clock/zx296718-clk.txt b/Documentation/devicetree/bindings/clock/zx296718-clk.txt deleted file mode 100644 index 3a46bf0b2540..000000000000 --- a/Documentation/devicetree/bindings/clock/zx296718-clk.txt +++ /dev/null @@ -1,37 +0,0 @@ -Device Tree Clock bindings for ZTE zx296718 - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "zte,zx296718-topcrm": - zx296718 top clock selection, divider and gating - - "zte,zx296718-lsp0crm" and - "zte,zx296718-lsp1crm": - zx296718 device level clock selection and gating - - "zte,zx296718-audiocrm": - zx296718 audio clock selection, divider and gating - -- reg: Address and length of the register set - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h -for the full list of zx296718 clock IDs. - - -topclk: topcrm@1461000 { - compatible = "zte,zx296718-topcrm-clk"; - reg = <0x01461000 0x1000>; - #clock-cells = <1>; -}; - -usbphy0:usb-phy0 { - compatible = "zte,zx296718-usb-phy"; - #phy-cells = <0>; - clocks = <&topclk USB20_PHY_CLK>; - clock-names = "phyclk"; -}; |