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-rw-r--r--Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml88
1 files changed, 82 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 7e8c7a2a5f9b..162406e0691a 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -53,6 +53,7 @@ properties:
- mediatek,mt8195-pcie
- const: mediatek,mt8192-pcie
- const: mediatek,mt8192-pcie
+ - const: airoha,en7581-pcie
reg:
maxItems: 1
@@ -76,20 +77,20 @@ properties:
resets:
minItems: 1
- maxItems: 2
+ maxItems: 3
reset-names:
minItems: 1
- maxItems: 2
+ maxItems: 3
items:
- enum: [ phy, mac ]
+ enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
clocks:
- minItems: 4
+ minItems: 1
maxItems: 6
clock-names:
- minItems: 4
+ minItems: 1
maxItems: 6
assigned-clocks:
@@ -108,6 +109,17 @@ properties:
power-domains:
maxItems: 1
+ mediatek,pbus-csr:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to pbus-csr syscon
+ - description: offset of pbus-csr base address register
+ - description: offset of pbus-csr base address mask register
+ description:
+ Phandle with two arguments to the syscon node used to detect if
+ a given address is accessible on PCIe controller.
+
'#interrupt-cells':
const: 1
@@ -140,13 +152,16 @@ required:
- interrupt-controller
allOf:
- - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:
const: mediatek,mt8192-pcie
then:
properties:
+ clocks:
+ minItems: 6
+
clock-names:
items:
- const: pl_250m
@@ -155,6 +170,17 @@ allOf:
- const: tl_32k
- const: peri_26m
- const: top_133m
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,pbus-csr: false
+
- if:
properties:
compatible:
@@ -164,6 +190,9 @@ allOf:
- mediatek,mt8195-pcie
then:
properties:
+ clocks:
+ minItems: 6
+
clock-names:
items:
- const: pl_250m
@@ -172,6 +201,17 @@ allOf:
- const: tl_32k
- const: peri_26m
- const: peri_mem
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,pbus-csr: false
+
- if:
properties:
compatible:
@@ -180,6 +220,10 @@ allOf:
- mediatek,mt7986-pcie
then:
properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+
clock-names:
items:
- const: pl_250m
@@ -187,6 +231,38 @@ allOf:
- const: peri_26m
- const: top_133m
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+
+ mediatek,pbus-csr: false
+
+ - if:
+ properties:
+ compatible:
+ const: airoha,en7581-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: sys-ck
+
+ resets:
+ minItems: 3
+
+ reset-names:
+ items:
+ - const: phy-lane0
+ - const: phy-lane1
+ - const: phy-lane2
+
unevaluatedProperties: false
examples: