diff options
Diffstat (limited to 'Documentation/devicetree/bindings/reset')
61 files changed, 1783 insertions, 929 deletions
diff --git a/Documentation/devicetree/bindings/reset/allwinner,sun6i-a31-clock-reset.yaml b/Documentation/devicetree/bindings/reset/allwinner,sun6i-a31-clock-reset.yaml new file mode 100644 index 000000000000..2a248e511c18 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/allwinner,sun6i-a31-clock-reset.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 Peripheral Reset Controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +deprecated: true + +select: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-ahb1-reset + - allwinner,sun6i-a31-clock-reset + + # The PRCM on the A31 and A23 will have the reg property missing, + # since it's set at the upper level node, and will be validated by + # PRCM's schema. Make sure we only validate standalone nodes. + required: + - compatible + - reg + +properties: + "#reset-cells": + const: 1 + description: > + This additional argument passed to that reset controller is the + offset of the bit controlling this particular reset line in the + register. + + compatible: + enum: + - allwinner,sun6i-a31-ahb1-reset + - allwinner,sun6i-a31-clock-reset + + reg: + maxItems: 1 + +required: + - "#reset-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + ahb1_rst: reset@1c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; + }; + + - | + apbs_rst: reset@80014b0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x080014b0 0x4>; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt deleted file mode 100644 index 4ca66c96fe97..000000000000 --- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt +++ /dev/null @@ -1,21 +0,0 @@ -Allwinner sunxi Peripheral Reset Controller -=========================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be one of the following: - "allwinner,sun6i-a31-ahb1-reset" - "allwinner,sun6i-a31-clock-reset" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -ahb1_rst: reset@1c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; -}; diff --git a/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml b/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml new file mode 100644 index 000000000000..761c70cf9ddf --- /dev/null +++ b/Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA Reset Manager + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + compatible: + oneOf: + - description: Cyclone5/Arria5/Arria10 + const: altr,rst-mgr + - description: Stratix10 ARM64 SoC + items: + - const: altr,stratix10-rst-mgr + - const: altr,rst-mgr + + reg: + maxItems: 1 + + altr,modrst-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset of the first modrst register + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +if: + properties: + compatible: + contains: + const: altr,stratix10-rst-mgr +then: + properties: + altr,modrst-offset: false + +additionalProperties: false + +examples: + - | + rstmgr@ffd05000 { + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + altr,modrst-offset = <0x10>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt deleted file mode 100644 index 43e580ef64ba..000000000000 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Amlogic audio memory arbiter controller - -The Amlogic Audio ARB is a simple device which enables or -disables the access of Audio FIFOs to DDR on AXG based SoC. - -Required properties: -- compatible: 'amlogic,meson-axg-audio-arb' or - 'amlogic,meson-sm1-audio-arb' -- reg: physical base address of the controller and length of memory - mapped region. -- clocks: phandle to the fifo peripheral clock provided by the audio - clock controller. -- #reset-cells: must be 1. - -Example on the A113 SoC: - -arb: reset-controller@280 { - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; -}; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml new file mode 100644 index 000000000000..bc1d284785e1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic audio memory arbiter controller + +maintainers: + - Jerome Brunet <jbrunet@baylibre.com> + +description: The Amlogic Audio ARB is a simple device which enables or disables + the access of Audio FIFOs to DDR on AXG based SoC. + +properties: + compatible: + enum: + - amlogic,meson-axg-audio-arb + - amlogic,meson-sm1-audio-arb + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: | + phandle to the fifo peripheral clock provided by the audio clock + controller. + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#reset-cells" + +additionalProperties: false + +examples: + - | + // on the A113 SoC: + #include <dt-bindings/clock/axg-audio-clkc.h> + bus { + #address-cells = <2>; + #size-cells = <2>; + + arb: reset-controller@280 { + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + }; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index b3f57d81f007..f0c6c0df0ce3 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -2,13 +2,13 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson SoC Reset Controller maintainers: - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> properties: compatible: @@ -17,6 +17,8 @@ properties: - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs + - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs + - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs reg: maxItems: 1 @@ -29,6 +31,8 @@ required: - reg - "#reset-cells" +additionalProperties: false + examples: - | reset-controller@c884404 { diff --git a/Documentation/devicetree/bindings/reset/ath79-reset.txt b/Documentation/devicetree/bindings/reset/ath79-reset.txt deleted file mode 100644 index 4c56330bf398..000000000000 --- a/Documentation/devicetree/bindings/reset/ath79-reset.txt +++ /dev/null @@ -1,20 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required Properties: -- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset" - as fallback -- reg: Base address and size of the controllers memory area -- #reset-cells : Specifies the number of cells needed to encode reset - line, should be 1 - -Example: - - reset-controller@1806001c { - compatible = "qca,ar9132-reset", "qca,ar7100-reset"; - reg = <0x1806001c 0x4>; - - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml new file mode 100644 index 000000000000..98465d26949e --- /dev/null +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip System Reset Controller + +maintainers: + - Claudiu Beznea <claudiu.beznea@microchip.com> + +description: | + The system reset controller can be used to reset the CPU. In case of + SAMA7G5 it can also reset some devices (e.g. USB PHYs). + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9260-rstc + - atmel,at91sam9g45-rstc + - atmel,sama5d3-rstc + - microchip,sam9x60-rstc + - microchip,sama7g5-rstc + - items: + - const: atmel,sama5d3-rstc + - const: atmel,at91sam9g45-rstc + + reg: + minItems: 1 + items: + - description: base registers for system reset control + - description: registers for device specific reset control + + clocks: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sama7g5-rstc + then: + required: + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + }; diff --git a/Documentation/devicetree/bindings/reset/berlin,reset.txt b/Documentation/devicetree/bindings/reset/berlin,reset.txt deleted file mode 100644 index 514fee098b4b..000000000000 --- a/Documentation/devicetree/bindings/reset/berlin,reset.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell Berlin reset controller -=============================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller node must be a sub-node of the chip controller -node on Berlin SoCs. - -Required properties: -- compatible: should be "marvell,berlin2-reset" -- #reset-cells: must be set to 2 - -Example: - -chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; -}; - -&usb_phy0 { - resets = <&chip_rst 0x104 12>; -}; diff --git a/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt deleted file mode 100644 index a6f8455ae6c4..000000000000 --- a/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt +++ /dev/null @@ -1,18 +0,0 @@ -Bitmain BM1880 SoC Reset Controller -=================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "bitmain,bm1880-reset" -- reg: Offset and length of reset controller space in SCTRL. -- #reset-cells: Must be 1. - -Example: - - rst: reset-controller@c00 { - compatible = "bitmain,bm1880-reset"; - reg = <0xc00 0x8>; - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.yaml b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.yaml new file mode 100644 index 000000000000..1f40b654f6a2 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Manivannan Sadhasivam <mani@kernel.org> +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 SoC Reset Controller + +maintainers: + - Manivannan Sadhasivam <mani@kernel.org> + +properties: + compatible: + const: bitmain,bm1880-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rst: reset-controller@c00 { + compatible = "bitmain,bm1880-reset"; + reg = <0xc00 0x8>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml new file mode 100644 index 000000000000..88aebb370838 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,bcm4908-misc-pcie-reset.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/brcm,bcm4908-misc-pcie-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom MISC block PCIe reset controller + +description: This document describes reset controller handling PCIe PERST# + signals. On BCM4908 it's a part of the MISC block. + +maintainers: + - Rafał Miłecki <rafal@milecki.pl> + +properties: + compatible: + const: brcm,bcm4908-misc-pcie-reset + + reg: + maxItems: 1 + + "#reset-cells": + description: PCIe core id + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@ff802644 { + compatible = "brcm,bcm4908-misc-pcie-reset"; + reg = <0xff802644 0x04>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml new file mode 100644 index 000000000000..00150b93fca0 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM6345 reset controller + +description: This document describes the BCM6345 reset controller. + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + +properties: + compatible: + const: brcm,bcm6345-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml new file mode 100644 index 000000000000..34cfc642d808 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 Broadcom +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM7216 RESCAL reset controller + +description: This document describes the BCM7216 RESCAL reset controller + which is responsible for controlling the reset of the SATA and PCIe0/1 + instances on BCM7216. + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + - Jim Quinlan <jim2101024@gmail.com> + +properties: + compatible: + const: brcm,bcm7216-pcie-sata-rescal + + reg: + maxItems: 1 + + "#reset-cells": + const: 0 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@8b2c800 { + compatible = "brcm,bcm7216-pcie-sata-rescal"; + reg = <0x8b2c800 0x10>; + #reset-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt deleted file mode 100644 index 6e5341b4f891..000000000000 --- a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt +++ /dev/null @@ -1,27 +0,0 @@ -Broadcom STB SW_INIT-style reset controller -=========================================== - -Broadcom STB SoCs have a SW_INIT-style reset controller with separate -SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit -reset lines. - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: should be brcm,brcmstb-reset -- reg: register base and length -- #reset-cells: must be set to 1 - -Example: - - reset: reset-controller@8404318 { - compatible = "brcm,brcmstb-reset"; - reg = <0x8404318 0x30>; - #reset-cells = <1>; - }; - - ðernet_switch { - resets = <&reset>; - reset-names = "switch"; - }; diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml new file mode 100644 index 000000000000..b115b86e2fe6 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB SW_INIT-style reset controller + +description: + Broadcom STB SoCs have a SW_INIT-style reset controller with separate + SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit + reset lines. + + Please also refer to reset.txt in this directory for common reset + controller binding usage. + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + const: brcm,brcmstb-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset: reset-controller@8404318 { + compatible = "brcm,brcmstb-reset"; + reg = <0x8404318 0x30>; + #reset-cells = <1>; + }; + + ethernet_switch { + resets = <&reset 26>; + reset-names = "switch"; + }; diff --git a/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml new file mode 100644 index 000000000000..0c0135964b91 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K210 Reset Controller + +maintainers: + - Damien Le Moal <dlemoal@kernel.org> + +description: | + Canaan Kendryte K210 reset controller driver which supports the SoC + system controller supplied reset registers for the various peripherals + of the SoC. The K210 reset controller node must be defined as a child + node of the K210 system controller node. + + See also: + - dt-bindings/reset/k210-rst.h + +properties: + compatible: + const: canaan,k210-rst + + '#reset-cells': + const: 1 + +required: + - '#reset-cells' + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/k210-rst.h> + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml b/Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml new file mode 100644 index 000000000000..0e5ee8decc0d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/delta,tn48m-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Delta Networks TN48M CPLD reset controller + +maintainers: + - Robert Marko <robert.marko@sartura.hr> + +description: | + This module is part of the Delta TN48M multi-function device. For more + details see ../mfd/delta,tn48m-cpld.yaml. + + Reset controller modules provides resets for the following: + * 88F7040 SoC + * 88F6820 SoC + * 98DX3265 switch MAC-s + * 88E1680 PHY-s + * 88E1512 PHY + * PoE PSE controller + +properties: + compatible: + const: delta,tn48m-reset + + "#reset-cells": + const: 1 + +required: + - compatible + - "#reset-cells" + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt deleted file mode 100644 index 6ed79e60248a..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt +++ /dev/null @@ -1,49 +0,0 @@ -Freescale i.MX System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "fsl,<chip>-src" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt and CPU WDOG interrupt, - in this order. -- #reset-cells: 1, see below - -example: - -src: src@20d8000 { - compatible = "fsl,imx6q-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 0x04 0 96 0x04>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset the GPU, VPU, -IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device -nodes should specify the reset line on the SRC in their resets -property, containing a phandle to the SRC device node and a -RESET_INDEX specifying which module to reset, as described in -reset.txt - -example: - - ipu1: ipu@2400000 { - resets = <&src 2>; - }; - ipu2: ipu@2800000 { - resets = <&src 4>; - }; - -The following RESET_INDEX values are valid for i.MX5: -GPU_RESET 0 -VPU_RESET 1 -IPU1_RESET 2 -OPEN_VG_RESET 3 -The following additional RESET_INDEX value is valid for i.MX6: -IPU2_RESET 4 diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml new file mode 100644 index 000000000000..f5ec1d54aa51 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX System Reset Controller + +maintainers: + - Philipp Zabel <p.zabel@pengutronix.de> + +description: | + The system reset controller can be used to reset the GPU, VPU, + IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device + nodes should specify the reset line on the SRC in their resets + property, containing a phandle to the SRC device node and a + RESET_INDEX specifying which module to reset, as described in + reset.txt + + The following RESET_INDEX values are valid for i.MX5: + GPU_RESET 0 + VPU_RESET 1 + IPU1_RESET 2 + OPEN_VG_RESET 3 + The following additional RESET_INDEX value is valid for i.MX6: + IPU2_RESET 4 + +properties: + compatible: + oneOf: + - const: fsl,imx51-src + - items: + - enum: + - fsl,imx50-src + - fsl,imx53-src + - fsl,imx6q-src + - fsl,imx6sx-src + - fsl,imx6sl-src + - fsl,imx6ul-src + - fsl,imx6sll-src + - const: fsl,imx51-src + + reg: + maxItems: 1 + + interrupts: + items: + - description: SRC interrupt + - description: CPU WDOG interrupts out of SRC + minItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@73fd0000 { + compatible = "fsl,imx51-src"; + reg = <0x73fd0000 0x4000>; + interrupts = <75>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt deleted file mode 100644 index c2489e41a801..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt +++ /dev/null @@ -1,52 +0,0 @@ -Freescale i.MX7 System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: - - For i.MX7 SoCs should be "fsl,imx7d-src", "syscon" - - For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon" - - For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt -- #reset-cells: 1, see below - -example: - -src: reset-controller@30390000 { - compatible = "fsl,imx7d-src", "syscon"; - reg = <0x30390000 0x2000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; -}; - - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset various set of -peripherals. Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -Example: - - pcie: pcie@33800000 { - - ... - - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>; - reset-names = "pciephy", "apps"; - - ... - }; - - -For list of all valid reset indices see -<dt-bindings/reset/imx7-reset.h> for i.MX7, -<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and -<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml new file mode 100644 index 000000000000..00430e2eabc8 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7 System Reset Controller + +maintainers: + - Andrey Smirnov <andrew.smirnov@gmail.com> + +description: | + The system reset controller can be used to reset various set of + peripherals. Device nodes that need access to reset lines should + specify them as a reset phandle in their corresponding node as + specified in reset.txt. + + For list of all valid reset indices see + <dt-bindings/reset/imx7-reset.h> for i.MX7, + <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN, + <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx7d-src + - fsl,imx8mq-src + - fsl,imx8mp-src + - const: syscon + - items: + - enum: + - fsl,imx8mm-src + - fsl,imx8mn-src + - const: fsl,imx8mq-src + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + reset-controller@30390000 { + compatible = "fsl,imx7d-src", "syscon"; + reg = <0x30390000 0x2000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt deleted file mode 100644 index 2df4bddeb688..000000000000 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt +++ /dev/null @@ -1,44 +0,0 @@ -Hisilicon System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller registers are part of the system-ctl block on -hi3660 and hi3670 SoCs. - -Required properties: -- compatible: should be one of the following: - "hisilicon,hi3660-reset" for HI3660 - "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670 -- hisi,rst-syscon: phandle of the reset's syscon. -- #reset-cells : Specifies the number of cells needed to encode a - reset source. The type shall be a <u32> and the value shall be 2. - - Cell #1 : offset of the reset assert control - register from the syscon register base - offset + 4: deassert control register - offset + 8: status control register - Cell #2 : bit position of the reset in the reset control register - -Example: - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3660-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - }; - - iomcu_rst: iomcu_rst_controller { - compatible = "hisilicon,hi3660-reset"; - hisi,rst-syscon = <&iomcu>; - #reset-cells = <2>; - }; - -Specifying reset lines connected to IP modules -============================================== -example: - - i2c0: i2c@..... { - ... - resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ - ... - }; diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml new file mode 100644 index 000000000000..e4de002d6903 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon System Reset Controller + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: | + Please also refer to reset.txt in this directory for common reset + controller binding usage. + The reset controller registers are part of the system-ctl block on + hi3660 and hi3670 SoCs. + +properties: + compatible: + oneOf: + - items: + - const: hisilicon,hi3660-reset + - items: + - const: hisilicon,hi3670-reset + - const: hisilicon,hi3660-reset + + hisi,rst-syscon: + deprecated: true + description: phandle of the reset's syscon, use hisilicon,rst-syscon instead + $ref: /schemas/types.yaml#/definitions/phandle + + hisilicon,rst-syscon: + description: phandle of the reset's syscon. + $ref: /schemas/types.yaml#/definitions/phandle + + '#reset-cells': + description: | + Specifies the number of cells needed to encode a reset source. + Cell #1 : offset of the reset assert control register from the syscon + register base + offset + 4: deassert control register + offset + 8: status control register + Cell #2 : bit position of the reset in the reset control register + const: 2 + +required: + - compatible + +additionalProperties: false + +examples: + - | + iomcu_rst_controller { + compatible = "hisilicon,hi3660-reset"; + hisilicon,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; +... diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt deleted file mode 100644 index ea0a6a9734c1..000000000000 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt +++ /dev/null @@ -1,37 +0,0 @@ -Hisilicon System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller registers are part of the system-ctl block on -hi6220 SoC. - -Required properties: -- compatible: should be one of the following: - - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. - - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. - - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller. -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -Example: -sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== -example: - - uart1: serial@..... { - ... - resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; - ... - }; - -The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>. diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml new file mode 100644 index 000000000000..13bf6bb3f097 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Reset Controller on Intel Gateway SoCs + +maintainers: + - Dilip Kota <eswara.kota@linux.intel.com> + +properties: + compatible: + enum: + - intel,rcu-lgm + - intel,rcu-xrx200 + + reg: + description: Reset controller registers. + maxItems: 1 + + intel,global-reset: + description: Global reset register offset and bit offset. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: Register offset + - description: Register bit offset + minimum: 0 + maximum: 31 + + "#reset-cells": + minimum: 2 + maximum: 3 + description: | + First cell is reset request register offset. + Second cell is bit offset in reset request register. + Third cell is bit offset in reset status register. + For LGM SoC, reset cell count is 2 as bit offset in + reset request and reset status registers is same. Whereas + 3 for legacy SoCs as bit offset differs. + +required: + - compatible + - reg + - intel,global-reset + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rcu0: reset-controller@e0000000 { + compatible = "intel,rcu-lgm"; + reg = <0xe0000000 0x20000>; + intel,global-reset = <0x10 30>; + #reset-cells = <2>; + }; + + pwm: pwm@e0d00000 { + compatible = "intel,lgm-pwm"; + reg = <0xe0d00000 0x30>; + clocks = <&cgu0 1>; + #pwm-cells = <2>; + resets = <&rcu0 0x30 21>; + }; diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.txt b/Documentation/devicetree/bindings/reset/lantiq,reset.txt deleted file mode 100644 index c6aef36b7d15..000000000000 --- a/Documentation/devicetree/bindings/reset/lantiq,reset.txt +++ /dev/null @@ -1,30 +0,0 @@ -Lantiq XWAY SoC RCU reset controller binding -============================================ - -This binding describes a reset-controller found on the RCU module on Lantiq -XWAY SoCs. - -This node has to be a sub node of the Lantiq RCU block. - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,danube-reset" - "lantiq,xrx200-reset" -- reg : Defines the following sets of registers in the parent - syscon device - - Offset of the reset set register - - Offset of the reset status register -- #reset-cells : Specifies the number of cells needed to encode the - reset line, should be 2. - The first cell takes the reset set bit and the - second cell takes the status bit. - -------------------------------------------------------------------------------- -Example for the reset-controllers on the xRX200 SoCs: - reset0: reset-controller@10 { - compatible = "lantiq,xrx200-reset"; - reg <0x10 0x04>, <0x14 0x04>; - - #reset-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.yaml b/Documentation/devicetree/bindings/reset/lantiq,reset.yaml new file mode 100644 index 000000000000..15d65a5dd631 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/lantiq,reset.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq XWAY SoC RCU reset controller + +maintainers: + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +description: | + This binding describes a reset-controller found on the RCU module on Lantiq + XWAY SoCs. This node has to be a sub node of the Lantiq RCU block. + +properties: + compatible: + enum: + - lantiq,danube-reset + - lantiq,xrx200-reset + + reg: + description: | + Defines the following sets of registers in the parent syscon device + Offset of the reset set register + Offset of the reset status register + maxItems: 2 + + '#reset-cells': + description: | + The first cell takes the reset set bit and the second cell takes the + status bit. + const: 2 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + // On the xRX200 SoCs: + reset0: reset-controller@10 { + compatible = "lantiq,xrx200-reset"; + reg = <0x10 0x04>, <0x14 0x04>; + #reset-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/reset/marvell,berlin2-reset.yaml b/Documentation/devicetree/bindings/reset/marvell,berlin2-reset.yaml new file mode 100644 index 000000000000..dc86568bfd75 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/marvell,berlin2-reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2015 Antoine Tenart <atenart@kernel.org> +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Berlin reset controller + +maintainers: + - Antoine Tenart <atenart@kernel.org> + +description: The reset controller node must be a sub-node of the chip + controller node on Berlin SoCs. + +properties: + compatible: + const: marvell,berlin2-reset + + "#reset-cells": + const: 2 + +required: + - compatible + - "#reset-cells" + +additionalProperties: false + +examples: + - | + chip: chip-control@ea0000 { + reg = <0xea0000 0x400>; + + chip_rst: reset { + compatible = "marvell,berlin2-reset"; + #reset-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..f2da0693b05a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/microchip,rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund <steen.hegelund@microchip.com> + - Lars Povlsen <lars.povlsen@microchip.com> + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + enum: + - microchip,sparx5-switch-reset + - microchip,lan966x-switch-reset + + reg: + items: + - description: global control block registers + + reg-names: + items: + - const: gcb + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: syscon used to access CPU reset + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + - cpu-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@11010008 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml new file mode 100644 index 000000000000..34c5c1c08ec1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Reset Controller + +maintainers: + - Chi-Fang Li <cfli0@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +description: + The system reset controller can be used to reset various peripheral + controllers in MA35D1 SoC. + +properties: + compatible: + items: + - const: nuvoton,ma35d1-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + # system reset controller node: + - | + + system-management@40460000 { + compatible = "nuvoton,ma35d1-reset"; + reg = <0x40460000 0x200>; + #reset-cells = <1>; + }; +... + diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml new file mode 100644 index 000000000000..d82e65e37cc0 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Reset controller + +maintainers: + - Tomer Maimon <tmaimon77@gmail.com> + +properties: + compatible: + enum: + - nuvoton,npcm750-reset # Poleg NPCM7XX SoC + - nuvoton,npcm845-reset # Arbel NPCM8XX SoC + + reg: + maxItems: 1 + + '#reset-cells': + const: 2 + + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to access GCR registers. + + nuvoton,sw-reset-number: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + description: | + Contains the software reset number to restart the SoC. + If not specified, software reset is disabled. + +required: + - compatible + - reg + - '#reset-cells' + - nuvoton,sysgcr + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> + rstc: rstc@f0801000 { + compatible = "nuvoton,npcm750-reset"; + reg = <0xf0801000 0x70>; + #reset-cells = <2>; + nuvoton,sysgcr = <&gcr>; + nuvoton,sw-reset-number = <2>; + }; + + // Specifying reset lines connected to IP NPCM7XX modules + spi0: spi { + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + }; diff --git a/Documentation/devicetree/bindings/reset/oxnas,reset.txt b/Documentation/devicetree/bindings/reset/oxnas,reset.txt deleted file mode 100644 index d27ccb5d04fc..000000000000 --- a/Documentation/devicetree/bindings/reset/oxnas,reset.txt +++ /dev/null @@ -1,32 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family RESET Controller -================================================ - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-reset" - For OX820, should be "oxsemi,ox820-reset" -- #reset-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be : - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be : - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -Reset indices are in dt-bindings include files : -- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h -- For OX820: include/dt-bindings/reset/oxsemi,ox820.h - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/reset/qca,ar7100-reset.yaml b/Documentation/devicetree/bindings/reset/qca,ar7100-reset.yaml new file mode 100644 index 000000000000..47f8525a9b38 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qca,ar7100-reset.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2015 Alban Bedel <albeu@free.fr> +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR7xxx/AR9XXX reset controller + +maintainers: + - Alban Bedel <albeu@free.fr> + +properties: + compatible: + items: + - enum: + - qca,ar9132-reset + - qca,ar9331-reset + - const: qca,ar7100-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@1806001c { + compatible = "qca,ar9132-reset", "qca,ar7100-reset"; + reg = <0x1806001c 0x4>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml index e2d85a1e1d63..24beb712b56d 100644 --- a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm AOSS Reset Controller maintainers: - - Sibi Sankar <sibis@codeaurora.org> + - Sibi Sankar <quic_sibis@quicinc.com> description: The bindings describe the reset-controller found on AOSS-CC (always on @@ -18,12 +18,17 @@ properties: oneOf: - description: on SC7180 SoCs the following compatibles must be specified items: - - const: "qcom,sc7180-aoss-cc" - - const: "qcom,sdm845-aoss-cc" + - const: qcom,sc7180-aoss-cc + - const: qcom,sdm845-aoss-cc + + - description: on SC7280 SoCs the following compatibles must be specified + items: + - const: qcom,sc7280-aoss-cc + - const: qcom,sdm845-aoss-cc - description: on SDM845 SoCs the following compatibles must be specified items: - - const: "qcom,sdm845-aoss-cc" + - const: qcom,sdm845-aoss-cc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml index d7d8cec9419f..f514363aa474 100644 --- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PDC Global maintainers: - - Sibi Sankar <sibis@codeaurora.org> + - Sibi Sankar <quic_sibis@quicinc.com> description: The bindings describes the reset-controller found on PDC-Global (Power Domain @@ -18,12 +18,16 @@ properties: oneOf: - description: on SC7180 SoCs the following compatibles must be specified items: - - const: "qcom,sc7180-pdc-global" - - const: "qcom,sdm845-pdc-global" + - const: qcom,sc7180-pdc-global + - const: qcom,sdm845-pdc-global + + - description: on SC7280 SoCs the following compatibles must be specified + items: + - const: qcom,sc7280-pdc-global - description: on SDM845 SoCs the following compatibles must be specified items: - - const: "qcom,sdm845-pdc-global" + - const: qcom,sdm845-pdc-global reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt deleted file mode 100644 index de7f06ccd003..000000000000 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ /dev/null @@ -1,48 +0,0 @@ -DT bindings for the Renesas R-Car and RZ/G Reset Controllers - -The R-Car and RZ/G Reset Controllers provide reset control, and implement the -following functions: - - Latching of the levels on mode pins when PRESET# is negated, - - Mode monitoring register, - - Reset control of peripheral devices (on R-Car Gen1), - - Watchdog timer (on R-Car Gen1), - - Register-based reset control and boot address registers for the various CPU - cores (on R-Car Gen2 and Gen3, and on RZ/G). - - -Required properties: - - compatible: Should be - - "renesas,<soctype>-reset-wdt" for R-Car Gen1, - - "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G - Examples with soctypes are: - - "renesas,r8a7743-rst" (RZ/G1M) - - "renesas,r8a7744-rst" (RZ/G1N) - - "renesas,r8a7745-rst" (RZ/G1E) - - "renesas,r8a77470-rst" (RZ/G1C) - - "renesas,r8a774a1-rst" (RZ/G2M) - - "renesas,r8a774b1-rst" (RZ/G2N) - - "renesas,r8a774c0-rst" (RZ/G2E) - - "renesas,r8a7778-reset-wdt" (R-Car M1A) - - "renesas,r8a7779-reset-wdt" (R-Car H1) - - "renesas,r8a7790-rst" (R-Car H2) - - "renesas,r8a7791-rst" (R-Car M2-W) - - "renesas,r8a7792-rst" (R-Car V2H - - "renesas,r8a7793-rst" (R-Car M2-N) - - "renesas,r8a7794-rst" (R-Car E2) - - "renesas,r8a7795-rst" (R-Car H3) - - "renesas,r8a7796-rst" (R-Car M3-W) - - "renesas,r8a77961-rst" (R-Car M3-W+) - - "renesas,r8a77965-rst" (R-Car M3-N) - - "renesas,r8a77970-rst" (R-Car V3M) - - "renesas,r8a77980-rst" (R-Car V3H) - - "renesas,r8a77990-rst" (R-Car E3) - - "renesas,r8a77995-rst" (R-Car D3) - - reg: Address start and address range for the device. - - -Example: - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7795-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml new file mode 100644 index 000000000000..e7e487247751 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/renesas,rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car and RZ/G Reset Controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Magnus Damm <magnus.damm@gmail.com> + +description: | + The R-Car and RZ/G Reset Controllers provide reset control, and implement the + following functions: + - Latching of the levels on mode pins when PRESET# is negated, + - Mode monitoring register, + - Reset control of peripheral devices (on R-Car Gen1), + - Watchdog timer (on R-Car Gen1), + - Register-based reset control and boot address registers for the various + CPU cores (on R-Car Gen2 and Gen3, and on RZ/G). + +properties: + compatible: + enum: + - renesas,r8a7742-rst # RZ/G1H + - renesas,r8a7743-rst # RZ/G1M + - renesas,r8a7744-rst # RZ/G1N + - renesas,r8a7745-rst # RZ/G1E + - renesas,r8a77470-rst # RZ/G1C + - renesas,r8a774a1-rst # RZ/G2M + - renesas,r8a774b1-rst # RZ/G2N + - renesas,r8a774c0-rst # RZ/G2E + - renesas,r8a774e1-rst # RZ/G2H + - renesas,r8a7778-reset-wdt # R-Car M1A + - renesas,r8a7779-reset-wdt # R-Car H1 + - renesas,r8a7790-rst # R-Car H2 + - renesas,r8a7791-rst # R-Car M2-W + - renesas,r8a7792-rst # R-Car V2H + - renesas,r8a7793-rst # R-Car M2-N + - renesas,r8a7794-rst # R-Car E2 + - renesas,r8a7795-rst # R-Car H3 + - renesas,r8a7796-rst # R-Car M3-W + - renesas,r8a77961-rst # R-Car M3-W+ + - renesas,r8a77965-rst # R-Car M3-N + - renesas,r8a77970-rst # R-Car V3M + - renesas,r8a77980-rst # R-Car V3H + - renesas,r8a77990-rst # R-Car E3 + - renesas,r8a77995-rst # R-Car D3 + - renesas,r8a779a0-rst # R-Car V3U + - renesas,r8a779f0-rst # R-Car S4-8 + - renesas,r8a779g0-rst # R-Car V4H + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7795-rst"; + reg = <0xe6160000 0x0200>; + }; diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml new file mode 100644 index 000000000000..03c18611e42d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/{G2L,V2L} USBPHY Control + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: + The RZ/G2L USBPHY Control mainly controls reset and power down of the + USB/PHY. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#reset-cells': + const: 1 + description: | + The phandle's argument in the reset specifier is the PHY reset associated + with the USB port. + 0 = Port 1 Phy reset + 1 = Port 2 Phy reset + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + + phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g044-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; + reg = <0x11c40000 0x10000>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; + resets = <&cpg R9A07G044_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/Documentation/devicetree/bindings/reset/sirf,rstc.txt deleted file mode 100644 index 0505de742d30..000000000000 --- a/Documentation/devicetree/bindings/reset/sirf,rstc.txt +++ /dev/null @@ -1,42 +0,0 @@ -CSR SiRFSoC Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The reset controller(rstc) manages various reset sources. This module provides -reset signals for most blocks in system. Those device nodes should specify the -reset line on the rstc in their resets property, containing a phandle to the -rstc device node and a RESET_INDEX specifying which module to reset, as described -in reset.txt. - -For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers. -For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose -rest_bit is in SW_RST1, its RESET_INDEX is 32~63. - -example: - -vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; -}; diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt deleted file mode 100644 index 32d8435a41df..000000000000 --- a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for the AXS10x reset controller - -This binding describes the ARC AXS10x boards custom IP-block which allows -to control reset signals of selected peripherals. For example DW GMAC, etc... -This block is controlled via memory-mapped register (AKA CREG) which -represents up-to 32 reset lines. - -As of today only the following lines are used: - - DW GMAC - line 5 - -This binding uses the common reset binding[1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -Required properties: -- compatible: should be "snps,axs10x-reset". -- reg: should always contain pair address - length: for creg reset - bits register. -- #reset-cells: from common reset binding; Should always be set to 1. - -Example: - reset: reset-controller@11220 { - compatible = "snps,axs10x-reset"; - #reset-cells = <1>; - reg = <0x11220 0x4>; - }; - -Specifying reset lines connected to IP modules: - ethernet@.... { - .... - resets = <&reset 5>; - .... - }; diff --git a/Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml new file mode 100644 index 000000000000..a75db3d405af --- /dev/null +++ b/Documentation/devicetree/bindings/reset/snps,axs10x-reset.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AXS10x reset controller + +maintainers: + - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + +description: | + This binding describes the ARC AXS10x boards custom IP-block which allows + to control reset signals of selected peripherals. For example DW GMAC, etc... + This block is controlled via memory-mapped register (AKA CREG) which + represents up-to 32 reset lines. + As of today only the following lines are used: + - DW GMAC - line 5 + +properties: + compatible: + const: snps,axs10x-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset: reset-controller@11220 { + compatible = "snps,axs10x-reset"; + #reset-cells = <1>; + reg = <0x11220 0x4>; + }; + + // Specifying reset lines connected to IP modules: + ethernet { + resets = <&reset 5>; + }; diff --git a/Documentation/devicetree/bindings/reset/snps,dw-reset.txt b/Documentation/devicetree/bindings/reset/snps,dw-reset.txt index f94f911dd98d..0c241d4aae76 100644 --- a/Documentation/devicetree/bindings/reset/snps,dw-reset.txt +++ b/Documentation/devicetree/bindings/reset/snps,dw-reset.txt @@ -23,7 +23,7 @@ example: #reset-cells = <1>; }; - dw_rst_2: reset-controller@1000 {i + dw_rst_2: reset-controller@1000 { compatible = "snps,dw-low-reset"; reg = <0x1000 0x8>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt deleted file mode 100644 index 38fe34fd8b8a..000000000000 --- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt +++ /dev/null @@ -1,16 +0,0 @@ -Altera SOCFPGA Reset Manager - -Required properties: -- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10) - "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC -- reg : Should contain 1 register ranges(address and length) -- altr,modrst-offset : Should contain the offset of the first modrst register. -- #reset-cells: 1 - -Example: - rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - altr,modrst-offset = <0x10>; - }; diff --git a/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml b/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml new file mode 100644 index 000000000000..fa253c518d79 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier peripheral core reset in glue layer + +description: | + Some peripheral core reset belongs to its own glue layer. Before using + this core reset, it is necessary to control the clocks and resets to + enable this layer. These clocks and resets should be described in each + property. + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +properties: + compatible: + enum: + - socionext,uniphier-pro4-usb3-reset + - socionext,uniphier-pro5-usb3-reset + - socionext,uniphier-pxs2-usb3-reset + - socionext,uniphier-ld20-usb3-reset + - socionext,uniphier-pxs3-usb3-reset + - socionext,uniphier-nx1-usb3-reset + - socionext,uniphier-pro4-ahci-reset + - socionext,uniphier-pxs2-ahci-reset + - socionext,uniphier-pxs3-ahci-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: true + + resets: + minItems: 1 + maxItems: 2 + + reset-names: true + +allOf: + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pro4-usb3-reset + - socionext,uniphier-pro5-usb3-reset + - socionext,uniphier-pro4-ahci-reset + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + else: + properties: + clocks: + maxItems: 1 + clock-names: + const: link + resets: + maxItems: 1 + reset-names: + const: link + +additionalProperties: false + +required: + - compatible + - reg + - "#reset-cells" + - clocks + - clock-names + - resets + - reset-names + +examples: + - | + usb_rst: reset-controller@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; diff --git a/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml b/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml new file mode 100644 index 000000000000..033b252a3dfe --- /dev/null +++ b/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier reset controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + oneOf: + - description: System reset + enum: + - socionext,uniphier-ld4-reset + - socionext,uniphier-pro4-reset + - socionext,uniphier-sld8-reset + - socionext,uniphier-pro5-reset + - socionext,uniphier-pxs2-reset + - socionext,uniphier-ld6b-reset + - socionext,uniphier-ld11-reset + - socionext,uniphier-ld20-reset + - socionext,uniphier-pxs3-reset + - socionext,uniphier-nx1-reset + - description: Media I/O (MIO) reset, SD reset + enum: + - socionext,uniphier-ld4-mio-reset + - socionext,uniphier-pro4-mio-reset + - socionext,uniphier-sld8-mio-reset + - socionext,uniphier-pro5-sd-reset + - socionext,uniphier-pxs2-sd-reset + - socionext,uniphier-ld11-mio-reset + - socionext,uniphier-ld11-sd-reset + - socionext,uniphier-ld20-sd-reset + - socionext,uniphier-pxs3-sd-reset + - socionext,uniphier-nx1-sd-reset + - description: Peripheral reset + enum: + - socionext,uniphier-ld4-peri-reset + - socionext,uniphier-pro4-peri-reset + - socionext,uniphier-sld8-peri-reset + - socionext,uniphier-pro5-peri-reset + - socionext,uniphier-pxs2-peri-reset + - socionext,uniphier-ld11-peri-reset + - socionext,uniphier-ld20-peri-reset + - socionext,uniphier-pxs3-peri-reset + - socionext,uniphier-nx1-peri-reset + - description: Analog signal amplifier reset + enum: + - socionext,uniphier-ld11-adamv-reset + - socionext,uniphier-ld20-adamv-reset + + "#reset-cells": + const: 1 + + resets: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - "#reset-cells" + +examples: + - | + reset-controller { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt b/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt deleted file mode 100644 index 9ca27761f811..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt +++ /dev/null @@ -1,42 +0,0 @@ -STMicroelectronics STi family Sysconfig Picophy SoftReset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in -the STi family SoC system configuration registers. - -The actual action taken when softreset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to Documentation/devicetree/bindings/reset/reset.txt -for common reset controller binding usage. - -Required properties: -- compatible: Should be "st,stih407-picophyreset" -- #reset-cells: 1, see below - -Example: - - picophyreset: picophyreset-controller { - compatible = "st,stih407-picophyreset"; - #reset-cells = <1>; - }; - -Specifying picophyreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the picophyreset device node and an -index specifying which channel to use, as described in -Documentation/devicetree/bindings/reset/reset.txt. - -Example: - - usb2_picophy0: usbpicophy@0 { - resets = <&picophyreset STIH407_PICOPHY0_RESET>; - }; - -Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt deleted file mode 100644 index 92527138bc93..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt +++ /dev/null @@ -1,45 +0,0 @@ -STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip peripheral controllers such as USB and SATA, using -"powerdown" control bits found in the STi family SoC system configuration -registers. These have been grouped together into a single reset controller -device for convenience. - -The actual action taken when powerdown is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "st,stih407-powerdown" -- #reset-cells: 1, see below - -example: - - powerdown: powerdown-controller { - compatible = "st,stih407-powerdown"; - #reset-cells = <1>; - }; - - -Specifying powerdown control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the powerdown device node and an -index specifying which channel to use, as described in reset.txt - -example: - - st_dwc3: dwc3@8f94000 { - resets = <&powerdown STIH407_USB3_POWERDOWN>, - }; - -Macro definitions for the supported reset channels can be found in: - -include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,stih407-picophyreset.yaml b/Documentation/devicetree/bindings/reset/st,stih407-picophyreset.yaml new file mode 100644 index 000000000000..329ae4ae1a10 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stih407-picophyreset.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi family Sysconfig Picophy SoftReset Controller + +maintainers: + - Peter Griffin <peter.griffin@linaro.org> + +description: | + This binding describes a reset controller device that is used to enable and + disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in + the STi family SoC system configuration registers. + + The actual action taken when softreset is asserted is hardware dependent. + However, when asserted it may not be possible to access the hardware's + registers and after an assert/deassert sequence the hardware's previous state + may no longer be valid. + +properties: + compatible: + const: st,stih407-picophyreset + + '#reset-cells': + const: 1 + +required: + - compatible + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/stih407-resets.h> + + picophyreset: picophyreset-controller { + compatible = "st,stih407-picophyreset"; + #reset-cells = <1>; + }; + + // Specifying picophyreset control of devices + usb2_picophy0: usbpicophy { + resets = <&picophyreset STIH407_PICOPHY0_RESET>; + }; diff --git a/Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml b/Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml new file mode 100644 index 000000000000..d3790e602659 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/st,stih407-powerdown.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@st.com> + +description: | + This binding describes a reset controller device that is used to enable and + disable on-chip peripheral controllers such as USB and SATA, using + "powerdown" control bits found in the STi family SoC system configuration + registers. These have been grouped together into a single reset controller + device for convenience. + + The actual action taken when powerdown is asserted is hardware dependent. + However, when asserted it may not be possible to access the hardware's + registers and after an assert/deassert sequence the hardware's previous state + may no longer be valid. + +properties: + compatible: + const: st,stih407-powerdown + + '#reset-cells': + const: 1 + +required: + - compatible + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/stih407-resets.h> + + powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; + #reset-cells = <1>; + }; + + // Specifying powerdown control of devices: + st_dwc3: dwc3 { + resets = <&powerdown STIH407_USB3_POWERDOWN>; + }; diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt index b4edaf7c7ff3..2880d5dda95e 100644 --- a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt +++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt @@ -3,4 +3,4 @@ STMicroelectronics STM32MP1 Peripheral Reset Controller The RCC IP is both a reset and a clock controller. -Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt +Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml new file mode 100644 index 000000000000..2f5bd616b7ae --- /dev/null +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 SoC Reset Controller + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +properties: + compatible: + enum: + - starfive,jh7100-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@11840000 { + compatible = "starfive,jh7100-reset"; + reg = <0x11840000 0x10000>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/sunplus,reset.yaml b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file mode 100644 index 000000000000..205918ce324c --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sunplus,reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian <qinjian@cqplus1.com> + +properties: + compatible: + const: sunplus,sp7021-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible = "sunplus,sp7021-reset"; + reg = <0x9c000054 0x28>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt deleted file mode 100644 index 8b1cf022f18a..000000000000 --- a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt +++ /dev/null @@ -1,62 +0,0 @@ -Texas Instruments System Control Interface (TI-SCI) Reset Controller -===================================================================== - -Some TI SoCs contain a system controller (like the Power Management Micro -Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling -the state of the various hardware modules present on the SoC. Communication -between the host processor running an OS and the system controller happens -through a protocol called TI System Control Interface (TI-SCI protocol). -For TI SCI details, please refer to the document, -Documentation/devicetree/bindings/arm/keystone/ti,sci.txt - -TI-SCI Reset Controller Node -============================ -This reset controller node uses the TI SCI protocol to perform the reset -management of various hardware modules present on the SoC. Must be a child -node of the associated TI-SCI system controller node. - -Required properties: --------------------- - - compatible : Should be "ti,sci-reset" - - #reset-cells : Should be 2. Please see the reset consumer node below for - usage details. - -TI-SCI Reset Consumer Nodes -=========================== -Each of the reset consumer nodes should have the following properties, -in addition to their own properties. - -Required properties: --------------------- - - resets : A phandle and reset specifier pair, one pair for each reset - signal that affects the device, or that the device manages. - The phandle should point to the TI-SCI reset controller node, - and the reset specifier should have 2 cell-values. The first - cell should contain the device ID. The second cell should - contain the reset mask value used by system controller. - Please refer to the protocol documentation for these values - to be used for different devices, - http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data - -Please also refer to Documentation/devicetree/bindings/reset/reset.txt for -common reset controller usage by consumers. - -Example: --------- -The following example demonstrates both a TI-SCI reset controller node and a -consumer (a DSP device) on the 66AK2G SoC. - -pmmc: pmmc { - compatible = "ti,k2g-sci"; - - k2g_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; -}; - -dsp0: dsp@10800000 { - ... - resets = <&k2g_reset 0x0046 0x1>; - ... -}; diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml new file mode 100644 index 000000000000..e10eb98eddad --- /dev/null +++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-SCI reset controller + +maintainers: + - Nishanth Menon <nm@ti.com> + +description: | + Some TI SoCs contain a system controller (like the Power Management Micro + Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling + the state of the various hardware modules present on the SoC. Communication + between the host processor running an OS and the system controller happens + through a protocol called TI System Control Interface (TI-SCI protocol). + + This reset controller node uses the TI SCI protocol to perform the reset + management of various hardware modules present on the SoC. Must be a child + node of the associated TI-SCI system controller node. + +properties: + $nodename: + pattern: "^reset-controller$" + + compatible: + const: ti,sci-reset + + "#reset-cells": + const: 2 + description: + The two cells represent values that the TI-SCI controller defines. + + The first cell should contain the device ID. + + The second cell should contain the reset mask corresponding to the device + used by system controller. + + Please see http://processors.wiki.ti.com/index.php/TISCI for + protocol documentation for the values to be used for different devices. + + +additionalProperties: false + +examples: + - | + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/reset/ti,tps380x-reset.yaml b/Documentation/devicetree/bindings/reset/ti,tps380x-reset.yaml new file mode 100644 index 000000000000..6063784f0352 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/ti,tps380x-reset.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TPS380x reset controller + +maintainers: + - Marco Felsch <kernel@pengutronix.de> + +description: | + The TPS380x family [1] of supervisory circuits monitor supply voltages to + provide circuit initialization and timing supervision. The devices assert a + RESET signal if the voltage drops below a preset threshold or upon a manual + reset input (MR). The RESET output remains asserted for the factory + programmed delay after the voltage return above its threshold or after the + manual reset input is released. + + [1] https://www.ti.com/product/TPS3801 + +properties: + compatible: + enum: + - ti,tps3801 + + reset-gpios: + maxItems: 1 + description: Reference to the GPIO connected to the MR pin. + + "#reset-cells": + const: 0 + +required: + - compatible + - reset-gpios + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + reset: reset-controller { + compatible = "ti,tps3801"; + #reset-cells = <0>; + reset-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; +... diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt index 86945502ccb5..61a0ff33e89f 100644 --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt @@ -43,7 +43,7 @@ Required properties: Cell #6 : bit position of the reset in the reset status register Cell #7 : Flags used to control reset behavior, - availible flags defined in the DT include + available flags defined in the DT include file <dt-bindings/reset/ti-syscon.h> SysCon Reset Consumer Nodes diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt deleted file mode 100644 index e320a8cc9e4d..000000000000 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ /dev/null @@ -1,180 +0,0 @@ -UniPhier reset controller - - -System reset ------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-reset" - for LD4 SoC - "socionext,uniphier-pro4-reset" - for Pro4 SoC - "socionext,uniphier-sld8-reset" - for sLD8 SoC - "socionext,uniphier-pro5-reset" - for Pro5 SoC - "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-reset" - for LD11 SoC - "socionext,uniphier-ld20-reset" - for LD20 SoC - "socionext,uniphier-pxs3-reset" - for PXs3 SoC -- #reset-cells: should be 1. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Media I/O (MIO) reset, SD reset -------------------------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-mio-reset" - for LD4 SoC - "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC - "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC - "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC - "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO) - "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD) - "socionext,uniphier-ld20-sd-reset" - for LD20 SoC - "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC -- #reset-cells: should be 1. - -Example: - - mioctrl@59810000 { - compatible = "socionext,uniphier-ld11-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Peripheral reset ----------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-peri-reset" - for LD4 SoC - "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC - "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC - "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC - "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-peri-reset" - for LD11 SoC - "socionext,uniphier-ld20-peri-reset" - for LD20 SoC - "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC -- #reset-cells: should be 1. - -Example: - - perictrl@59820000 { - compatible = "socionext,uniphier-ld11-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Analog signal amplifier reset ------------------------------ - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC - "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC -- #reset-cells: should be 1. - -Example: - - adamv@57920000 { - compatible = "socionext,uniphier-ld11-adamv", - "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - adamv_rst: reset { - compatible = "socionext,uniphier-ld11-adamv-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Peripheral core reset in glue layer ------------------------------------ - -Some peripheral core reset belongs to its own glue layer. Before using -this core reset, it is necessary to control the clocks and resets to enable -this layer. These clocks and resets should be described in each property. - -Required properties: -- compatible: Should be - "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3 - "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3 - "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3 - "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3 - "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3 - "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI - "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI - "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI -- #reset-cells: Should be 1. -- reg: Specifies offset and length of the register set for the device. -- clocks: A list of phandles to the clock gate for the glue layer. - According to the clock-names, appropriate clocks are required. -- clock-names: Should contain - "gio", "link" - for Pro4 and Pro5 SoCs - "link" - for others -- resets: A list of phandles to the reset control for the glue layer. - According to the reset-names, appropriate resets are required. -- reset-names: Should contain - "gio", "link" - for Pro4 and Pro5 SoCs - "link" - for others - -Example: - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_rst: reset@0 { - compatible = "socionext,uniphier-ld20-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - regulator { - ... - }; - - phy { - ... - }; - ... - }; diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt deleted file mode 100644 index 27a45fe5ecf1..000000000000 --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt +++ /dev/null @@ -1,52 +0,0 @@ --------------------------------------------------------------------------- - = Zynq UltraScale+ MPSoC reset driver binding = --------------------------------------------------------------------------- -The Zynq UltraScale+ MPSoC has several different resets. - -See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information -about zynqmp resets. - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required Properties: -- compatible: "xlnx,zynqmp-reset" -- #reset-cells: Specifies the number of cells needed to encode reset - line, should be 1 - -------- -Example -------- - -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - - zynqmp_reset: reset-controller { - compatible = "xlnx,zynqmp-reset"; - #reset-cells = <1>; - }; - }; -}; - -Specifying reset lines connected to IP modules -============================================== - -Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -For list of all valid reset indicies see -<dt-bindings/reset/xlnx-zynqmp-resets.h> - -Example: - -serdes: zynqmp_phy@fd400000 { - ... - - resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - reset-names = "sata_rst"; - - ... -}; diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml new file mode 100644 index 000000000000..49db66801429 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq UltraScale+ MPSoC and Versal reset + +maintainers: + - Piyush Mehta <piyush.mehta@amd.com> + +description: | + The Zynq UltraScale+ MPSoC and Versal has several different resets. + + The PS reset subsystem is responsible for handling the external reset + input to the device and that all internal reset requirements are met + for the system (as a whole) and for the functional units. + + Please also refer to reset.txt in this directory for common reset + controller binding usage. Device nodes that need access to reset + lines should specify them as a reset phandle in their corresponding + node as specified in reset.txt. + + For list of all valid reset indices for Zynq UltraScale+ MPSoC + <dt-bindings/reset/xlnx-zynqmp-resets.h> + + For list of all valid reset indices for Versal + <dt-bindings/reset/xlnx-versal-resets.h> + +properties: + compatible: + enum: + - xlnx,zynqmp-reset + - xlnx,versal-reset + - xlnx,versal-net-reset + + "#reset-cells": + const: 1 + +required: + - compatible + - "#reset-cells" + +additionalProperties: false + +examples: + - | + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt deleted file mode 100644 index b015508f9780..000000000000 --- a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt +++ /dev/null @@ -1,20 +0,0 @@ -ZTE zx2967 SoCs Reset Controller -======================================= - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: should be one of the following. - * zte,zx296718-reset -- reg: physical base address of the controller and length of memory mapped - region. -- #reset-cells: must be 1. - -example: - - reset: reset-controller@1461060 { - compatible = "zte,zx296718-reset"; - reg = <0x01461060 0x8>; - #reset-cells = <1>; - }; |