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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SPI (Serial Peripheral Interface) controller
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ enum:
+ - fsl,spi
+ - aeroflexgaisler,spictrl
+
+ reg:
+ maxItems: 1
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
+
+ mode:
+ description: SPI operation mode
+ enum:
+ - cpu
+ - cpu-qe
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ description: input clock frequency to non FSL_SOC cores
+
+ cs-gpios: true
+
+ fsl,spisel_boot:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used
+ as chip select for a slave device. Use reg = <number of gpios> in the
+ corresponding child node, i.e. 0 if the cs-gpios property is not present.
+
+required:
+ - compatible
+ - reg
+ - mode
+ - interrupts
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi@4c0 {
+ compatible = "fsl,spi";
+ reg = <0x4c0 0x40>;
+ cell-index = <0>;
+ interrupts = <82 0>;
+ mode = "cpu";
+ cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING // device reg=<0>
+ &gpio 19 IRQ_TYPE_EDGE_RISING>; // device reg=<1>
+ };
+
+...