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Diffstat (limited to 'Documentation/devicetree/bindings/timer/cdns,ttc.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/timer/cdns,ttc.yaml | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml new file mode 100644 index 000000000000..da342464d32e --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence TTC - Triple Timer Counter + +maintainers: + - Michal Simek <michal.simek@amd.com> + +properties: + compatible: + const: cdns,ttc + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + description: | + A list of 3 interrupts; one per timer channel. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + timer-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Bit width of the timer, necessary if not 16. + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + not: + required: + - "#pwm-cells" + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + compatible = "cdns,ttc"; + reg = <0xF8001000 0x1000>; + clocks = <&cpu_clk 3>; + timer-width = <32>; + }; + + - | + pwm: pwm@f8002000 { + compatible = "cdns,ttc"; + reg = <0xf8002000 0x1000>; + clocks = <&cpu_clk 3>; + timer-width = <32>; + #pwm-cells = <3>; + }; |