diff options
Diffstat (limited to 'Documentation')
18 files changed, 413 insertions, 23 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-i2c-devices-turris-omnia-mcu b/Documentation/ABI/testing/sysfs-bus-i2c-devices-turris-omnia-mcu new file mode 100644 index 000000000000..307a55f599cb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-i2c-devices-turris-omnia-mcu @@ -0,0 +1,113 @@ +What: /sys/bus/i2c/devices/<mcu_device>/board_revision +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains board revision number. + + Only available if board information is burned in the MCU (older + revisions have board information burned in the ATSHA204-A chip). + + Format: %u. + +What: /sys/bus/i2c/devices/<mcu_device>/first_mac_address +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains device first MAC address. Each Turris Omnia is + allocated 3 MAC addresses. The two additional addresses are + computed from the first one by incrementing it. + + Only available if board information is burned in the MCU (older + revisions have board information burned in the ATSHA204-A chip). + + Format: %pM. + +What: /sys/bus/i2c/devices/<mcu_device>/front_button_mode +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RW) The front button on the Turris Omnia router can be + configured either to change the intensity of all the LEDs on the + front panel, or to send the press event to the CPU as an + interrupt. + + This file switches between these two modes: + - "mcu" makes the button press event be handled by the MCU to + change the LEDs panel intensity. + - "cpu" makes the button press event be handled by the CPU. + + Format: %s. + +What: /sys/bus/i2c/devices/<mcu_device>/front_button_poweron +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RW) Newer versions of the microcontroller firmware of the + Turris Omnia router support powering off the router into true + low power mode. The router can be powered on by pressing the + front button. + + This file configures whether front button power on is enabled. + + This file is present only if the power off feature is supported + by the firmware. + + Format: %i. + +What: /sys/bus/i2c/devices/<mcu_device>/fw_features +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Newer versions of the microcontroller firmware report the + features they support. These can be read from this file. If the + MCU firmware is too old, this file reads 0x0. + + Format: 0x%x. + +What: /sys/bus/i2c/devices/<mcu_device>/fw_version_hash_application +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains the version hash (commit hash) of the application + part of the microcontroller firmware. + + Format: %s. + +What: /sys/bus/i2c/devices/<mcu_device>/fw_version_hash_bootloader +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains the version hash (commit hash) of the bootloader + part of the microcontroller firmware. + + Format: %s. + +What: /sys/bus/i2c/devices/<mcu_device>/mcu_type +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains the microcontroller type (STM32, GD32, MKL). + + Format: %s. + +What: /sys/bus/i2c/devices/<mcu_device>/reset_selector +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains the selected factory reset level, determined by + how long the rear reset button was held by the user during board + reset. + + Format: %i. + +What: /sys/bus/i2c/devices/<mcu_device>/serial_number +Date: September 2024 +KernelVersion: 6.11 +Contact: Marek Behún <kabel@kernel.org> +Description: (RO) Contains the 64-bit board serial number in hexadecimal + format. + + Only available if board information is burned in the MCU (older + revisions have board information burned in the ATSHA204-A chip). + + Format: %016X. diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml index 7f06b1080244..25a2b42105e5 100644 --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml @@ -20,7 +20,7 @@ description: | initialized early into boot process and provides services to Operating Systems on multiple processors including ones running Linux. - See http://processors.wiki.ti.com/index.php/TISCI for protocol definition. + See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition. The TI-SCI node describes the Texas Instrument's System Controller entity node. This parent node may optionally have additional children nodes which describe diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index b9a9f2cf32a1..68ea5f70b75f 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,qdu1000-llcc + - qcom,sa8775p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -84,6 +85,33 @@ allOf: compatible: contains: enum: + - qcom,sa8775p-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: - qcom,sc7280-llcc then: properties: @@ -141,8 +169,31 @@ allOf: - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: - qcom,sm8450-llcc - qcom,sm8550-llcc + - qcom,sm8650-llcc then: properties: reg: @@ -151,7 +202,8 @@ allOf: - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - - description: LLCC broadcast base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region reg-names: items: - const: llcc0_base @@ -159,6 +211,7 @@ allOf: - const: llcc2_base - const: llcc3_base - const: llcc_broadcast_base + - const: llcc_broadcast_and_base additionalProperties: false diff --git a/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml new file mode 100644 index 000000000000..6d61098e388b --- /dev/null +++ b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive StarLink Cache Controller + +maintainers: + - Joshua Yeong <joshua.yeong@starfivetech.com> + +description: + StarFive's StarLink Cache Controller manages the L3 cache shared between + clusters of CPU cores. The cache driver enables RISC-V non-standard cache + management as an alternative to instructions in the RISC-V Zicbom extension. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +# We need a select here so we don't match all nodes with 'cache' +select: + properties: + compatible: + contains: + enum: + - starfive,jh8100-starlink-cache + + required: + - compatible + +properties: + compatible: + items: + - const: starfive,jh8100-starlink-cache + - const: cache + + reg: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + cache-controller@15000000 { + compatible = "starfive,jh8100-starlink-cache", "cache"; + reg = <0x0 0x15000000 0x0 0x278>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml index 0a9d6a4c4b66..66e8e66ca175 100644 --- a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml +++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml @@ -36,7 +36,7 @@ properties: The second cell should contain the clock ID. - Please see http://processors.wiki.ti.com/index.php/TISCI for + Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. additionalProperties: false diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 7de2c29606e5..308af58180d1 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -72,14 +72,17 @@ properties: - const: tx - const: tx_reply - const: rx + - const: rx_reply minItems: 2 mboxes: description: List of phandle and mailbox channel specifiers. It should contain - exactly one, two or three mailboxes; the first one or two for transmitting - messages ("tx") and another optional ("rx") for receiving notifications - and delayed responses, if supported by the platform. + exactly one, two, three or four mailboxes; the first one or two for + transmitting messages ("tx") and another optional ("rx") for receiving + notifications and delayed responses, if supported by the platform. + The optional ("rx_reply") is for notifications completion interrupt, + if supported by the platform. The number of mailboxes needed for transmitting messages depends on the type of channels exposed by the specific underlying mailbox controller; one single channel descriptor is enough if such channel is bidirectional, @@ -92,9 +95,10 @@ properties: 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels + 4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels Any other combination of mboxes and shmem is invalid. minItems: 1 - maxItems: 3 + maxItems: 4 shmem: description: diff --git a/Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml b/Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml new file mode 100644 index 000000000000..af9249695ef5 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CZ.NIC's Turris Omnia MCU + +maintainers: + - Marek Behún <kabel@kernel.org> + +description: + The MCU on Turris Omnia acts as a system controller providing additional + GPIOs, interrupts, watchdog, system power off and wakeup configuration. + +properties: + compatible: + const: cznic,turris-omnia-mcu + + reg: + description: MCU I2C slave address + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: | + The first cell specifies the interrupt number (0 to 63), the second cell + specifies interrupt type (which can be one of IRQ_TYPE_EDGE_RISING, + IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH). + The interrupt numbers correspond sequentially to GPIO numbers, taking the + GPIO banks into account: + IRQ number GPIO bank GPIO pin within bank + 0 - 15 0 0 - 15 + 16 - 47 1 0 - 31 + 48 - 63 2 0 - 15 + There are several exceptions: + IRQ number meaning + 11 LED panel brightness changed by button press + 13 TRNG entropy ready + 14 ECDSA message signature computation done + + gpio-controller: true + + '#gpio-cells': + const: 3 + description: + The first cell is bank number (0, 1 or 2), the second cell is pin number + within the bank (0 to 15 for banks 0 and 2, 0 to 31 for bank 1), and the + third cell specifies consumer flags. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - gpio-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + system-controller@2a { + compatible = "cznic,turris-omnia-mcu"; + reg = <0x2a>; + + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_NONE>; + + gpio-controller; + #gpio-cells = <3>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 47d3d2d52acd..2cc83771d8e7 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -93,6 +93,11 @@ properties: protocol to handle sleeping SCM calls. maxItems: 1 + memory-region: + description: + Phandle to the memory region reserved for the shared memory bridge to TZ. + maxItems: 1 + qcom,sdi-enabled: description: Indicates that the SDI (Secure Debug Image) has been enabled by TZ @@ -193,6 +198,16 @@ allOf: then: properties: interrupts: false + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,scm-sa8775p + then: + properties: + memory-region: false required: - compatible diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 05067e197abe..2cd1f5590fd9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -35,6 +35,7 @@ properties: - qcom,sm8250-cpu-bwmon - qcom,sm8550-cpu-bwmon - qcom,sm8650-cpu-bwmon + - qcom,x1e80100-cpu-bwmon - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: @@ -44,6 +45,7 @@ properties: - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon - qcom,sm8650-llcc-bwmon + - qcom,x1e80100-llcc-bwmon - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 @@ -72,7 +74,6 @@ required: - interconnects - interrupts - operating-points-v2 - - opp-table - reg additionalProperties: false diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml index 3be1db30bf41..d1c3421bee10 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: FSL/NXP Integrated Flash Controller maintainers: - - Li Yang <leoyang.li@nxp.com> + - Shawn Guo <shawnguo@kernel.org> description: | NXP's integrated flash controller (IFC) is an advanced version of the diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index 03c18611e42d..b0b20af15313 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -42,6 +42,12 @@ properties: 0 = Port 1 Phy reset 1 = Port 2 Phy reset + regulator-vbus: + type: object + description: USB VBUS regulator + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -49,6 +55,7 @@ required: - resets - power-domains - '#reset-cells' + - regulator-vbus additionalProperties: false @@ -64,4 +71,7 @@ examples: resets = <&cpg R9A07G044_USB_PRESETN>; power-domains = <&cpg>; #reset-cells = <1>; + regulator-vbus { + regulator-name = "vbus"; + }; }; diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml index e10eb98eddad..1db08ce9ae27 100644 --- a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml +++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml @@ -37,7 +37,7 @@ properties: The second cell should contain the reset mask corresponding to the device used by system controller. - Please see http://processors.wiki.ti.com/index.php/TISCI for + Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index b4478f417edc..7afdb60edb22 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -31,6 +31,7 @@ properties: - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp - qcom,sc8280xp-aoss-qmp + - qcom,sdx75-aoss-qmp - qcom,sdm845-aoss-qmp - qcom,sm6350-aoss-qmp - qcom,sm8150-aoss-qmp diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml index 58500529b90f..141d666dc3f7 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml @@ -41,6 +41,7 @@ properties: description: Three entries specifying the outgoing ipc bit used for signaling the remote end of the smp2p edge. + deprecated: true qcom,local-pid: $ref: /schemas/types.yaml#/definitions/uint32 @@ -128,7 +129,7 @@ examples: compatible = "qcom,smp2p"; qcom,smem = <431>, <451>; interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml index db67cf043256..4900215f26af 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml @@ -33,6 +33,14 @@ properties: specifier of the column in the subscription matrix representing the local processor. + mboxes: + minItems: 1 + maxItems: 5 + description: + Reference to the mailbox representing the outgoing doorbell in APCS for + this client. Each entry represents the N:th remote processor by index + (0-indexed). + '#size-cells': const: 0 @@ -47,6 +55,7 @@ patternProperties: description: Three entries specifying the outgoing ipc bit used for signaling the N:th remote processor. + deprecated: true "@[0-9a-f]$": type: object @@ -98,15 +107,18 @@ required: - '#address-cells' - '#size-cells' -anyOf: - - required: - - qcom,ipc-1 - - required: - - qcom,ipc-2 - - required: - - qcom,ipc-3 +oneOf: - required: - - qcom,ipc-4 + - mboxes + - anyOf: + - required: + - qcom,ipc-1 + - required: + - qcom,ipc-2 + - required: + - qcom,ipc-3 + - required: + - qcom,ipc-4 additionalProperties: false @@ -122,7 +134,7 @@ examples: compatible = "qcom,smsm"; #address-cells = <1>; #size-cells = <0>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <0>, <0>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml index a750035d6234..b6da72032151 100644 --- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml +++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml @@ -40,7 +40,7 @@ properties: TI_SCI_PD_SHARED - Allows the device to be shared by multiple hosts. Please refer to dt-bindings/soc/ti,sci_pm_domain.h for the definitions. - Please see http://processors.wiki.ti.com/index.php/TISCI for + Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index e6289fbe6907..378e9cc5fac2 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -2,7 +2,7 @@ # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ %YAML 1.2 --- -$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml# +$id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI J721e System Controller Registers R/W @@ -19,7 +19,7 @@ description: | and access the registers directly. maintainers: - - Kishon Vijay Abraham I <kishon@ti.com> + - Kishon Vijay Abraham I <kishon@kernel.org> - Roger Quadros <rogerq@kernel.org> properties: diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index cf07b8f787a6..d9322704f358 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -56,6 +56,9 @@ properties: ranges: true patternProperties: + "^regulators@[0-9a-f]+$": + $ref: /schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml# + "^sram@[a-f0-9]+": $ref: /schemas/sram/sram.yaml# unevaluatedProperties: false @@ -130,3 +133,28 @@ examples: }; }; }; + + - | + syscon@3000000 { + compatible = "allwinner,sun20i-d1-system-control"; + reg = <0x3000000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + regulators@3000150 { + compatible = "allwinner,sun20i-d1-system-ldos"; + reg = <0x3000150 0x4>; + + reg_ldoa: ldoa { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_ldob: ldob { + regulator-name = "vcc-dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + }; + }; |