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-rw-r--r--Documentation/devicetree/bindings/arm/arm,scpi.txt34
-rw-r--r--Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt45
-rw-r--r--Documentation/devicetree/bindings/clock/clps711x-clock.txt4
-rw-r--r--Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt4
-rw-r--r--Documentation/devicetree/bindings/input/clps711x-keypad.txt4
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt4
-rw-r--r--Documentation/devicetree/bindings/media/nokia,n900-ir20
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt136
-rw-r--r--Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt5
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt4
-rw-r--r--Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt18
-rw-r--r--Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt4
-rw-r--r--Documentation/devicetree/bindings/reset/ti-syscon-reset.txt91
-rw-r--r--Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt4
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt4
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt4
-rw-r--r--Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt6
-rw-r--r--Documentation/driver-model/devres.txt4
18 files changed, 374 insertions, 21 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt
index 313dabdc14f9..faa4b44572e3 100644
--- a/Documentation/devicetree/bindings/arm/arm,scpi.txt
+++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt
@@ -87,10 +87,33 @@ Required properties:
implementation for the IDs to use. For Juno
R0 and Juno R1 refer to [3].
+Power domain bindings for the power domains based on SCPI Message Protocol
+------------------------------------------------------------
+
+This binding uses the generic power domain binding[4].
+
+PM domain providers
+===================
+
+Required properties:
+ - #power-domain-cells : Should be 1. Contains the device or the power
+ domain ID value used by SCPI commands.
+ - num-domains: Total number of power domains provided by SCPI. This is
+ needed as the SCPI message protocol lacks a mechanism to
+ query this information at runtime.
+
+PM domain consumers
+===================
+
+Required properties:
+ - power-domains : A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle.
+
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/thermal/thermal.txt
[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
+[4] Documentation/devicetree/bindings/power/power_domain.txt
Example:
@@ -144,6 +167,12 @@ scpi_protocol: scpi@2e000000 {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
+
+ scpi_devpd: scpi-power-domains {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
};
cpu@0 {
@@ -156,6 +185,7 @@ hdlcd@7ff60000 {
...
reg = <0 0x7ff60000 0 0x1000>;
clocks = <&scpi_clk 4>;
+ power-domains = <&scpi_devpd 1>;
};
thermal-zones {
@@ -186,3 +216,7 @@ The thermal-sensors property in the soc_thermal node uses the
temperature sensor provided by SCP firmware to setup a thermal
zone. The ID "3" is the sensor identifier for the temperature sensor
as used by the firmware.
+
+The num-domains property in scpi-power-domains domain specifies that
+SCPI provides 2 power domains. The hdlcd node uses the power domain with
+domain ID 1.
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
new file mode 100644
index 000000000000..7ff13be1750b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
@@ -0,0 +1,45 @@
+NVIDIA Tegra ACONNECT Bus
+
+The Tegra ACONNECT bus is an AXI switch which is used to connnect various
+components inside the Audio Processing Engine (APE). All CPU accesses to
+the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
+
+Required properties:
+- compatible: Must be "nvidia,tegra210-aconnect".
+- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
+ and APE interface clock (TEGRA210_CLK_APB2APE).
+- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
+ 'clocks' entries.
+- power-domains: Must contain a phandle that points to the audio powergate
+ (namely 'aud') for Tegra210.
+- #address-cells: The number of cells used to represent physical base addresses
+ in the aconnect address space. Should be 1.
+- #size-cells: The number of cells used to represent the size of an address
+ range in the aconnect address space. Should be 1.
+- ranges: Mapping of the aconnect address space to the CPU address space.
+
+All devices accessed via the ACONNNECT are described by child-nodes.
+
+Example:
+
+ aconnect@702c0000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&tegra_car TEGRA210_CLK_APE>,
+ <&tegra_car TEGRA210_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&pd_audio>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
+
+ status = "disabled";
+
+ child1 {
+ ...
+ };
+
+ child2 {
+ ...
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/clps711x-clock.txt b/Documentation/devicetree/bindings/clock/clps711x-clock.txt
index ce5a7476f05d..f1bd53f79d91 100644
--- a/Documentation/devicetree/bindings/clock/clps711x-clock.txt
+++ b/Documentation/devicetree/bindings/clock/clps711x-clock.txt
@@ -1,7 +1,7 @@
* Clock bindings for the Cirrus Logic CLPS711X CPUs
Required properties:
-- compatible : Shall contain "cirrus,clps711x-clk".
+- compatible : Shall contain "cirrus,ep7209-clk".
- reg : Address of the internal register set.
- startup-frequency: Factory set CPU startup frequency in HZ.
- #clock-cells : Should be <1>.
@@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs.
Example:
clks: clks@80000000 {
#clock-cells = <1>;
- compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
+ compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
reg = <0x80000000 0xc000>;
startup-frequency = <73728000>;
};
diff --git a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt
index d685be898d0c..e9c65746e2f1 100644
--- a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt
+++ b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt
@@ -1,7 +1,7 @@
* Currus Logic CLPS711X Framebuffer
Required properties:
-- compatible: Shall contain "cirrus,clps711x-fb".
+- compatible: Shall contain "cirrus,ep7209-fb".
- reg : Physical base address and length of the controller's registers +
location and size of the framebuffer memory.
- clocks : phandle + clock specifier pair of the FB reference clock.
@@ -18,7 +18,7 @@ Optional properties:
Example:
fb: fb@800002c0 {
- compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb";
+ compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
clocks = <&clks 2>;
lcd-supply = <&reg5v0>;
diff --git a/Documentation/devicetree/bindings/input/clps711x-keypad.txt b/Documentation/devicetree/bindings/input/clps711x-keypad.txt
index e68d2bbc6c07..3eed8819d05d 100644
--- a/Documentation/devicetree/bindings/input/clps711x-keypad.txt
+++ b/Documentation/devicetree/bindings/input/clps711x-keypad.txt
@@ -1,7 +1,7 @@
* Cirrus Logic CLPS711X matrix keypad device tree bindings
Required Properties:
-- compatible: Shall contain "cirrus,clps711x-keypad".
+- compatible: Shall contain "cirrus,ep7209-keypad".
- row-gpios: List of GPIOs used as row lines.
- poll-interval: Poll interval time in milliseconds.
- linux,keymap: The definition can be found at
@@ -12,7 +12,7 @@ Optional Properties:
Example:
keypad {
- compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad";
+ compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad";
autorepeat;
poll-interval = <120>;
row-gpios = <&porta 0 0>,
diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt
index 759339c34e4f..969b4582ec60 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt
@@ -2,7 +2,7 @@ Cirrus Logic CLPS711X Interrupt Controller
Required properties:
-- compatible: Should be "cirrus,clps711x-intc".
+- compatible: Should be "cirrus,ep7209-intc".
- reg: Specifies base physical address of the registers set.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
@@ -34,7 +34,7 @@ ID Name Description
Example:
intc: interrupt-controller {
- compatible = "cirrus,clps711x-intc";
+ compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
reg = <0x80000000 0x4000>;
interrupt-controller;
#interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/media/nokia,n900-ir b/Documentation/devicetree/bindings/media/nokia,n900-ir
new file mode 100644
index 000000000000..13a18ce37dd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nokia,n900-ir
@@ -0,0 +1,20 @@
+Device-Tree bindings for LIRC TX driver for Nokia N900(RX51)
+
+Required properties:
+ - compatible: should be "nokia,n900-ir".
+ - pwms: specifies PWM used for IR signal transmission.
+
+Example node:
+
+ pwm9: dmtimer-pwm@9 {
+ compatible = "ti,omap-dmtimer-pwm";
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x00>; /* timer_sys_ck */
+ #pwm-cells = <3>;
+ };
+
+ ir: n900-ir {
+ compatible = "nokia,n900-ir";
+
+ pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
+ };
diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt
new file mode 100644
index 000000000000..9bb5f57e2066
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt
@@ -0,0 +1,136 @@
+* Device tree bindings for Atmel EBI
+
+The External Bus Interface (EBI) controller is a bus where you can connect
+asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
+The EBI provides a glue-less interface to asynchronous memories through the SMC
+(Static Memory Controller).
+
+Required properties:
+
+- compatible: "atmel,at91sam9260-ebi"
+ "atmel,at91sam9261-ebi"
+ "atmel,at91sam9263-ebi0"
+ "atmel,at91sam9263-ebi1"
+ "atmel,at91sam9rl-ebi"
+ "atmel,at91sam9g45-ebi"
+ "atmel,at91sam9x5-ebi"
+ "atmel,sama5d3-ebi"
+
+- reg: Contains offset/length value for EBI memory mapping.
+ This property might contain several entries if the EBI
+ memory range is not contiguous
+
+- #address-cells: Must be 2.
+ The first cell encodes the CS.
+ The second cell encode the offset into the CS memory
+ range.
+
+- #size-cells: Must be set to 1.
+
+- ranges: Encodes CS to memory region association.
+
+- clocks: Clock feeding the EBI controller.
+ See clock-bindings.txt
+
+Children device nodes are representing device connected to the EBI bus.
+
+Required device node properties:
+
+- reg: Contains the chip-select id, the offset and the length
+ of the memory region requested by the device.
+
+EBI bus configuration will be defined directly in the device subnode.
+
+Optional EBI/SMC properties:
+
+- atmel,smc-bus-width: width of the asynchronous device's data bus
+ 8, 16 or 32.
+ Default to 8 when undefined.
+
+- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet).
+ Default to "select" when undefined.
+
+- atmel,smc-read-mode "nrd" or "ncs".
+ Default to "ncs" when undefined.
+
+- atmel,smc-write-mode "nwe" or "ncs".
+ Default to "ncs" when undefined.
+
+- atmel,smc-exnw-mode "disabled", "frozen" or "ready".
+ Default to "disabled" when undefined.
+
+- atmel,smc-page-mode enable page mode if present. The provided value
+ defines the page size (supported values: 4, 8,
+ 16 and 32).
+
+- atmel,smc-tdf-mode: "normal" or "optimized". When set to
+ "optimized" the data float time is optimized
+ depending on the next device being accessed
+ (next device setup time is subtracted to the
+ current device data float time).
+ Default to "normal" when undefined.
+
+If at least one atmel,smc- property is defined the following SMC timing
+properties become mandatory. In the other hand, if none of the atmel,smc-
+properties are specified, we assume that the EBI bus configuration will be
+handled by the sub-device driver, and none of those properties should be
+defined.
+
+All the timings are expressed in nanoseconds (see Atmel datasheet for a full
+description).
+
+- atmel,smc-ncs-rd-setup-ns
+- atmel,smc-nrd-setup-ns
+- atmel,smc-ncs-wr-setup-ns
+- atmel,smc-nwe-setup-ns
+- atmel,smc-ncs-rd-pulse-ns
+- atmel,smc-nrd-pulse-ns
+- atmel,smc-ncs-wr-pulse-ns
+- atmel,smc-nwe-pulse-ns
+- atmel,smc-nwe-cycle-ns
+- atmel,smc-nrd-cycle-ns
+- atmel,smc-tdf-ns
+
+Example:
+
+ ebi: ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&hsmc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x10000000
+ 0x40000000 0x30000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x40000000 0x10000000
+ 0x2 0x0 0x50000000 0x10000000
+ 0x3 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr>;
+
+ nor: flash@0,0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+
+ atmel,smc-read-mode = "nrd";
+ atmel,smc-write-mode = "nwe";
+ atmel,smc-bus-width = <16>;
+ atmel,smc-ncs-rd-setup-ns = <0>;
+ atmel,smc-ncs-wr-setup-ns = <0>;
+ atmel,smc-nwe-setup-ns = <8>;
+ atmel,smc-nrd-setup-ns = <16>;
+ atmel,smc-ncs-rd-pulse-ns = <84>;
+ atmel,smc-ncs-wr-pulse-ns = <84>;
+ atmel,smc-nrd-pulse-ns = <76>;
+ atmel,smc-nwe-pulse-ns = <76>;
+ atmel,smc-nrd-cycle-ns = <107>;
+ atmel,smc-nwe-cycle-ns = <84>;
+ atmel,smc-tdf-ns = <16>;
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt
index a183db48f910..c0b2028238d6 100644
--- a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt
@@ -1,15 +1,14 @@
* Cirris Logic CLPS711X PWM controller
Required properties:
-- compatible: Shall contain "cirrus,clps711x-pwm".
+- compatible: Shall contain "cirrus,ep7209-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks: phandle + clock specifier pair of the PWM reference clock.
- #pwm-cells: Should be 1. The cell specifies the index of the channel.
Example:
pwm: pwm@80000400 {
- compatible = "cirrus,ep7312-pwm",
- "cirrus,clps711x-pwm";
+ compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
reg = <0x80000400 0x4>;
clocks = <&clks 8>;
#pwm-cells = <1>;
diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
index 5befb538db95..2e53324fb720 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
@@ -9,6 +9,10 @@ Required properties:
Optional properties:
- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
+- ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
+ - 0x00 - high-frequency system clock (timer_sys_ck)
+ - 0x01 - 32-kHz always-on clock (timer_32k_ck)
+ - 0x02 - external clock (timer_ext_ck, OMAP2 only)
Example:
pwm9: dmtimer-pwm@9 {
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
new file mode 100644
index 000000000000..e746b631793a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
@@ -0,0 +1,18 @@
+Amlogic Meson SoC Reset Controller
+=======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset"
+- reg: should contain the register address base
+- #reset-cells: 1, see below
+
+example:
+
+reset: reset-controller {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x04404 0x0 0x20>;
+ #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
index e0b185a944ba..c25da39df707 100644
--- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -8,7 +8,9 @@ The reset controller registers are part of the system-ctl block on
hi6220 SoC.
Required properties:
-- compatible: may be "hisilicon,hi6220-sysctrl"
+- compatible: should be one of the following:
+ - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
+ - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
new file mode 100644
index 000000000000..164c7f34c451
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -0,0 +1,91 @@
+TI SysCon Reset Controller
+=======================
+
+Almost all SoCs have hardware modules that require reset control in addition
+to clock and power control for their functionality. The reset control is
+typically provided by means of memory-mapped I/O registers. These registers are
+sometimes a part of a larger register space region implementing various
+functionalities. This register range is best represented as a syscon node to
+allow multiple entities to access their relevant registers in the common
+register space.
+
+A SysCon Reset Controller node defines a device that uses a syscon node
+and provides reset management functionality for various hardware modules
+present on the SoC.
+
+SysCon Reset Controller Node
+============================
+Each of the reset provider/controller nodes should be a child of a syscon
+node and have the following properties.
+
+Required properties:
+--------------------
+ - compatible : Should be,
+ "ti,k2e-pscrst"
+ "ti,k2l-pscrst"
+ "ti,k2hk-pscrst"
+ "ti,syscon-reset"
+ - #reset-cells : Should be 1. Please see the reset consumer node below
+ for usage details
+ - ti,reset-bits : Contains the reset control register information
+ Should contain 7 cells for each reset exposed to
+ consumers, defined as:
+ Cell #1 : offset of the reset assert control
+ register from the syscon register base
+ Cell #2 : bit position of the reset in the reset
+ assert control register
+ Cell #3 : offset of the reset deassert control
+ register from the syscon register base
+ Cell #4 : bit position of the reset in the reset
+ deassert control register
+ Cell #5 : offset of the reset status register
+ from the syscon register base
+ Cell #6 : bit position of the reset in the
+ reset status register
+ Cell #7 : Flags used to control reset behavior,
+ availible flags defined in the DT include
+ file <dt-bindings/reset/ti-syscon.h>
+
+SysCon Reset Consumer Nodes
+===========================
+Each of the reset consumer nodes should have the following properties,
+in addition to their own properties.
+
+Required properties:
+--------------------
+ - resets : A phandle to the reset controller node and an index number
+ to a reset specifier as defined above.
+
+Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
+common reset controller usage by consumers.
+
+Example:
+--------
+The following example demonstrates a syscon node, the reset controller node
+using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
+Edison SoC.
+
+/ {
+ soc {
+ psc: power-sleep-controller@02350000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x02350000 0x1000>;
+
+ pscrst: psc-reset {
+ compatible = "ti,k2e-pscrst", "ti,syscon-reset";
+ #reset-cells = <1>;
+
+ ti,reset-bits = <
+ 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */
+ 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */
+ >;
+ };
+ };
+
+ dsp0: dsp0 {
+ ...
+ resets = <&pscrst 0>;
+ ...
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt
index caaeb2583579..07013fa60a48 100644
--- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt
+++ b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt
@@ -1,7 +1,7 @@
* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
Required properties:
-- compatible: Should be "cirrus,clps711x-uart".
+- compatible: Should be "cirrus,ep7209-uart".
- reg: Address and length of the register set for the device.
- interrupts: Should contain UART TX and RX interrupt.
- clocks: Should contain UART core clock number.
@@ -20,7 +20,7 @@ Example:
};
uart1: uart@80000480 {
- compatible = "cirrus,clps711x-uart";
+ compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
reg = <0x80000480 0x80>;
interrupts = <12 13>;
clocks = <&clks 11>;
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt
index 5cc82b8353d8..af9ca37221ce 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt
@@ -68,7 +68,7 @@ important.
Value type: <u32>
Definition: must be 2 - denoting the bit in the entry and IRQ flags
-- #qcom,state-cells:
+- #qcom,smem-state-cells:
Usage: required for outgoing entries
Value type: <u32>
Definition: must be 1 - denoting the bit in the entry
@@ -92,7 +92,7 @@ wcnss-smp2p {
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
- #qcom,state-cells = <1>;
+ #qcom,smem-state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
index a6634c70850d..2993b5a97dd6 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
@@ -51,7 +51,7 @@ important.
Definition: specifies the offset, in words, of the first bit for this
entry
-- #qcom,state-cells:
+- #qcom,smem-state-cells:
Usage: required for local entry
Value type: <u32>
Definition: must be 1 - denotes bit number
@@ -91,7 +91,7 @@ smsm {
apps_smsm: apps@0 {
reg = <0>;
- #qcom,state-cells = <1>;
+ #qcom,smem-state-cells = <1>;
};
wcnss_smsm: wcnss@7 {
diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt
index cd55b52548e4..d4c62e7b1714 100644
--- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt
+++ b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt
@@ -1,7 +1,7 @@
* Cirrus Logic CLPS711X Timer Counter
Required properties:
-- compatible: Shall contain "cirrus,clps711x-timer".
+- compatible: Shall contain "cirrus,ep7209-timer".
- reg : Address and length of the register set.
- interrupts: The interrupt number of the timer.
- clocks : phandle of timer reference clock.
@@ -15,14 +15,14 @@ Example:
};
timer1: timer@80000300 {
- compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer";
+ compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
reg = <0x80000300 0x4>;
interrupts = <8>;
clocks = <&clks 5>;
};
timer2: timer@80000340 {
- compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer";
+ compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
reg = <0x80000340 0x4>;
interrupts = <9>;
clocks = <&clks 6>;
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 589296bdc133..b0d775d28e97 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -352,6 +352,10 @@ REGULATOR
devm_regulator_put()
devm_regulator_register()
+RESET
+ devm_reset_control_get()
+ devm_reset_controller_register()
+
SLAVE DMA ENGINE
devm_acpi_dma_controller_register()