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Diffstat (limited to 'Documentation')
20 files changed, 968 insertions, 623 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt deleted file mode 100644 index cb12f33a247f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ /dev/null @@ -1,300 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -== Power Management Controller Node == - -The PMC block interacts with an external Power Management Unit. The PMC -mostly controls the entry and exit of the system from different sleep -modes. It provides power-gating controllers for SoC and CPU power-islands. - -Required properties: -- name : Should be pmc -- compatible : Should contain one of the following: - For Tegra20 must contain "nvidia,tegra20-pmc". - For Tegra30 must contain "nvidia,tegra30-pmc". - For Tegra114 must contain "nvidia,tegra114-pmc" - For Tegra124 must contain "nvidia,tegra124-pmc" - For Tegra132 must contain "nvidia,tegra124-pmc" - For Tegra210 must contain "nvidia,tegra210-pmc" -- reg : Offset and length of the register set for the device -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - "pclk" (The Tegra clock of that name), - "clk32k_in" (The 32KHz clock input to Tegra). - -Optional properties: -- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and then - fed into the ARM GIC. The PMC is not involved in the detection or - handling of this interrupt signal, merely its inversion. -- nvidia,suspend-mode : The suspend mode that the platform should use. - Valid values are 0, 1 and 2: - 0 (LP0): CPU + Core voltage off and DRAM in self-refresh - 1 (LP1): CPU voltage off and DRAM in self-refresh - 2 (LP2): CPU voltage off -- nvidia,core-power-req-active-high : Boolean, core power request active-high -- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high -- nvidia,combined-power-req : Boolean, combined power request for CPU & Core -- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) - is enabled. - -Required properties when nvidia,suspend-mode is specified: -- nvidia,cpu-pwr-good-time : CPU power good time in uS. -- nvidia,cpu-pwr-off-time : CPU power off time in uS. -- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time> - Core power good time in uS. -- nvidia,core-pwr-off-time : Core power off time in uS. - -Required properties when nvidia,suspend-mode=<0>: -- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector - The LP0 vector contains the warm boot code that is executed by AVP when - resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 - processor and always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed from the deep - sleep mode, the warm boot code will restore some PLLs, clocks and then - bring up CPU0 for resuming the system. - -Hardware-triggered thermal reset: -On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists, -hardware-triggered thermal reset will be enabled. - -Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are - described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the - Tegra K1 Technical Reference Manual. -- nvidia,bus-addr : Bus address of the PMU on the I2C bus -- nvidia,reg-addr : I2C register address to write poweroff command to -- nvidia,reg-data : Poweroff command to write to PMU - -Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. - -Optional nodes: -- powergates : This node contains a hierarchy of power domain nodes, which - should match the powergates on the Tegra SoC. See "Powergate - Nodes" below. - -Example: - -/ SoC dts including file -pmc@7000f400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,lp0-vec = <0xbdffd000 0x2000>; -}; - -/ Tegra board dts file -{ - ... - pmc@7000f400 { - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - ... - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - ... -}; - - -== Powergate Nodes == - -Each of the powergate nodes represents a power-domain on the Tegra SoC -that can be power-gated by the Tegra PMC. The name of the powergate node -should be one of the below. Note that not every powergate is applicable -to all Tegra devices and the following list shows which powergates are -applicable to which devices. Please refer to the Tegra TRM for more -details on the various powergates. - - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 - -Required properties: - - clocks: Must contain an entry for each clock required by the PMC for - controlling a power-gate. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each reset required by the PMC for - controlling a power-gate. See ../reset/reset.txt for details. - - #power-domain-cells: Must be 0. - -Example: - - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - #power-domain-cells = <0>; - }; - }; - }; - - -== Powergate Clients == - -Hardware blocks belonging to a power domain should contain a "power-domains" -property that is a phandle pointing to the corresponding powergate node. - -Example: - - adma: adma@702e2000 { - ... - power-domains = <&pd_audio>; - ... - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -The pad configuration state nodes are placed under the pmc node and they -are referred to by the pinctrl client properties. For more information -see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. -The pad name should be used as the value of the pins property in pin -configuration nodes. - -The following pads are present on Tegra124 and Tegra132: -audio bb cam comp -csia csb cse dsi -dsib dsic dsid hdmi -hsic hv lvds mipi-bias -nand pex-bias pex-clk1 pex-clk2 -pex-cntrl sdmmc1 sdmmc3 sdmmc4 -sys_ddc uart usb0 usb1 -usb2 usb_bias - -The following pads are present on Tegra210: -audio audio-hv cam csia -csib csic csid csie -csif dbg debug-nonao dmic -dp dsi dsib dsic -dsid emmc emmc2 gpio -hdmi hsic lvds mipi-bias -pex-bias pex-clk1 pex-clk2 pex-cntrl -sdmmc1 sdmmc3 spi spi-hv -uart usb0 usb1 usb2 -usb3 usb-bias - -Required pin configuration properties: - - pins: Must contain name of the pad(s) to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 - or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the Tegra124 and - Tegra132 pads. None of the Tegra124 or Tegra132 pads support - signaling voltage switching. - -Note: All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported on - following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio, - pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@700b0000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - ... - sor@54540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml new file mode 100644 index 000000000000..f17bb353f65e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -0,0 +1,354 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra20-pmc + - nvidia,tegra20-pmc + - nvidia,tegra30-pmc + - nvidia,tegra114-pmc + - nvidia,tegra124-pmc + - nvidia,tegra210-pmc + + reg: + maxItems: 1 + description: + Offset and length of the register set for the device. + + clock-names: + items: + - const: pclk + - const: clk32k_in + description: + Must includes entries pclk and clk32k_in. + pclk is the Tegra clock of that name and clk32k_in is 32KHz clock + input to Tegra. + + clocks: + maxItems: 2 + description: + Must contain an entry for each entry in clock-names. + See ../clocks/clocks-bindings.txt for details. + + '#clock-cells': + const: 1 + description: + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. + PMC also has blink control which allows 32Khz clock output to + Tegra blink pad. + Consumer of PMC clock should specify the desired clock by having + the clock ID in its "clocks" phandle cell with pmc clock provider. + See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC + clock IDs. + + '#interrupt-cells': + const: 2 + description: + Specifies number of cells needed to encode an interrupt source. + The value must be 2. + + interrupt-controller: true + + nvidia,invert-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: Inverts the PMU interrupt signal. + The PMU is an external Power Management Unit, whose interrupt output + signal is fed into the PMC. This signal is optionally inverted, and + then fed into the ARM GIC. The PMC is not involved in the detection + or handling of this interrupt signal, merely its inversion. + + nvidia,core-power-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: Core power request active-high. + + nvidia,sys-clock-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: System clock request active-high. + + nvidia,combined-power-req: + $ref: /schemas/types.yaml#/definitions/flag + description: combined power request for CPU and Core. + + nvidia,cpu-pwr-good-en: + $ref: /schemas/types.yaml#/definitions/flag + description: + CPU power good signal from external PMIC to PMC is enabled. + + nvidia,suspend-mode: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2] + description: + The suspend mode that the platform should use. + Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh + Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh + Mode 2 is for LP2, CPU voltage off + + nvidia,cpu-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power good time in uSec. + + nvidia,cpu-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power off time in uSec. + + nvidia,core-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + <Oscillator-stable-time Power-stable-time> + Core power good time in uSec. + + nvidia,core-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Core power off time in uSec. + + nvidia,lp0-vec: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + <start length> Starting address and length of LP0 vector. + The LP0 vector contains the warm boot code that is executed + by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and + always being the first boot processor when chip is power on + or resume from deep sleep mode. When the system is resumed + from the deep sleep mode, the warm boot code will restore + some PLLs, clocks and then brings up CPU0 for resuming the + system. + + i2c-thermtrip: + type: object + description: + On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, + hardware-triggered thermal reset will be enabled. + + properties: + nvidia,i2c-controller-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 + "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference + Manual. + + nvidia,bus-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bus address of the PMU on the I2C bus. + + nvidia,reg-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PMU I2C register address to issue poweroff command. + + nvidia,reg-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Poweroff command to write to PMU. + + nvidia,pinmux-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pinmux used by the hardware when issuing Poweroff command. + Defaults to 0. Valid values are described in section 12.5.2 + "Pinmux Support" of the Tegra4 Technical Reference Manual. + + required: + - nvidia,i2c-controller-id + - nvidia,bus-addr + - nvidia,reg-addr + - nvidia,reg-data + + additionalProperties: false + + powergates: + type: object + description: | + This node contains a hierarchy of power domain nodes, which should + match the powergates on the Tegra SoC. Each powergate node + represents a power-domain on the Tegra SoC that can be power-gated + by the Tegra PMC. + Hardware blocks belonging to a power domain should contain + "power-domains" property that is a phandle pointing to corresponding + powergate node. + The name of the powergate node should be one of the below. Note that + not every powergate is applicable to all Tegra devices and the following + list shows which powergates are applicable to which devices. + Please refer to Tegra TRM for mode details on the powergate nodes to + use for each power-gate block inside Tegra. + Name Description Devices Applicable + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 + + patternProperties: + "^[a-z0-9]+$": + type: object + + patternProperties: + clocks: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each clock required by the PMC + for controlling a power-gate. + See ../clocks/clock-bindings.txt document for more details. + + resets: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each reset required by the PMC + for controlling a power-gate. + See ../reset/reset.txt for more details. + + '#power-domain-cells': + const: 0 + description: Must be 0. + + required: + - clocks + - resets + - '#power-domain-cells' + + additionalProperties: false + +patternProperties: + "^[a-f0-9]+-[a-f0-9]+$": + type: object + description: + This is a Pad configuration node. On Tegra SOCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power state + and signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages + are supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and they + are referred to by the pinctrl client properties. For more information + see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132 + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, + hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. + + The following pads are present on Tegra210 + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, + hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. + The values are defined in + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. + Power state can be configured on all Tegra124 and Tegra132 + pads. None of the Tegra124 or Tegra132 pads support signaling + voltage switching. + All of the listed Tegra210 pads except pex-cntrl support power + state configuration. Signaling voltage switching is supported + on below Tegra210 pads. + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, and uart. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - clock-names + - clocks + - '#clock-cells' + +dependencies: + "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] + "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] + "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] + +examples: + - | + + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> + #include <dt-bindings/soc/tegra-pmc.h> + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + #power-domain-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml new file mode 100644 index 000000000000..de9a465096db --- /dev/null +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM System Controller ICST Clocks + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: | + The ICS525 and ICS307 oscillators are produced by Integrated + Devices Technology (IDT). ARM integrated these oscillators deeply into their + reference designs by adding special control registers that manage such + oscillators to their system controllers. + + The various ARM system controllers contain logic to serialize and initialize + an ICST clock request after a write to the 32 bit register at an offset + into the system controller. Furthermore, to even be able to alter one of + these frequencies, the system controller must first be unlocked by + writing a special token to another offset in the system controller. + + Some ARM hardware contain special versions of the serial interface that only + connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to + different values and sometimes also hard-wires the output divider. They + therefore have special compatible strings as per this table (the OD value is + the value on the pins, not the resulting output divider). + + In the core modules and logic tiles, the ICST is a configurable clock fed + from a 24 MHz clock on the motherboard (usually the main crystal) used for + generating e.g. video clocks. It is located on the core module and there is + only one of these. This clock node must be a subnode of the core module. + + Hardware variant RDW OD VDW + + Integrator/AP 22 1 Bit 8 0, rest variable + integratorap-cm + + Integrator/AP 46 3 Bit 8 0, rest variable + integratorap-sys + + Integrator/AP 22 or 1 17 or (33 or 25 MHz) + integratorap-pci 14 1 14 + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-core + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-mem + + The ICST oscillator must be provided inside a system controller node. + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - arm,syscon-icst525 + - arm,syscon-icst307 + - arm,syscon-icst525-integratorap-cm + - arm,syscon-icst525-integratorap-sys + - arm,syscon-icst525-integratorap-pci + - arm,syscon-icst525-integratorcp-cm-core + - arm,syscon-icst525-integratorcp-cm-mem + - arm,integrator-cm-auxosc + - arm,versatile-cm-auxosc + - arm,impd-vco1 + - arm,impd-vco2 + + clocks: + description: Parent clock for the ICST VCO + maxItems: 1 + + clock-output-names: + maxItems: 1 + + lock-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the unlocking register for the oscillator + + vco-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the VCO register for the oscillator + +required: + - "#clock-cells" + - compatible + - clocks + +examples: + - | + vco1: clock@00 { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt deleted file mode 100644 index 11f5f95f571b..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ /dev/null @@ -1,34 +0,0 @@ -Clock bindings for ARM Integrator and Versatile Core Module clocks - -Auxiliary Oscillator Clock - -This is a configurable clock fed from a 24 MHz chrystal, -used for generating e.g. video clocks. It is located on the -core module and there is only one of these. - -This clock node *must* be a subnode of the core module, since -it obtains the base address for it's address range from its -parent node. - - -Required properties: -- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -Example: - -core-module@10000000 { - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - auxosc: cm_aux_osc@25M { - #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt deleted file mode 100644 index 4cd81742038f..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM System Controller ICST clocks - -The ICS525 and ICS307 oscillators are produced by Integrated Devices -Technology (IDT). ARM integrated these oscillators deeply into their -reference designs by adding special control registers that manage such -oscillators to their system controllers. - -The various ARM system controllers contain logic to serialize and initialize -an ICST clock request after a write to the 32 bit register at an offset -into the system controller. Furthermore, to even be able to alter one of -these frequencies, the system controller must first be unlocked by -writing a special token to another offset in the system controller. - -Some ARM hardware contain special versions of the serial interface that only -connects the low 8 bits of the VDW (missing one bit), hardwires RDW to -different values and sometimes also hardwire the output divider. They -therefore have special compatible strings as per this table (the OD value is -the value on the pins, not the resulting output divider): - -Hardware variant: RDW OD VDW - -Integrator/AP 22 1 Bit 8 0, rest variable -integratorap-cm - -Integrator/AP 46 3 Bit 8 0, rest variable -integratorap-sys - -Integrator/AP 22 or 1 17 or (33 or 25 MHz) -integratorap-pci 14 1 14 - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-core - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-mem - -The ICST oscillator must be provided inside a system controller node. - -Required properties: -- compatible: must be one of - "arm,syscon-icst525" - "arm,syscon-icst307" - "arm,syscon-icst525-integratorap-cm" - "arm,syscon-icst525-integratorap-sys" - "arm,syscon-icst525-integratorap-pci" - "arm,syscon-icst525-integratorcp-cm-core" - "arm,syscon-icst525-integratorcp-cm-mem" -- lock-offset: the offset address into the system controller where the - unlocking register is located -- vco-offset: the offset address into the system controller where the - ICST control register is located (even 32 bit address) -- #clock-cells: must be <0> -- clocks: parent clock, since the ICST needs a parent clock to derive its - frequency from, this attribute is compulsory. - -Example: - -syscon: syscon@10000000 { - compatible = "syscon"; - reg = <0x10000000 0x1000>; - - oscclk0: osc0@c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0c>; - clocks = <&xtal24mhz>; - }; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt b/Documentation/devicetree/bindings/clock/imx8mm-clock.txt deleted file mode 100644 index 8e4ab9e619a1..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Clock bindings for NXP i.MX8M Mini - -Required properties: -- compatible: Should be "fsl,imx8mm-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include the following entries: - - "osc_32k" - - "osc_24m" - - "clk_ext1" - - "clk_ext2" - - "clk_ext3" - - "clk_ext4" - -clk: clock-controller@30380000 { - compatible = "fsl,imx8mm-ccm"; - reg = <0x0 0x30380000 0x0 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; -}; - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h -for the full list of i.MX8M Mini clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml new file mode 100644 index 000000000000..ec830db1367b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Mini Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: | + NXP i.MX8M Mini clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: fsl,imx8mm-ccm + + reg: + maxItems: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h + for the full list of i.MX8M Mini clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + clk: clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml index cd0b8a341321..49730474c1a7 100644 --- a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml @@ -40,7 +40,7 @@ properties: '#clock-cells': const: 1 - description: | + description: The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h for the full list of i.MX8M Nano clock IDs. @@ -57,7 +57,7 @@ examples: - | clk: clock-controller@30380000 { compatible = "fsl,imx8mn-ccm"; - reg = <0x0 0x30380000 0x0 0x10000>; + reg = <0x30380000 0x10000>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; @@ -65,48 +65,4 @@ examples: "clk_ext2", "clk_ext3", "clk_ext4"; }; - # Required external clocks for Clock Control Module node: - - | - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - ... diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt deleted file mode 100644 index 52de8263e012..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Clock bindings for NXP i.MX8M Quad - -Required properties: -- compatible: Should be "fsl,imx8mq-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include the following entries: - - "ckil" - - "osc_25m" - - "osc_27m" - - "clk_ext1" - - "clk_ext2" - - "clk_ext3" - - "clk_ext4" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h -for the full list of i.MX8M Quad clock IDs. diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml new file mode 100644 index 000000000000..05d7d1471e0c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Quad Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: | + NXP i.MX8M Quad clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: fsl,imx8mq-ccm + + reg: + maxItems: 1 + + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h + for the full list of i.MX8M Quad clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + clk: clock-controller@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, + <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", + "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml new file mode 100644 index 000000000000..e2b6ac96bbcb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 and MMP3 Clock Controller + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +description: | + The clock subsystem on MMP2 or MMP3 generates and supplies clock to various + controllers within the SoC. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. + +properties: + compatible: + enum: + - marvell,mmp2-clock # controller compatible with MMP2 SoC + - marvell,mmp3-clock # controller compatible with MMP3 SoC + + reg: + items: + - description: MPMU register region + - description: APMU register region + - description: APBC register region + + reg-names: + items: + - const: mpmu + - const: apmu + - const: apbc + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@d4050000 { + compatible = "marvell,mmp2-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt deleted file mode 100644 index 23b52dc02266..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell MMP2 Clock Controller - -The MMP2 clock subsystem generates and supplies clock to various -controllers within the MMP2 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,mmp2-clock" - controller compatible with MMP2 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 3 places in SOC has clock control logic: - "mpmu", "apmu", "apbc". So three reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml new file mode 100644 index 000000000000..2c40a8aa9815 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8250 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8250. + + See also: + - dt-bindings/clock/qcom,gcc-sm8250.h + +properties: + compatible: + const: qcom,gcc-sm8250 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sm8250"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 944719bd586f..90a1349bc713 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -14,7 +14,9 @@ Required properties : "qcom,rpmcc-apq8060", "qcom,rpmcc" "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-msm8974", "qcom,rpmcc" + "qcom,rpmcc-msm8976", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" + "qcom,rpmcc-ipq806x", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" "qcom,rpmcc-msm8998", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 2cd158f13bab..2b633a4b0bc2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc7180-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sm8150-rpmh-clk + - qcom,sm8250-rpmh-clk clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml new file mode 100644 index 000000000000..0dd5d25ae7d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Modem Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm modem clock control module which supports the clocks on SC7180. + + See also: + - dt-bindings/clock/qcom,mss-sc7180.h + +properties: + compatible: + const: qcom,sc7180-mss + + clocks: + items: + - description: gcc_mss_mfab_axi clock from GCC + - description: gcc_mss_nav_axi clock from GCC + - description: gcc_mss_cfg_ahb clock from GCC + + clock-names: + items: + - const: gcc_mss_mfab_axis + - const: gcc_mss_nav_axi + - const: cfg_ahb + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + clock-controller@41a8000 { + compatible = "qcom,sc7180-mss"; + reg = <0 0x041a8000 0 0x8000>; + clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>; + clock-names = "gcc_mss_mfab_axis", + "gcc_mss_nav_axi", + "cfg_ahb"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt deleted file mode 100644 index f4d153f24a0f..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ /dev/null @@ -1,100 +0,0 @@ -* Renesas Clock Pulse Generator / Module Standby and Software Reset - -On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) -and MSSR (Module Standby and Software Reset) blocks are intimately connected, -and share the same register block. - -They provide the following functionalities: - - The CPG block generates various core clocks, - - The MSSR block provides two functions: - 1. Module Standby, providing a Clock Domain to control the clock supply - to individual SoC devices, - 2. Reset Control, to perform a software reset of individual SoC devices. - -Required Properties: - - compatible: Must be one of: - - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2) - - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) - - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N) - - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N) - - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) - - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) - - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) - - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W) - - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+) - - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) - - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3) - - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - - - reg: Base address and length of the memory resource used by the CPG/MSSR - block - - - clocks: References to external parent clocks, one entry for each entry in - clock-names - - clock-names: List of external parent clock names. Valid names are: - - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, - r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, - r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970, - r8a77980, r8a77990, r8a77995) - - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965, - r8a77970, r8a77980) - - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, - r8a7793, r8a7794) - - - #clock-cells: Must be 2 - - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" - and a core clock reference, as defined in - <dt-bindings/clock/*-cpg-mssr.h>. - - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the datasheet. - - - #power-domain-cells: Must be 0 - - SoC devices that are part of the CPG/MSSR Clock Domain and can be - power-managed through Module Standby should refer to the CPG device - node in their "power-domains" property, as documented by the generic PM - Domain bindings in - Documentation/devicetree/bindings/power/power-domain.yaml. - - - #reset-cells: Must be 1 - - The single reset specifier cell must be the module number, as defined - in the datasheet. - - -Examples --------- - - - CPG device node: - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - - - CPG/MSSR Clock Domain member device node: - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 310>; - clock-names = "fck"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>; - dma-names = "tx", "rx"; - power-domains = <&cpg>; - resets = <&cpg 310>; - }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml new file mode 100644 index 000000000000..9cd102e5fed5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas Clock Pulse Generator / Module Standby and Software Reset + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: | + On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) + and MSSR (Module Standby and Software Reset) blocks are intimately connected, + and share the same register block. + + They provide the following functionalities: + - The CPG block generates various core clocks, + - The MSSR block provides two functions: + 1. Module Standby, providing a Clock Domain to control the clock supply + to individual SoC devices, + 2. Reset Control, to perform a software reset of individual SoC devices. + +properties: + compatible: + enum: + - renesas,r7s9210-cpg-mssr # RZ/A2 + - renesas,r8a7743-cpg-mssr # RZ/G1M + - renesas,r8a7744-cpg-mssr # RZ/G1N + - renesas,r8a7745-cpg-mssr # RZ/G1E + - renesas,r8a77470-cpg-mssr # RZ/G1C + - renesas,r8a774a1-cpg-mssr # RZ/G2M + - renesas,r8a774b1-cpg-mssr # RZ/G2N + - renesas,r8a774c0-cpg-mssr # RZ/G2E + - renesas,r8a7790-cpg-mssr # R-Car H2 + - renesas,r8a7791-cpg-mssr # R-Car M2-W + - renesas,r8a7792-cpg-mssr # R-Car V2H + - renesas,r8a7793-cpg-mssr # R-Car M2-N + - renesas,r8a7794-cpg-mssr # R-Car E2 + - renesas,r8a7795-cpg-mssr # R-Car H3 + - renesas,r8a7796-cpg-mssr # R-Car M3-W + - renesas,r8a77961-cpg-mssr # R-Car M3-W+ + - renesas,r8a77965-cpg-mssr # R-Car M3-N + - renesas,r8a77970-cpg-mssr # R-Car V3M + - renesas,r8a77980-cpg-mssr # R-Car V3H + - renesas,r8a77990-cpg-mssr # R-Car E3 + - renesas,r8a77995-cpg-mssr # R-Car D3 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - extal # All + - extalr # Most R-Car Gen3 and RZ/G2 + - usb_extal # Most R-Car Gen2 and RZ/G1 + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + <dt-bindings/clock/*-cpg-mssr.h> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, as defined in the datasheet. + const: 2 + + '#power-domain-cells': + description: + SoC devices that are part of the CPG/MSSR Clock Domain and can be + power-managed through Module Standby should refer to the CPG device node + in their "power-domains" property, as documented by the generic PM Domain + bindings in Documentation/devicetree/bindings/power/power-domain.yaml. + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the module number, as defined in + the datasheet. + const: 1 + +if: + not: + properties: + compatible: + items: + enum: + - renesas,r7s9210-cpg-mssr +then: + required: + - '#reset-cells' + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0xe6150000 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt index 83f6c6a7c41c..4bf6f53bd95e 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt @@ -38,10 +38,17 @@ Required properties: - reg: offset and length of the USB 2.0 clock selector register block. - clocks: A list of phandles and specifier pairs. - clock-names: Name of the clocks. - - The functional clock must be "ehci_ohci" + - The functional clock of USB 2.0 host side must be "ehci_ohci" + - The functional clock of HS-USB side must be "hs-usb-if" - The USB_EXTAL clock pin must be "usb_extal" - The USB_XTAL clock pin must be "usb_xtal" - #clock-cells: Must be 0 +- power-domains: A phandle and symbolic PM domain specifier. + See power/renesas,rcar-sysc.yaml. +- resets: A list of phandles and specifier pairs. +- reset-names: Name of the resets. + - The reset of USB 2.0 host side must be "ehci_ohci" + - The reset of HS-USB side must be "hs-usb-if" Example (R-Car H3): @@ -49,7 +56,11 @@ Example (R-Car H3): compatible = "renesas,r8a7795-rcar-usb2-clock-sel", "renesas,rcar-gen3-usb2-clock-sel"; reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>; - clock-names = "ehci_ohci", "usb_extal", "usb_xtal"; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal>, <&usb_xtal>; + clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal"; #clock-cells = <0>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; }; diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file mode 100644 index 000000000000..869b18ac88d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI EHRPWM Time Base Clock + +maintainers: + - Vignesh Raghavendra <vigneshr@ti.com> + +properties: + compatible: + items: + - const: ti,am654-ehrpwm-tbclk + - const: syscon + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +examples: + - | + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; |