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Diffstat (limited to 'arch/arm/boot/dts/meson8.dtsi')
-rw-r--r--arch/arm/boot/dts/meson8.dtsi68
1 files changed, 68 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 157a950a55d3..f80ddc98d3a2 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -304,14 +304,42 @@
"pp2", "ppmmu2", "pp4", "ppmmu4",
"pp5", "ppmmu5", "pp6", "ppmmu6";
resets = <&reset RESET_MALI>;
+
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
+
+ assigned-clocks = <&clkc CLKID_MALI>;
+ assigned-clock-rates = <318750000>;
+
operating-points-v2 = <&gpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
};
};
}; /* end of / */
+&aiu {
+ compatible = "amlogic,aiu-meson8", "amlogic,aiu";
+ clocks = <&clkc CLKID_AIU_GLUE>,
+ <&clkc CLKID_I2S_OUT>,
+ <&clkc CLKID_AOCLK_GATE>,
+ <&clkc CLKID_CTS_AMCLK>,
+ <&clkc CLKID_MIXER_IFACE>,
+ <&clkc CLKID_IEC958>,
+ <&clkc CLKID_IEC958_GATE>,
+ <&clkc CLKID_CTS_MCLK_I958>,
+ <&clkc CLKID_CTS_I958>;
+ clock-names = "pclk",
+ "i2s_pclk",
+ "i2s_aoclk",
+ "i2s_mclk",
+ "i2s_mixer",
+ "spdif_pclk",
+ "spdif_aoclk",
+ "spdif_mclk",
+ "spdif_mclk_sel";
+ resets = <&reset RESET_AIU>;
+};
+
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
@@ -335,6 +363,38 @@
gpio-ranges = <&pinctrl_aobus 0 0 16>;
};
+ i2s_am_clk_pins: i2s-am-clk-out {
+ mux {
+ groups = "i2s_am_clk_out_ao";
+ function = "i2s_ao";
+ bias-disable;
+ };
+ };
+
+ i2s_out_ao_clk_pins: i2s-ao-clk-out {
+ mux {
+ groups = "i2s_ao_clk_out_ao";
+ function = "i2s_ao";
+ bias-disable;
+ };
+ };
+
+ i2s_out_lr_clk_pins: i2s-lr-clk-out {
+ mux {
+ groups = "i2s_lr_clk_out_ao";
+ function = "i2s_ao";
+ bias-disable;
+ };
+ };
+
+ i2s_out_ch01_ao_pins: i2s-out-ch01 {
+ mux {
+ groups = "i2s_out_ch01_ao";
+ function = "i2s_ao";
+ bias-disable;
+ };
+ };
+
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
@@ -455,6 +515,14 @@
};
};
+ spdif_out_pins: spdif-out {
+ mux {
+ groups = "spdif_out";
+ function = "spdif";
+ bias-disable;
+ };
+ };
+
spi_nor_pins: nor {
mux {
groups = "nor_d", "nor_q", "nor_c", "nor_cs";