diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom/qcom-sdx65.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 51 |
1 files changed, 27 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index e559adaaeee7..40591a4da6a4 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -204,8 +204,16 @@ gcc: clock-controller@100000 { compatible = "qcom,gcc-sdx65"; reg = <0x00100000 0x001f7400>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie_phy>, + <0>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "pcie_pipe_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; @@ -233,32 +241,27 @@ usb_qmpphy: phy@ff6000 { compatible = "qcom,sdx65-qmp-usb3-uni-phy"; - reg = <0x00ff6000 0x1c8>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x00ff6000 0x2000>; clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_EN>; - clock-names = "aux", "cfg_ahb", "ref"; + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; - resets = <&gcc GCC_USB3PHY_PHY_BCR>, - <&gcc GCC_USB3_PHY_BCR>; - reset-names = "phy", "common"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; status = "disabled"; - usb_ssphy: phy@ff6200 { - reg = <0x00ff6e00 0x160>, - <0x00ff7000 0x1ec>, - <0x00ff6200 0x1e00>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; }; system_noc: interconnect@1620000 { @@ -338,7 +341,7 @@ power-domains = <&gcc PCIE_GDSC>; phys = <&pcie_phy>; - phy-names = "pcie-phy"; + phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -520,7 +523,7 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_hsphy>, <&usb_ssphy>; + phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; }; @@ -530,7 +533,7 @@ reg = <0x0c264000 0x1000>; }; - spmi_bus: qcom,spmi@c440000 { + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, <0xc600000 0x2000000>, |