diff options
Diffstat (limited to 'arch/arm/boot/dts/rockchip/rk3128.dtsi')
-rw-r--r-- | arch/arm/boot/dts/rockchip/rk3128.dtsi | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fb98873fd94e..d4572146d135 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -216,6 +216,8 @@ <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>, <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, + <&cru SCLK_MIPI_24M>, <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru ACLK_VIO0>, @@ -252,6 +254,30 @@ }; }; + vpu: video-codec@10106000 { + compatible = "rockchip,rk3128-vpu", "rockchip,rk3066-vpu"; + reg = <0x10106000 0x800>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3128_PD_VIDEO>; + }; + + vpu_mmu: iommu@10106800 { + compatible = "rockchip,iommu"; + reg = <0x10106800 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VEPU>, <&cru HCLK_VDPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3128_PD_VIDEO>; + #iommu-cells = <0>; + }; + vop: vop@1010e000 { compatible = "rockchip,rk3126-vop"; reg = <0x1010e000 0x300>; @@ -275,6 +301,43 @@ reg = <0>; remote-endpoint = <&hdmi_in_vop>; }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + + dsi: dsi@10110000 { + compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x10110000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MIPI>; + clock-names = "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&power RK3128_PD_VIO>; + resets = <&cru SRST_VIO_MIPI_DSI>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + dsi_out: port@1 { + reg = <1>; + }; }; }; @@ -360,6 +423,41 @@ status = "disabled"; }; + i2s_8ch: i2s@10200000 { + compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; + reg = <0x10200000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif: spdif@10204000 { + compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif"; + reg = <0x10204000 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 13>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sfc: spi@1020c000 { + compatible = "rockchip,sfc"; + reg = <0x1020c000 0x8000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -408,6 +506,21 @@ status = "disabled"; }; + i2s_2ch: i2s@10220000 { + compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; + reg = <0x10220000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + nfc: nand-controller@10500000 { compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; reg = <0x10500000 0x4000>; @@ -477,6 +590,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; power-domains = <&power RK3128_PD_VIO>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -496,6 +610,18 @@ }; }; + dphy: phy@20038000 { + compatible = "rockchip,rk3128-dsi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; + clock-names = "ref", "pclk"; + #phy-cells = <0>; + power-domains = <&power RK3128_PD_VIO>; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + status = "disabled"; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; @@ -1104,6 +1230,32 @@ }; }; + sfc { + sfc_bus2: sfc-bus2 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>; + }; + + sfc_bus4: sfc-bus4 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>, + <1 RK_PD2 3 &pcfg_pull_default>, + <1 RK_PD3 3 &pcfg_pull_default>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>; + }; + }; + spdif { spdif_tx: spdif-tx { rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; |