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Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi56
1 files changed, 32 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2c43c4d85dee..b2674bdb8e6a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -15,7 +15,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/reset/altr,rst-mgr.h>
/ {
@@ -38,13 +37,13 @@
#size-cells = <0>;
enable-method = "altr,socfpga-smp";
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
@@ -52,6 +51,15 @@
};
};
+ pmu: pmu@ff111000 {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <0 176 4>, <0 177 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ reg = <0xff111000 0x1000>,
+ <0xff113000 0x1000>;
+ };
+
intc: intc@fffed000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -145,7 +153,7 @@
compatible = "fixed-clock";
};
- main_pll: main_pll {
+ main_pll: main_pll@40 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -153,7 +161,7 @@
clocks = <&osc1>;
reg = <0x40>;
- mpuclk: mpuclk {
+ mpuclk: mpuclk@48 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -161,7 +169,7 @@
reg = <0x48>;
};
- mainclk: mainclk {
+ mainclk: mainclk@4c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -169,7 +177,7 @@
reg = <0x4C>;
};
- dbg_base_clk: dbg_base_clk {
+ dbg_base_clk: dbg_base_clk@50 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>, <&osc1>;
@@ -177,21 +185,21 @@
reg = <0x50>;
};
- main_qspi_clk: main_qspi_clk {
+ main_qspi_clk: main_qspi_clk@54 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x54>;
};
- main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+ main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x58>;
};
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -199,7 +207,7 @@
};
};
- periph_pll: periph_pll {
+ periph_pll: periph_pll@80 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -207,42 +215,42 @@
clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
reg = <0x80>;
- emac0_clk: emac0_clk {
+ emac0_clk: emac0_clk@88 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x88>;
};
- emac1_clk: emac1_clk {
+ emac1_clk: emac1_clk@8c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x8C>;
};
- per_qspi_clk: per_qsi_clk {
+ per_qspi_clk: per_qsi_clk@90 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x90>;
};
- per_nand_mmc_clk: per_nand_mmc_clk {
+ per_nand_mmc_clk: per_nand_mmc_clk@94 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x94>;
};
- per_base_clk: per_base_clk {
+ per_base_clk: per_base_clk@98 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x98>;
};
- h2f_usr1_clk: h2f_usr1_clk {
+ h2f_usr1_clk: h2f_usr1_clk@9c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
@@ -250,7 +258,7 @@
};
};
- sdram_pll: sdram_pll {
+ sdram_pll: sdram_pll@c0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -258,28 +266,28 @@
clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
reg = <0xC0>;
- ddr_dqs_clk: ddr_dqs_clk {
+ ddr_dqs_clk: ddr_dqs_clk@c8 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xC8>;
};
- ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+ ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xCC>;
};
- ddr_dq_clk: ddr_dq_clk {
+ ddr_dq_clk: ddr_dq_clk@d0 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xD0>;
};
- h2f_usr2_clk: h2f_usr2_clk {
+ h2f_usr2_clk: h2f_usr2_clk@d4 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
@@ -678,7 +686,7 @@
status = "disabled";
};
- eccmgr: eccmgr@ffd08140 {
+ eccmgr: eccmgr {
compatible = "altr,socfpga-ecc-manager";
#address-cells = <1>;
#size-cells = <1>;
@@ -879,7 +887,7 @@
dma-names = "tx", "rx";
};
- usbphy0: usbphy@0 {
+ usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";