diff options
Diffstat (limited to 'arch/arm/boot/dts/vf610-twr.dts')
| -rw-r--r-- | arch/arm/boot/dts/vf610-twr.dts | 66 |
1 files changed, 61 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index c8047ca16501..e3a3805c2236 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -39,7 +39,7 @@ &dspi0 { bus-num = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0_1>; + pinctrl-0 = <&pinctrl_dspi0>; status = "okay"; sflash: at26df081a@0 { @@ -56,26 +56,82 @@ &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec0_1>; + pinctrl-0 = <&pinctrl_fec0>; status = "okay"; }; &fec1 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1_1>; + pinctrl-0 = <&pinctrl_fec1>; status = "okay"; }; &i2c0 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_1>; + pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; }; +&iomuxc { + vf610-twr { + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x30d3 + VF610_PAD_PTB15__I2C0_SDA 0x30d3 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + }; +}; + &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; |