summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/cachetype.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/include/asm/cachetype.h')
-rw-r--r--arch/arm/include/asm/cachetype.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index 8609de8e313a..01509ae0bbec 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -67,6 +67,7 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
#define CSSELR_L6 (5 << 1)
#define CSSELR_L7 (6 << 1)
+#ifndef CONFIG_CPU_V7M
static inline void set_csselr(unsigned int cache_selector)
{
asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
@@ -79,5 +80,19 @@ static inline unsigned int read_ccsidr(void)
asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
return val;
}
+#else /* CONFIG_CPU_V7M */
+#include <linux/io.h>
+#include "asm/v7m.h"
+
+static inline void set_csselr(unsigned int cache_selector)
+{
+ writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
+}
+
+static inline unsigned int read_ccsidr(void)
+{
+ return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
+}
+#endif
#endif