diff options
Diffstat (limited to 'arch/arm/mach-davinci')
52 files changed, 833 insertions, 15546 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index dd427bd2768c..2a8a9fe46586 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -3,40 +3,23 @@ menuconfig ARCH_DAVINCI bool "TI DaVinci" depends on ARCH_MULTI_V5 + depends on CPU_LITTLE_ENDIAN + select CPU_ARM926T select DAVINCI_TIMER select ZONE_DMA - select ARCH_HAS_HOLES_MEMORYMODEL select PM_GENERIC_DOMAINS if PM select PM_GENERIC_DOMAINS_OF if PM && OF select REGMAP_MMIO - select HAVE_IDE + select RESET_CONTROLLER + select PINCTRL select PINCTRL_SINGLE if ARCH_DAVINCI -config ARCH_DAVINCI_DMx - bool - comment "DaVinci Core Type" -config ARCH_DAVINCI_DM644x - bool "DaVinci 644x based system" - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - -config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - -config ARCH_DAVINCI_DM646x - bool "DaVinci 646x based system" - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" - depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) select ARCH_DAVINCI_DA8XX # needed on silicon revs 1.0, 1.1: select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE @@ -44,173 +27,11 @@ config ARCH_DAVINCI_DA830 config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" - depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) - select ARCH_DAVINCI_DA8XX select DAVINCI_CP_INTC config ARCH_DAVINCI_DA8XX bool -config ARCH_DAVINCI_DM365 - bool "DaVinci 365 based system" - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - -comment "DaVinci Board Type" - -config MACH_DA8XX_DT - bool "Support DA8XX platforms using device tree" - default y - depends on ARCH_DAVINCI_DA850 - select PINCTRL - select TIMER_OF - help - Say y here to include support for TI DaVinci DA850 based using - Flattened Device Tree. More information at Documentation/devicetree - -config MACH_DAVINCI_EVM - bool "TI DM644x EVM" - default ARCH_DAVINCI_DM644x - depends on ARCH_DAVINCI_DM644x - help - Configure this option to specify the whether the board used - for development is a DM644x EVM - -config MACH_SFFSDR - bool "Lyrtech SFFSDR" - depends on ARCH_DAVINCI_DM644x - help - Say Y here to select the Lyrtech Small Form Factor - Software Defined Radio (SFFSDR) board. - -config MACH_NEUROS_OSD2 - bool "Neuros OSD2 Open Television Set Top Box" - depends on ARCH_DAVINCI_DM644x - help - Configure this option to specify the whether the board used - for development is a Neuros OSD2 Open Set Top Box. - -config MACH_DAVINCI_DM355_EVM - bool "TI DM355 EVM" - default ARCH_DAVINCI_DM355 - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 EVM - -config MACH_DM355_LEOPARD - bool "DM355 Leopard board" - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 Leopard board. - -config MACH_DAVINCI_DM6467_EVM - bool "TI DM6467 EVM" - default ARCH_DAVINCI_DM646x - depends on ARCH_DAVINCI_DM646x - select MACH_DAVINCI_DM6467TEVM - help - Configure this option to specify the whether the board used - for development is a DM6467 EVM - -config MACH_DAVINCI_DM6467TEVM - bool - -config MACH_DAVINCI_DM365_EVM - bool "TI DM365 EVM" - default ARCH_DAVINCI_DM365 - depends on ARCH_DAVINCI_DM365 - help - Configure this option to specify whether the board used - for development is a DM365 EVM - -config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137/AM17x Reference Platform" - default ARCH_DAVINCI_DA830 - depends on ARCH_DAVINCI_DA830 - select GPIO_PCF857X if I2C - help - Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. - -choice - prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" - depends on MACH_DAVINCI_DA830_EVM - help - The presence of UI card on the DA830/OMAP-L137/AM17x EVM is - detected automatically based on successful probe of the I2C - based GPIO expander on that board. This option selected in this - menu has an effect only in case of a successful UI card detection. - -config DA830_UI_LCD - bool "LCD" - help - Say Y here to use the LCD as a framebuffer or simple character - display. - -config DA830_UI_NAND - bool "NAND flash" - help - Say Y here to use the NAND flash. Do not forget to setup - the switch correctly. -endchoice - -config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138/AM18x Reference Platform" - default ARCH_DAVINCI_DA850 - depends on ARCH_DAVINCI_DA850 - help - Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. - -choice - prompt "Select peripherals connected to expander on UI board" - depends on MACH_DAVINCI_DA850_EVM - help - The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x - EVM is detected automatically based on successful probe of the I2C - based GPIO expander on that card. This option selected in this - menu has an effect only in case of a successful UI card detection. - -config DA850_UI_NONE - bool "No peripheral is enabled" - help - Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card - -config DA850_UI_RMII - bool "RMII Ethernet PHY" - help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x - EVM. This PHY is found on the UI daughter card that is supplied with - the EVM. - NOTE: Please take care while choosing this option, MII PHY will - not be functional if RMII mode is selected. - -config DA850_UI_SD_VIDEO_PORT - bool "Video Port Interface" - help - Say Y if you want to use Video Port Interface (VPIF) on the - DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the - UI daughter card that is supplied with the EVM. - -endchoice - -config MACH_MITYOMAPL138 - bool "Critical Link MityDSP-L138/MityARM-1808 SoM" - depends on ARCH_DAVINCI_DA850 - help - Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 - System on Module. Information on this SoM may be found at - http://www.mitydsp.com - -config MACH_OMAPL138_HAWKBOARD - bool "TI AM1808 / OMAPL-138 Hawkboard platform" - depends on ARCH_DAVINCI_DA850 - help - Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform . - Information of this board may be found at - http://www.hawkboard.org/ - config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index a03d8443ef08..450883ea0e73 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -3,36 +3,17 @@ # Makefile for the linux kernel. # # - -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include - +# # Common objects -obj-y := time.o serial.o usb.o \ - common.o sram.o +obj-y := common.o sram.o devices-da8xx.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific -obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o pdata-quirks.o -# Board specific -obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o -obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o -obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o -obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o -obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o -obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o -obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o -obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o -obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o -obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o -obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o -obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o +obj-y += da8xx-dt.o # Power Management obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot deleted file mode 100644 index d36b251f325b..000000000000 --- a/arch/arm/mach-davinci/Makefile.boot +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX) += 0xc0008000 -params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0000100 -initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0800000 - -zreladdr-$(CONFIG_ARCH_DAVINCI_DMx) += 0x80008000 -params_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80000100 -initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80800000 diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h deleted file mode 100644 index d0ecd1d0f084..000000000000 --- a/arch/arm/mach-davinci/asp.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * TI DaVinci Audio definitions - */ -#ifndef __ASM_ARCH_DAVINCI_ASP_H -#define __ASM_ARCH_DAVINCI_ASP_H - -/* Bases of dm644x and dm355 register banks */ -#define DAVINCI_ASP0_BASE 0x01E02000 -#define DAVINCI_ASP1_BASE 0x01E04000 - -/* Bases of dm365 register banks */ -#define DAVINCI_DM365_ASP0_BASE 0x01D02000 - -/* Bases of dm646x register banks */ -#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 -#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 - -/* Bases of da850/da830 McASP0 register banks */ -#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 - -/* Bases of da830 McASP1 register banks */ -#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 - -/* Bases of da830 McASP2 register banks */ -#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000 - -/* EDMA channels of dm644x and dm355 */ -#define DAVINCI_DMA_ASP0_TX 2 -#define DAVINCI_DMA_ASP0_RX 3 -#define DAVINCI_DMA_ASP1_TX 8 -#define DAVINCI_DMA_ASP1_RX 9 - -/* EDMA channels of dm646x */ -#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 -#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 -#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 - -/* EDMA channels of da850/da830 McASP0 */ -#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 -#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 - -/* EDMA channels of da830 McASP1 */ -#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 -#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 - -/* EDMA channels of da830 McASP2 */ -#define DAVINCI_DA830_DMA_MCASP2_AREVT 4 -#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5 - -/* Interrupts */ -#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) -#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) -#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) -#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) - -#endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c deleted file mode 100644 index a273ab25c668..000000000000 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ /dev/null @@ -1,690 +0,0 @@ -/* - * TI DA830/OMAP L137 EVM board - * - * Author: Mark A. Greer <mgreer@mvista.com> - * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c - * - * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/console.h> -#include <linux/interrupt.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/platform_data/pcf857x.h> -#include <linux/property.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/spi-davinci.h> -#include <linux/platform_data/usb-davinci.h> -#include <linux/platform_data/ti-aemif.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/nvmem-provider.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/mux.h> -#include <mach/da8xx.h> - -#include "irqs.h" - -#define DA830_EVM_PHY_ID "" -/* - * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. - */ -#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15) -#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4) - -static const short da830_evm_usb11_pins[] = { - DA830_GPIO1_15, DA830_GPIO2_4, - -1 -}; - -static struct regulator_consumer_supply da830_evm_usb_supplies[] = { - REGULATOR_SUPPLY("vbus", NULL), -}; - -static struct regulator_init_data da830_evm_usb_vbus_data = { - .consumer_supplies = da830_evm_usb_supplies, - .num_consumer_supplies = ARRAY_SIZE(da830_evm_usb_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config da830_evm_usb_vbus = { - .supply_name = "vbus", - .microvolts = 33000000, - .init_data = &da830_evm_usb_vbus_data, -}; - -static struct platform_device da830_evm_usb_vbus_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &da830_evm_usb_vbus, - }, -}; - -static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = { - .dev_id = "ohci-da8xx", - .table = { - GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0), - { } - }, -}; - -static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = { - .dev_id = "reg-fixed-voltage.0", - .table = { - GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = { - &da830_evm_usb_oc_gpio_lookup, - &da830_evm_usb_vbus_gpio_lookup, -}; - -static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = { - /* TPS2065 switch @ 5V */ - .potpgt = (3 + 1) / 2, /* 3 ms max */ -}; - -static __init void da830_evm_usb_init(void) -{ - int ret; - - ret = da8xx_register_usb_phy_clocks(); - if (ret) - pr_warn("%s: USB PHY CLK registration failed: %d\n", - __func__, ret); - - gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups, - ARRAY_SIZE(da830_evm_usb_gpio_lookups)); - - ret = da8xx_register_usb_phy(); - if (ret) - pr_warn("%s: USB PHY registration failed: %d\n", - __func__, ret); - - ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); - if (ret) - pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret); - else { - /* - * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A), - * with the power on to power good time of 3 ms. - */ - ret = da8xx_register_usb20(1000, 3); - if (ret) - pr_warn("%s: USB 2.0 registration failed: %d\n", - __func__, ret); - } - - ret = davinci_cfg_reg_list(da830_evm_usb11_pins); - if (ret) { - pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); - return; - } - - ret = platform_device_register(&da830_evm_usb_vbus_device); - if (ret) { - pr_warn("%s: Unable to register the vbus supply\n", __func__); - return; - } - - ret = da8xx_register_usb11(&da830_evm_usb11_pdata); - if (ret) - pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret); -} - -static const short da830_evm_mcasp1_pins[] = { - DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, - DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, - DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10, - DA830_AXR1_11, - -1 -}; - -static u8 da830_iis_serializer_direction[] = { - RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static struct snd_platform_data da830_evm_snd_data = { - .tx_dma_offset = 0x2000, - .rx_dma_offset = 0x2000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = da830_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - .version = MCASP_VERSION_2, - .txnumevt = 1, - .rxnumevt = 1, -}; - -/* - * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS. - */ -static const short da830_evm_mmc_sd_pins[] = { - DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, - DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2, - -1 -}; - -#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) -#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - /* gpio chip 1 contains gpio range 32-63 */ - GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_LOW), - { } - }, -}; - -static struct davinci_mmc_config da830_evm_mmc_config = { - .wires = 8, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static inline void da830_evm_init_mmc(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins); - if (ret) { - pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret); - return; - } - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); - if (ret) { - pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret); - gpiod_remove_lookup_table(&mmc_gpios_table); - } -} - -#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI) - -#ifdef CONFIG_DA830_UI_NAND -static struct mtd_partition da830_evm_nand_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - [0] = { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - [1] = { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* kernel */ - [2] = { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0, - }, - /* file system */ - [3] = { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } -}; - -/* flash bbt decriptors */ -static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' }; -static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' }; - -static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = { - .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | - NAND_BBT_WRITE | NAND_BBT_2BIT | - NAND_BBT_VERSION | NAND_BBT_PERCHIP, - .offs = 2, - .len = 4, - .veroffs = 16, - .maxblocks = 4, - .pattern = da830_evm_nand_bbt_pattern -}; - -static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { - .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | - NAND_BBT_WRITE | NAND_BBT_2BIT | - NAND_BBT_VERSION | NAND_BBT_PERCHIP, - .offs = 2, - .len = 4, - .veroffs = 16, - .maxblocks = 4, - .pattern = da830_evm_nand_mirror_pattern -}; - -static struct davinci_aemif_timing da830_evm_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata da830_evm_nand_pdata = { - .core_chipsel = 1, - .parts = da830_evm_nand_partitions, - .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), - .ecc_mode = NAND_ECC_HW, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .bbt_td = &da830_evm_nand_bbt_main_descr, - .bbt_md = &da830_evm_nand_bbt_mirror_descr, - .timing = &da830_evm_nandflash_timing, -}; - -static struct resource da830_evm_nand_resources[] = { - [0] = { /* First memory resource is NAND I/O window */ - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { /* Second memory resource is AEMIF control registers */ - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_evm_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da830_evm_nand_pdata, - }, - .num_resources = ARRAY_SIZE(da830_evm_nand_resources), - .resource = da830_evm_nand_resources, - }, -}; - -static struct resource da830_evm_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data da830_evm_aemif_abus_data[] = { - { - .cs = 3, - }, -}; - -static struct aemif_platform_data da830_evm_aemif_pdata = { - .abus_data = da830_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data), - .sub_devices = da830_evm_aemif_devices, - .num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices), - .cs_offset = 2, -}; - -static struct platform_device da830_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &da830_evm_aemif_pdata, - }, - .resource = da830_evm_aemif_resource, - .num_resources = ARRAY_SIZE(da830_evm_aemif_resource), -}; - -/* - * UI board NAND/NOR flashes only use 8-bit data bus. - */ -static const short da830_evm_emif25_pins[] = { - DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, - DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, - DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, - DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, - DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, - DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE, - DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0, - -1 -}; - -static inline void da830_evm_init_nand(int mux_mode) -{ - int ret; - - if (HAS_MMC) { - pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n" - "\tDisable MMC/SD for NAND support\n"); - return; - } - - ret = davinci_cfg_reg_list(da830_evm_emif25_pins); - if (ret) - pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret); - - ret = platform_device_register(&da830_evm_aemif_device); - if (ret) - pr_warn("%s: AEMIF device not registered\n", __func__); - - gpio_direction_output(mux_mode, 1); -} -#else -static inline void da830_evm_init_nand(int mux_mode) { } -#endif - -#ifdef CONFIG_DA830_UI_LCD -static inline void da830_evm_init_lcdc(int mux_mode) -{ - int ret; - - ret = davinci_cfg_reg_list(da830_lcdcntl_pins); - if (ret) - pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata); - if (ret) - pr_warn("%s: lcd setup failed: %d\n", __func__, ret); - - gpio_direction_output(mux_mode, 0); -} -#else -static inline void da830_evm_init_lcdc(int mux_mode) { } -#endif - -static struct nvmem_cell_info da830_evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table da830_evm_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = da830_evm_nvmem_cells, - .ncells = ARRAY_SIZE(da830_evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry da830_evm_i2c_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -static int __init da830_evm_ui_expander_setup(struct i2c_client *client, - int gpio, unsigned ngpio, void *context) -{ - gpio_request(gpio + 6, "UI MUX_MODE"); - - /* Drive mux mode low to match the default without UI card */ - gpio_direction_output(gpio + 6, 0); - - da830_evm_init_lcdc(gpio + 6); - - da830_evm_init_nand(gpio + 6); - - return 0; -} - -static int da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *context) -{ - gpio_free(gpio + 6); - return 0; -} - -static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = { - .gpio_base = DAVINCI_N_GPIO, - .setup = da830_evm_ui_expander_setup, - .teardown = da830_evm_ui_expander_teardown, -}; - -static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .properties = da830_evm_i2c_eeprom_properties, - }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, - { - I2C_BOARD_INFO("pcf8574", 0x3f), - .platform_data = &da830_evm_ui_expander_info, - }, -}; - -static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence - * they are being reserved for codecs on the DSP side. - */ -static const s16 da830_dma_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 2}, - {12, 2}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da830_dma_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 2}, - {12, 2}, - {24, 4}, - {30, 26}, - {-1, -1} -}; - -static struct edma_rsv_info da830_edma_rsv[] = { - { - .rsv_chans = da830_dma_rsv_chans, - .rsv_slots = da830_dma_rsv_slots, - }, -}; - -static struct mtd_partition da830evm_spiflash_part[] = { - [0] = { - .name = "DSP-UBL", - .offset = 0, - .size = SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "ARM-UBL", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16K + SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K - SZ_32K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "U-Boot-Environment", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16K, - .mask_flags = 0, - }, - [4] = { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct flash_platform_data da830evm_spiflash_data = { - .name = "m25p80", - .parts = da830evm_spiflash_part, - .nr_parts = ARRAY_SIZE(da830evm_spiflash_part), - .type = "w25x32", -}; - -static struct davinci_spi_config da830evm_spiflash_cfg = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info da830evm_spi_info[] = { - { - .modalias = "m25p80", - .platform_data = &da830evm_spiflash_data, - .controller_data = &da830evm_spiflash_cfg, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static __init void da830_evm_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - int ret; - - da830_register_clocks(); - - ret = da830_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - ret = da830_register_edma(da830_edma_rsv); - if (ret) - pr_warn("%s: edma registration failed: %d\n", __func__, ret); - - ret = davinci_cfg_reg_list(da830_i2c0_pins); - if (ret) - pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); - if (ret) - pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret); - - da830_evm_usb_init(); - - soc_info->emac_pdata->rmii_en = 1; - soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID; - - ret = davinci_cfg_reg_list(da830_cpgmac_pins); - if (ret) - pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: emac registration failed: %d\n", __func__, ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - davinci_serial_init(da8xx_serial_device); - - nvmem_add_cell_table(&da830_evm_nvmem_cell_table); - nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1); - - i2c_register_board_info(1, da830_evm_i2c_devices, - ARRAY_SIZE(da830_evm_i2c_devices)); - - ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins); - if (ret) - pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret); - - da8xx_register_mcasp(1, &da830_evm_snd_data); - - da830_evm_init_mmc(); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("%s: rtc setup failed: %d\n", __func__, ret); - - ret = spi_register_board_info(da830evm_spi_info, - ARRAY_SIZE(da830evm_spi_info)); - if (ret) - pr_warn("%s: spi info registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info)); - if (ret) - pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init da830_evm_console_init(void) -{ - if (!machine_is_davinci_da830_evm()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(da830_evm_console_init); -#endif - -static void __init da830_evm_map_io(void) -{ - da830_init(); -} - -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") - .atag_offset = 0x100, - .map_io = da830_evm_map_io, - .init_irq = da830_init_irq, - .init_time = da830_init_time, - .init_machine = da830_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c deleted file mode 100644 index 5b3549f1236c..000000000000 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ /dev/null @@ -1,1555 +0,0 @@ -/* - * TI DA850/OMAP-L138 EVM board - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * Derived from: arch/arm/mach-davinci/board-da830-evm.c - * Original Copyrights follow: - * - * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/console.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/gpio/machine.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/leds.h> -#include <linux/i2c.h> -#include <linux/platform_data/pca953x.h> -#include <linux/input.h> -#include <linux/input/tps6507x-ts.h> -#include <linux/mfd/tps6507x.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/partitions.h> -#include <linux/nvmem-provider.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/ti-aemif.h> -#include <linux/platform_data/spi-davinci.h> -#include <linux/platform_data/uio_pruss.h> -#include <linux/property.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/tps6507x.h> -#include <linux/regulator/fixed.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> - -#include <mach/common.h> -#include <mach/da8xx.h> -#include <mach/mux.h> - -#include "irqs.h" -#include "sram.h" - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/system_info.h> - -#include <media/i2c/tvp514x.h> -#include <media/i2c/adv7343.h> - -#define DA850_EVM_PHY_ID "davinci_mdio-0:00" -#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) -#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) - -#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) - -static struct mtd_partition da850evm_spiflash_part[] = { - [0] = { - .name = "UBL", - .offset = 0, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "U-Boot-Env", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M + SZ_512K, - .mask_flags = 0, - }, - [4] = { - .name = "Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, - [5] = { - .name = "MAC-Address", - .offset = SZ_8M - SZ_64K, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct nvmem_cell_info da850evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x0, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table da850evm_nvmem_cell_table = { - /* - * The nvmem name differs from the partition name because of the - * internal works of the nvmem framework. - */ - .nvmem_name = "MAC-Address0", - .cells = da850evm_nvmem_cells, - .ncells = ARRAY_SIZE(da850evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = { - .nvmem_name = "MAC-Address0", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static struct flash_platform_data da850evm_spiflash_data = { - .name = "m25p80", - .parts = da850evm_spiflash_part, - .nr_parts = ARRAY_SIZE(da850evm_spiflash_part), - .type = "m25p64", -}; - -static struct davinci_spi_config da850evm_spiflash_cfg = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info da850evm_spi_info[] = { - { - .modalias = "m25p80", - .platform_data = &da850evm_spiflash_data, - .controller_data = &da850evm_spiflash_cfg, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -static struct mtd_partition da850_evm_norflash_partition[] = { - { - .name = "bootloaders + env", - .offset = 0, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0, - }, - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct physmap_flash_data da850_evm_norflash_data = { - .width = 2, - .parts = da850_evm_norflash_partition, - .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition), -}; - -static struct resource da850_evm_norflash_resource[] = { - { - .start = DA8XX_AEMIF_CS2_BASE, - .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, -}; - -/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash - * (128K blocks). It may be used instead of the (default) SPI flash - * to boot, using TI's tools to install the secondary boot loader - * (UBL) and U-Boot. - */ -static struct mtd_partition da850_evm_nandflash_partition[] = { - { - .name = "u-boot env", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "UBL", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = 4 * SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = 0x200000, - .size = SZ_2M, - .mask_flags = 0, - }, - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_aemif_timing da850_evm_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata da850_evm_nandflash_data = { - .core_chipsel = 1, - .parts = da850_evm_nandflash_partition, - .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), - .ecc_mode = NAND_ECC_HW, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .timing = &da850_evm_nandflash_timing, -}; - -static struct resource da850_evm_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource da850_evm_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - } -}; - -static struct aemif_abus_data da850_evm_aemif_abus_data[] = { - { - .cs = 3, - } -}; - -static struct platform_device da850_evm_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da850_evm_nandflash_data, - }, - .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), - .resource = da850_evm_nandflash_resource, - }, - { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &da850_evm_norflash_data, - }, - .num_resources = 1, - .resource = da850_evm_norflash_resource, - } -}; - -static struct aemif_platform_data da850_evm_aemif_pdata = { - .cs_offset = 2, - .abus_data = da850_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), - .sub_devices = da850_evm_aemif_devices, - .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices), -}; - -static struct platform_device da850_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &da850_evm_aemif_pdata, - }, - .resource = da850_evm_aemif_resource, - .num_resources = ARRAY_SIZE(da850_evm_aemif_resource), -}; - -static const short da850_evm_nand_pins[] = { - DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, - DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, - DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, - DA850_NEMA_WE, DA850_NEMA_OE, - -1 -}; - -static const short da850_evm_nor_pins[] = { - DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, - DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, - DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, - DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, - DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, - DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, - DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, - DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, - DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, - DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, - DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, - DA850_EMA_A_22, DA850_EMA_A_23, - -1 -}; - -#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI) - -static inline void da850_evm_setup_nor_nand(void) -{ - int ret = 0; - - if (!HAS_MMC) { - ret = davinci_cfg_reg_list(da850_evm_nand_pins); - if (ret) - pr_warn("%s: NAND mux setup failed: %d\n", - __func__, ret); - - ret = davinci_cfg_reg_list(da850_evm_nor_pins); - if (ret) - pr_warn("%s: NOR mux setup failed: %d\n", - __func__, ret); - - ret = platform_device_register(&da850_evm_aemif_device); - if (ret) - pr_warn("%s: registering aemif failed: %d\n", - __func__, ret); - } -} - -#ifdef CONFIG_DA850_UI_RMII -static inline void da850_evm_setup_emac_rmii(int rmii_sel) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - soc_info->emac_pdata->rmii_en = 1; - gpio_set_value_cansleep(rmii_sel, 0); -} -#else -static inline void da850_evm_setup_emac_rmii(int rmii_sel) { } -#endif - - -#define DA850_KEYS_DEBOUNCE_MS 10 -/* - * At 200ms polling interval it is possible to miss an - * event by tapping very lightly on the push button but most - * pushes do result in an event; longer intervals require the - * user to hold the button whereas shorter intervals require - * more CPU time for polling. - */ -#define DA850_GPIO_KEYS_POLL_MS 200 - -enum da850_evm_ui_exp_pins { - DA850_EVM_UI_EXP_SEL_C = 5, - DA850_EVM_UI_EXP_SEL_B, - DA850_EVM_UI_EXP_SEL_A, - DA850_EVM_UI_EXP_PB8, - DA850_EVM_UI_EXP_PB7, - DA850_EVM_UI_EXP_PB6, - DA850_EVM_UI_EXP_PB5, - DA850_EVM_UI_EXP_PB4, - DA850_EVM_UI_EXP_PB3, - DA850_EVM_UI_EXP_PB2, - DA850_EVM_UI_EXP_PB1, -}; - -static const char * const da850_evm_ui_exp[] = { - [DA850_EVM_UI_EXP_SEL_C] = "sel_c", - [DA850_EVM_UI_EXP_SEL_B] = "sel_b", - [DA850_EVM_UI_EXP_SEL_A] = "sel_a", - [DA850_EVM_UI_EXP_PB8] = "pb8", - [DA850_EVM_UI_EXP_PB7] = "pb7", - [DA850_EVM_UI_EXP_PB6] = "pb6", - [DA850_EVM_UI_EXP_PB5] = "pb5", - [DA850_EVM_UI_EXP_PB4] = "pb4", - [DA850_EVM_UI_EXP_PB3] = "pb3", - [DA850_EVM_UI_EXP_PB2] = "pb2", - [DA850_EVM_UI_EXP_PB1] = "pb1", -}; - -#define DA850_N_UI_PB 8 - -static struct gpio_keys_button da850_evm_ui_keys[] = { - [0 ... DA850_N_UI_PB - 1] = { - .type = EV_KEY, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = -1, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - .desc = NULL, /* assigned at runtime */ - }, -}; - -static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = { - .buttons = da850_evm_ui_keys, - .nbuttons = ARRAY_SIZE(da850_evm_ui_keys), - .poll_interval = DA850_GPIO_KEYS_POLL_MS, -}; - -static struct platform_device da850_evm_ui_keys_device = { - .name = "gpio-keys-polled", - .id = 0, - .dev = { - .platform_data = &da850_evm_ui_keys_pdata - }, -}; - -static void da850_evm_ui_keys_init(unsigned gpio) -{ - int i; - struct gpio_keys_button *button; - - for (i = 0; i < DA850_N_UI_PB; i++) { - button = &da850_evm_ui_keys[i]; - button->code = KEY_F8 - i; - button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i]; - button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i; - } -} - -#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT -static inline void da850_evm_setup_video_port(int video_sel) -{ - gpio_set_value_cansleep(video_sel, 0); -} -#else -static inline void da850_evm_setup_video_port(int video_sel) { } -#endif - -static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, - unsigned ngpio, void *c) -{ - int sel_a, sel_b, sel_c, ret; - - sel_a = gpio + DA850_EVM_UI_EXP_SEL_A; - sel_b = gpio + DA850_EVM_UI_EXP_SEL_B; - sel_c = gpio + DA850_EVM_UI_EXP_SEL_C; - - ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_a); - goto exp_setup_sela_fail; - } - - ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_b); - goto exp_setup_selb_fail; - } - - ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_c); - goto exp_setup_selc_fail; - } - - /* deselect all functionalities */ - gpio_direction_output(sel_a, 1); - gpio_direction_output(sel_b, 1); - gpio_direction_output(sel_c, 1); - - da850_evm_ui_keys_init(gpio); - ret = platform_device_register(&da850_evm_ui_keys_device); - if (ret) { - pr_warn("Could not register UI GPIO expander push-buttons"); - goto exp_setup_keys_fail; - } - - pr_info("DA850/OMAP-L138 EVM UI card detected\n"); - - da850_evm_setup_nor_nand(); - - da850_evm_setup_emac_rmii(sel_a); - - da850_evm_setup_video_port(sel_c); - - return 0; - -exp_setup_keys_fail: - gpio_free(sel_c); -exp_setup_selc_fail: - gpio_free(sel_b); -exp_setup_selb_fail: - gpio_free(sel_a); -exp_setup_sela_fail: - return ret; -} - -static int da850_evm_ui_expander_teardown(struct i2c_client *client, - unsigned gpio, unsigned ngpio, void *c) -{ - platform_device_unregister(&da850_evm_ui_keys_device); - - /* deselect all functionalities */ - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1); - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1); - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1); - - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C); - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B); - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A); - - return 0; -} - -/* assign the baseboard expander's GPIOs after the UI board's */ -#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp) -#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS) - -enum da850_evm_bb_exp_pins { - DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0, - DA850_EVM_BB_EXP_SW_RST, - DA850_EVM_BB_EXP_TP_23, - DA850_EVM_BB_EXP_TP_22, - DA850_EVM_BB_EXP_TP_21, - DA850_EVM_BB_EXP_USER_PB1, - DA850_EVM_BB_EXP_USER_LED2, - DA850_EVM_BB_EXP_USER_LED1, - DA850_EVM_BB_EXP_USER_SW1, - DA850_EVM_BB_EXP_USER_SW2, - DA850_EVM_BB_EXP_USER_SW3, - DA850_EVM_BB_EXP_USER_SW4, - DA850_EVM_BB_EXP_USER_SW5, - DA850_EVM_BB_EXP_USER_SW6, - DA850_EVM_BB_EXP_USER_SW7, - DA850_EVM_BB_EXP_USER_SW8 -}; - -static const char * const da850_evm_bb_exp[] = { - [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en", - [DA850_EVM_BB_EXP_SW_RST] = "sw_rst", - [DA850_EVM_BB_EXP_TP_23] = "tp_23", - [DA850_EVM_BB_EXP_TP_22] = "tp_22", - [DA850_EVM_BB_EXP_TP_21] = "tp_21", - [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1", - [DA850_EVM_BB_EXP_USER_LED2] = "user_led2", - [DA850_EVM_BB_EXP_USER_LED1] = "user_led1", - [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1", - [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2", - [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3", - [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4", - [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5", - [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6", - [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7", - [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8", -}; - -#define DA850_N_BB_USER_SW 8 - -static struct gpio_keys_button da850_evm_bb_keys[] = { - [0] = { - .type = EV_KEY, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = KEY_PROG1, - .desc = NULL, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - }, - [1 ... DA850_N_BB_USER_SW] = { - .type = EV_SW, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = -1, /* assigned at runtime */ - .desc = NULL, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - }, -}; - -static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = { - .buttons = da850_evm_bb_keys, - .nbuttons = ARRAY_SIZE(da850_evm_bb_keys), - .poll_interval = DA850_GPIO_KEYS_POLL_MS, -}; - -static struct platform_device da850_evm_bb_keys_device = { - .name = "gpio-keys-polled", - .id = 1, - .dev = { - .platform_data = &da850_evm_bb_keys_pdata - }, -}; - -static void da850_evm_bb_keys_init(unsigned gpio) -{ - int i; - struct gpio_keys_button *button; - - button = &da850_evm_bb_keys[0]; - button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1]; - button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1; - - for (i = 0; i < DA850_N_BB_USER_SW; i++) { - button = &da850_evm_bb_keys[i + 1]; - button->code = SW_LID + i; - button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i]; - button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i; - } -} - -static struct gpio_led da850_evm_bb_leds[] = { - { - .name = "user_led2", - }, - { - .name = "user_led1", - }, -}; - -static struct gpio_led_platform_data da850_evm_bb_leds_pdata = { - .leds = da850_evm_bb_leds, - .num_leds = ARRAY_SIZE(da850_evm_bb_leds), -}; - -static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = { - .dev_id = "leds-gpio", - .table = { - GPIO_LOOKUP_IDX("i2c-bb-expander", - DA850_EVM_BB_EXP_USER_LED2, NULL, - 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("i2c-bb-expander", - DA850_EVM_BB_EXP_USER_LED2 + 1, NULL, - 1, GPIO_ACTIVE_LOW), - - { }, - }, -}; - -static struct platform_device da850_evm_bb_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &da850_evm_bb_leds_pdata - } -}; - -static int da850_evm_bb_expander_setup(struct i2c_client *client, - unsigned gpio, unsigned ngpio, - void *c) -{ - int ret; - - /* - * Register the switches and pushbutton on the baseboard as a gpio-keys - * device. - */ - da850_evm_bb_keys_init(gpio); - ret = platform_device_register(&da850_evm_bb_keys_device); - if (ret) { - pr_warn("Could not register baseboard GPIO expander keys"); - goto io_exp_setup_sw_fail; - } - - gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table); - ret = platform_device_register(&da850_evm_bb_leds_device); - if (ret) { - pr_warn("Could not register baseboard GPIO expander LEDs"); - goto io_exp_setup_leds_fail; - } - - return 0; - -io_exp_setup_leds_fail: - platform_device_unregister(&da850_evm_bb_keys_device); -io_exp_setup_sw_fail: - return ret; -} - -static int da850_evm_bb_expander_teardown(struct i2c_client *client, - unsigned gpio, unsigned ngpio, void *c) -{ - platform_device_unregister(&da850_evm_bb_leds_device); - platform_device_unregister(&da850_evm_bb_keys_device); - - return 0; -} - -static struct pca953x_platform_data da850_evm_ui_expander_info = { - .gpio_base = DAVINCI_N_GPIO, - .setup = da850_evm_ui_expander_setup, - .teardown = da850_evm_ui_expander_teardown, - .names = da850_evm_ui_exp, -}; - -static struct pca953x_platform_data da850_evm_bb_expander_info = { - .gpio_base = DA850_BB_EXPANDER_GPIO_BASE, - .setup = da850_evm_bb_expander_setup, - .teardown = da850_evm_bb_expander_teardown, - .names = da850_evm_bb_exp, -}; - -static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, - { - I2C_BOARD_INFO("tca6416", 0x20), - .dev_name = "ui-expander", - .platform_data = &da850_evm_ui_expander_info, - }, - { - I2C_BOARD_INFO("tca6416", 0x21), - .dev_name = "bb-expander", - .platform_data = &da850_evm_bb_expander_info, - }, -}; - -static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* davinci da850 evm audio machine driver */ -static u8 da850_iis_serializer_direction[] = { - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, - RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static struct snd_platform_data da850_evm_snd_data = { - .tx_dma_offset = 0x2000, - .rx_dma_offset = 0x2000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = da850_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - .ram_chan_q = EVENTQ_1, - .version = MCASP_VERSION_2, - .txnumevt = 1, - .rxnumevt = 1, - .sram_size_playback = SZ_8K, - .sram_size_capture = SZ_8K, -}; - -static const short da850_evm_mcasp_pins[] __initconst = { - DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, - DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, - DA850_AXR_11, DA850_AXR_12, - -1 -}; - -#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) -#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - /* gpio chip 2 contains gpio range 64-95 */ - GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_HIGH), - { } - }, -}; - -static struct davinci_mmc_config da850_mmc_config = { - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static const short da850_evm_mmcsd0_pins[] __initconst = { - DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, - DA850_GPIO4_0, DA850_GPIO4_1, - -1 -}; - -static struct property_entry da850_lcd_backlight_props[] = { - PROPERTY_ENTRY_BOOL("default-on"), - { } -}; - -static struct gpiod_lookup_table da850_lcd_backlight_gpio_table = { - .dev_id = "gpio-backlight", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_LCD_BL_PIN, NULL, 0), - { } - }, -}; - -static const struct platform_device_info da850_lcd_backlight_info = { - .name = "gpio-backlight", - .id = PLATFORM_DEVID_NONE, - .properties = da850_lcd_backlight_props, -}; - -static struct regulator_consumer_supply da850_lcd_supplies[] = { - REGULATOR_SUPPLY("lcd", NULL), -}; - -static struct regulator_init_data da850_lcd_supply_data = { - .consumer_supplies = da850_lcd_supplies, - .num_consumer_supplies = ARRAY_SIZE(da850_lcd_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config da850_lcd_supply = { - .supply_name = "lcd", - .microvolts = 33000000, - .init_data = &da850_lcd_supply_data, -}; - -static struct platform_device da850_lcd_supply_device = { - .name = "reg-fixed-voltage", - .id = 1, /* Dummy fixed regulator is 0 */ - .dev = { - .platform_data = &da850_lcd_supply, - }, -}; - -static struct gpiod_lookup_table da850_lcd_supply_gpio_table = { - .dev_id = "reg-fixed-voltage.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_LCD_PWR_PIN, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *da850_lcd_gpio_lookups[] = { - &da850_lcd_backlight_gpio_table, - &da850_lcd_supply_gpio_table, -}; - -static int da850_lcd_hw_init(void) -{ - struct platform_device *backlight; - int status; - - gpiod_add_lookup_tables(da850_lcd_gpio_lookups, - ARRAY_SIZE(da850_lcd_gpio_lookups)); - - backlight = platform_device_register_full(&da850_lcd_backlight_info); - if (IS_ERR(backlight)) - return PTR_ERR(backlight); - - status = platform_device_register(&da850_lcd_supply_device); - if (status) - return status; - - return 0; -} - -/* Fixed regulator support */ -static struct regulator_consumer_supply fixed_supplies[] = { - /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */ - REGULATOR_SUPPLY("AVDD", "1-0018"), - REGULATOR_SUPPLY("DRVDD", "1-0018"), - - /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */ - REGULATOR_SUPPLY("DVDD", "1-0018"), - - /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */ - REGULATOR_SUPPLY("vcc", "1-0020"), -}; - -/* TPS65070 voltage regulator support */ - -/* 3.3V */ -static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { - { - .supply = "usb0_vdda33", - }, - { - .supply = "usb1_vdda33", - }, -}; - -/* 3.3V or 1.8V */ -static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { - { - .supply = "dvdd3318_a", - }, - { - .supply = "dvdd3318_b", - }, - { - .supply = "dvdd3318_c", - }, - REGULATOR_SUPPLY("IOVDD", "1-0018"), -}; - -/* 1.2V */ -static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { - { - .supply = "cvdd", - }, -}; - -/* 1.8V LDO */ -static struct regulator_consumer_supply tps65070_ldo1_consumers[] = { - { - .supply = "sata_vddr", - }, - { - .supply = "usb0_vdda18", - }, - { - .supply = "usb1_vdda18", - }, - { - .supply = "ddr_dvdd18", - }, -}; - -/* 1.2V LDO */ -static struct regulator_consumer_supply tps65070_ldo2_consumers[] = { - { - .supply = "sata_vdd", - }, - { - .supply = "pll0_vdda", - }, - { - .supply = "pll1_vdda", - }, - { - .supply = "usbs_cvdd", - }, - { - .supply = "vddarnwa1", - }, -}; - -/* We take advantage of the fact that both defdcdc{2,3} are tied high */ -static struct tps6507x_reg_platform_data tps6507x_platform_data = { - .defdcdc_default = true, -}; - -static struct regulator_init_data tps65070_regulator_data[] = { - /* dcdc1 */ - { - .constraints = { - .min_uV = 3150000, - .max_uV = 3450000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers), - .consumer_supplies = tps65070_dcdc1_consumers, - }, - - /* dcdc2 */ - { - .constraints = { - .min_uV = 1710000, - .max_uV = 3450000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), - .consumer_supplies = tps65070_dcdc2_consumers, - .driver_data = &tps6507x_platform_data, - }, - - /* dcdc3 */ - { - .constraints = { - .min_uV = 950000, - .max_uV = 1350000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers), - .consumer_supplies = tps65070_dcdc3_consumers, - .driver_data = &tps6507x_platform_data, - }, - - /* ldo1 */ - { - .constraints = { - .min_uV = 1710000, - .max_uV = 1890000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers), - .consumer_supplies = tps65070_ldo1_consumers, - }, - - /* ldo2 */ - { - .constraints = { - .min_uV = 1140000, - .max_uV = 1320000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers), - .consumer_supplies = tps65070_ldo2_consumers, - }, -}; - -static struct touchscreen_init_data tps6507x_touchscreen_data = { - .poll_period = 30, /* ms between touch samples */ - .min_pressure = 0x30, /* minimum pressure to trigger touch */ - .vendor = 0, /* /sys/class/input/input?/id/vendor */ - .product = 65070, /* /sys/class/input/input?/id/product */ - .version = 0x100, /* /sys/class/input/input?/id/version */ -}; - -static struct tps6507x_board tps_board = { - .tps6507x_pmic_init_data = &tps65070_regulator_data[0], - .tps6507x_ts_init_data = &tps6507x_touchscreen_data, -}; - -static struct i2c_board_info __initdata da850_evm_tps65070_info[] = { - { - I2C_BOARD_INFO("tps6507x", 0x48), - .platform_data = &tps_board, - }, -}; - -static int __init pmic_tps65070_init(void) -{ - return i2c_register_board_info(1, da850_evm_tps65070_info, - ARRAY_SIZE(da850_evm_tps65070_info)); -} - -static const short da850_evm_lcdc_pins[] = { - DA850_GPIO2_8, DA850_GPIO2_15, - -1 -}; - -static const short da850_evm_mii_pins[] = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static const short da850_evm_rmii_pins[] = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static struct gpiod_hog da850_evm_emac_gpio_hogs[] = { - { - .chip_label = "davinci_gpio", - .chip_hwnum = DA850_MII_MDIO_CLKEN_PIN, - .line_name = "mdio_clk_en", - .lflags = 0, - /* dflags set in da850_evm_config_emac() */ - }, - { } -}; - -static int __init da850_evm_config_emac(void) -{ - void __iomem *cfg_chip3_base; - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - u8 rmii_en = soc_info->emac_pdata->rmii_en; - - if (!machine_is_davinci_da850_evm()) - return 0; - - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - - val = __raw_readl(cfg_chip3_base); - - if (rmii_en) { - val |= BIT(8); - ret = davinci_cfg_reg_list(da850_evm_rmii_pins); - pr_info("EMAC: RMII PHY configured, MII PHY will not be" - " functional\n"); - } else { - val &= ~BIT(8); - ret = davinci_cfg_reg_list(da850_evm_mii_pins); - pr_info("EMAC: MII PHY configured, RMII PHY will not be" - " functional\n"); - } - - if (ret) - pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n", - __func__, ret); - - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - ret = davinci_cfg_reg(DA850_GPIO2_6); - if (ret) - pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__); - - da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH - : GPIOD_OUT_LOW; - gpiod_add_hogs(da850_evm_emac_gpio_hogs); - - soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); - - return 0; -} -device_initcall(da850_evm_config_emac); - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence - * they are being reserved for codecs on the DSP side. - */ -static const s16 da850_dma0_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma0_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 50}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 90}, - {-1, -1} -}; - -static struct edma_rsv_info da850_edma_cc0_rsv = { - .rsv_chans = da850_dma0_rsv_chans, - .rsv_slots = da850_dma0_rsv_slots, -}; - -static struct edma_rsv_info da850_edma_cc1_rsv = { - .rsv_chans = da850_dma1_rsv_chans, - .rsv_slots = da850_dma1_rsv_slots, -}; - -static struct edma_rsv_info *da850_edma_rsv[2] = { - &da850_edma_cc0_rsv, - &da850_edma_cc1_rsv, -}; - -#ifdef CONFIG_CPU_FREQ -static __init int da850_evm_init_cpufreq(void) -{ - switch (system_rev & 0xF) { - case 3: - da850_max_speed = 456000; - break; - case 2: - da850_max_speed = 408000; - break; - case 1: - da850_max_speed = 372000; - break; - } - - return da850_register_cpufreq("pll0_sysclk3"); -} -#else -static __init int da850_evm_init_cpufreq(void) { return 0; } -#endif - -#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT) - -#define TVP5147_CH0 "tvp514x-0" -#define TVP5147_CH1 "tvp514x-1" - -/* VPIF capture configuration */ -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1, -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -static struct vpif_input da850_ch0_inputs[] = { - { - .input = { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_CVBS_VI2B, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH0, - }, -}; - -static struct vpif_input da850_ch1_inputs[] = { - { - .input = { - .index = 0, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_SVIDEO_VI2C_VI1C, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH1, - }, -}; - -static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = { - { - .name = TVP5147_CH0, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, - { - .name = TVP5147_CH1, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5c), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpif_capture_config da850_vpif_capture_config = { - .subdev_info = da850_vpif_capture_sdev_info, - .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), - .i2c_adapter_id = 1, - .chan_config[0] = { - .inputs = da850_ch0_inputs, - .input_count = ARRAY_SIZE(da850_ch0_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .chan_config[1] = { - .inputs = da850_ch1_inputs, - .input_count = ARRAY_SIZE(da850_ch1_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .card_name = "DA850/OMAP-L138 Video Capture", -}; - -/* VPIF display configuration */ - -static struct adv7343_platform_data adv7343_pdata = { - .mode_config = { - .dac = { 1, 1, 1 }, - }, - .sd_config = { - .sd_dac_out = { 1 }, - }, -}; - -static struct vpif_subdev_info da850_vpif_subdev[] = { - { - .name = "adv7343", - .board_info = { - I2C_BOARD_INFO("adv7343", 0x2a), - .platform_data = &adv7343_pdata, - }, - }, -}; - -static const struct vpif_output da850_ch0_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPOSITE_ID, - }, - { - .output = { - .index = 1, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_SVIDEO_ID, - }, -}; - -static struct vpif_display_config da850_vpif_display_config = { - .subdevinfo = da850_vpif_subdev, - .subdev_count = ARRAY_SIZE(da850_vpif_subdev), - .chan_config[0] = { - .outputs = da850_ch0_outputs, - .output_count = ARRAY_SIZE(da850_ch0_outputs), - }, - .card_name = "DA850/OMAP-L138 Video Display", - .i2c_adapter_id = 1, -}; - -static __init void da850_vpif_init(void) -{ - int ret; - - ret = da850_register_vpif(); - if (ret) - pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_capture_pins); - if (ret) - pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_capture(&da850_vpif_capture_config); - if (ret) - pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_display_pins); - if (ret) - pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_display(&da850_vpif_display_config); - if (ret) - pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret); -} - -#else -static __init void da850_vpif_init(void) {} -#endif - -#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) - -static __init void da850_evm_init(void) -{ - int ret; - - da850_register_clocks(); - - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies)); - - ret = pmic_tps65070_init(); - if (ret) - pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); - - ret = da850_register_edma(da850_edma_rsv); - if (ret) - pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); - - ret = davinci_cfg_reg_list(da850_i2c0_pins); - if (ret) - pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); - if (ret) - pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret); - - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - if (HAS_MMC) { - ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins); - if (ret) - pr_warn("%s: MMCSD0 mux setup failed: %d\n", - __func__, ret); - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da850_mmc_config); - if (ret) - pr_warn("%s: MMCSD0 registration failed: %d\n", - __func__, ret); - } - - davinci_serial_init(da8xx_serial_device); - - nvmem_add_cell_table(&da850evm_nvmem_cell_table); - nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1); - - i2c_register_board_info(1, da850_evm_i2c_devices, - ARRAY_SIZE(da850_evm_i2c_devices)); - - /* - * shut down uart 0 and 1; they are not used on the board and - * accessing them causes endless "too much work in irq53" messages - * with arago fs - */ - __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); - __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); - - ret = davinci_cfg_reg_list(da850_evm_mcasp_pins); - if (ret) - pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret); - - da850_evm_snd_data.sram_pool = sram_get_gen_pool(); - da8xx_register_mcasp(0, &da850_evm_snd_data); - - ret = davinci_cfg_reg_list(da850_lcdcntl_pins); - if (ret) - pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_uio_pruss(); - if (ret) - pr_warn("da850_evm_init: pruss initialization failed: %d\n", - ret); - - /* Handle board specific muxing for LCD here */ - ret = davinci_cfg_reg_list(da850_evm_lcdc_pins); - if (ret) - pr_warn("%s: EVM specific LCD mux setup failed: %d\n", - __func__, ret); - - ret = da850_lcd_hw_init(); - if (ret) - pr_warn("%s: LCD initialization failed: %d\n", __func__, ret); - - ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); - if (ret) - pr_warn("%s: LCDC registration failed: %d\n", __func__, ret); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("%s: RTC setup failed: %d\n", __func__, ret); - - ret = da850_evm_init_cpufreq(); - if (ret) - pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret); - - ret = da8xx_register_cpuidle(); - if (ret) - pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret); - - davinci_pm_init(); - da850_vpif_init(); - - ret = spi_register_board_info(da850evm_spi_info, - ARRAY_SIZE(da850evm_spi_info)); - if (ret) - pr_warn("%s: spi info registration failed: %d\n", __func__, - ret); - - ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info)); - if (ret) - pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret); - - ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE); - if (ret) - pr_warn("%s: SATA registration failed: %d\n", __func__, ret); - - ret = da8xx_register_rproc(); - if (ret) - pr_warn("%s: dsp/rproc registration failed: %d\n", - __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init da850_evm_console_init(void) -{ - if (!machine_is_davinci_da850_evm()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(da850_evm_console_init); -#endif - -static void __init da850_evm_map_io(void) -{ - da850_init(); -} - -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") - .atag_offset = 0x100, - .map_io = da850_evm_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = da850_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .reserve = da8xx_rproc_reserve_cma, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c deleted file mode 100644 index 5113273fda69..000000000000 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * TI DaVinci EVM board support - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/rawnand.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/clk.h> -#include <linux/dm9000.h> -#include <linux/videodev2.h> -#include <media/i2c/tvp514x.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/usb-davinci.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/serial.h> -#include <mach/common.h> - -#include "davinci.h" - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 4, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM355_ASYNC_EMIF_CONTROL_BASE, - .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15) -#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14) - -static struct gpiod_lookup_table i2c_recovery_gpiod_table = { - .dev_id = "i2c_davinci.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - { } - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, - .gpio_recovery = true, -}; - -static int dm355evm_mmc_gpios = -EINVAL; - -static void dm355evm_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - dm355evm_mmc_gpios = gpio; -} - -static struct i2c_board_info dm355evm_i2c_info[] = { - { I2C_BOARD_INFO("dm355evm_msp", 0x25), - .platform_data = dm355evm_mmcsd_gpios, - }, - /* { plus irq }, */ - { I2C_BOARD_INFO("tlv320aic33", 0x1b), }, -}; - -static void __init evm_init_i2c(void) -{ - gpiod_add_lookup_table(&i2c_recovery_gpiod_table); - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355evm_msp"); - gpio_direction_input(5); - dm355evm_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355evm_i2c_info, - ARRAY_SIZE(dm355evm_i2c_info)); -} - -static struct resource dm355evm_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04014000, - .end = 0x04014001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04014002, - .end = 0x04014003, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct dm9000_plat_data dm335evm_dm9000_platdata; - -static struct platform_device dm355evm_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355evm_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), - .dev = { - .platform_data = &dm335evm_dm9000_platdata, - }, -}; - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, - { - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(tvp5146_inputs), - .inputs = tvp5146_inputs, - .routes = tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - } -}; - -static struct vpfe_config vpfe_cfg = { - .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), - .i2c_adapter_id = 1, - .sub_devs = vpfe_sub_devs, - .card_name = "DM355 EVM", - .ccdc = "DM355 CCDC", -}; - -/* venc standards timings */ -static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7E, - .upper_margin = 0x16 - }, -}; - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* - * The outputs available from VPBE + ecnoders. Keep the - * the order same as that of encoders. First those from venc followed by that - * from encoders. Index in the output refers to index on a particular encoder. - * Driver uses this index to pass it to encoder when it supports more than - * one output. Application uses index of the array to set an output. - */ -static struct vpbe_output dm355evm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM355_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm355evm_enc_preset_timing), - .modes = dm355evm_enc_preset_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, -}; - -static struct vpbe_config dm355evm_display_cfg = { - .module_name = "dm355-vpbe-display", - .i2c_adapter_id = 1, - .osd = { - .module_name = DM355_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM355_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm355evm_vpbe_outputs), - .outputs = dm355evm_vpbe_outputs, -}; - -static struct platform_device *davinci_evm_devices[] __initdata = { - &dm355evm_dm9000, - &davinci_nand_device, -}; - -static void __init dm355_evm_map_io(void) -{ - dm355_init(); -} - -static int dm355evm_mmc_get_cd(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1); -} - -static int dm355evm_mmc_get_ro(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0); -} - -static struct davinci_mmc_config dm355evm_mmc_config = { - .get_cd = dm355evm_mmc_get_cd, - .get_ro = dm355evm_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#define USB_ID_VALUE 1 /* ID pulled low */ - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm355_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_evm_init(void) -{ - struct clk *aemif; - int ret; - - dm355_register_clocks(); - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - gpio_request(1, "dm9000"); - gpio_direction_input(1); - dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); - - aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); - if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) - clk_prepare_enable(aemif); - - platform_add_devices(davinci_evm_devices, - ARRAY_SIZE(davinci_evm_devices)); - evm_init_i2c(); - davinci_serial_init(dm355_serial_device); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - davinci_setup_usb(1000, 8); - - davinci_setup_mmc(0, &dm355evm_mmc_config); - davinci_setup_mmc(1, &dm355evm_mmc_config); - - dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg); - - dm355_init_spi0(BIT(0), dm355_evm_spi_info, - ARRAY_SIZE(dm355_evm_spi_info)); - - /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ - dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN); -} - -MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") - .atag_offset = 0x100, - .map_io = dm355_evm_map_io, - .init_irq = dm355_init_irq, - .init_time = dm355_init_time, - .init_machine = dm355_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c deleted file mode 100644 index b9e9950dd300..000000000000 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * DM355 leopard board support - * - * Based on board-dm355-evm.c - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/rawnand.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/usb-davinci.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/serial.h> - -#include "davinci.h" - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW_SYNDROME, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM355_ASYNC_EMIF_CONTROL_BASE, - .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static int leopard_mmc_gpio = -EINVAL; - -static void dm355leopard_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - leopard_mmc_gpio = gpio; -} - -static struct i2c_board_info dm355leopard_i2c_info[] = { - { I2C_BOARD_INFO("dm355leopard_msp", 0x25), - .platform_data = dm355leopard_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ -}; - -static void __init leopard_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355leopard_msp"); - gpio_direction_input(5); - dm355leopard_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355leopard_i2c_info, - ARRAY_SIZE(dm355leopard_i2c_info)); -} - -static struct resource dm355leopard_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04000000, - .end = 0x04000001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04000016, - .end = 0x04000017, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct platform_device dm355leopard_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355leopard_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc), -}; - -static struct platform_device *davinci_leopard_devices[] __initdata = { - &dm355leopard_dm9000, - &davinci_nand_device, -}; - -static void __init dm355_leopard_map_io(void) -{ - dm355_init(); -} - -static int dm355leopard_mmc_get_cd(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1); -} - -static int dm355leopard_mmc_get_ro(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0); -} - -static struct davinci_mmc_config dm355leopard_mmc_config = { - .get_cd = dm355leopard_mmc_get_cd, - .get_ro = dm355leopard_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#define USB_ID_VALUE 1 /* ID pulled low */ - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm355_leopard_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_leopard_init(void) -{ - struct clk *aemif; - int ret; - - dm355_register_clocks(); - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - gpio_request(9, "dm9000"); - gpio_direction_input(9); - dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); - - aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); - if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) - clk_prepare_enable(aemif); - - platform_add_devices(davinci_leopard_devices, - ARRAY_SIZE(davinci_leopard_devices)); - leopard_init_i2c(); - davinci_serial_init(dm355_serial_device); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - davinci_setup_usb(1000, 8); - - davinci_setup_mmc(0, &dm355leopard_mmc_config); - davinci_setup_mmc(1, &dm355leopard_mmc_config); - - dm355_init_spi0(BIT(0), dm355_leopard_spi_info, - ARRAY_SIZE(dm355_leopard_spi_info)); -} - -MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") - .atag_offset = 0x100, - .map_io = dm355_leopard_map_io, - .init_irq = dm355_init_irq, - .init_time = dm355_init_time, - .init_machine = dm355_leopard_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c deleted file mode 100644 index 150a36f333df..000000000000 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ /dev/null @@ -1,840 +0,0 @@ -/* - * TI DaVinci DM365 EVM board support - * - * Copyright (C) 2009 Texas Instruments Incorporated - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/i2c.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/property.h> -#include <linux/leds.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/slab.h> -#include <linux/mtd/rawnand.h> -#include <linux/nvmem-provider.h> -#include <linux/input.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> -#include <linux/v4l2-dv-timings.h> -#include <linux/platform_data/ti-aemif.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/mux.h> -#include <mach/common.h> -#include <linux/platform_data/i2c-davinci.h> -#include <mach/serial.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/keyscan-davinci.h> - -#include <media/i2c/ths7303.h> -#include <media/i2c/tvp514x.h> - -#include "davinci.h" - -static inline int have_imager(void) -{ - /* REVISIT when it's supported, trigger via Kconfig */ - return 0; -} - -static inline int have_tvp7002(void) -{ - /* REVISIT when it's supported, trigger via Kconfig */ - return 0; -} - -#define DM365_EVM_PHY_ID "davinci_mdio-0:01" -/* - * A MAX-II CPLD is used for various board control functions. - */ -#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) - -#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ -#define CPLD_TEST CPLD_OFFSET(0,1) -#define CPLD_LEDS CPLD_OFFSET(0,2) -#define CPLD_MUX CPLD_OFFSET(0,3) -#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ -#define CPLD_POWER CPLD_OFFSET(1,1) -#define CPLD_VIDEO CPLD_OFFSET(1,2) -#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ - -#define CPLD_DILC_OUT CPLD_OFFSET(2,0) -#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ - -#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) -#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) -#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) -#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) -#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) -#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) -#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) -#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) -#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) - -#define CPLD_RESETS CPLD_OFFSET(4,3) - -#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) -#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) -#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) -#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) -#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) -#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) - -static void __iomem *cpld; - - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips with a different block size, partitioning will - * need to be changed. This NAND chip MT29F16G08FAA is the default - * NAND shipped with the Spectrum Digital DM365 EVM - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 30 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 2 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 4, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM365_ASYNC_EMIF_CONTROL_BASE, - .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 0, - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - .dev = { - .platform_data = &davinci_nand_data, - }, - } -}; - -static struct resource davinci_aemif_resources[] = { - { - .start = DM365_ASYNC_EMIF_CONTROL_BASE, - .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data da850_evm_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data davinci_aemif_pdata = { - .abus_data = da850_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), - .sub_devices = davinci_aemif_devices, - .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices), -}; - -static struct platform_device davinci_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &davinci_aemif_pdata, - }, - .resource = davinci_aemif_resources, - .num_resources = ARRAY_SIZE(davinci_aemif_resources), -}; - -static struct nvmem_cell_info davinci_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table davinci_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = davinci_nvmem_cells, - .ncells = ARRAY_SIZE(davinci_nvmem_cells), -}; - -static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -static struct i2c_board_info i2c_info[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .properties = eeprom_properties, - }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static int dm365evm_keyscan_enable(struct device *dev) -{ - return davinci_cfg_reg(DM365_KEYSCAN); -} - -static unsigned short dm365evm_keymap[] = { - KEY_KP2, - KEY_LEFT, - KEY_EXIT, - KEY_DOWN, - KEY_ENTER, - KEY_UP, - KEY_KP1, - KEY_RIGHT, - KEY_MENU, - KEY_RECORD, - KEY_REWIND, - KEY_KPMINUS, - KEY_STOP, - KEY_FASTFORWARD, - KEY_KPPLUS, - KEY_PLAYPAUSE, - 0 -}; - -static struct davinci_ks_platform_data dm365evm_ks_data = { - .device_enable = dm365evm_keyscan_enable, - .keymap = dm365evm_keymap, - .keymapsize = ARRAY_SIZE(dm365evm_keymap), - .rep = 1, - /* Scan period = strobe + interval */ - .strobe = 0x5, - .interval = 0x2, - .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4, -}; - -static int cpld_mmc_get_cd(int module) -{ - if (!cpld) - return -ENXIO; - - /* low == card present */ - return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); -} - -static int cpld_mmc_get_ro(int module) -{ - if (!cpld) - return -ENXIO; - - /* high == card's write protect switch active */ - return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); -} - -static struct davinci_mmc_config dm365evm_mmc_config = { - .get_cd = cpld_mmc_get_cd, - .get_ro = cpld_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static void dm365evm_emac_configure(void) -{ - /* - * EMAC pins are multiplexed with GPIO and UART - * Further details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 - */ - davinci_cfg_reg(DM365_EMAC_TX_EN); - davinci_cfg_reg(DM365_EMAC_TX_CLK); - davinci_cfg_reg(DM365_EMAC_COL); - davinci_cfg_reg(DM365_EMAC_TXD3); - davinci_cfg_reg(DM365_EMAC_TXD2); - davinci_cfg_reg(DM365_EMAC_TXD1); - davinci_cfg_reg(DM365_EMAC_TXD0); - davinci_cfg_reg(DM365_EMAC_RXD3); - davinci_cfg_reg(DM365_EMAC_RXD2); - davinci_cfg_reg(DM365_EMAC_RXD1); - davinci_cfg_reg(DM365_EMAC_RXD0); - davinci_cfg_reg(DM365_EMAC_RX_CLK); - davinci_cfg_reg(DM365_EMAC_RX_DV); - davinci_cfg_reg(DM365_EMAC_RX_ER); - davinci_cfg_reg(DM365_EMAC_CRS); - davinci_cfg_reg(DM365_EMAC_MDIO); - davinci_cfg_reg(DM365_EMAC_MDCLK); - - /* - * EMAC interrupts are multiplexed with GPIO interrupts - * Details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 - */ - davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); - davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); - davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); - davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); -} - -static void dm365evm_mmc_configure(void) -{ - /* - * MMC/SD pins are multiplexed with GPIO and EMIF - * Further details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 - */ - davinci_cfg_reg(DM365_SD1_CLK); - davinci_cfg_reg(DM365_SD1_CMD); - davinci_cfg_reg(DM365_SD1_DATA3); - davinci_cfg_reg(DM365_SD1_DATA2); - davinci_cfg_reg(DM365_SD1_DATA1); - davinci_cfg_reg(DM365_SD1_DATA0); -} - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -{ - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(tvp5146_inputs), - .inputs = tvp5146_inputs, - .routes = tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpfe_config vpfe_cfg = { - .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), - .sub_devs = vpfe_sub_devs, - .i2c_adapter_id = 1, - .card_name = "DM365 EVM", - .ccdc = "ISIF", -}; - -/* venc standards timings */ -static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7E, - .upper_margin = 0x16, - }, -}; - -/* venc dv timings */ -static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = { - { - .name = "480p59_94", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, - .interlaced = 0, - .xres = 720, - .yres = 480, - .aspect = {1, 1}, - .fps = {5994, 100}, - .left_margin = 0x8F, - .upper_margin = 0x2D, - }, - { - .name = "576p50", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X576P50, - .interlaced = 0, - .xres = 720, - .yres = 576, - .aspect = {1, 1}, - .fps = {50, 1}, - .left_margin = 0x8C, - .upper_margin = 0x36, - }, - { - .name = "720p60", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_1280X720P60, - .interlaced = 0, - .xres = 1280, - .yres = 720, - .aspect = {1, 1}, - .fps = {60, 1}, - .left_margin = 0x117, - .right_margin = 70, - .upper_margin = 38, - .lower_margin = 3, - .hsync_len = 80, - .vsync_len = 5, - }, - { - .name = "1080i60", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_1920X1080I60, - .interlaced = 1, - .xres = 1920, - .yres = 1080, - .aspect = {1, 1}, - .fps = {30, 1}, - .left_margin = 0xc9, - .right_margin = 80, - .upper_margin = 30, - .lower_margin = 3, - .hsync_len = 88, - .vsync_len = 5, - }, -}; - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* - * The outputs available from VPBE + ecnoders. Keep the - * the order same as that of encoders. First those from venc followed by that - * from encoders. Index in the output refers to index on a particular - * encoder.Driver uses this index to pass it to encoder when it supports more - * than one output. Application uses index of the array to set an output. - */ -static struct vpbe_output dm365evm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing), - .modes = dm365evm_enc_std_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, - { - .output = { - .index = 1, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, - }, - .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, - .default_mode = "480p59_94", - .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing), - .modes = dm365evm_enc_preset_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, -}; - -/* - * Amplifiers on the board - */ -static struct ths7303_platform_data ths7303_pdata = { - .ch_1 = 3, - .ch_2 = 3, - .ch_3 = 3, -}; - -static struct amp_config_info vpbe_amp = { - .module_name = "ths7303", - .is_i2c = 1, - .board_info = { - I2C_BOARD_INFO("ths7303", 0x2c), - .platform_data = &ths7303_pdata, - } -}; - -static struct vpbe_config dm365evm_display_cfg = { - .module_name = "dm365-vpbe-display", - .i2c_adapter_id = 1, - .amp = &vpbe_amp, - .osd = { - .module_name = DM365_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM365_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs), - .outputs = dm365evm_vpbe_outputs, -}; - -static void __init evm_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} - -static inline int have_leds(void) -{ -#ifdef CONFIG_LEDS_CLASS - return 1; -#else - return 0; -#endif -} - -struct cpld_led { - struct led_classdev cdev; - u8 mask; -}; - -static const struct { - const char *name; - const char *trigger; -} cpld_leds[] = { - { "dm365evm::ds2", }, - { "dm365evm::ds3", }, - { "dm365evm::ds4", }, - { "dm365evm::ds5", }, - { "dm365evm::ds6", "nand-disk", }, - { "dm365evm::ds7", "mmc1", }, - { "dm365evm::ds8", "mmc0", }, - { "dm365evm::ds9", "heartbeat", }, -}; - -static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) -{ - struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); - u8 reg = __raw_readb(cpld + CPLD_LEDS); - - if (b != LED_OFF) - reg &= ~led->mask; - else - reg |= led->mask; - __raw_writeb(reg, cpld + CPLD_LEDS); -} - -static enum led_brightness cpld_led_get(struct led_classdev *cdev) -{ - struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); - u8 reg = __raw_readb(cpld + CPLD_LEDS); - - return (reg & led->mask) ? LED_OFF : LED_FULL; -} - -static int __init cpld_leds_init(void) -{ - int i; - - if (!have_leds() || !cpld) - return 0; - - /* setup LEDs */ - __raw_writeb(0xff, cpld + CPLD_LEDS); - for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { - struct cpld_led *led; - - led = kzalloc(sizeof(*led), GFP_KERNEL); - if (!led) - break; - - led->cdev.name = cpld_leds[i].name; - led->cdev.brightness_set = cpld_led_set; - led->cdev.brightness_get = cpld_led_get; - led->cdev.default_trigger = cpld_leds[i].trigger; - led->mask = BIT(i); - - if (led_classdev_register(NULL, &led->cdev) < 0) { - kfree(led); - break; - } - } - - return 0; -} -/* run after subsys_initcall() for LEDs */ -fs_initcall(cpld_leds_init); - - -static void __init evm_init_cpld(void) -{ - u8 mux, resets; - const char *label; - struct clk *aemif_clk; - int rc; - - /* Make sure we can configure the CPLD through CS1. Then - * leave it on for later access to MMC and LED registers. - */ - aemif_clk = clk_get(NULL, "aemif"); - if (IS_ERR(aemif_clk)) - return; - clk_prepare_enable(aemif_clk); - - if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, - "cpld") == NULL) - goto fail; - cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); - if (!cpld) { - release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, - SECTION_SIZE); -fail: - pr_err("ERROR: can't map CPLD\n"); - clk_disable_unprepare(aemif_clk); - return; - } - - /* External muxing for some signals */ - mux = 0; - - /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). - * NOTE: SW4 bus width setting must match! - */ - if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { - /* external keypad mux */ - mux |= BIT(7); - - rc = platform_device_register(&davinci_aemif_device); - if (rc) - pr_warn("%s(): error registering the aemif device: %d\n", - __func__, rc); - } else { - /* no OneNAND support yet */ - } - - /* Leave external chips in reset when unused. */ - resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); - - /* Static video input config with SN74CBT16214 1-of-3 mux: - * - port b1 == tvp7002 (mux lowbits == 1 or 6) - * - port b2 == imager (mux lowbits == 2 or 7) - * - port b3 == tvp5146 (mux lowbits == 5) - * - * Runtime switching could work too, with limitations. - */ - if (have_imager()) { - label = "HD imager"; - mux |= 2; - - /* externally mux MMC1/ENET/AIC33 to imager */ - mux |= BIT(6) | BIT(5) | BIT(3); - } else { - struct davinci_soc_info *soc_info = &davinci_soc_info; - - /* we can use MMC1 ... */ - dm365evm_mmc_configure(); - davinci_setup_mmc(1, &dm365evm_mmc_config); - - /* ... and ENET ... */ - dm365evm_emac_configure(); - soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; - resets &= ~BIT(3); - - /* ... and AIC33 */ - resets &= ~BIT(1); - - if (have_tvp7002()) { - mux |= 1; - resets &= ~BIT(2); - label = "tvp7002 HD"; - } else { - /* default to tvp5146 */ - mux |= 5; - resets &= ~BIT(0); - label = "tvp5146 SD"; - } - } - __raw_writeb(mux, cpld + CPLD_MUX); - __raw_writeb(resets, cpld + CPLD_RESETS); - pr_info("EVM: %s video input\n", label); - - /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ -} - -static void __init dm365_evm_map_io(void) -{ - dm365_init(); -} - -static struct spi_eeprom at25640 = { - .byte_len = SZ_64K / 8, - .name = "at25640", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm365_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm365_evm_init(void) -{ - int ret; - - dm365_register_clocks(); - - ret = dm365_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - nvmem_add_cell_table(&davinci_nvmem_cell_table); - nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1); - - evm_init_i2c(); - davinci_serial_init(dm365_serial_device); - - dm365evm_emac_configure(); - dm365evm_mmc_configure(); - - davinci_setup_mmc(0, &dm365evm_mmc_config); - - dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg); - - /* maybe setup mmc1/etc ... _after_ mmc0 */ - evm_init_cpld(); - -#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC - dm365_init_asp(); -#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC) - dm365_init_vc(); -#endif - dm365_init_rtc(); - dm365_init_ks(&dm365evm_ks_data); - - dm365_init_spi0(BIT(0), dm365_evm_spi_info, - ARRAY_SIZE(dm365_evm_spi_info)); -} - -MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") - .atag_offset = 0x100, - .map_io = dm365_evm_map_io, - .init_irq = dm365_init_irq, - .init_time = dm365_init_time, - .init_machine = dm365_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END - diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c deleted file mode 100644 index 9d87d4e440ea..000000000000 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ /dev/null @@ -1,897 +0,0 @@ -/* - * TI DaVinci EVM board support - * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/i2c.h> -#include <linux/platform_data/pcf857x.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/property.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/nvmem-provider.h> -#include <linux/phy.h> -#include <linux/clk.h> -#include <linux/videodev2.h> -#include <linux/v4l2-dv-timings.h> -#include <linux/export.h> -#include <linux/leds.h> - -#include <media/i2c/tvp514x.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/mux.h> -#include <mach/serial.h> - -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/usb-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/ti-aemif.h> - -#include "davinci.h" -#include "irqs.h" - -#define DM644X_EVM_PHY_ID "davinci_mdio-0:01" -#define LXT971_PHY_ID (0x001378e2) -#define LXT971_PHY_MASK (0xfffffff0) - -static struct mtd_partition davinci_evm_norflash_partitions[] = { - /* bootloader (UBL, U-Boot, etc) in first 5 sectors */ - { - .name = "bootloader", - .offset = 0, - .size = 5 * SZ_64K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next 1 sectors */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data davinci_evm_norflash_data = { - .width = 2, - .parts = davinci_evm_norflash_partitions, - .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions), -}; - -/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF - * limits addresses to 16M, so using addresses past 16M will wrap */ -static struct resource davinci_evm_norflash_resource = { - .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device davinci_evm_norflash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &davinci_evm_norflash_data, - }, - .num_resources = 1, - .resource = &davinci_evm_norflash_resource, -}; - -/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks). - * It may used instead of the (default) NOR chip to boot, using TI's - * tools to install the secondary boot loader (UBL) and U-Boot. - */ -static struct mtd_partition davinci_evm_nandflash_partition[] = { - /* Bootloader layout depends on whose u-boot is installed, but we - * can hide all the details. - * - block 0 for u-boot environment ... in mainline u-boot - * - block 1 for UBL (plus up to four backup copies in blocks 2..5) - * - blocks 6...? for u-boot - * - blocks 16..23 for u-boot environment ... in TI's u-boot - */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_256K + SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* Kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, - /* File system (older GIT kernels started this on the 5MB mark) */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* A few blocks at end hold a flash BBT ... created by TI's CCS - * using flashwriter_nand.out, but ignored by TI's versions of - * Linux and u-boot. We boot faster by using them. - */ -}; - -static struct davinci_aemif_timing davinci_evm_nandflash_timing = { - .wsetup = 20, - .wstrobe = 40, - .whold = 20, - .rsetup = 10, - .rstrobe = 40, - .rhold = 10, - .ta = 40, -}; - -static struct davinci_nand_pdata davinci_evm_nandflash_data = { - .core_chipsel = 0, - .parts = davinci_evm_nandflash_partition, - .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), - .ecc_mode = NAND_ECC_HW, - .ecc_bits = 1, - .bbt_options = NAND_BBT_USE_FLASH, - .timing = &davinci_evm_nandflash_timing, -}; - -static struct resource davinci_evm_nandflash_resource[] = { - { - .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM644X_ASYNC_EMIF_CONTROL_BASE, - .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource davinci_evm_aemif_resource[] = { - { - .start = DM644X_ASYNC_EMIF_CONTROL_BASE, - .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data davinci_evm_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct platform_device davinci_evm_nandflash_devices[] = { - { - .name = "davinci_nand", - .id = 0, - .dev = { - .platform_data = &davinci_evm_nandflash_data, - }, - .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), - .resource = davinci_evm_nandflash_resource, - }, -}; - -static struct aemif_platform_data davinci_evm_aemif_pdata = { - .abus_data = davinci_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data), - .sub_devices = davinci_evm_nandflash_devices, - .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices), -}; - -static struct platform_device davinci_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &davinci_evm_aemif_pdata, - }, - .resource = davinci_evm_aemif_resource, - .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource), -}; - -static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device davinci_fb_device = { - .name = "davincifb", - .id = -1, - .dev = { - .dma_mask = &davinci_fb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = 0, -}; - -static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input dm644xevm_tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route dm644xevm_tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, - { - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs), - .inputs = dm644xevm_tvp5146_inputs, - .routes = dm644xevm_tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &dm644xevm_tvp5146_pdata, - }, - }, -}; - -static struct vpfe_config dm644xevm_capture_cfg = { - .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs), - .i2c_adapter_id = 1, - .sub_devs = dm644xevm_vpfe_sub_devs, - .card_name = "DM6446 EVM", - .ccdc = "DM6446 CCDC", -}; - -static struct platform_device rtc_dev = { - .name = "rtc_davinci_evm", - .id = -1, -}; - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_I2C -/* - * I2C GPIO expanders - */ - -#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8)) - - -/* U2 -- LEDs */ - -static struct gpio_led evm_leds[] = { - { .name = "DS8", .active_low = 1, - .default_trigger = "heartbeat", }, - { .name = "DS7", .active_low = 1, }, - { .name = "DS6", .active_low = 1, }, - { .name = "DS5", .active_low = 1, }, - { .name = "DS4", .active_low = 1, }, - { .name = "DS3", .active_low = 1, }, - { .name = "DS2", .active_low = 1, - .default_trigger = "mmc0", }, - { .name = "DS1", .active_low = 1, - .default_trigger = "disk-activity", }, -}; - -static const struct gpio_led_platform_data evm_led_data = { - .num_leds = ARRAY_SIZE(evm_leds), - .leds = evm_leds, -}; - -static struct platform_device *evm_led_dev; - -static int -evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) -{ - struct gpio_led *leds = evm_leds; - int status; - - while (ngpio--) { - leds->gpio = gpio++; - leds++; - } - - /* what an extremely annoying way to be forced to handle - * device unregistration ... - */ - evm_led_dev = platform_device_alloc("leds-gpio", 0); - platform_device_add_data(evm_led_dev, - &evm_led_data, sizeof evm_led_data); - - evm_led_dev->dev.parent = &client->dev; - status = platform_device_add(evm_led_dev); - if (status < 0) { - platform_device_put(evm_led_dev); - evm_led_dev = NULL; - } - return status; -} - -static int -evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) -{ - if (evm_led_dev) { - platform_device_unregister(evm_led_dev); - evm_led_dev = NULL; - } - return 0; -} - -static struct pcf857x_platform_data pcf_data_u2 = { - .gpio_base = PCF_Uxx_BASE(0), - .setup = evm_led_setup, - .teardown = evm_led_teardown, -}; - - -/* U18 - A/V clock generator and user switch */ - -static int sw_gpio; - -static ssize_t -sw_show(struct device *d, struct device_attribute *a, char *buf) -{ - char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n"; - - strcpy(buf, s); - return strlen(s); -} - -static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL); - -static int -evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) -{ - int status; - - /* export dip switch option */ - sw_gpio = gpio + 7; - status = gpio_request(sw_gpio, "user_sw"); - if (status == 0) - status = gpio_direction_input(sw_gpio); - if (status == 0) - status = device_create_file(&client->dev, &dev_attr_user_sw); - else - gpio_free(sw_gpio); - if (status != 0) - sw_gpio = -EINVAL; - - /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */ - gpio_request(gpio + 3, "pll_fs2"); - gpio_direction_output(gpio + 3, 0); - - gpio_request(gpio + 2, "pll_fs1"); - gpio_direction_output(gpio + 2, 0); - - gpio_request(gpio + 1, "pll_sr"); - gpio_direction_output(gpio + 1, 0); - - return 0; -} - -static int -evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) -{ - gpio_free(gpio + 1); - gpio_free(gpio + 2); - gpio_free(gpio + 3); - - if (sw_gpio > 0) { - device_remove_file(&client->dev, &dev_attr_user_sw); - gpio_free(sw_gpio); - } - return 0; -} - -static struct pcf857x_platform_data pcf_data_u18 = { - .gpio_base = PCF_Uxx_BASE(1), - .n_latch = (1 << 3) | (1 << 2) | (1 << 1), - .setup = evm_u18_setup, - .teardown = evm_u18_teardown, -}; - - -/* U35 - various I/O signals used to manage USB, CF, ATA, etc */ - -static int -evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) -{ - /* p0 = nDRV_VBUS (initial: don't supply it) */ - gpio_request(gpio + 0, "nDRV_VBUS"); - gpio_direction_output(gpio + 0, 1); - - /* p1 = VDDIMX_EN */ - gpio_request(gpio + 1, "VDDIMX_EN"); - gpio_direction_output(gpio + 1, 1); - - /* p2 = VLYNQ_EN */ - gpio_request(gpio + 2, "VLYNQ_EN"); - gpio_direction_output(gpio + 2, 1); - - /* p3 = n3V3_CF_RESET (initial: stay in reset) */ - gpio_request(gpio + 3, "nCF_RESET"); - gpio_direction_output(gpio + 3, 0); - - /* (p4 unused) */ - - /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */ - gpio_request(gpio + 5, "WLAN_RESET"); - gpio_direction_output(gpio + 5, 1); - - /* p6 = nATA_SEL (initial: select) */ - gpio_request(gpio + 6, "nATA_SEL"); - gpio_direction_output(gpio + 6, 0); - - /* p7 = nCF_SEL (initial: deselect) */ - gpio_request(gpio + 7, "nCF_SEL"); - gpio_direction_output(gpio + 7, 1); - - return 0; -} - -static int -evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) -{ - gpio_free(gpio + 7); - gpio_free(gpio + 6); - gpio_free(gpio + 5); - gpio_free(gpio + 3); - gpio_free(gpio + 2); - gpio_free(gpio + 1); - gpio_free(gpio + 0); - return 0; -} - -static struct pcf857x_platform_data pcf_data_u35 = { - .gpio_base = PCF_Uxx_BASE(2), - .setup = evm_u35_setup, - .teardown = evm_u35_teardown, -}; - -/*----------------------------------------------------------------------*/ - -/* Most of this EEPROM is unused, but U-Boot uses some data: - * - 0x7f00, 6 bytes Ethernet Address - * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) - * - ... newer boards may have more - */ - -static struct nvmem_cell_info dm644evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table dm644evm_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = dm644evm_nvmem_cells, - .ncells = ARRAY_SIZE(dm644evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -/* - * MSP430 supports RTC, card detection, input from IR remote, and - * a bit more. It triggers interrupts on GPIO(7) from pressing - * buttons on the IR remote, and for card detect switches. - */ -static struct i2c_client *dm6446evm_msp; - -static int dm6446evm_msp_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - dm6446evm_msp = client; - return 0; -} - -static int dm6446evm_msp_remove(struct i2c_client *client) -{ - dm6446evm_msp = NULL; - return 0; -} - -static const struct i2c_device_id dm6446evm_msp_ids[] = { - { "dm6446evm_msp", 0, }, - { /* end of list */ }, -}; - -static struct i2c_driver dm6446evm_msp_driver = { - .driver.name = "dm6446evm_msp", - .id_table = dm6446evm_msp_ids, - .probe = dm6446evm_msp_probe, - .remove = dm6446evm_msp_remove, -}; - -static int dm6444evm_msp430_get_pins(void) -{ - static const char txbuf[2] = { 2, 4, }; - char buf[4]; - struct i2c_msg msg[2] = { - { - .flags = 0, - .len = 2, - .buf = (void __force *)txbuf, - }, - { - .flags = I2C_M_RD, - .len = 4, - .buf = buf, - }, - }; - int status; - - if (!dm6446evm_msp) - return -ENXIO; - - msg[0].addr = dm6446evm_msp->addr; - msg[1].addr = dm6446evm_msp->addr; - - /* Command 4 == get input state, returns port 2 and port3 data - * S Addr W [A] len=2 [A] cmd=4 [A] - * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P - */ - status = i2c_transfer(dm6446evm_msp->adapter, msg, 2); - if (status < 0) - return status; - - dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf); - - return (buf[3] << 8) | buf[2]; -} - -static int dm6444evm_mmc_get_cd(int module) -{ - int status = dm6444evm_msp430_get_pins(); - - return (status < 0) ? status : !(status & BIT(1)); -} - -static int dm6444evm_mmc_get_ro(int module) -{ - int status = dm6444evm_msp430_get_pins(); - - return (status < 0) ? status : status & BIT(6 + 8); -} - -static struct davinci_mmc_config dm6446evm_mmc_config = { - .get_cd = dm6444evm_mmc_get_cd, - .get_ro = dm6444evm_mmc_get_ro, - .wires = 4, -}; - -static struct i2c_board_info __initdata i2c_info[] = { - { - I2C_BOARD_INFO("dm6446evm_msp", 0x23), - }, - { - I2C_BOARD_INFO("pcf8574", 0x38), - .platform_data = &pcf_data_u2, - }, - { - I2C_BOARD_INFO("pcf8574", 0x39), - .platform_data = &pcf_data_u18, - }, - { - I2C_BOARD_INFO("pcf8574", 0x3a), - .platform_data = &pcf_data_u35, - }, - { - I2C_BOARD_INFO("24c256", 0x50), - .properties = eeprom_properties, - }, - { - I2C_BOARD_INFO("tlv320aic33", 0x1b), - }, -}; - -#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12) -#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11) - -static struct gpiod_lookup_table i2c_recovery_gpiod_table = { - .dev_id = "i2c_davinci.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - { } - }, -}; - -/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), - * which requires 100 usec of idle bus after i2c writes sent to it. - */ -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 20 /* kHz */, - .bus_delay = 100 /* usec */, - .gpio_recovery = true, -}; - -static void __init evm_init_i2c(void) -{ - gpiod_add_lookup_table(&i2c_recovery_gpiod_table); - davinci_init_i2c(&i2c_pdata); - i2c_add_driver(&dm6446evm_msp_driver); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} -#endif - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* venc standard timings */ -static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7e, - .upper_margin = 0x16, - }, -}; - -/* venc dv preset timings */ -static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = { - { - .name = "480p59_94", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, - .interlaced = 0, - .xres = 720, - .yres = 480, - .aspect = {1, 1}, - .fps = {5994, 100}, - .left_margin = 0x80, - .upper_margin = 0x20, - }, - { - .name = "576p50", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X576P50, - .interlaced = 0, - .xres = 720, - .yres = 576, - .aspect = {1, 1}, - .fps = {50, 1}, - .left_margin = 0x7e, - .upper_margin = 0x30, - }, -}; - -/* - * The outputs available from VPBE + encoders. Keep the order same - * as that of encoders. First those from venc followed by that from - * encoders. Index in the output refers to index on a particular encoder. - * Driver uses this index to pass it to encoder when it supports more - * than one output. Userspace applications use index of the array to - * set an output. - */ -static struct vpbe_output dm644xevm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing), - .modes = dm644xevm_enc_std_timing, - }, - { - .output = { - .index = 1, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, - }, - .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME, - .default_mode = "480p59_94", - .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing), - .modes = dm644xevm_enc_preset_timing, - }, -}; - -static struct vpbe_config dm644xevm_display_cfg = { - .module_name = "dm644x-vpbe-display", - .i2c_adapter_id = 1, - .osd = { - .module_name = DM644X_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM644X_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs), - .outputs = dm644xevm_vpbe_outputs, -}; - -static struct platform_device *davinci_evm_devices[] __initdata = { - &davinci_fb_device, - &rtc_dev, -}; - -static void __init -davinci_evm_map_io(void) -{ - dm644x_init(); -} - -static int davinci_phy_fixup(struct phy_device *phydev) -{ - unsigned int control; - /* CRITICAL: Fix for increasing PHY signal drive strength for - * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY - * signal strength was low causing TX to fail randomly. The - * fix is to Set bit 11 (Increased MII drive strength) of PHY - * register 26 (Digital Config register) on this phy. */ - control = phy_read(phydev, 26); - phy_write(phydev, 26, (control | 0x800)); - return 0; -} - -#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - IS_ENABLED(CONFIG_PATA_BK3710)) - -#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP) - -#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI) - -static __init void davinci_evm_init(void) -{ - int ret; - struct clk *aemif_clk; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - dm644x_register_clocks(); - - dm644x_init_devices(); - - ret = dm644x_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - aemif_clk = clk_get(NULL, "aemif"); - clk_prepare_enable(aemif_clk); - - if (HAS_ATA) { - if (HAS_NAND || HAS_NOR) - pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n" - "\tDisable IDE for NAND/NOR support\n"); - davinci_init_ide(); - } else if (HAS_NAND || HAS_NOR) { - davinci_cfg_reg(DM644X_HPIEN_DISABLE); - davinci_cfg_reg(DM644X_ATAEN_DISABLE); - - /* only one device will be jumpered and detected */ - if (HAS_NAND) { - platform_device_register(&davinci_evm_aemif_device); -#ifdef CONFIG_I2C - evm_leds[7].default_trigger = "nand-disk"; -#endif - if (HAS_NOR) - pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n"); - } else if (HAS_NOR) - platform_device_register(&davinci_evm_norflash_device); - } - - platform_add_devices(davinci_evm_devices, - ARRAY_SIZE(davinci_evm_devices)); -#ifdef CONFIG_I2C - nvmem_add_cell_table(&dm644evm_nvmem_cell_table); - nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1); - evm_init_i2c(); - davinci_setup_mmc(0, &dm6446evm_mmc_config); -#endif - dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); - - davinci_serial_init(dm644x_serial_device); - dm644x_init_asp(); - - /* irlml6401 switches over 1A, in under 8 msec */ - davinci_setup_usb(1000, 8); - - if (IS_BUILTIN(CONFIG_PHYLIB)) { - soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; - /* Register the fixup for PHY on DaVinci */ - phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, - davinci_phy_fixup); - } -} - -MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") - /* Maintainer: MontaVista Software <source@mvista.com> */ - .atag_offset = 0x100, - .map_io = davinci_evm_map_io, - .init_irq = dm644x_init_irq, - .init_time = dm644x_init_time, - .init_machine = davinci_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c deleted file mode 100644 index 4600b617f9b4..000000000000 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ /dev/null @@ -1,879 +0,0 @@ -/* - * TI DaVinci DM646X EVM board - * - * Derived from: arch/arm/mach-davinci/board-evm.c - * Copyright (C) 2006 Texas Instruments. - * - * (C) 2007-2008, MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - * - */ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/property.h> -#include <linux/platform_data/pcf857x.h> -#include <linux/platform_data/ti-aemif.h> - -#include <media/i2c/tvp514x.h> -#include <media/i2c/adv7343.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/partitions.h> -#include <linux/nvmem-provider.h> -#include <linux/clk.h> -#include <linux/export.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/serial.h> - -#include "davinci.h" -#include "irqs.h" - -#define NAND_BLOCK_SIZE SZ_128K - -/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot - * and U-Boot environment this avoids dependency on any particular combination - * of UBL, U-Boot or flashing tools etc. - */ -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL, U-Boot with environment */ - .name = "bootloader", - .offset = MTDPART_OFS_APPEND, - .size = 16 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } -}; - -static struct davinci_aemif_timing dm6467tevm_nandflash_timing = { - .wsetup = 29, - .wstrobe = 24, - .whold = 14, - .rsetup = 19, - .rstrobe = 33, - .rhold = 0, - .ta = 29, -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_cle = 0x80000, - .mask_ale = 0x40000, - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW, - .ecc_bits = 1, - .options = 0, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE, - .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM646X_ASYNC_EMIF_CONTROL_BASE, - .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 0, - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - .dev = { - .platform_data = &davinci_nand_data, - }, - }, -}; - -static struct resource davinci_aemif_resources[] = { - { - .start = DM646X_ASYNC_EMIF_CONTROL_BASE, - .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data davinci_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data davinci_aemif_pdata = { - .abus_data = davinci_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(davinci_aemif_abus_data), - .sub_devices = davinci_aemif_devices, - .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices), -}; - -static struct platform_device davinci_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &davinci_aemif_pdata, - }, - .resource = davinci_aemif_resources, - .num_resources = ARRAY_SIZE(davinci_aemif_resources), -}; - -#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - IS_ENABLED(CONFIG_PATA_BK3710)) - -#ifdef CONFIG_I2C -/* CPLD Register 0 bits to control ATA */ -#define DM646X_EVM_ATA_RST BIT(0) -#define DM646X_EVM_ATA_PWD BIT(1) - -/* CPLD Register 0 Client: used for I/O Control */ -static int cpld_reg0_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - if (HAS_ATA) { - u8 data; - struct i2c_msg msg[2] = { - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = 1, - .buf = &data, - }, - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = &data, - }, - }; - - /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */ - i2c_transfer(client->adapter, msg, 1); - data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD); - i2c_transfer(client->adapter, msg + 1, 1); - } - - return 0; -} - -static const struct i2c_device_id cpld_reg_ids[] = { - { "cpld_reg0", 0, }, - { }, -}; - -static struct i2c_driver dm6467evm_cpld_driver = { - .driver.name = "cpld_reg0", - .id_table = cpld_reg_ids, - .probe = cpld_reg0_probe, -}; - -/* LEDS */ - -static struct gpio_led evm_leds[] = { - { .name = "DS1", .active_low = 1, }, - { .name = "DS2", .active_low = 1, }, - { .name = "DS3", .active_low = 1, }, - { .name = "DS4", .active_low = 1, }, -}; - -static const struct gpio_led_platform_data evm_led_data = { - .num_leds = ARRAY_SIZE(evm_leds), - .leds = evm_leds, -}; - -static struct platform_device *evm_led_dev; - -static int evm_led_setup(struct i2c_client *client, int gpio, - unsigned int ngpio, void *c) -{ - struct gpio_led *leds = evm_leds; - int status; - - while (ngpio--) { - leds->gpio = gpio++; - leds++; - } - - evm_led_dev = platform_device_alloc("leds-gpio", 0); - platform_device_add_data(evm_led_dev, &evm_led_data, - sizeof(evm_led_data)); - - evm_led_dev->dev.parent = &client->dev; - status = platform_device_add(evm_led_dev); - if (status < 0) { - platform_device_put(evm_led_dev); - evm_led_dev = NULL; - } - return status; -} - -static int evm_led_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *c) -{ - if (evm_led_dev) { - platform_device_unregister(evm_led_dev); - evm_led_dev = NULL; - } - return 0; -} - -static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL }; - -static int evm_sw_setup(struct i2c_client *client, int gpio, - unsigned ngpio, void *c) -{ - int status; - int i; - char label[10]; - - for (i = 0; i < 4; ++i) { - snprintf(label, 10, "user_sw%d", i); - status = gpio_request(gpio, label); - if (status) - goto out_free; - evm_sw_gpio[i] = gpio++; - - status = gpio_direction_input(evm_sw_gpio[i]); - if (status) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - goto out_free; - } - - status = gpio_export(evm_sw_gpio[i], 0); - if (status) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - goto out_free; - } - } - return status; -out_free: - for (i = 0; i < 4; ++i) { - if (evm_sw_gpio[i] != -EINVAL) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - } - } - return status; -} - -static int evm_sw_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *c) -{ - int i; - - for (i = 0; i < 4; ++i) { - if (evm_sw_gpio[i] != -EINVAL) { - gpio_unexport(evm_sw_gpio[i]); - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; - } - } - return 0; -} - -static int evm_pcf_setup(struct i2c_client *client, int gpio, - unsigned int ngpio, void *c) -{ - int status; - - if (ngpio < 8) - return -EINVAL; - - status = evm_sw_setup(client, gpio, 4, c); - if (status) - return status; - - return evm_led_setup(client, gpio+4, 4, c); -} - -static int evm_pcf_teardown(struct i2c_client *client, int gpio, - unsigned int ngpio, void *c) -{ - BUG_ON(ngpio < 8); - - evm_sw_teardown(client, gpio, 4, c); - evm_led_teardown(client, gpio+4, 4, c); - - return 0; -} - -static struct pcf857x_platform_data pcf_data = { - .gpio_base = DAVINCI_N_GPIO+1, - .setup = evm_pcf_setup, - .teardown = evm_pcf_teardown, -}; - -/* Most of this EEPROM is unused, but U-Boot uses some data: - * - 0x7f00, 6 bytes Ethernet Address - * - ... newer boards may have more - */ - -static struct nvmem_cell_info dm646x_evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table dm646x_evm_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = dm646x_evm_nvmem_cells, - .ncells = ARRAY_SIZE(dm646x_evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; -#endif - -static u8 dm646x_iis_serializer_direction[] = { - TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static u8 dm646x_dit_serializer_direction[] = { - TX_MODE, -}; - -static struct snd_platform_data dm646x_evm_snd_data[] = { - { - .tx_dma_offset = 0x400, - .rx_dma_offset = 0x400, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = dm646x_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - }, - { - .tx_dma_offset = 0x400, - .rx_dma_offset = 0, - .op_mode = DAVINCI_MCASP_DIT_MODE, - .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), - .tdm_slots = 32, - .serial_dir = dm646x_dit_serializer_direction, - .asp_chan_q = EVENTQ_0, - }, -}; - -#ifdef CONFIG_I2C -static struct i2c_client *cpld_client; - -static int cpld_video_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - cpld_client = client; - return 0; -} - -static int cpld_video_remove(struct i2c_client *client) -{ - cpld_client = NULL; - return 0; -} - -static const struct i2c_device_id cpld_video_id[] = { - { "cpld_video", 0 }, - { } -}; - -static struct i2c_driver cpld_video_driver = { - .driver = { - .name = "cpld_video", - }, - .probe = cpld_video_probe, - .remove = cpld_video_remove, - .id_table = cpld_video_id, -}; - -static void evm_init_cpld(void) -{ - i2c_add_driver(&cpld_video_driver); -} - -static struct i2c_board_info __initdata i2c_info[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .properties = eeprom_properties, - }, - { - I2C_BOARD_INFO("pcf8574a", 0x38), - .platform_data = &pcf_data, - }, - { - I2C_BOARD_INFO("cpld_reg0", 0x3a), - }, - { - I2C_BOARD_INFO("tlv320aic33", 0x18), - }, - { - I2C_BOARD_INFO("cpld_video", 0x3b), - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 100 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) -#define VCH2CLK_SYSCLK8 (BIT(9)) -#define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) -#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12)) -#define VCH3CLK_SYSCLK8 (BIT(13)) -#define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) - -#define VIDCH2CLK (BIT(10)) -#define VIDCH3CLK (BIT(11)) -#define VIDCH1CLK (BIT(4)) -#define TVP7002_INPUT (BIT(4)) -#define TVP5147_INPUT (~BIT(4)) -#define VPIF_INPUT_ONE_CHANNEL (BIT(5)) -#define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) -#define TVP5147_CH0 "tvp514x-0" -#define TVP5147_CH1 "tvp514x-1" - -/* spin lock for updating above registers */ -static spinlock_t vpif_reg_lock; - -static int set_vpif_clock(int mux_mode, int hd) -{ - unsigned long flags; - unsigned int value; - int val = 0; - int err = 0; - - if (!cpld_client) - return -ENXIO; - - /* disable the clock */ - spin_lock_irqsave(&vpif_reg_lock, flags); - value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); - value |= (VIDCH3CLK | VIDCH2CLK); - __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); - spin_unlock_irqrestore(&vpif_reg_lock, flags); - - val = i2c_smbus_read_byte(cpld_client); - if (val < 0) - return val; - - if (mux_mode == 1) - val &= ~0x40; - else - val |= 0x40; - - err = i2c_smbus_write_byte(cpld_client, val); - if (err) - return err; - - value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); - value &= ~(VCH2CLK_MASK); - value &= ~(VCH3CLK_MASK); - - if (hd >= 1) - value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8); - else - value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); - - __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); - - spin_lock_irqsave(&vpif_reg_lock, flags); - value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); - /* enable the clock */ - value &= ~(VIDCH3CLK | VIDCH2CLK); - __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); - spin_unlock_irqrestore(&vpif_reg_lock, flags); - - return 0; -} - -static struct vpif_subdev_info dm646x_vpif_subdev[] = { - { - .name = "adv7343", - .board_info = { - I2C_BOARD_INFO("adv7343", 0x2a), - }, - }, - { - .name = "ths7303", - .board_info = { - I2C_BOARD_INFO("ths7303", 0x2c), - }, - }, -}; - -static const struct vpif_output dm6467_ch0_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPOSITE_ID, - }, - { - .output = { - .index = 1, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPONENT_ID, - }, - { - .output = { - .index = 2, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_SVIDEO_ID, - }, -}; - -static struct vpif_display_config dm646x_vpif_display_config = { - .set_clock = set_vpif_clock, - .subdevinfo = dm646x_vpif_subdev, - .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), - .i2c_adapter_id = 1, - .chan_config[0] = { - .outputs = dm6467_ch0_outputs, - .output_count = ARRAY_SIZE(dm6467_ch0_outputs), - }, - .card_name = "DM646x EVM Video Display", -}; - -/** - * setup_vpif_input_path() - * @channel: channel id (0 - CH0, 1 - CH1) - * @sub_dev_name: ptr sub device name - * - * This will set vpif input to capture data from tvp514x or - * tvp7002. - */ -static int setup_vpif_input_path(int channel, const char *sub_dev_name) -{ - int err = 0; - int val; - - /* for channel 1, we don't do anything */ - if (channel != 0) - return 0; - - if (!cpld_client) - return -ENXIO; - - val = i2c_smbus_read_byte(cpld_client); - if (val < 0) - return val; - - if (!strcmp(sub_dev_name, TVP5147_CH0) || - !strcmp(sub_dev_name, TVP5147_CH1)) - val &= TVP5147_INPUT; - else - val |= TVP7002_INPUT; - - err = i2c_smbus_write_byte(cpld_client, val); - if (err) - return err; - return 0; -} - -/** - * setup_vpif_input_channel_mode() - * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel - * - * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147) - */ -static int setup_vpif_input_channel_mode(int mux_mode) -{ - unsigned long flags; - int err = 0; - int val; - u32 value; - - if (!cpld_client) - return -ENXIO; - - val = i2c_smbus_read_byte(cpld_client); - if (val < 0) - return val; - - spin_lock_irqsave(&vpif_reg_lock, flags); - value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); - if (mux_mode) { - val &= VPIF_INPUT_TWO_CHANNEL; - value |= VIDCH1CLK; - } else { - val |= VPIF_INPUT_ONE_CHANNEL; - value &= ~VIDCH1CLK; - } - __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); - spin_unlock_irqrestore(&vpif_reg_lock, flags); - - err = i2c_smbus_write_byte(cpld_client, val); - if (err) - return err; - - return 0; -} - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -static struct vpif_subdev_info vpif_capture_sdev_info[] = { - { - .name = TVP5147_CH0, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, - { - .name = TVP5147_CH1, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5c), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpif_input dm6467_ch0_inputs[] = { - { - .input = { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .subdev_name = TVP5147_CH0, - .input_route = INPUT_CVBS_VI2B, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpif_input dm6467_ch1_inputs[] = { - { - .input = { - .index = 0, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .subdev_name = TVP5147_CH1, - .input_route = INPUT_SVIDEO_VI2C_VI1C, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpif_capture_config dm646x_vpif_capture_cfg = { - .setup_input_path = setup_vpif_input_path, - .setup_input_channel_mode = setup_vpif_input_channel_mode, - .subdev_info = vpif_capture_sdev_info, - .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info), - .i2c_adapter_id = 1, - .chan_config[0] = { - .inputs = dm6467_ch0_inputs, - .input_count = ARRAY_SIZE(dm6467_ch0_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .chan_config[1] = { - .inputs = dm6467_ch1_inputs, - .input_count = ARRAY_SIZE(dm6467_ch1_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .card_name = "DM646x EVM Video Capture", -}; - -static void __init evm_init_video(void) -{ - spin_lock_init(&vpif_reg_lock); - - dm646x_setup_vpif(&dm646x_vpif_display_config, - &dm646x_vpif_capture_cfg); -} - -static void __init evm_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_add_driver(&dm6467evm_cpld_driver); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); - evm_init_cpld(); - evm_init_video(); -} -#endif - -#define DM646X_REF_FREQ 27000000 -#define DM646X_AUX_FREQ 24000000 -#define DM6467T_EVM_REF_FREQ 33000000 - -static void __init davinci_map_io(void) -{ - dm646x_init(); -} - -static void __init dm646x_evm_init_time(void) -{ - dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ); -} - -static void __init dm6467t_evm_init_time(void) -{ - dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ); -} - -#define DM646X_EVM_PHY_ID "davinci_mdio-0:01" -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on dm646x, hence they are being - * reserved for codecs on the DSP side. - */ -static const s16 dm646x_dma_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 4}, - {13, 3}, - {24, 4}, - {30, 2}, - {54, 3}, - {-1, -1} -}; - -static const s16 dm646x_dma_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 4}, - {13, 3}, - {24, 4}, - {30, 2}, - {54, 3}, - {128, 384}, - {-1, -1} -}; - -static struct edma_rsv_info dm646x_edma_rsv[] = { - { - .rsv_chans = dm646x_dma_rsv_chans, - .rsv_slots = dm646x_dma_rsv_slots, - }, -}; - -static __init void evm_init(void) -{ - int ret; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - dm646x_register_clocks(); - - ret = dm646x_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - -#ifdef CONFIG_I2C - nvmem_add_cell_table(&dm646x_evm_nvmem_cell_table); - nvmem_add_cell_lookups(&dm646x_evm_nvmem_cell_lookup, 1); - evm_init_i2c(); -#endif - - davinci_serial_init(dm646x_serial_device); - dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); - dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); - - if (machine_is_davinci_dm6467tevm()) - davinci_nand_data.timing = &dm6467tevm_nandflash_timing; - - if (platform_device_register(&davinci_aemif_device)) - pr_warn("%s: Cannot register AEMIF device.\n", __func__); - - dm646x_init_edma(dm646x_edma_rsv); - - if (HAS_ATA) - davinci_init_ide(); - - soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; -} - -MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") - .atag_offset = 0x100, - .map_io = davinci_map_io, - .init_irq = dm646x_init_irq, - .init_time = dm646x_evm_init_time, - .init_machine = evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END - -MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") - .atag_offset = 0x100, - .map_io = davinci_map_io, - .init_irq = dm646x_init_irq, - .init_time = dm6467t_evm_init_time, - .init_machine = evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END - diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c deleted file mode 100644 index dfce421c0579..000000000000 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ /dev/null @@ -1,635 +0,0 @@ -/* - * Critical Link MityOMAP-L138 SoM - * - * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of - * any kind, whether express or implied. - */ - -#define pr_fmt(fmt) "MityOMAPL138: " fmt - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/console.h> -#include <linux/platform_device.h> -#include <linux/property.h> -#include <linux/mtd/partitions.h> -#include <linux/notifier.h> -#include <linux/nvmem-consumer.h> -#include <linux/nvmem-provider.h> -#include <linux/regulator/machine.h> -#include <linux/i2c.h> -#include <linux/etherdevice.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> - -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/common.h> -#include <mach/da8xx.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/ti-aemif.h> -#include <mach/mux.h> -#include <linux/platform_data/spi-davinci.h> - -#define MITYOMAPL138_PHY_ID "" - -#define FACTORY_CONFIG_MAGIC 0x012C0138 -#define FACTORY_CONFIG_VERSION 0x00010001 - -/* Data Held in On-Board I2C device */ -struct factory_config { - u32 magic; - u32 version; - u8 mac[6]; - u32 fpga_type; - u32 spare; - u32 serialnumber; - char partnum[32]; -}; - -static struct factory_config factory_config; - -#ifdef CONFIG_CPU_FREQ -struct part_no_info { - const char *part_no; /* part number string of interest */ - int max_freq; /* khz */ -}; - -static struct part_no_info mityomapl138_pn_info[] = { - { - .part_no = "L138-C", - .max_freq = 300000, - }, - { - .part_no = "L138-D", - .max_freq = 375000, - }, - { - .part_no = "L138-F", - .max_freq = 456000, - }, - { - .part_no = "1808-C", - .max_freq = 300000, - }, - { - .part_no = "1808-D", - .max_freq = 375000, - }, - { - .part_no = "1808-F", - .max_freq = 456000, - }, - { - .part_no = "1810-D", - .max_freq = 375000, - }, -}; - -static void mityomapl138_cpufreq_init(const char *partnum) -{ - int i, ret; - - for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) { - /* - * the part number has additional characters beyond what is - * stored in the table. This information is not needed for - * determining the speed grade, and would require several - * more table entries. Only check the first N characters - * for a match. - */ - if (!strncmp(partnum, mityomapl138_pn_info[i].part_no, - strlen(mityomapl138_pn_info[i].part_no))) { - da850_max_speed = mityomapl138_pn_info[i].max_freq; - break; - } - } - - ret = da850_register_cpufreq("pll0_sysclk3"); - if (ret) - pr_warn("cpufreq registration failed: %d\n", ret); -} -#else -static void mityomapl138_cpufreq_init(const char *partnum) { } -#endif - -static int read_factory_config(struct notifier_block *nb, - unsigned long event, void *data) -{ - int ret; - const char *partnum = NULL; - struct nvmem_device *nvmem = data; - - if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0) - return NOTIFY_DONE; - - if (!IS_BUILTIN(CONFIG_NVMEM)) { - pr_warn("Factory Config not available without CONFIG_NVMEM\n"); - goto bad_config; - } - - ret = nvmem_device_read(nvmem, 0, sizeof(factory_config), - &factory_config); - if (ret != sizeof(struct factory_config)) { - pr_warn("Read Factory Config Failed: %d\n", ret); - goto bad_config; - } - - if (factory_config.magic != FACTORY_CONFIG_MAGIC) { - pr_warn("Factory Config Magic Wrong (%X)\n", - factory_config.magic); - goto bad_config; - } - - if (factory_config.version != FACTORY_CONFIG_VERSION) { - pr_warn("Factory Config Version Wrong (%X)\n", - factory_config.version); - goto bad_config; - } - - partnum = factory_config.partnum; - pr_info("Part Number = %s\n", partnum); - -bad_config: - /* default maximum speed is valid for all platforms */ - mityomapl138_cpufreq_init(partnum); - - return NOTIFY_STOP; -} - -static struct notifier_block mityomapl138_nvmem_notifier = { - .notifier_call = read_factory_config, -}; - -/* - * We don't define a cell for factory config as it will be accessed from the - * board file using the nvmem notifier chain. - */ -static struct nvmem_cell_info mityomapl138_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x64, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table mityomapl138_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = mityomapl138_nvmem_cells, - .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells), -}; - -static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry mityomapl138_fd_chip_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 8), - PROPERTY_ENTRY_BOOL("read-only"), - { } -}; - -static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* TPS65023 voltage regulator support */ -/* 1.2V Core */ -static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { - { - .supply = "cvdd", - }, -}; - -/* 1.8V */ -static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { - { - .supply = "usb0_vdda18", - }, - { - .supply = "usb1_vdda18", - }, - { - .supply = "ddr_dvdd18", - }, - { - .supply = "sata_vddr", - }, -}; - -/* 1.2V */ -static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { - { - .supply = "sata_vdd", - }, - { - .supply = "usb_cvdd", - }, - { - .supply = "pll0_vdda", - }, - { - .supply = "pll1_vdda", - }, -}; - -/* 1.8V Aux LDO, not used */ -static struct regulator_consumer_supply tps65023_ldo1_consumers[] = { - { - .supply = "1.8v_aux", - }, -}; - -/* FPGA VCC Aux (2.5 or 3.3) LDO */ -static struct regulator_consumer_supply tps65023_ldo2_consumers[] = { - { - .supply = "vccaux", - }, -}; - -static struct regulator_init_data tps65023_regulator_data[] = { - /* dcdc1 */ - { - .constraints = { - .min_uV = 1150000, - .max_uV = 1350000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), - .consumer_supplies = tps65023_dcdc1_consumers, - }, - /* dcdc2 */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), - .consumer_supplies = tps65023_dcdc2_consumers, - }, - /* dcdc3 */ - { - .constraints = { - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), - .consumer_supplies = tps65023_dcdc3_consumers, - }, - /* ldo1 */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), - .consumer_supplies = tps65023_ldo1_consumers, - }, - /* ldo2 */ - { - .constraints = { - .min_uV = 2500000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), - .consumer_supplies = tps65023_ldo2_consumers, - }, -}; - -static struct i2c_board_info __initdata mityomap_tps65023_info[] = { - { - I2C_BOARD_INFO("tps65023", 0x48), - .platform_data = &tps65023_regulator_data[0], - }, - { - I2C_BOARD_INFO("24c02", 0x50), - .properties = mityomapl138_fd_chip_properties, - }, -}; - -static int __init pmic_tps65023_init(void) -{ - return i2c_register_board_info(1, mityomap_tps65023_info, - ARRAY_SIZE(mityomap_tps65023_info)); -} - -/* - * SPI Devices: - * SPI1_CS0: 8M Flash ST-M25P64-VME6G - */ -static struct mtd_partition spi_flash_partitions[] = { - [0] = { - .name = "ubl", - .offset = 0, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "u-boot-env", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "periph-config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [4] = { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K + SZ_64K, - }, - [5] = { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M + SZ_1M, - }, - [6] = { - .name = "fpga", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - }, - [7] = { - .name = "spare", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data mityomapl138_spi_flash_data = { - .name = "m25p80", - .parts = spi_flash_partitions, - .nr_parts = ARRAY_SIZE(spi_flash_partitions), - .type = "m24p64", -}; - -static struct davinci_spi_config spi_eprom_config = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info mityomapl138_spi_flash_info[] = { - { - .modalias = "m25p80", - .platform_data = &mityomapl138_spi_flash_data, - .controller_data = &spi_eprom_config, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -/* - * MityDSP-L138 includes a 256 MByte large-page NAND flash - * (128K blocks). - */ -static struct mtd_partition mityomapl138_nandflash_partition[] = { - { - .name = "rootfs", - .offset = 0, - .size = SZ_128M, - .mask_flags = 0, /* MTD_WRITEABLE, */ - }, - { - .name = "homefs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_nand_pdata mityomapl138_nandflash_data = { - .core_chipsel = 1, - .parts = mityomapl138_nandflash_partition, - .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), - .ecc_mode = NAND_ECC_HW, - .bbt_options = NAND_BBT_USE_FLASH, - .options = NAND_BUSWIDTH_16, - .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ -}; - -static struct resource mityomapl138_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mityomapl138_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &mityomapl138_nandflash_data, - }, - .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), - .resource = mityomapl138_nandflash_resource, - }, -}; - -static struct resource mityomapl138_aemif_resources[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data mityomapl138_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data mityomapl138_aemif_pdata = { - .abus_data = mityomapl138_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data), - .sub_devices = mityomapl138_aemif_devices, - .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices), -}; - -static struct platform_device mityomapl138_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &mityomapl138_aemif_pdata, - }, - .resource = mityomapl138_aemif_resources, - .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources), -}; - -static void __init mityomapl138_setup_nand(void) -{ - if (platform_device_register(&mityomapl138_aemif_device)) - pr_warn("%s: Cannot register AEMIF device\n", __func__); -} - -static const short mityomap_mii_pins[] = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static const short mityomap_rmii_pins[] = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static void __init mityomapl138_config_emac(void) -{ - void __iomem *cfg_chip3_base; - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ - - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - val = __raw_readl(cfg_chip3_base); - - if (soc_info->emac_pdata->rmii_en) { - val |= BIT(8); - ret = davinci_cfg_reg_list(mityomap_rmii_pins); - pr_info("RMII PHY configured\n"); - } else { - val &= ~BIT(8); - ret = davinci_cfg_reg_list(mityomap_mii_pins); - pr_info("MII PHY configured\n"); - } - - if (ret) { - pr_warn("mii/rmii mux setup failed: %d\n", ret); - return; - } - - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("emac registration failed: %d\n", ret); -} - -static void __init mityomapl138_init(void) -{ - int ret; - - da850_register_clocks(); - - /* for now, no special EDMA channels are reserved */ - ret = da850_register_edma(NULL); - if (ret) - pr_warn("edma registration failed: %d\n", ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("watchdog registration failed: %d\n", ret); - - davinci_serial_init(da8xx_serial_device); - - nvmem_register_notifier(&mityomapl138_nvmem_notifier); - nvmem_add_cell_table(&mityomapl138_nvmem_cell_table); - nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1); - - ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); - if (ret) - pr_warn("i2c0 registration failed: %d\n", ret); - - ret = pmic_tps65023_init(); - if (ret) - pr_warn("TPS65023 PMIC init failed: %d\n", ret); - - mityomapl138_setup_nand(); - - ret = spi_register_board_info(mityomapl138_spi_flash_info, - ARRAY_SIZE(mityomapl138_spi_flash_info)); - if (ret) - pr_warn("spi info registration failed: %d\n", ret); - - ret = da8xx_register_spi_bus(1, - ARRAY_SIZE(mityomapl138_spi_flash_info)); - if (ret) - pr_warn("spi 1 registration failed: %d\n", ret); - - mityomapl138_config_emac(); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("rtc setup failed: %d\n", ret); - - ret = da8xx_register_cpuidle(); - if (ret) - pr_warn("cpuidle registration failed: %d\n", ret); - - davinci_pm_init(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init mityomapl138_console_init(void) -{ - if (!machine_is_mityomapl138()) - return 0; - - return add_preferred_console("ttyS", 1, "115200"); -} -console_initcall(mityomapl138_console_init); -#endif - -static void __init mityomapl138_map_io(void) -{ - da850_init(); -} - -MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") - .atag_offset = 0x100, - .map_io = mityomapl138_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = mityomapl138_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c deleted file mode 100644 index ce99f782811a..000000000000 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Neuros Technologies OSD2 board support - * - * Modified from original 644X-EVM board support. - * 2008 (c) Neuros Technology, LLC. - * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com> - * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com> - * - * The Neuros OSD 2.0 is the hardware component of the Neuros Open - * Internet Television Platform. Hardware is very close to TI - * DM644X-EVM board. It has: - * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC, - * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video. - * Additionally realtime clock, IR remote control receiver, - * IR Blaster based on MSP430 (firmware although is different - * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive - * with PATA interface, two muxed red-green leds. - * - * For more information please refer to - * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/usb-davinci.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/serial.h> -#include <mach/mux.h> - -#include "davinci.h" - -#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01" -#define LXT971_PHY_ID 0x001378e2 -#define LXT971_PHY_MASK 0xfffffff0 - -#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18 -#define NTOSD2_MSP430_I2C_ADDR 0x59 -#define NTOSD2_MSP430_IRQ 2 - -/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA, - * 2048 blocks in the device, 64 pages per block, 2048 bytes per - * page. - */ - -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_ntosd2_nandflash_partition[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - /* Kernel */ - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - /* File System */ - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* A few blocks at end hold a flash Bad Block Table. */ -}; - -static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = { - .core_chipsel = 0, - .parts = davinci_ntosd2_nandflash_partition, - .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition), - .ecc_mode = NAND_ECC_HW, - .ecc_bits = 1, - .bbt_options = NAND_BBT_USE_FLASH, -}; - -static struct resource davinci_ntosd2_nandflash_resource[] = { - { - .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM644X_ASYNC_EMIF_CONTROL_BASE, - .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_ntosd2_nandflash_device = { - .name = "davinci_nand", - .id = 0, - .dev = { - .platform_data = &davinci_ntosd2_nandflash_data, - }, - .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource), - .resource = davinci_ntosd2_nandflash_resource, -}; - -static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device davinci_fb_device = { - .name = "davincifb", - .id = -1, - .dev = { - .dma_mask = &davinci_fb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = 0, -}; - -static const struct gpio_led ntosd2_leds[] = { - { .name = "led1_green", .gpio = 10, }, - { .name = "led1_red", .gpio = 11, }, - { .name = "led2_green", .gpio = 12, }, - { .name = "led2_red", .gpio = 13, }, -}; - -static struct gpio_led_platform_data ntosd2_leds_data = { - .num_leds = ARRAY_SIZE(ntosd2_leds), - .leds = ntosd2_leds, -}; - -static struct platform_device ntosd2_leds_dev = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &ntosd2_leds_data, - }, -}; - - -static struct platform_device *davinci_ntosd2_devices[] __initdata = { - &davinci_fb_device, - &ntosd2_leds_dev, -}; - -static void __init davinci_ntosd2_map_io(void) -{ - dm644x_init(); -} - -static struct davinci_mmc_config davinci_ntosd2_mmc_config = { - .wires = 4, -}; - -#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - IS_ENABLED(CONFIG_PATA_BK3710)) - -#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI) - -static __init void davinci_ntosd2_init(void) -{ - int ret; - struct clk *aemif_clk; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - dm644x_register_clocks(); - - dm644x_init_devices(); - - ret = dm644x_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - aemif_clk = clk_get(NULL, "aemif"); - clk_prepare_enable(aemif_clk); - - if (HAS_ATA) { - if (HAS_NAND) - pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n" - "\tDisable IDE for NAND/NOR support\n"); - davinci_init_ide(); - } else if (HAS_NAND) { - davinci_cfg_reg(DM644X_HPIEN_DISABLE); - davinci_cfg_reg(DM644X_ATAEN_DISABLE); - - /* only one device will be jumpered and detected */ - if (HAS_NAND) - platform_device_register( - &davinci_ntosd2_nandflash_device); - } - - platform_add_devices(davinci_ntosd2_devices, - ARRAY_SIZE(davinci_ntosd2_devices)); - - davinci_serial_init(dm644x_serial_device); - dm644x_init_asp(); - - soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; - - davinci_setup_usb(1000, 8); - /* - * Mux the pins to be GPIOs, VLYNQEN is already done at startup. - * The AEAWx are five new AEAW pins that can be muxed by separately. - * They are a bitmask for GPIO management. According TI - * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ - * gpio(10,11,12,13) for leds any combination of bits works except - * four last. So we are to reset all five. - */ - davinci_cfg_reg(DM644X_AEAW0); - davinci_cfg_reg(DM644X_AEAW1); - davinci_cfg_reg(DM644X_AEAW2); - davinci_cfg_reg(DM644X_AEAW3); - davinci_cfg_reg(DM644X_AEAW4); - - davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); -} - -MACHINE_START(NEUROS_OSD2, "Neuros OSD2") - /* Maintainer: Neuros Technologies <neuros@groups.google.com> */ - .atag_offset = 0x100, - .map_io = davinci_ntosd2_map_io, - .init_irq = dm644x_init_irq, - .init_time = dm644x_init_time, - .init_machine = davinci_ntosd2_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c deleted file mode 100644 index 5390a8630cf0..000000000000 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Hawkboard.org based on TI's OMAP-L138 Platform - * - * Initial code: Syed Mohammed Khasim - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of - * any kind, whether express or implied. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/console.h> -#include <linux/interrupt.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/rawnand.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/ti-aemif.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/da8xx.h> -#include <mach/mux.h> - -#define HAWKBOARD_PHY_ID "davinci_mdio-0:07" - -#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4) -#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13) - -static short omapl138_hawk_mii_pins[] __initdata = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static __init void omapl138_hawk_config_emac(void) -{ - void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - val = __raw_readl(cfgchip3); - val &= ~BIT(8); - ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins); - if (ret) { - pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret); - return; - } - - /* configure the CFGCHIP3 register for MII */ - __raw_writel(val, cfgchip3); - pr_info("EMAC: MII PHY configured\n"); - - soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); -} - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard, - * hence they are being reserved for codecs on the DSP side. - */ -static const s16 da850_dma0_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma0_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 50}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 90}, - {-1, -1} -}; - -static struct edma_rsv_info da850_edma_cc0_rsv = { - .rsv_chans = da850_dma0_rsv_chans, - .rsv_slots = da850_dma0_rsv_slots, -}; - -static struct edma_rsv_info da850_edma_cc1_rsv = { - .rsv_chans = da850_dma1_rsv_chans, - .rsv_slots = da850_dma1_rsv_slots, -}; - -static struct edma_rsv_info *da850_edma_rsv[2] = { - &da850_edma_cc0_rsv, - &da850_edma_cc1_rsv, -}; - -static const short hawk_mmcsd0_pins[] = { - DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, - DA850_GPIO3_12, DA850_GPIO3_13, - -1 -}; - -#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) -#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_LOW), - }, -}; - -static struct davinci_mmc_config da850_mmc_config = { - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static __init void omapl138_hawk_mmc_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(hawk_mmcsd0_pins); - if (ret) { - pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret); - return; - } - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da850_mmc_config); - if (ret) { - pr_warn("%s: MMC/SD0 registration failed: %d\n", __func__, ret); - goto mmc_setup_mmcsd_fail; - } - - return; - -mmc_setup_mmcsd_fail: - gpiod_remove_lookup_table(&mmc_gpios_table); -} - -static struct mtd_partition omapl138_hawk_nandflash_partition[] = { - { - .name = "u-boot env", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "free space", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata omapl138_hawk_nandflash_data = { - .core_chipsel = 1, - .parts = omapl138_hawk_nandflash_partition, - .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), - .ecc_mode = NAND_ECC_HW, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .options = NAND_BUSWIDTH_16, - .timing = &omapl138_hawk_nandflash_timing, - .mask_chipsel = 0, - .mask_ale = 0, - .mask_cle = 0, -}; - -static struct resource omapl138_hawk_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_32M, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource omapl138_hawk_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - } -}; - -static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = { - { - .cs = 3, - } -}; - -static struct platform_device omapl138_hawk_aemif_devices[] = { - { - .name = "davinci_nand", - .id = -1, - .dev = { - .platform_data = &omapl138_hawk_nandflash_data, - }, - .resource = omapl138_hawk_nandflash_resource, - .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource), - } -}; - -static struct aemif_platform_data omapl138_hawk_aemif_pdata = { - .cs_offset = 2, - .abus_data = omapl138_hawk_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data), - .sub_devices = omapl138_hawk_aemif_devices, - .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices), -}; - -static struct platform_device omapl138_hawk_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &omapl138_hawk_aemif_pdata, - }, - .resource = omapl138_hawk_aemif_resource, - .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource), -}; - -static const short omapl138_hawk_nand_pins[] = { - DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3, - DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, - DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, - DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, - DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, - DA850_EMA_A_1, DA850_EMA_A_2, - -1 -}; - -static int omapl138_hawk_register_aemif(void) -{ - int ret; - - ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins); - if (ret) - pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret); - - return platform_device_register(&omapl138_hawk_aemif_device); -} - -static const short da850_hawk_usb11_pins[] = { - DA850_GPIO2_4, DA850_GPIO6_13, - -1 -}; - -static struct regulator_consumer_supply hawk_usb_supplies[] = { - REGULATOR_SUPPLY("vbus", NULL), -}; - -static struct regulator_init_data hawk_usb_vbus_data = { - .consumer_supplies = hawk_usb_supplies, - .num_consumer_supplies = ARRAY_SIZE(hawk_usb_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config hawk_usb_vbus = { - .supply_name = "vbus", - .microvolts = 3300000, - .init_data = &hawk_usb_vbus_data, -}; - -static struct platform_device hawk_usb_vbus_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &hawk_usb_vbus, - }, -}; - -static struct gpiod_lookup_table hawk_usb_oc_gpio_lookup = { - .dev_id = "ohci-da8xx", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0), - { } - }, -}; - -static struct gpiod_lookup_table hawk_usb_vbus_gpio_lookup = { - .dev_id = "reg-fixed-voltage.0", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *hawk_usb_gpio_lookups[] = { - &hawk_usb_oc_gpio_lookup, - &hawk_usb_vbus_gpio_lookup, -}; - -static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = { - /* TPS2087 switch @ 5V */ - .potpgt = (3 + 1) / 2, /* 3 ms max */ -}; - -static __init void omapl138_hawk_usb_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da850_hawk_usb11_pins); - if (ret) { - pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); - return; - } - - ret = da8xx_register_usb_phy_clocks(); - if (ret) - pr_warn("%s: USB PHY CLK registration failed: %d\n", - __func__, ret); - - gpiod_add_lookup_tables(hawk_usb_gpio_lookups, - ARRAY_SIZE(hawk_usb_gpio_lookups)); - - ret = da8xx_register_usb_phy(); - if (ret) - pr_warn("%s: USB PHY registration failed: %d\n", - __func__, ret); - - ret = platform_device_register(&hawk_usb_vbus_device); - if (ret) { - pr_warn("%s: Unable to register the vbus supply\n", __func__); - return; - } - - ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata); - if (ret) - pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret); - - return; -} - -static __init void omapl138_hawk_init(void) -{ - int ret; - - da850_register_clocks(); - - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - davinci_serial_init(da8xx_serial_device); - - omapl138_hawk_config_emac(); - - ret = da850_register_edma(da850_edma_rsv); - if (ret) - pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); - - omapl138_hawk_mmc_init(); - - omapl138_hawk_usb_init(); - - ret = omapl138_hawk_register_aemif(); - if (ret) - pr_warn("%s: aemif registration failed: %d\n", __func__, ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_rproc(); - if (ret) - pr_warn("%s: dsp/rproc registration failed: %d\n", - __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init omapl138_hawk_console_init(void) -{ - if (!machine_is_omapl138_hawkboard()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(omapl138_hawk_console_init); -#endif - -static void __init omapl138_hawk_map_io(void) -{ - da850_init(); -} - -MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") - .atag_offset = 0x100, - .map_io = omapl138_hawk_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = omapl138_hawk_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .reserve = da8xx_rproc_reserve_cma, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c deleted file mode 100644 index 79b47958e992..000000000000 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Lyrtech SFFSDR board support. - * - * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * - * Based on DV-EVM platform, original copyright follows: - * - * Copyright (C) 2007 MontaVista Software, Inc. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/property.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/partitions.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> - -#include <mach/common.h> -#include <linux/platform_data/i2c-davinci.h> -#include <mach/serial.h> -#include <mach/mux.h> -#include <linux/platform_data/usb-davinci.h> - -#include "davinci.h" - -#define SFFSDR_PHY_ID "davinci_mdio-0:01" -static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { - /* U-Boot Environment: Block 0 - * UBL: Block 1 - * U-Boot: Blocks 6-7 (256 kb) - * Integrity Kernel: Blocks 8-31 (3 Mb) - * Integrity Data: Blocks 100-END - */ - { - .name = "Linux Kernel", - .offset = 32 * SZ_128K, - .size = 16 * SZ_128K, /* 2 Mb */ - .mask_flags = MTD_WRITEABLE, /* Force read-only */ - }, - { - .name = "Linux ROOT", - .offset = MTDPART_OFS_APPEND, - .size = 256 * SZ_128K, /* 32 Mb */ - .mask_flags = 0, /* R/W */ - }, -}; - -static struct flash_platform_data davinci_sffsdr_nandflash_data = { - .parts = davinci_sffsdr_nandflash_partition, - .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition), -}; - -static struct resource davinci_sffsdr_nandflash_resource[] = { - { - .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM644X_ASYNC_EMIF_CONTROL_BASE, - .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_sffsdr_nandflash_device = { - .name = "davinci_nand", /* Name of driver */ - .id = 0, - .dev = { - .platform_data = &davinci_sffsdr_nandflash_data, - }, - .num_resources = ARRAY_SIZE(davinci_sffsdr_nandflash_resource), - .resource = davinci_sffsdr_nandflash_resource, -}; - -static const struct property_entry eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 32), - { } -}; - -static struct i2c_board_info __initdata i2c_info[] = { - { - I2C_BOARD_INFO("24c64", 0x50), - .properties = eeprom_properties, - }, - /* Other I2C devices: - * MSP430, addr 0x23 (not used) - * PCA9543, addr 0x70 (setup done by U-Boot) - * ADS7828, addr 0x48 (ADC for voltage monitoring.) - */ -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 20 /* kHz */, - .bus_delay = 100 /* usec */, -}; - -static void __init sffsdr_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} - -static struct platform_device *davinci_sffsdr_devices[] __initdata = { - &davinci_sffsdr_nandflash_device, -}; - -static void __init davinci_sffsdr_map_io(void) -{ - dm644x_init(); -} - -static __init void davinci_sffsdr_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - dm644x_register_clocks(); - - dm644x_init_devices(); - - platform_add_devices(davinci_sffsdr_devices, - ARRAY_SIZE(davinci_sffsdr_devices)); - sffsdr_init_i2c(); - davinci_serial_init(dm644x_serial_device); - soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; - davinci_setup_usb(0, 0); /* We support only peripheral mode. */ - - /* mux VLYNQ pins */ - davinci_cfg_reg(DM644X_VLYNQEN); - davinci_cfg_reg(DM644X_VLYNQWD); -} - -MACHINE_START(SFFSDR, "Lyrtech SFFSDR") - .atag_offset = 0x100, - .map_io = davinci_sffsdr_map_io, - .init_irq = dm644x_init_irq, - .init_time = dm644x_init_time, - .init_machine = davinci_sffsdr_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index ae61d19f9b3a..7bc7018688de 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -1,24 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Code commons to all DaVinci SoCs. * * Author: Mark A. Greer <mgreer@mvista.com> * - * 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2009 (c) MontaVista Software, Inc. */ #include <linux/module.h> #include <linux/io.h> #include <linux/etherdevice.h> #include <linux/davinci_emac.h> #include <linux/dma-mapping.h> +#include <linux/platform_data/davinci-cpufreq.h> #include <asm/tlb.h> #include <asm/mach/map.h> -#include <mach/common.h> -#include <mach/cputype.h> +#include "common.h" +#include "cputype.h" struct davinci_soc_info davinci_soc_info; EXPORT_SYMBOL(davinci_soc_info); diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/common.h index 9526e5da0d33..8aa6d4fc3f6f 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/common.h @@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header for code common to all DaVinci machines. * * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2007 (c) MontaVista Software, Inc. */ #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H @@ -19,24 +17,8 @@ #include <asm/irq.h> -#define DAVINCI_INTC_START NR_IRQS -#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) - -void davinci_timer_init(struct clk *clk); - -struct davinci_timer_instance { - u32 base; - u32 bottom_irq; - u32 top_irq; - unsigned long cmp_off; - unsigned int cmp_irq; -}; - -struct davinci_timer_info { - struct davinci_timer_instance *timers; - unsigned int clockevent_id; - unsigned int clocksource_id; -}; +#define DAVINCI_INTC_START NR_IRQS +#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) struct davinci_gpio_controller; @@ -58,15 +40,11 @@ struct davinci_soc_info { u32 pinmux_base; const struct mux_config *pinmux_pins; unsigned long pinmux_pins_num; - struct davinci_timer_info *timer_info; int gpio_type; u32 gpio_base; unsigned gpio_num; unsigned gpio_irq; unsigned gpio_unbanked; - struct davinci_gpio_controller *gpio_ctlrs; - int gpio_ctlrs_num; - struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; unsigned sram_len; }; @@ -77,12 +55,6 @@ extern void davinci_common_init(const struct davinci_soc_info *soc_info); extern void davinci_init_ide(void); void davinci_init_late(void); -#ifdef CONFIG_CPU_FREQ -int davinci_cpufreq_init(void); -#else -static inline int davinci_cpufreq_init(void) { return 0; } -#endif - #ifdef CONFIG_SUSPEND int davinci_pm_init(void); #else diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index b795f671bd03..78a1575c387d 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -2,7 +2,7 @@ /* * CPU idle for DaVinci SoCs * - * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated. https://www.ti.com/ * * Derived from Marvell Kirkwood CPU idle code * (arch/arm/mach-kirkwood/cpuidle.c) @@ -44,8 +44,8 @@ static void davinci_save_ddr_power(int enter, bool pdown) } /* Actual code that puts the SoC in different idle states */ -static int davinci_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) +static __cpuidle int davinci_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) { davinci_save_ddr_power(1, ddr2_pdown); cpu_do_idle(); diff --git a/arch/arm/mach-davinci/cpuidle.h b/arch/arm/mach-davinci/cpuidle.h index 74f088b0edfb..976d43073597 100644 --- a/arch/arm/mach-davinci/cpuidle.h +++ b/arch/arm/mach-davinci/cpuidle.h @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * TI DaVinci cpuidle platform support * - * 2009 (C) Texas Instruments, Inc. http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * 2009 (C) Texas Instruments, Inc. https://www.ti.com/ */ #ifndef _MACH_DAVINCI_CPUIDLE_H #define _MACH_DAVINCI_CPUIDLE_H diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h new file mode 100644 index 000000000000..148a738391dc --- /dev/null +++ b/arch/arm/mach-davinci/cputype.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * DaVinci CPU type detection + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Defines the cpu_is_*() macros for runtime detection of DaVinci + * device type. In addition, if support for a given device is not + * compiled in to the kernel, the macros return 0 so that + * resulting code can be optimized out. + * + * 2009 (c) Deep Root Systems, LLC. + */ +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +#include "common.h" + +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u16 manufacturer; /* JTAG ID bits 11:1 */ + u32 cpu_id; + char *name; +}; + +/* Can use lower 16 bits of cpu id for a variant when required */ +#define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 + +#endif diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 018ab4b549f1..2e497745b624 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DA830/OMAP L137 chip specific setup * * Author: Mark A. Greer <mgreer@mvista.com> * - * 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2009 (c) MontaVista Software, Inc. */ #include <linux/clk-provider.h> #include <linux/clk/davinci.h> @@ -14,16 +12,14 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/irqchip/irq-davinci-cp-intc.h> -#include <linux/platform_data/gpio-davinci.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/da8xx.h> #include <clocksource/timer-davinci.h> +#include <asm/mach/map.h> + +#include "common.h" +#include "cputype.h" +#include "da8xx.h" #include "irqs.h" #include "mux.h" @@ -451,181 +447,6 @@ static const struct mux_config da830_pins[] = { #endif }; -const short da830_emif25_pins[] __initconst = { - DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, - DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, - DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, - DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, - DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, - DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, - DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, - DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, - DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, - DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, - DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, - -1 -}; - -const short da830_spi0_pins[] __initconst = { - DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, - DA830_NSPI0_SCS_0, - -1 -}; - -const short da830_spi1_pins[] __initconst = { - DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, - DA830_NSPI1_SCS_0, - -1 -}; - -const short da830_mmc_sd_pins[] __initconst = { - DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, - DA830_MMCSD_CMD, - -1 -}; - -const short da830_uart0_pins[] __initconst = { - DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, - -1 -}; - -const short da830_uart1_pins[] __initconst = { - DA830_UART1_RXD, DA830_UART1_TXD, - -1 -}; - -const short da830_uart2_pins[] __initconst = { - DA830_UART2_RXD, DA830_UART2_TXD, - -1 -}; - -const short da830_usb20_pins[] __initconst = { - DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, - -1 -}; - -const short da830_usb11_pins[] __initconst = { - DA830_USB_REFCLKIN, - -1 -}; - -const short da830_uhpi_pins[] __initconst = { - DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, - DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, - DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, - DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, - DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, - DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, - DA830_NUHPI_HINT, DA830_NUHPI_HRDY, - -1 -}; - -const short da830_cpgmac_pins[] __initconst = { - DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, - DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, - DA830_MDIO_D, - -1 -}; - -const short da830_emif3c_pins[] __initconst = { - DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, - DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, - DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, - DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, - DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, - DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, - DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, - DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, - DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, - DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, - DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, - DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, - DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, - DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, - DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, - -1 -}; - -const short da830_mcasp0_pins[] __initconst = { - DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, - DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, - DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, - DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, - DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, - DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, - -1 -}; - -const short da830_mcasp1_pins[] __initconst = { - DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, - DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, - DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, - DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, - DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, - -1 -}; - -const short da830_mcasp2_pins[] __initconst = { - DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, - DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, - DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, - -1 -}; - -const short da830_i2c0_pins[] __initconst = { - DA830_I2C0_SDA, DA830_I2C0_SCL, - -1 -}; - -const short da830_i2c1_pins[] __initconst = { - DA830_I2C1_SCL, DA830_I2C1_SDA, - -1 -}; - -const short da830_lcdcntl_pins[] __initconst = { - DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, - DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, - DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, - DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, - DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, - DA830_LCD_MCLK, - -1 -}; - -const short da830_pwm_pins[] __initconst = { - DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, - DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, - DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, - -1 -}; - -const short da830_ecap0_pins[] __initconst = { - DA830_ECAP0_APWM0, - -1 -}; - -const short da830_ecap1_pins[] __initconst = { - DA830_ECAP1_APWM1, - -1 -}; - -const short da830_ecap2_pins[] __initconst = { - DA830_ECAP2_APWM2, - -1 -}; - -const short da830_eqep0_pins[] __initconst = { - DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, - -1 -}; - -const short da830_eqep1_pins[] __initconst = { - DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, - -1 -}; - static struct map_desc da830_io_desc[] = { { .virtual = IO_VIRT, @@ -666,30 +487,6 @@ static struct davinci_id da830_ids[] = { }, }; -static struct davinci_gpio_platform_data da830_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 128, -}; - -int __init da830_register_gpio(void) -{ - return da8xx_register_gpio(&da830_gpio_platform_data); -} - -/* - * Bottom half of timer0 is used both for clock even and clocksource. - * Top half is used by DSP. - */ -static const struct davinci_timer_cfg da830_timer_cfg = { - .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), - }, - .cmp_off = DA830_CMP12_0, -}; - static const struct davinci_soc_info davinci_soc_info_da830 = { .io_desc = da830_io_desc, .io_desc_num = ARRAY_SIZE(da830_io_desc), @@ -699,7 +496,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), - .emac_pdata = &da8xx_emac_pdata, }; void __init da830_init(void) @@ -709,76 +505,3 @@ void __init da830_init(void) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); } - -static const struct davinci_cp_intc_config da830_cp_intc_config = { - .reg = { - .start = DA8XX_CP_INTC_BASE, - .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = DA830_N_CP_INTC_IRQ, -}; - -void __init da830_init_irq(void) -{ - davinci_cp_intc_init(&da830_cp_intc_config); -} - -void __init da830_init_time(void) -{ - void __iomem *pll; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ); - - pll = ioremap(DA8XX_PLL0_BASE, SZ_4K); - - da830_pll_init(NULL, pll, NULL); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &da830_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource da830_psc0_resources[] = { - { - .start = DA8XX_PSC0_BASE, - .end = DA8XX_PSC0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_psc0_device = { - .name = "da830-psc0", - .id = -1, - .resource = da830_psc0_resources, - .num_resources = ARRAY_SIZE(da830_psc0_resources), -}; - -static struct resource da830_psc1_resources[] = { - { - .start = DA8XX_PSC1_BASE, - .end = DA8XX_PSC1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_psc1_device = { - .name = "da830-psc1", - .id = -1, - .resource = da830_psc1_resources, - .num_resources = ARRAY_SIZE(da830_psc1_resources), -}; - -void __init da830_register_clocks(void) -{ - /* PLL is registered in da830_init_time() */ - platform_device_register(&da830_psc0_device); - platform_device_register(&da830_psc1_device); -} diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 73b7cc53f966..287dd987908e 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1,43 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DA850/OMAP-L138 chip specific setup * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ * * Derived from: arch/arm/mach-davinci/da830.c * Original Copyrights follow: * - * 2009 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2009 (c) MontaVista Software, Inc. */ -#include <linux/clk-provider.h> -#include <linux/clk/davinci.h> -#include <linux/clkdev.h> -#include <linux/cpufreq.h> #include <linux/gpio.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/irqchip/irq-davinci-cp-intc.h> #include <linux/mfd/da8xx-cfgchip.h> -#include <linux/platform_data/clk-da8xx-cfgchip.h> -#include <linux/platform_data/clk-davinci-pll.h> -#include <linux/platform_data/davinci-cpufreq.h> -#include <linux/platform_data/gpio-davinci.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <clocksource/timer-davinci.h> #include <asm/mach/map.h> -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/da8xx.h> -#include <mach/pm.h> - -#include <clocksource/timer-davinci.h> - +#include "common.h" +#include "cputype.h" +#include "da8xx.h" +#include "hardware.h" +#include "pm.h" #include "irqs.h" #include "mux.h" @@ -262,45 +250,6 @@ static const struct mux_config da850_pins[] = { #endif }; -const short da850_i2c0_pins[] __initconst = { - DA850_I2C0_SDA, DA850_I2C0_SCL, - -1 -}; - -const short da850_i2c1_pins[] __initconst = { - DA850_I2C1_SCL, DA850_I2C1_SDA, - -1 -}; - -const short da850_lcdcntl_pins[] __initconst = { - DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, - DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, - DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, - DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, - DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, - -1 -}; - -const short da850_vpif_capture_pins[] __initconst = { - DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, - DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, - DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, - DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, - DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, - DA850_VPIF_CLKIN3, - -1 -}; - -const short da850_vpif_display_pins[] __initconst = { - DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, - DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, - DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, - DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, - DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, - DA850_VPIF_CLKO3, - -1 -}; - static struct map_desc da850_io_desc[] = { { .virtual = IO_VIRT, @@ -334,204 +283,9 @@ static struct davinci_id da850_ids[] = { }, }; -/* - * Bottom half of timer 0 is used for clock_event, top half for - * clocksource. - */ -static const struct davinci_timer_cfg da850_timer_cfg = { - .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), - }, -}; - -#ifdef CONFIG_CPU_FREQ -/* - * Notes: - * According to the TRM, minimum PLLM results in maximum power savings. - * The OPP definitions below should keep the PLLM as low as possible. - * - * The output of the PLLM must be between 300 to 600 MHz. - */ -struct da850_opp { - unsigned int freq; /* in KHz */ - unsigned int prediv; - unsigned int mult; - unsigned int postdiv; - unsigned int cvdd_min; /* in uV */ - unsigned int cvdd_max; /* in uV */ -}; - -static const struct da850_opp da850_opp_456 = { - .freq = 456000, - .prediv = 1, - .mult = 19, - .postdiv = 1, - .cvdd_min = 1300000, - .cvdd_max = 1350000, -}; - -static const struct da850_opp da850_opp_408 = { - .freq = 408000, - .prediv = 1, - .mult = 17, - .postdiv = 1, - .cvdd_min = 1300000, - .cvdd_max = 1350000, -}; - -static const struct da850_opp da850_opp_372 = { - .freq = 372000, - .prediv = 2, - .mult = 31, - .postdiv = 1, - .cvdd_min = 1200000, - .cvdd_max = 1320000, -}; - -static const struct da850_opp da850_opp_300 = { - .freq = 300000, - .prediv = 1, - .mult = 25, - .postdiv = 2, - .cvdd_min = 1200000, - .cvdd_max = 1320000, -}; - -static const struct da850_opp da850_opp_200 = { - .freq = 200000, - .prediv = 1, - .mult = 25, - .postdiv = 3, - .cvdd_min = 1100000, - .cvdd_max = 1160000, -}; - -static const struct da850_opp da850_opp_96 = { - .freq = 96000, - .prediv = 1, - .mult = 20, - .postdiv = 5, - .cvdd_min = 1000000, - .cvdd_max = 1050000, -}; - -#define OPP(freq) \ - { \ - .driver_data = (unsigned int) &da850_opp_##freq, \ - .frequency = freq * 1000, \ - } - -static struct cpufreq_frequency_table da850_freq_table[] = { - OPP(456), - OPP(408), - OPP(372), - OPP(300), - OPP(200), - OPP(96), - { - .driver_data = 0, - .frequency = CPUFREQ_TABLE_END, - }, -}; - -#ifdef CONFIG_REGULATOR -static int da850_set_voltage(unsigned int index); -static int da850_regulator_init(void); -#endif - -static struct davinci_cpufreq_config cpufreq_info = { - .freq_table = da850_freq_table, -#ifdef CONFIG_REGULATOR - .init = da850_regulator_init, - .set_voltage = da850_set_voltage, -#endif -}; - -#ifdef CONFIG_REGULATOR -static struct regulator *cvdd; - -static int da850_set_voltage(unsigned int index) -{ - struct da850_opp *opp; - - if (!cvdd) - return -ENODEV; - - opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; - - return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); -} - -static int da850_regulator_init(void) -{ - cvdd = regulator_get(NULL, "cvdd"); - if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" - " voltage scaling unsupported\n")) { - return PTR_ERR(cvdd); - } - - return 0; -} -#endif - -static struct platform_device da850_cpufreq_device = { - .name = "cpufreq-davinci", - .dev = { - .platform_data = &cpufreq_info, - }, - .id = -1, -}; - -unsigned int da850_max_speed = 300000; - -int da850_register_cpufreq(char *async_clk) -{ - int i; - - /* cpufreq driver can help keep an "async" clock constant */ - if (async_clk) - clk_add_alias("async", da850_cpufreq_device.name, - async_clk, NULL); - for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { - if (da850_freq_table[i].frequency <= da850_max_speed) { - cpufreq_info.freq_table = &da850_freq_table[i]; - break; - } - } - - return platform_device_register(&da850_cpufreq_device); -} -#else -int __init da850_register_cpufreq(char *async_clk) -{ - return 0; -} -#endif - /* VPIF resource, platform data */ static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); -static struct resource da850_vpif_resource[] = { - { - .start = DA8XX_VPIF_BASE, - .end = DA8XX_VPIF_BASE + 0xfff, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device da850_vpif_dev = { - .name = "vpif", - .id = -1, - .dev = { - .dma_mask = &da850_vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da850_vpif_resource, - .num_resources = ARRAY_SIZE(da850_vpif_resource), -}; - static struct resource da850_vpif_display_resource[] = { { .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), @@ -575,11 +329,6 @@ static struct platform_device da850_vpif_capture_dev = { .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), }; -int __init da850_register_vpif(void) -{ - return platform_device_register(&da850_vpif_dev); -} - int __init da850_register_vpif_display(struct vpif_display_config *display_config) { @@ -594,17 +343,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config return platform_device_register(&da850_vpif_capture_dev); } -static struct davinci_gpio_platform_data da850_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 144, -}; - -int __init da850_register_gpio(void) -{ - return da8xx_register_gpio(&da850_gpio_platform_data); -} - static const struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), @@ -614,7 +352,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), - .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, }; @@ -630,142 +367,3 @@ void __init da850_init(void) da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); } - -static const struct davinci_cp_intc_config da850_cp_intc_config = { - .reg = { - .start = DA8XX_CP_INTC_BASE, - .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = DA850_N_CP_INTC_IRQ, -}; - -void __init da850_init_irq(void) -{ - davinci_cp_intc_init(&da850_cp_intc_config); -} - -void __init da850_init_time(void) -{ - void __iomem *pll0; - struct regmap *cfgchip; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); - - pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); - cfgchip = da8xx_get_cfgchip(); - - da850_pll0_init(NULL, pll0, cfgchip); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &da850_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource da850_pll1_resources[] = { - { - .start = DA850_PLL1_BASE, - .end = DA850_PLL1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct davinci_pll_platform_data da850_pll1_pdata; - -static struct platform_device da850_pll1_device = { - .name = "da850-pll1", - .id = -1, - .resource = da850_pll1_resources, - .num_resources = ARRAY_SIZE(da850_pll1_resources), - .dev = { - .platform_data = &da850_pll1_pdata, - }, -}; - -static struct resource da850_psc0_resources[] = { - { - .start = DA8XX_PSC0_BASE, - .end = DA8XX_PSC0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da850_psc0_device = { - .name = "da850-psc0", - .id = -1, - .resource = da850_psc0_resources, - .num_resources = ARRAY_SIZE(da850_psc0_resources), -}; - -static struct resource da850_psc1_resources[] = { - { - .start = DA8XX_PSC1_BASE, - .end = DA8XX_PSC1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da850_psc1_device = { - .name = "da850-psc1", - .id = -1, - .resource = da850_psc1_resources, - .num_resources = ARRAY_SIZE(da850_psc1_resources), -}; - -static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata; - -static struct platform_device da850_async1_clksrc_device = { - .name = "da850-async1-clksrc", - .id = -1, - .dev = { - .platform_data = &da850_async1_pdata, - }, -}; - -static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata; - -static struct platform_device da850_async3_clksrc_device = { - .name = "da850-async3-clksrc", - .id = -1, - .dev = { - .platform_data = &da850_async3_pdata, - }, -}; - -static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata; - -static struct platform_device da850_tbclksync_device = { - .name = "da830-tbclksync", - .id = -1, - .dev = { - .platform_data = &da850_tbclksync_pdata, - }, -}; - -void __init da850_register_clocks(void) -{ - /* PLL0 is registered in da850_init_time() */ - - da850_pll1_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_pll1_device); - - da850_async1_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_async1_clksrc_device); - - da850_async3_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_async3_clksrc_device); - - platform_device_register(&da850_psc0_device); - - platform_device_register(&da850_psc1_device); - - da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_tbclksync_device); -} diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 9c0dd028d5ad..45763a9b37ee 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Modified from mach-omap/omap2/board-generic.c */ #include <asm/mach/arch.h> -#include <mach/common.h> -#include <mach/da8xx.h> +#include "common.h" +#include "da8xx.h" #ifdef CONFIG_ARCH_DAVINCI_DA850 diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h new file mode 100644 index 000000000000..54a255b8d8d8 --- /dev/null +++ b/arch/arm/mach-davinci/da8xx.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007, 2009-2010 (c) MontaVista Software, Inc. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/videodev2.h> +#include <linux/reboot.h> +#include <linux/regmap.h> + +#include "hardware.h" +#include "pm.h" + +#include <media/davinci/vpif_types.h> + +extern void __iomem *da8xx_syscfg0_base; +extern void __iomem *da8xx_syscfg1_base; + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) +#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) +#define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_HOST1CFG_REG 0x44 +#define DA8XX_CHIPSIG_REG 0x174 +#define DA8XX_CFGCHIP0_REG 0x17c +#define DA8XX_CFGCHIP1_REG 0x180 +#define DA8XX_CFGCHIP2_REG 0x184 +#define DA8XX_CFGCHIP3_REG 0x188 +#define DA8XX_CFGCHIP4_REG 0x18c + +#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) +#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) +#define DA8XX_DEEPSLEEP_REG 0x8 +#define DA8XX_PWRDN_REG 0x18 + +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_VPIF_BASE 0x01e17000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 + +#define DA8XX_DSP_L2_RAM_BASE 0x11800000 +#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000) +#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000) + +#define DA8XX_AEMIF_CS2_BASE 0x60000000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 +#define DA8XX_SHARED_RAM_BASE 0x80000000 +#define DA8XX_ARM_RAM_BASE 0xffff0000 + +void da830_init(void); + +void da850_init(void); + +int da850_register_vpif_display + (struct vpif_display_config *display_config); +int da850_register_vpif_capture + (struct vpif_capture_config *capture_config); +struct regmap *da8xx_get_cfgchip(void); +void __iomem *da8xx_get_mem_ctlr(void); + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h deleted file mode 100644 index 208d7a4d3597..000000000000 --- a/arch/arm/mach-davinci/davinci.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file contains the processor specific definitions - * of the TI DM644x, DM355, DM365, and DM646x. - * - * Copyright (C) 2011 Texas Instruments Incorporated - * Copyright (c) 2007 Deep Root Systems, LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DAVINCI_H -#define __DAVINCI_H - -#include <linux/clk.h> -#include <linux/videodev2.h> -#include <linux/davinci_emac.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/platform_data/davinci_asp.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/keyscan-davinci.h> -#include <mach/hardware.h> - -#include <media/davinci/vpfe_capture.h> -#include <media/davinci/vpif_types.h> -#include <media/davinci/vpss.h> -#include <media/davinci/vpbe_types.h> -#include <media/davinci/vpbe_venc.h> -#include <media/davinci/vpbe.h> -#include <media/davinci/vpbe_osd.h> - -#define DAVINCI_PLL1_BASE 0x01c40800 -#define DAVINCI_PLL2_BASE 0x01c40c00 -#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000 - -#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 -#define SYSMOD_VDAC_CONFIG 0x2c -#define SYSMOD_VIDCLKCTL 0x38 -#define SYSMOD_VPSS_CLKCTL 0x44 -#define SYSMOD_VDD3P3VPWDN 0x48 -#define SYSMOD_VSCLKDIS 0x6c -#define SYSMOD_PUPDCTL1 0x7c - -/* VPSS CLKCTL bit definitions */ -#define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1) -#define VPSS_VENCCLKEN_ENABLE BIT(3) -#define VPSS_DACCLKEN_ENABLE BIT(4) -#define VPSS_PLLC2SYSCLK5_ENABLE BIT(5) - -extern void __iomem *davinci_sysmod_base; -#define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x)) -void davinci_map_sysmod(void); - -#define DAVINCI_GPIO_BASE 0x01C67000 -int davinci_gpio_register(struct resource *res, int size, void *pdata); - -#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) -#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) - -/* DM355 base addresses */ -#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000 -#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 - -#define ASP1_TX_EVT_EN 1 -#define ASP1_RX_EVT_EN 2 - -/* DM365 base addresses */ -#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 -#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 -#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 - -/* DM644x base addresses */ -#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000 -#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 -#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 -#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 -#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 - -/* DM646x base addresses */ -#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 -#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 - -int davinci_init_wdt(void); - -/* DM355 function declarations */ -void dm355_init(void); -void dm355_init_time(void); -void dm355_init_irq(void); -void dm355_register_clocks(void); -void dm355_init_spi0(unsigned chipselect_mask, - const struct spi_board_info *info, unsigned len); -void dm355_init_asp1(u32 evt_enable); -int dm355_init_video(struct vpfe_config *, struct vpbe_config *); -int dm355_gpio_register(void); - -/* DM365 function declarations */ -void dm365_init(void); -void dm365_init_irq(void); -void dm365_init_time(void); -void dm365_register_clocks(void); -void dm365_init_asp(void); -void dm365_init_vc(void); -void dm365_init_ks(struct davinci_ks_platform_data *pdata); -void dm365_init_rtc(void); -void dm365_init_spi0(unsigned chipselect_mask, - const struct spi_board_info *info, unsigned len); -int dm365_init_video(struct vpfe_config *, struct vpbe_config *); -int dm365_gpio_register(void); - -/* DM644x function declarations */ -void dm644x_init(void); -void dm644x_init_irq(void); -void dm644x_init_devices(void); -void dm644x_init_time(void); -void dm644x_register_clocks(void); -void dm644x_init_asp(void); -int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); -int dm644x_gpio_register(void); - -/* DM646x function declarations */ -void dm646x_init(void); -void dm646x_init_irq(void); -void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate); -void dm646x_register_clocks(void); -void dm646x_init_mcasp0(struct snd_platform_data *pdata); -void dm646x_init_mcasp1(struct snd_platform_data *pdata); -int dm646x_init_edma(struct edma_rsv_info *rsv); -void dm646x_video_init(void); -void dm646x_setup_vpif(struct vpif_display_config *, - struct vpif_capture_config *); -int dm646x_gpio_register(void); - -extern struct platform_device dm365_serial_device[]; -extern struct platform_device dm355_serial_device[]; -extern struct platform_device dm644x_serial_device[]; -extern struct platform_device dm646x_serial_device[]; -#endif /*__DAVINCI_H */ diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 2d69e704f7f6..6939166c33c2 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -10,7 +10,7 @@ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> -#include <linux/dma-contiguous.h> +#include <linux/dma-map-ops.h> #include <linux/dmaengine.h> #include <linux/init.h> #include <linux/io.h> @@ -18,12 +18,9 @@ #include <linux/reboot.h> #include <linux/serial_8250.h> -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/da8xx.h> -#include <mach/time.h> - -#include "asp.h" +#include "common.h" +#include "cputype.h" +#include "da8xx.h" #include "cpuidle.h" #include "irqs.h" #include "sram.h" @@ -59,907 +56,6 @@ void __iomem *da8xx_syscfg0_base; void __iomem *da8xx_syscfg1_base; -static struct plat_serial8250_port da8xx_serial0_pdata[] = { - { - .mapbase = DA8XX_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port da8xx_serial1_pdata[] = { - { - .mapbase = DA8XX_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port da8xx_serial2_pdata[] = { - { - .mapbase = DA8XX_UART2_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device da8xx_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = da8xx_serial0_pdata, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = da8xx_serial1_pdata, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = da8xx_serial2_pdata, - } - }, - { - } -}; - -static s8 da8xx_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1} -}; - -static s8 da850_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {-1, -1} -}; - -static struct edma_soc_info da8xx_edma0_pdata = { - .queue_priority_mapping = da8xx_queue_priority_mapping, - .default_queue = EVENTQ_1, -}; - -static struct edma_soc_info da850_edma1_pdata = { - .queue_priority_mapping = da850_queue_priority_mapping, - .default_queue = EVENTQ_0, -}; - -static struct resource da8xx_edma0_resources[] = { - { - .name = "edma3_cc", - .start = DA8XX_TPCC_BASE, - .end = DA8XX_TPCC_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = DA8XX_TPTC0_BASE, - .end = DA8XX_TPTC0_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = DA8XX_TPTC1_BASE, - .end = DA8XX_TPTC1_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource da850_edma1_resources[] = { - { - .name = "edma3_cc", - .start = DA850_TPCC1_BASE, - .end = DA850_TPCC1_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = DA850_TPTC2_BASE, - .end = DA850_TPTC2_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct platform_device_info da8xx_edma0_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = da8xx_edma0_resources, - .num_res = ARRAY_SIZE(da8xx_edma0_resources), - .data = &da8xx_edma0_pdata, - .size_data = sizeof(da8xx_edma0_pdata), -}; - -static const struct platform_device_info da850_edma1_device __initconst = { - .name = "edma", - .id = 1, - .dma_mask = DMA_BIT_MASK(32), - .res = da850_edma1_resources, - .num_res = ARRAY_SIZE(da850_edma1_resources), - .data = &da850_edma1_pdata, - .size_data = sizeof(da850_edma1_pdata), -}; - -static const struct dma_slave_map da830_edma_map[] = { - { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, - { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, - { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, - { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, - { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, - { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, - { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, - { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, - { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, - { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, - { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, -}; - -int __init da830_register_edma(struct edma_rsv_info *rsv) -{ - struct platform_device *edma_pdev; - - da8xx_edma0_pdata.rsv = rsv; - - da8xx_edma0_pdata.slave_map = da830_edma_map; - da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); - - edma_pdev = platform_device_register_full(&da8xx_edma0_device); - return PTR_ERR_OR_ZERO(edma_pdev); -} - -static const struct dma_slave_map da850_edma0_map[] = { - { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, - { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, - { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, - { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, - { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, - { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, - { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, - { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, - { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, - { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, - { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, -}; - -static const struct dma_slave_map da850_edma1_map[] = { - { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) }, - { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) }, -}; - -int __init da850_register_edma(struct edma_rsv_info *rsv[2]) -{ - struct platform_device *edma_pdev; - - if (rsv) { - da8xx_edma0_pdata.rsv = rsv[0]; - da850_edma1_pdata.rsv = rsv[1]; - } - - da8xx_edma0_pdata.slave_map = da850_edma0_map; - da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); - - edma_pdev = platform_device_register_full(&da8xx_edma0_device); - if (IS_ERR(edma_pdev)) { - pr_warn("%s: Failed to register eDMA0\n", __func__); - return PTR_ERR(edma_pdev); - } - - da850_edma1_pdata.slave_map = da850_edma1_map; - da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); - - edma_pdev = platform_device_register_full(&da850_edma1_device); - return PTR_ERR_OR_ZERO(edma_pdev); -} - -static struct resource da8xx_i2c_resources0[] = { - { - .start = DA8XX_I2C0_BASE, - .end = DA8XX_I2C0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_i2c_device0 = { - .name = "i2c_davinci", - .id = 1, - .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), - .resource = da8xx_i2c_resources0, -}; - -static struct resource da8xx_i2c_resources1[] = { - { - .start = DA8XX_I2C1_BASE, - .end = DA8XX_I2C1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_i2c_device1 = { - .name = "i2c_davinci", - .id = 2, - .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), - .resource = da8xx_i2c_resources1, -}; - -int __init da8xx_register_i2c(int instance, - struct davinci_i2c_platform_data *pdata) -{ - struct platform_device *pdev; - - if (instance == 0) - pdev = &da8xx_i2c_device0; - else if (instance == 1) - pdev = &da8xx_i2c_device1; - else - return -EINVAL; - - pdev->dev.platform_data = pdata; - return platform_device_register(pdev); -} - -static struct resource da8xx_watchdog_resources[] = { - { - .start = DA8XX_WDOG_BASE, - .end = DA8XX_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da8xx_wdt_device = { - .name = "davinci-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), - .resource = da8xx_watchdog_resources, -}; - -int __init da8xx_register_watchdog(void) -{ - return platform_device_register(&da8xx_wdt_device); -} - -static struct resource da8xx_emac_resources[] = { - { - .start = DA8XX_EMAC_CPPI_PORT_BASE, - .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE), - .flags = IORESOURCE_IRQ, - }, -}; - -struct emac_platform_data da8xx_emac_pdata = { - .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, - .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, - .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, - .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, - .version = EMAC_VERSION_2, -}; - -static struct platform_device da8xx_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &da8xx_emac_pdata, - }, - .num_resources = ARRAY_SIZE(da8xx_emac_resources), - .resource = da8xx_emac_resources, -}; - -static struct resource da8xx_mdio_resources[] = { - { - .start = DA8XX_EMAC_MDIO_BASE, - .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da8xx_mdio_device = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(da8xx_mdio_resources), - .resource = da8xx_mdio_resources, -}; - -int __init da8xx_register_emac(void) -{ - int ret; - - ret = platform_device_register(&da8xx_mdio_device); - if (ret < 0) - return ret; - - return platform_device_register(&da8xx_emac_device); -} - -static struct resource da830_mcasp1_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DA830_MCASP1_REG_BASE, - .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, - .flags = IORESOURCE_MEM, - }, - /* TX event */ - { - .name = "tx", - .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, - .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, - .flags = IORESOURCE_DMA, - }, - /* RX event */ - { - .name = "rx", - .start = DAVINCI_DA830_DMA_MCASP1_AREVT, - .end = DAVINCI_DA830_DMA_MCASP1_AREVT, - .flags = IORESOURCE_DMA, - }, - { - .name = "common", - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da830_mcasp1_device = { - .name = "davinci-mcasp", - .id = 1, - .num_resources = ARRAY_SIZE(da830_mcasp1_resources), - .resource = da830_mcasp1_resources, -}; - -static struct resource da830_mcasp2_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DA830_MCASP2_REG_BASE, - .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, - .flags = IORESOURCE_MEM, - }, - /* TX event */ - { - .name = "tx", - .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, - .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, - .flags = IORESOURCE_DMA, - }, - /* RX event */ - { - .name = "rx", - .start = DAVINCI_DA830_DMA_MCASP2_AREVT, - .end = DAVINCI_DA830_DMA_MCASP2_AREVT, - .flags = IORESOURCE_DMA, - }, - { - .name = "common", - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da830_mcasp2_device = { - .name = "davinci-mcasp", - .id = 2, - .num_resources = ARRAY_SIZE(da830_mcasp2_resources), - .resource = da830_mcasp2_resources, -}; - -static struct resource da850_mcasp_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DA8XX_MCASP0_REG_BASE, - .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, - .flags = IORESOURCE_MEM, - }, - /* TX event */ - { - .name = "tx", - .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, - .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, - .flags = IORESOURCE_DMA, - }, - /* RX event */ - { - .name = "rx", - .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, - .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, - .flags = IORESOURCE_DMA, - }, - { - .name = "common", - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da850_mcasp_device = { - .name = "davinci-mcasp", - .id = 0, - .num_resources = ARRAY_SIZE(da850_mcasp_resources), - .resource = da850_mcasp_resources, -}; - -void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) -{ - struct platform_device *pdev; - - switch (id) { - case 0: - /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ - pdev = &da850_mcasp_device; - break; - case 1: - /* Valid for DA830/OMAP-L137 only */ - if (!cpu_is_davinci_da830()) - return; - pdev = &da830_mcasp1_device; - break; - case 2: - /* Valid for DA830/OMAP-L137 only */ - if (!cpu_is_davinci_da830()) - return; - pdev = &da830_mcasp2_device; - break; - default: - return; - } - - pdev->dev.platform_data = pdata; - platform_device_register(pdev); -} - -static struct resource da8xx_pruss_resources[] = { - { - .start = DA8XX_PRUSS_MEM_BASE, - .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { - .pintc_base = 0x4000, -}; - -static struct platform_device da8xx_uio_pruss_dev = { - .name = "pruss_uio", - .id = -1, - .num_resources = ARRAY_SIZE(da8xx_pruss_resources), - .resource = da8xx_pruss_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &da8xx_uio_pruss_pdata, - } -}; - -int __init da8xx_register_uio_pruss(void) -{ - da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); - return platform_device_register(&da8xx_uio_pruss_dev); -} - -static struct lcd_ctrl_config lcd_cfg = { - .panel_shade = COLOR_ACTIVE, - .bpp = 16, -}; - -struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { - .manu_name = "sharp", - .controller_data = &lcd_cfg, - .type = "Sharp_LCD035Q3DG01", -}; - -struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { - .manu_name = "sharp", - .controller_data = &lcd_cfg, - .type = "Sharp_LK043T1DG01", -}; - -static struct resource da8xx_lcdc_resources[] = { - [0] = { /* registers */ - .start = DA8XX_LCD_CNTRL_BASE, - .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_lcdc_device = { - .name = "da8xx_lcdc", - .id = 0, - .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), - .resource = da8xx_lcdc_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; - -int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) -{ - da8xx_lcdc_device.dev.platform_data = pdata; - return platform_device_register(&da8xx_lcdc_device); -} - -static struct resource da8xx_gpio_resources[] = { - { /* registers */ - .start = DA8XX_GPIO_BASE, - .end = DA8XX_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_gpio_device = { - .name = "davinci_gpio", - .id = -1, - .num_resources = ARRAY_SIZE(da8xx_gpio_resources), - .resource = da8xx_gpio_resources, -}; - -int __init da8xx_register_gpio(void *pdata) -{ - da8xx_gpio_device.dev.platform_data = pdata; - return platform_device_register(&da8xx_gpio_device); -} - -static struct resource da8xx_mmcsd0_resources[] = { - { /* registers */ - .start = DA8XX_MMCSD0_BASE, - .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_mmcsd0_device = { - .name = "da830-mmc", - .id = 0, - .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), - .resource = da8xx_mmcsd0_resources, -}; - -int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) -{ - da8xx_mmcsd0_device.dev.platform_data = config; - return platform_device_register(&da8xx_mmcsd0_device); -} - -#ifdef CONFIG_ARCH_DAVINCI_DA850 -static struct resource da850_mmcsd1_resources[] = { - { /* registers */ - .start = DA850_MMCSD1_BASE, - .end = DA850_MMCSD1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), - .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da850_mmcsd1_device = { - .name = "da830-mmc", - .id = 1, - .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), - .resource = da850_mmcsd1_resources, -}; - -int __init da850_register_mmcsd1(struct davinci_mmc_config *config) -{ - da850_mmcsd1_device.dev.platform_data = config; - return platform_device_register(&da850_mmcsd1_device); -} -#endif - -static struct resource da8xx_rproc_resources[] = { - { /* DSP boot address */ - .name = "host1cfg", - .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, - .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, - .flags = IORESOURCE_MEM, - }, - { /* DSP interrupt registers */ - .name = "chipsig", - .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, - .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, - .flags = IORESOURCE_MEM, - }, - { /* DSP L2 RAM */ - .name = "l2sram", - .start = DA8XX_DSP_L2_RAM_BASE, - .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, - .flags = IORESOURCE_MEM, - }, - { /* DSP L1P RAM */ - .name = "l1pram", - .start = DA8XX_DSP_L1P_RAM_BASE, - .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { /* DSP L1D RAM */ - .name = "l1dram", - .start = DA8XX_DSP_L1D_RAM_BASE, - .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { /* dsp irq */ - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_dsp = { - .name = "davinci-rproc", - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(da8xx_rproc_resources), - .resource = da8xx_rproc_resources, -}; - -static bool rproc_mem_inited __initdata; - -#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) - -static phys_addr_t rproc_base __initdata; -static unsigned long rproc_size __initdata; - -static int __init early_rproc_mem(char *p) -{ - char *endp; - - if (p == NULL) - return 0; - - rproc_size = memparse(p, &endp); - if (*endp == '@') - rproc_base = memparse(endp + 1, NULL); - - return 0; -} -early_param("rproc_mem", early_rproc_mem); - -void __init da8xx_rproc_reserve_cma(void) -{ - int ret; - - if (!rproc_base || !rproc_size) { - pr_err("%s: 'rproc_mem=nn@address' badly specified\n" - " 'nn' and 'address' must both be non-zero\n", - __func__); - - return; - } - - pr_info("%s: reserving 0x%lx @ 0x%lx...\n", - __func__, rproc_size, (unsigned long)rproc_base); - - ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); - if (ret) - pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); - else - rproc_mem_inited = true; -} - -#else - -void __init da8xx_rproc_reserve_cma(void) -{ -} - -#endif - -int __init da8xx_register_rproc(void) -{ - int ret; - - if (!rproc_mem_inited) { - pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", - __func__); - return -ENOMEM; - } - - ret = platform_device_register(&da8xx_dsp); - if (ret) - pr_err("%s: can't register DSP device: %d\n", __func__, ret); - - return ret; -}; - -static struct resource da8xx_rtc_resources[] = { - { - .start = DA8XX_RTC_BASE, - .end = DA8XX_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* timer irq */ - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), - .flags = IORESOURCE_IRQ, - }, - { /* alarm irq */ - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_rtc_device = { - .name = "da830-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(da8xx_rtc_resources), - .resource = da8xx_rtc_resources, -}; - -int da8xx_register_rtc(void) -{ - return platform_device_register(&da8xx_rtc_device); -} - static void __iomem *da8xx_ddr2_ctlr_base; void __iomem * __init da8xx_get_mem_ctlr(void) { @@ -972,192 +68,3 @@ void __iomem * __init da8xx_get_mem_ctlr(void) return da8xx_ddr2_ctlr_base; } - -static struct resource da8xx_cpuidle_resources[] = { - { - .start = DA8XX_DDR2_CTL_BASE, - .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -/* DA8XX devices support DDR2 power down */ -static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { - .ddr2_pdown = 1, -}; - - -static struct platform_device da8xx_cpuidle_device = { - .name = "cpuidle-davinci", - .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), - .resource = da8xx_cpuidle_resources, - .dev = { - .platform_data = &da8xx_cpuidle_pdata, - }, -}; - -int __init da8xx_register_cpuidle(void) -{ - da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); - - return platform_device_register(&da8xx_cpuidle_device); -} - -static struct resource da8xx_spi0_resources[] = { - [0] = { - .start = DA8XX_SPI0_BASE, - .end = DA8XX_SPI0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource da8xx_spi1_resources[] = { - [0] = { - .start = DA830_SPI1_BASE, - .end = DA830_SPI1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_spi_platform_data da8xx_spi_pdata[] = { - [0] = { - .version = SPI_VERSION_2, - .intr_line = 1, - .dma_event_q = EVENTQ_0, - .prescaler_limit = 2, - }, - [1] = { - .version = SPI_VERSION_2, - .intr_line = 1, - .dma_event_q = EVENTQ_0, - .prescaler_limit = 2, - }, -}; - -static struct platform_device da8xx_spi_device[] = { - [0] = { - .name = "spi_davinci", - .id = 0, - .num_resources = ARRAY_SIZE(da8xx_spi0_resources), - .resource = da8xx_spi0_resources, - .dev = { - .platform_data = &da8xx_spi_pdata[0], - }, - }, - [1] = { - .name = "spi_davinci", - .id = 1, - .num_resources = ARRAY_SIZE(da8xx_spi1_resources), - .resource = da8xx_spi1_resources, - .dev = { - .platform_data = &da8xx_spi_pdata[1], - }, - }, -}; - -int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) -{ - if (instance < 0 || instance > 1) - return -EINVAL; - - da8xx_spi_pdata[instance].num_chipselect = num_chipselect; - - if (instance == 1 && cpu_is_davinci_da850()) { - da8xx_spi1_resources[0].start = DA850_SPI1_BASE; - da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; - } - - return platform_device_register(&da8xx_spi_device[instance]); -} - -#ifdef CONFIG_ARCH_DAVINCI_DA850 -int __init da850_register_sata_refclk(int rate) -{ - struct clk *clk; - - clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - return clk_register_clkdev(clk, "refclk", "ahci_da850"); -} - -static struct resource da850_sata_resources[] = { - { - .start = DA850_SATA_BASE, - .end = DA850_SATA_BASE + 0x1fff, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, - .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 da850_sata_dmamask = DMA_BIT_MASK(32); - -static struct platform_device da850_sata_device = { - .name = "ahci_da850", - .id = -1, - .dev = { - .dma_mask = &da850_sata_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(da850_sata_resources), - .resource = da850_sata_resources, -}; - -int __init da850_register_sata(unsigned long refclkpn) -{ - int ret; - - ret = da850_register_sata_refclk(refclkpn); - if (ret) - return ret; - - return platform_device_register(&da850_sata_device); -} -#endif - -static struct regmap *da8xx_cfgchip; - -static const struct regmap_config da8xx_cfgchip_config __initconst = { - .name = "cfgchip", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, -}; - -/** - * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap - * - * This is for use on non-DT boards only. For DT boards, use - * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") - * - * Returns: Pointer to the CFGCHIP regmap or negative error code. - */ -struct regmap * __init da8xx_get_cfgchip(void) -{ - if (IS_ERR_OR_NULL(da8xx_cfgchip)) - da8xx_cfgchip = regmap_init_mmio(NULL, - DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), - &da8xx_cfgchip_config); - - return da8xx_cfgchip; -} diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c deleted file mode 100644 index 3e447d468845..000000000000 --- a/arch/arm/mach-davinci/devices.c +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * mach-davinci/devices.c - * - * DaVinci platform device setup/initialization - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/edma.h> -#include <linux/dma-mapping.h> -#include <linux/io.h> -#include <linux/reboot.h> - -#include <mach/hardware.h> -#include <mach/cputype.h> -#include <mach/mux.h> -#include <mach/time.h> - -#include "davinci.h" -#include "irqs.h" - -#define DAVINCI_I2C_BASE 0x01C21000 -#define DAVINCI_ATA_BASE 0x01C66000 -#define DAVINCI_MMCSD0_BASE 0x01E10000 -#define DM355_MMCSD0_BASE 0x01E11000 -#define DM355_MMCSD1_BASE 0x01E00000 -#define DM365_MMCSD0_BASE 0x01D11000 -#define DM365_MMCSD1_BASE 0x01D00000 - -void __iomem *davinci_sysmod_base; - -void davinci_map_sysmod(void) -{ - davinci_sysmod_base = ioremap_nocache(DAVINCI_SYSTEM_MODULE_BASE, - 0x800); - /* - * Throw a bug since a lot of board initialization code depends - * on system module availability. ioremap() failing this early - * need careful looking into anyway. - */ - BUG_ON(!davinci_sysmod_base); -} - -static struct resource i2c_resources[] = { - { - .start = DAVINCI_I2C_BASE, - .end = DAVINCI_I2C_BASE + 0x40, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_I2C), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device davinci_i2c_device = { - .name = "i2c_davinci", - .id = 1, - .num_resources = ARRAY_SIZE(i2c_resources), - .resource = i2c_resources, -}; - -void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) -{ - if (cpu_is_davinci_dm644x()) - davinci_cfg_reg(DM644X_I2C); - - davinci_i2c_device.dev.platform_data = pdata; - (void) platform_device_register(&davinci_i2c_device); -} - -static struct resource ide_resources[] = { - { - .start = DAVINCI_ATA_BASE, - .end = DAVINCI_ATA_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_IDE), - .end = DAVINCI_INTC_IRQ(IRQ_IDE), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ide_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device ide_device = { - .name = "palm_bk3710", - .id = -1, - .resource = ide_resources, - .num_resources = ARRAY_SIZE(ide_resources), - .dev = { - .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init davinci_init_ide(void) -{ - if (cpu_is_davinci_dm644x()) { - davinci_cfg_reg(DM644X_HPIEN_DISABLE); - davinci_cfg_reg(DM644X_ATAEN); - davinci_cfg_reg(DM644X_HDIREN); - } else if (cpu_is_davinci_dm646x()) { - /* IRQ_DM646X_IDE is the same as IRQ_IDE */ - davinci_cfg_reg(DM646X_ATAEN); - } else { - WARN_ON(1); - return; - } - - platform_device_register(&ide_device); -} - -#if IS_ENABLED(CONFIG_MMC_DAVINCI) - -static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); - -static struct resource mmcsd0_resources[] = { - { - /* different on dm355 */ - .start = DAVINCI_MMCSD0_BASE, - .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - /* IRQs: MMC/SD, then SDIO */ - { - .start = DAVINCI_INTC_IRQ(IRQ_MMCINT), - .flags = IORESOURCE_IRQ, - }, { - /* different on dm355 */ - .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device davinci_mmcsd0_device = { - .name = "dm6441-mmc", - .id = 0, - .dev = { - .dma_mask = &mmcsd0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmcsd0_resources), - .resource = mmcsd0_resources, -}; - -static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); - -static struct resource mmcsd1_resources[] = { - { - .start = DM355_MMCSD1_BASE, - .end = DM355_MMCSD1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - /* IRQs: MMC/SD, then SDIO */ - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1), - .flags = IORESOURCE_IRQ, - }, { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device davinci_mmcsd1_device = { - .name = "dm6441-mmc", - .id = 1, - .dev = { - .dma_mask = &mmcsd1_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmcsd1_resources), - .resource = mmcsd1_resources, -}; - - -void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) -{ - struct platform_device *pdev = NULL; - - if (WARN_ON(cpu_is_davinci_dm646x())) - return; - - /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too; - * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused. - * - * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are - * not handled right here ... - */ - switch (module) { - case 1: - if (cpu_is_davinci_dm355()) { - /* REVISIT we may not need all these pins if e.g. this - * is a hard-wired SDIO device... - */ - davinci_cfg_reg(DM355_SD1_CMD); - davinci_cfg_reg(DM355_SD1_CLK); - davinci_cfg_reg(DM355_SD1_DATA0); - davinci_cfg_reg(DM355_SD1_DATA1); - davinci_cfg_reg(DM355_SD1_DATA2); - davinci_cfg_reg(DM355_SD1_DATA3); - } else if (cpu_is_davinci_dm365()) { - /* Configure pull down control */ - unsigned v; - - v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); - __raw_writel(v & ~0xfc0, - DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); - - mmcsd1_resources[0].start = DM365_MMCSD1_BASE; - mmcsd1_resources[0].end = DM365_MMCSD1_BASE + - SZ_4K - 1; - mmcsd1_resources[2].start = DAVINCI_INTC_IRQ( - IRQ_DM365_SDIOINT1); - davinci_mmcsd1_device.name = "da830-mmc"; - } else - break; - - pdev = &davinci_mmcsd1_device; - break; - case 0: - if (cpu_is_davinci_dm355()) { - mmcsd0_resources[0].start = DM355_MMCSD0_BASE; - mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; - mmcsd0_resources[2].start = DAVINCI_INTC_IRQ( - IRQ_DM355_SDIOINT0); - - /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ - davinci_cfg_reg(DM355_MMCSD0); - - /* enable RX EDMA */ - davinci_cfg_reg(DM355_EVT26_MMC0_RX); - } else if (cpu_is_davinci_dm365()) { - mmcsd0_resources[0].start = DM365_MMCSD0_BASE; - mmcsd0_resources[0].end = DM365_MMCSD0_BASE + - SZ_4K - 1; - mmcsd0_resources[2].start = DAVINCI_INTC_IRQ( - IRQ_DM365_SDIOINT0); - davinci_mmcsd0_device.name = "da830-mmc"; - } else if (cpu_is_davinci_dm644x()) { - /* REVISIT: should this be in board-init code? */ - /* Power-on 3.3V IO cells */ - __raw_writel(0, - DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); - /*Set up the pull regiter for MMC */ - davinci_cfg_reg(DM644X_MSTK); - } - - pdev = &davinci_mmcsd0_device; - break; - } - - if (WARN_ON(!pdev)) - return; - - pdev->dev.platform_data = config; - platform_device_register(pdev); -} - -#else - -void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) -{ -} - -#endif - -/*-------------------------------------------------------------------------*/ - -static struct resource wdt_resources[] = { - { - .start = DAVINCI_WDOG_BASE, - .end = DAVINCI_WDOG_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_wdt_device = { - .name = "davinci-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -int davinci_init_wdt(void) -{ - return platform_device_register(&davinci_wdt_device); -} - -static struct platform_device davinci_gpio_device = { - .name = "davinci_gpio", - .id = -1, -}; - -int davinci_gpio_register(struct resource *res, int size, void *pdata) -{ - davinci_gpio_device.resource = res; - davinci_gpio_device.num_resources = size; - davinci_gpio_device.dev.platform_data = pdata; - return platform_device_register(&davinci_gpio_device); -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -struct davinci_timer_instance davinci_timer_instance[2] = { - { - .base = DAVINCI_TIMER0_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12), - .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34), - }, - { - .base = DAVINCI_TIMER1_BASE, - .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12), - .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34), - }, -}; - diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c deleted file mode 100644 index 5de72d2fa8f0..000000000000 --- a/arch/arm/mach-davinci/dm355.c +++ /dev/null @@ -1,836 +0,0 @@ -/* - * TI DaVinci DM355 chip specific setup - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/clk-provider.h> -#include <linux/clk/davinci.h> -#include <linux/clkdev.h> -#include <linux/dma-mapping.h> -#include <linux/dmaengine.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/irq-davinci-aintc.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/spi-davinci.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/spi/spi.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/mux.h> -#include <mach/serial.h> - -#include <clocksource/timer-davinci.h> - -#include "asp.h" -#include "davinci.h" -#include "irqs.h" -#include "mux.h" - -#define DM355_UART2_BASE (IO_PHYS + 0x206000) -#define DM355_OSD_BASE (IO_PHYS + 0x70200) -#define DM355_VENC_BASE (IO_PHYS + 0x70400) - -/* - * Device specific clocks - */ -#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ - -static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); - -static struct resource dm355_spi0_resources[] = { - { - .start = 0x01c66000, - .end = 0x01c667ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_spi_platform_data dm355_spi0_pdata = { - .version = SPI_VERSION_1, - .num_chipselect = 2, - .cshold_bug = true, - .dma_event_q = EVENTQ_1, - .prescaler_limit = 1, -}; -static struct platform_device dm355_spi0_device = { - .name = "spi_davinci", - .id = 0, - .dev = { - .dma_mask = &dm355_spi0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dm355_spi0_pdata, - }, - .num_resources = ARRAY_SIZE(dm355_spi0_resources), - .resource = dm355_spi0_resources, -}; - -void __init dm355_init_spi0(unsigned chipselect_mask, - const struct spi_board_info *info, unsigned len) -{ - /* for now, assume we need MISO */ - davinci_cfg_reg(DM355_SPI0_SDI); - - /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM355_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM355_SPI0_SDENA1); - - spi_register_board_info(info, len); - - platform_device_register(&dm355_spi0_device); -} - -/*----------------------------------------------------------------------*/ - -#define INTMUX 0x18 -#define EVTMUX 0x1c - -/* - * Device specific mux setup - * - * soc description mux mode mode mux dbg - * reg offset mask mode - */ -static const struct mux_config dm355_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) - -MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) -MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false) -MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false) -MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false) -MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false) -MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false) - -MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false) -MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false) - -MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) -MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) -MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) -MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) - -MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) -MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) -MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) - -INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false) -INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false) -INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) - -EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) -EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) -EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) - -MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) -MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) -MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) -MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) -MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) - -MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) -MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) -MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) -MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) -MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) -MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false) -MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false) -#endif -}; - -static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM355_CCDC_VDINT0] = 2, - [IRQ_DM355_CCDC_VDINT1] = 6, - [IRQ_DM355_CCDC_VDINT2] = 6, - [IRQ_DM355_IPIPE_HST] = 6, - [IRQ_DM355_H3AINT] = 6, - [IRQ_DM355_IPIPE_SDR] = 6, - [IRQ_DM355_IPIPEIFINT] = 6, - [IRQ_DM355_OSDINT] = 7, - [IRQ_DM355_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM355_RTOINT] = 4, - [IRQ_DM355_UARTINT2] = 7, - [IRQ_DM355_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_DM355_SPINT2_1] = 7, - [IRQ_DM355_TINT7] = 4, - [IRQ_DM355_SDIOINT0] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_DM355_MMCINT1] = 7, - [IRQ_DM355_PWMINT3] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_DM355_SDIOINT1] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM355_SPINT0_0] = 3, - [IRQ_DM355_SPINT0_1] = 3, - [IRQ_DM355_GPIO0] = 3, - [IRQ_DM355_GPIO1] = 7, - [IRQ_DM355_GPIO2] = 4, - [IRQ_DM355_GPIO3] = 4, - [IRQ_DM355_GPIO4] = 7, - [IRQ_DM355_GPIO5] = 7, - [IRQ_DM355_GPIO6] = 7, - [IRQ_DM355_GPIO7] = 7, - [IRQ_DM355_GPIO8] = 7, - [IRQ_DM355_GPIO9] = 7, - [IRQ_DM355_GPIOBNK0] = 7, - [IRQ_DM355_GPIOBNK1] = 7, - [IRQ_DM355_GPIOBNK2] = 7, - [IRQ_DM355_GPIOBNK3] = 7, - [IRQ_DM355_GPIOBNK4] = 7, - [IRQ_DM355_GPIOBNK5] = 7, - [IRQ_DM355_GPIOBNK6] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -/*----------------------------------------------------------------------*/ - -static s8 queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1}, -}; - -static const struct dma_slave_map dm355_edma_map[] = { - { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) }, - { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) }, - { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, - { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, - { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, - { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, - { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, - { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, - { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, - { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, - { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, - { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, -}; - -static struct edma_soc_info dm355_edma_pdata = { - .queue_priority_mapping = queue_priority_mapping, - .default_queue = EVENTQ_1, - .slave_map = dm355_edma_map, - .slavecnt = ARRAY_SIZE(dm355_edma_map), -}; - -static struct resource edma_resources[] = { - { - .name = "edma3_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), - .flags = IORESOURCE_IRQ, - }, - /* not using (or muxing) TC*_ERR */ -}; - -static const struct platform_device_info dm355_edma_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = edma_resources, - .num_res = ARRAY_SIZE(edma_resources), - .data = &dm355_edma_pdata, - .size_data = sizeof(dm355_edma_pdata), -}; - -static struct resource dm355_asp1_resources[] = { - { - .name = "mpu", - .start = DAVINCI_ASP1_BASE, - .end = DAVINCI_ASP1_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_ASP1_TX, - .end = DAVINCI_DMA_ASP1_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_ASP1_RX, - .end = DAVINCI_DMA_ASP1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm355_asp1_device = { - .name = "davinci-mcbsp", - .id = 1, - .num_resources = ARRAY_SIZE(dm355_asp1_resources), - .resource = dm355_asp1_resources, -}; - -static void dm355_ccdc_setup_pinmux(void) -{ - davinci_cfg_reg(DM355_VIN_PCLK); - davinci_cfg_reg(DM355_VIN_CAM_WEN); - davinci_cfg_reg(DM355_VIN_CAM_VD); - davinci_cfg_reg(DM355_VIN_CAM_HD); - davinci_cfg_reg(DM355_VIN_YIN_EN); - davinci_cfg_reg(DM355_VIN_CINL_EN); - davinci_cfg_reg(DM355_VIN_CINH_EN); -} - -static struct resource dm355_vpss_resources[] = { - { - /* VPSS BL Base address */ - .name = "vpss", - .start = 0x01c70800, - .end = 0x01c70800 + 0xff, - .flags = IORESOURCE_MEM, - }, - { - /* VPSS CLK Base address */ - .name = "vpss", - .start = 0x01c70000, - .end = 0x01c70000 + 0xf, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm355_vpss_device = { - .name = "vpss", - .id = -1, - .dev.platform_data = "dm355_vpss", - .num_resources = ARRAY_SIZE(dm355_vpss_resources), - .resource = dm355_vpss_resources, -}; - -static struct resource vpfe_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); -static struct resource dm355_ccdc_resource[] = { - /* CCDC Base address */ - { - .flags = IORESOURCE_MEM, - .start = 0x01c70600, - .end = 0x01c70600 + 0x1ff, - }, -}; -static struct platform_device dm355_ccdc_dev = { - .name = "dm355_ccdc", - .id = -1, - .num_resources = ARRAY_SIZE(dm355_ccdc_resource), - .resource = dm355_ccdc_resource, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = dm355_ccdc_setup_pinmux, - }, -}; - -static struct platform_device vpfe_capture_dev = { - .name = CAPTURE_DRV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(vpfe_resources), - .resource = vpfe_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm355_osd_resources[] = { - { - .start = DM355_OSD_BASE, - .end = DM355_OSD_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm355_osd_dev = { - .name = DM355_VPBE_OSD_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm355_osd_resources), - .resource = dm355_osd_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm355_venc_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM355_VENC_BASE, - .end = DM355_VENC_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, - /* VDAC config register io space */ - { - .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, - .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource dm355_v4l2_disp_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM355_VENC_BASE, - .end = DM355_VENC_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, -}; - -static int dm355_vpbe_setup_pinmux(u32 if_type, int field) -{ - switch (if_type) { - case MEDIA_BUS_FMT_SGRBG8_1X8: - davinci_cfg_reg(DM355_VOUT_FIELD_G70); - break; - case MEDIA_BUS_FMT_YUYV10_1X20: - if (field) - davinci_cfg_reg(DM355_VOUT_FIELD); - else - davinci_cfg_reg(DM355_VOUT_FIELD_G70); - break; - default: - return -EINVAL; - } - - davinci_cfg_reg(DM355_VOUT_COUTL_EN); - davinci_cfg_reg(DM355_VOUT_COUTH_EN); - - return 0; -} - -static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int pclock) -{ - void __iomem *vpss_clk_ctrl_reg; - - vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); - - switch (type) { - case VPBE_ENC_STD: - writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE, - vpss_clk_ctrl_reg); - break; - case VPBE_ENC_DV_TIMINGS: - if (pclock > 27000000) - /* - * For HD, use external clock source since we cannot - * support HD mode with internal clocks. - */ - writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg); - break; - default: - return -EINVAL; - } - - return 0; -} - -static struct platform_device dm355_vpbe_display = { - .name = "vpbe-v4l2", - .id = -1, - .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources), - .resource = dm355_v4l2_disp_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct venc_platform_data dm355_venc_pdata = { - .setup_pinmux = dm355_vpbe_setup_pinmux, - .setup_clock = dm355_venc_setup_clock, -}; - -static struct platform_device dm355_venc_dev = { - .name = DM355_VPBE_VENC_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm355_venc_resources), - .resource = dm355_venc_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *)&dm355_venc_pdata, - }, -}; - -static struct platform_device dm355_vpbe_dev = { - .name = "vpbe_controller", - .id = -1, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm355_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6), - .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm355_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 104, -}; - -int __init dm355_gpio_register(void) -{ - return davinci_gpio_register(dm355_gpio_resources, - ARRAY_SIZE(dm355_gpio_resources), - &dm355_gpio_platform_data); -} -/*----------------------------------------------------------------------*/ - -static struct map_desc dm355_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm355_ids[] = { - { - .variant = 0x0, - .part_no = 0xb73b, - .manufacturer = 0x00f, - .cpu_id = DAVINCI_CPU_ID_DM355, - .name = "dm355", - }, -}; - -/* - * Bottom half of timer0 is used for clockevent, top half is used for - * clocksource. - */ -static const struct davinci_timer_cfg dm355_timer_cfg = { - .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), - }, -}; - -static struct plat_serial8250_port dm355_serial0_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm355_serial1_platform_data[] = { - { - .mapbase = DAVINCI_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm355_serial2_platform_data[] = { - { - .mapbase = DM355_UART2_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device dm355_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm355_serial0_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dm355_serial1_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = dm355_serial2_platform_data, - } - }, - { - } -}; - -static const struct davinci_soc_info davinci_soc_info_dm355 = { - .io_desc = dm355_io_desc, - .io_desc_num = ARRAY_SIZE(dm355_io_desc), - .jtag_id_reg = 0x01c40028, - .ids = dm355_ids, - .ids_num = ARRAY_SIZE(dm355_ids), - .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, - .pinmux_pins = dm355_pins, - .pinmux_pins_num = ARRAY_SIZE(dm355_pins), - .sram_dma = 0x00010000, - .sram_len = SZ_32K, -}; - -void __init dm355_init_asp1(u32 evt_enable) -{ - /* we don't use ASP1 IRQs, or we'd need to mux them ... */ - if (evt_enable & ASP1_TX_EVT_EN) - davinci_cfg_reg(DM355_EVT8_ASP1_TX); - - if (evt_enable & ASP1_RX_EVT_EN) - davinci_cfg_reg(DM355_EVT9_ASP1_RX); - - platform_device_register(&dm355_asp1_device); -} - -void __init dm355_init(void) -{ - davinci_common_init(&davinci_soc_info_dm355); - davinci_map_sysmod(); -} - -void __init dm355_init_time(void) -{ - void __iomem *pll1, *psc; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); - - pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); - dm355_pll1_init(NULL, pll1, NULL); - - psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); - dm355_psc_init(NULL, psc); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &dm355_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource dm355_pll2_resources[] = { - { - .start = DAVINCI_PLL2_BASE, - .end = DAVINCI_PLL2_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm355_pll2_device = { - .name = "dm355-pll2", - .id = -1, - .resource = dm355_pll2_resources, - .num_resources = ARRAY_SIZE(dm355_pll2_resources), -}; - -void __init dm355_register_clocks(void) -{ - /* PLL1 and PSC are registered in dm355_init_time() */ - platform_device_register(&dm355_pll2_device); -} - -int __init dm355_init_video(struct vpfe_config *vpfe_cfg, - struct vpbe_config *vpbe_cfg) -{ - if (vpfe_cfg || vpbe_cfg) - platform_device_register(&dm355_vpss_device); - - if (vpfe_cfg) { - vpfe_capture_dev.dev.platform_data = vpfe_cfg; - platform_device_register(&dm355_ccdc_dev); - platform_device_register(&vpfe_capture_dev); - } - - if (vpbe_cfg) { - dm355_vpbe_dev.dev.platform_data = vpbe_cfg; - platform_device_register(&dm355_osd_dev); - platform_device_register(&dm355_venc_dev); - platform_device_register(&dm355_vpbe_dev); - platform_device_register(&dm355_vpbe_display); - } - - return 0; -} - -static const struct davinci_aintc_config dm355_aintc_config = { - .reg = { - .start = DAVINCI_ARM_INTC_BASE, - .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = 64, - .prios = dm355_default_priorities, -}; - -void __init dm355_init_irq(void) -{ - davinci_aintc_init(&dm355_aintc_config); -} - -static int __init dm355_init_devices(void) -{ - struct platform_device *edma_pdev; - int ret = 0; - - if (!cpu_is_davinci_dm355()) - return 0; - - davinci_cfg_reg(DM355_INT_EDMA_CC); - edma_pdev = platform_device_register_full(&dm355_edma_device); - if (IS_ERR(edma_pdev)) { - pr_warn("%s: Failed to register eDMA\n", __func__); - return PTR_ERR(edma_pdev); - } - - ret = davinci_init_wdt(); - if (ret) - pr_warn("%s: watchdog init failed: %d\n", __func__, ret); - - return ret; -} -postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c deleted file mode 100644 index 9fc5c73cc0be..000000000000 --- a/arch/arm/mach-davinci/dm365.c +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * TI DaVinci DM365 chip specific setup - * - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/clk-provider.h> -#include <linux/clk/davinci.h> -#include <linux/clkdev.h> -#include <linux/dma-mapping.h> -#include <linux/dmaengine.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/irq-davinci-aintc.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/keyscan-davinci.h> -#include <linux/platform_data/spi-davinci.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/spi/spi.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/mux.h> -#include <mach/serial.h> -#include <mach/time.h> - -#include "asp.h" -#include "davinci.h" -#include "irqs.h" -#include "mux.h" - -#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ -#define DM365_RTC_BASE 0x01c69000 -#define DM365_KEYSCAN_BASE 0x01c69400 -#define DM365_OSD_BASE 0x01c71c00 -#define DM365_VENC_BASE 0x01c71e00 -#define DAVINCI_DM365_VC_BASE 0x01d0c000 -#define DAVINCI_DMA_VC_TX 2 -#define DAVINCI_DMA_VC_RX 3 -#define DM365_EMAC_BASE 0x01d07000 -#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) -#define DM365_EMAC_CNTRL_OFFSET 0x0000 -#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000 -#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000 -#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000 - -#define INTMUX 0x18 -#define EVTMUX 0x1c - - -static const struct mux_config dm365_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) - -MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) -MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) -MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) -MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) -MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) -MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) - -MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) -MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) - -MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false) -MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false) -MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) -MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) -MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) -MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) -MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false) -MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false) - -MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) -MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) -MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) -MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) -MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) -MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) - -MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) -MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) -MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) -MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) -MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) - -MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) -MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) -MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) -MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) -MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) -MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) - -MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) -MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) -MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) -MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) -MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) -MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) -MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) -MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) -MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) -MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) -MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) - -MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false) - -MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) -MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) -MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) -MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) -MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) -MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) -MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) -MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) -MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) -MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) -MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) -MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) - -MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) -MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) -MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) -MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) -MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) - -MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) -MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) -MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) -MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) -MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) - -MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) -MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) -MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) -MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) -MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) - -MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) -MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) -MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) -MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) -MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) - -MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false) -MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false) -MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false) - -MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) -MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false) -MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false) -MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false) -MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) -MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) -MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false) - -MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) -MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) -MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) -MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) -MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) -MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) -MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) -MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) -MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) -MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) - -INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) -INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) -INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) -INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) -INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) -INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) -INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) -INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) -INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) -INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) -INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) -INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) -INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) -INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) -INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) - -EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false) -EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false) -EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false) -EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false) -#endif -}; - -static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); - -static struct davinci_spi_platform_data dm365_spi0_pdata = { - .version = SPI_VERSION_1, - .num_chipselect = 2, - .dma_event_q = EVENTQ_3, - .prescaler_limit = 1, -}; - -static struct resource dm365_spi0_resources[] = { - { - .start = 0x01c66000, - .end = 0x01c667ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_spi0_device = { - .name = "spi_davinci", - .id = 0, - .dev = { - .dma_mask = &dm365_spi0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dm365_spi0_pdata, - }, - .num_resources = ARRAY_SIZE(dm365_spi0_resources), - .resource = dm365_spi0_resources, -}; - -void __init dm365_init_spi0(unsigned chipselect_mask, - const struct spi_board_info *info, unsigned len) -{ - davinci_cfg_reg(DM365_SPI0_SCLK); - davinci_cfg_reg(DM365_SPI0_SDI); - davinci_cfg_reg(DM365_SPI0_SDO); - - /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM365_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM365_SPI0_SDENA1); - - spi_register_board_info(info, len); - - platform_device_register(&dm365_spi0_device); -} - -static struct resource dm365_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm365_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 104, - .gpio_unbanked = 8, -}; - -int __init dm365_gpio_register(void) -{ - return davinci_gpio_register(dm365_gpio_resources, - ARRAY_SIZE(dm365_gpio_resources), - &dm365_gpio_platform_data); -} - -static struct emac_platform_data dm365_emac_pdata = { - .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, - .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, - .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, - .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, - .version = EMAC_VERSION_2, -}; - -static struct resource dm365_emac_resources[] = { - { - .start = DM365_EMAC_BASE, - .end = DM365_EMAC_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &dm365_emac_pdata, - }, - .num_resources = ARRAY_SIZE(dm365_emac_resources), - .resource = dm365_emac_resources, -}; - -static struct resource dm365_mdio_resources[] = { - { - .start = DM365_EMAC_MDIO_BASE, - .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm365_mdio_device = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(dm365_mdio_resources), - .resource = dm365_mdio_resources, -}; - -static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_VDINT0] = 2, - [IRQ_VDINT1] = 6, - [IRQ_VDINT2] = 6, - [IRQ_HISTINT] = 6, - [IRQ_H3AINT] = 6, - [IRQ_PRVUINT] = 6, - [IRQ_RSZINT] = 6, - [IRQ_DM365_INSFINT] = 7, - [IRQ_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_DM365_IMCOPINT] = 4, - [IRQ_USBINT] = 4, - [IRQ_DM365_RTOINT] = 7, - [IRQ_DM365_TINT5] = 7, - [IRQ_DM365_TINT6] = 5, - [IRQ_CCINT0] = 5, - [IRQ_CCERRINT] = 5, - [IRQ_TCERRINT0] = 5, - [IRQ_TCERRINT] = 7, - [IRQ_PSCIN] = 4, - [IRQ_DM365_SPINT2_1] = 7, - [IRQ_DM365_TINT7] = 7, - [IRQ_DM365_SDIOINT0] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_DM365_MMCINT1] = 7, - [IRQ_DM365_PWMINT3] = 7, - [IRQ_AEMIFINT] = 2, - [IRQ_DM365_SDIOINT1] = 2, - [IRQ_TINT0_TINT12] = 7, - [IRQ_TINT0_TINT34] = 7, - [IRQ_TINT1_TINT12] = 7, - [IRQ_TINT1_TINT34] = 7, - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 3, - [IRQ_PWMINT2] = 3, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM365_RTCINT] = 3, - [IRQ_DM365_SPIINT0_0] = 3, - [IRQ_DM365_SPIINT3_0] = 3, - [IRQ_DM365_GPIO0] = 3, - [IRQ_DM365_GPIO1] = 7, - [IRQ_DM365_GPIO2] = 4, - [IRQ_DM365_GPIO3] = 4, - [IRQ_DM365_GPIO4] = 7, - [IRQ_DM365_GPIO5] = 7, - [IRQ_DM365_GPIO6] = 7, - [IRQ_DM365_GPIO7] = 7, - [IRQ_DM365_EMAC_RXTHRESH] = 7, - [IRQ_DM365_EMAC_RXPULSE] = 7, - [IRQ_DM365_EMAC_TXPULSE] = 7, - [IRQ_DM365_EMAC_MISCPULSE] = 7, - [IRQ_DM365_GPIO12] = 7, - [IRQ_DM365_GPIO13] = 7, - [IRQ_DM365_GPIO14] = 7, - [IRQ_DM365_GPIO15] = 7, - [IRQ_DM365_KEYINT] = 7, - [IRQ_DM365_TCERRINT2] = 7, - [IRQ_DM365_TCERRINT3] = 7, - [IRQ_DM365_EMUINT] = 7, -}; - -/* Four Transfer Controllers on DM365 */ -static s8 dm365_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 7}, - {1, 7}, - {2, 7}, - {3, 0}, - {-1, -1}, -}; - -static const struct dma_slave_map dm365_edma_map[] = { - { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, - { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, - { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, - { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, - { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, - { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, - { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) }, - { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) }, - { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, - { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, - { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, - { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, -}; - -static struct edma_soc_info dm365_edma_pdata = { - .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, - .slave_map = dm365_edma_map, - .slavecnt = ARRAY_SIZE(dm365_edma_map), -}; - -static struct resource edma_resources[] = { - { - .name = "edma3_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc2", - .start = 0x01c10800, - .end = 0x01c10800 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc3", - .start = 0x01c10c00, - .end = 0x01c10c00 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), - .flags = IORESOURCE_IRQ, - }, - /* not using TC*_ERR */ -}; - -static const struct platform_device_info dm365_edma_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = edma_resources, - .num_res = ARRAY_SIZE(edma_resources), - .data = &dm365_edma_pdata, - .size_data = sizeof(dm365_edma_pdata), -}; - -static struct resource dm365_asp_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DM365_ASP0_BASE, - .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_ASP0_TX, - .end = DAVINCI_DMA_ASP0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_ASP0_RX, - .end = DAVINCI_DMA_ASP0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm365_asp_device = { - .name = "davinci-mcbsp", - .id = -1, - .num_resources = ARRAY_SIZE(dm365_asp_resources), - .resource = dm365_asp_resources, -}; - -static struct resource dm365_vc_resources[] = { - { - .start = DAVINCI_DM365_VC_BASE, - .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_VC_TX, - .end = DAVINCI_DMA_VC_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_VC_RX, - .end = DAVINCI_DMA_VC_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm365_vc_device = { - .name = "davinci_voicecodec", - .id = -1, - .num_resources = ARRAY_SIZE(dm365_vc_resources), - .resource = dm365_vc_resources, -}; - -static struct resource dm365_rtc_resources[] = { - { - .start = DM365_RTC_BASE, - .end = DM365_RTC_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_rtc_device = { - .name = "rtc_davinci", - .id = 0, - .num_resources = ARRAY_SIZE(dm365_rtc_resources), - .resource = dm365_rtc_resources, -}; - -static struct map_desc dm365_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -static struct resource dm365_ks_resources[] = { - { - /* registers */ - .start = DM365_KEYSCAN_BASE, - .end = DM365_KEYSCAN_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT), - .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm365_ks_device = { - .name = "davinci_keyscan", - .id = 0, - .num_resources = ARRAY_SIZE(dm365_ks_resources), - .resource = dm365_ks_resources, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm365_ids[] = { - { - .variant = 0x0, - .part_no = 0xb83e, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM365, - .name = "dm365_rev1.1", - }, - { - .variant = 0x8, - .part_no = 0xb83e, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM365, - .name = "dm365_rev1.2", - }, -}; - -static struct davinci_timer_info dm365_timer_info = { - .timers = davinci_timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, -}; - -#define DM365_UART1_BASE (IO_PHYS + 0x106000) - -static struct plat_serial8250_port dm365_serial0_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm365_serial1_platform_data[] = { - { - .mapbase = DM365_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device dm365_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm365_serial0_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dm365_serial1_platform_data, - } - }, - { - } -}; - -static const struct davinci_soc_info davinci_soc_info_dm365 = { - .io_desc = dm365_io_desc, - .io_desc_num = ARRAY_SIZE(dm365_io_desc), - .jtag_id_reg = 0x01c40028, - .ids = dm365_ids, - .ids_num = ARRAY_SIZE(dm365_ids), - .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, - .pinmux_pins = dm365_pins, - .pinmux_pins_num = ARRAY_SIZE(dm365_pins), - .timer_info = &dm365_timer_info, - .emac_pdata = &dm365_emac_pdata, - .sram_dma = 0x00010000, - .sram_len = SZ_32K, -}; - -void __init dm365_init_asp(void) -{ - davinci_cfg_reg(DM365_MCBSP0_BDX); - davinci_cfg_reg(DM365_MCBSP0_X); - davinci_cfg_reg(DM365_MCBSP0_BFSX); - davinci_cfg_reg(DM365_MCBSP0_BDR); - davinci_cfg_reg(DM365_MCBSP0_R); - davinci_cfg_reg(DM365_MCBSP0_BFSR); - davinci_cfg_reg(DM365_EVT2_ASP_TX); - davinci_cfg_reg(DM365_EVT3_ASP_RX); - platform_device_register(&dm365_asp_device); -} - -void __init dm365_init_vc(void) -{ - davinci_cfg_reg(DM365_EVT2_VC_TX); - davinci_cfg_reg(DM365_EVT3_VC_RX); - platform_device_register(&dm365_vc_device); -} - -void __init dm365_init_ks(struct davinci_ks_platform_data *pdata) -{ - dm365_ks_device.dev.platform_data = pdata; - platform_device_register(&dm365_ks_device); -} - -void __init dm365_init_rtc(void) -{ - davinci_cfg_reg(DM365_INT_PRTCSS); - platform_device_register(&dm365_rtc_device); -} - -void __init dm365_init(void) -{ - davinci_common_init(&davinci_soc_info_dm365); - davinci_map_sysmod(); -} - -void __init dm365_init_time(void) -{ - void __iomem *pll1, *pll2, *psc; - struct clk *clk; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ); - - pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); - dm365_pll1_init(NULL, pll1, NULL); - - pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); - dm365_pll2_init(NULL, pll2, NULL); - - psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); - dm365_psc_init(NULL, psc); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - davinci_timer_init(clk); -} - -void __init dm365_register_clocks(void) -{ - /* all clocks are currently registered in dm365_init_time() */ -} - -static struct resource dm365_vpss_resources[] = { - { - /* VPSS ISP5 Base address */ - .name = "isp5", - .start = 0x01c70000, - .end = 0x01c70000 + 0xff, - .flags = IORESOURCE_MEM, - }, - { - /* VPSS CLK Base address */ - .name = "vpss", - .start = 0x01c70200, - .end = 0x01c70200 + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm365_vpss_device = { - .name = "vpss", - .id = -1, - .dev.platform_data = "dm365_vpss", - .num_resources = ARRAY_SIZE(dm365_vpss_resources), - .resource = dm365_vpss_resources, -}; - -static struct resource vpfe_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); -static struct platform_device vpfe_capture_dev = { - .name = CAPTURE_DRV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(vpfe_resources), - .resource = vpfe_resources, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static void dm365_isif_setup_pinmux(void) -{ - davinci_cfg_reg(DM365_VIN_CAM_WEN); - davinci_cfg_reg(DM365_VIN_CAM_VD); - davinci_cfg_reg(DM365_VIN_CAM_HD); - davinci_cfg_reg(DM365_VIN_YIN4_7_EN); - davinci_cfg_reg(DM365_VIN_YIN0_3_EN); -} - -static struct resource isif_resource[] = { - /* ISIF Base address */ - { - .start = 0x01c71000, - .end = 0x01c71000 + 0x1ff, - .flags = IORESOURCE_MEM, - }, - /* ISIF Linearization table 0 */ - { - .start = 0x1C7C000, - .end = 0x1C7C000 + 0x2ff, - .flags = IORESOURCE_MEM, - }, - /* ISIF Linearization table 1 */ - { - .start = 0x1C7C400, - .end = 0x1C7C400 + 0x2ff, - .flags = IORESOURCE_MEM, - }, -}; -static struct platform_device dm365_isif_dev = { - .name = "isif", - .id = -1, - .num_resources = ARRAY_SIZE(isif_resource), - .resource = isif_resource, - .dev = { - .dma_mask = &vpfe_capture_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = dm365_isif_setup_pinmux, - }, -}; - -static struct resource dm365_osd_resources[] = { - { - .start = DM365_OSD_BASE, - .end = DM365_OSD_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static u64 dm365_video_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device dm365_osd_dev = { - .name = DM365_VPBE_OSD_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm365_osd_resources), - .resource = dm365_osd_resources, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm365_venc_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM365_VENC_BASE, - .end = DM365_VENC_BASE + 0x177, - .flags = IORESOURCE_MEM, - }, - /* vdaccfg registers io space */ - { - .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, - .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource dm365_v4l2_disp_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, - /* venc registers io space */ - { - .start = DM365_VENC_BASE, - .end = DM365_VENC_BASE + 0x177, - .flags = IORESOURCE_MEM, - }, -}; - -static int dm365_vpbe_setup_pinmux(u32 if_type, int field) -{ - switch (if_type) { - case MEDIA_BUS_FMT_SGRBG8_1X8: - davinci_cfg_reg(DM365_VOUT_FIELD_G81); - davinci_cfg_reg(DM365_VOUT_COUTL_EN); - davinci_cfg_reg(DM365_VOUT_COUTH_EN); - break; - case MEDIA_BUS_FMT_YUYV10_1X20: - if (field) - davinci_cfg_reg(DM365_VOUT_FIELD); - else - davinci_cfg_reg(DM365_VOUT_FIELD_G81); - davinci_cfg_reg(DM365_VOUT_COUTL_EN); - davinci_cfg_reg(DM365_VOUT_COUTH_EN); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int pclock) -{ - void __iomem *vpss_clkctl_reg; - u32 val; - - vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); - - switch (type) { - case VPBE_ENC_STD: - val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; - break; - case VPBE_ENC_DV_TIMINGS: - if (pclock <= 27000000) { - val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; - } else { - /* set sysclk4 to output 74.25 MHz from pll1 */ - val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE | - VPSS_VENCCLKEN_ENABLE; - } - break; - default: - return -EINVAL; - } - writel(val, vpss_clkctl_reg); - - return 0; -} - -static struct platform_device dm365_vpbe_display = { - .name = "vpbe-v4l2", - .id = -1, - .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources), - .resource = dm365_v4l2_disp_resources, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct venc_platform_data dm365_venc_pdata = { - .setup_pinmux = dm365_vpbe_setup_pinmux, - .setup_clock = dm365_venc_setup_clock, -}; - -static struct platform_device dm365_venc_dev = { - .name = DM365_VPBE_VENC_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm365_venc_resources), - .resource = dm365_venc_resources, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *)&dm365_venc_pdata, - }, -}; - -static struct platform_device dm365_vpbe_dev = { - .name = "vpbe_controller", - .id = -1, - .dev = { - .dma_mask = &dm365_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -int __init dm365_init_video(struct vpfe_config *vpfe_cfg, - struct vpbe_config *vpbe_cfg) -{ - if (vpfe_cfg || vpbe_cfg) - platform_device_register(&dm365_vpss_device); - - if (vpfe_cfg) { - vpfe_capture_dev.dev.platform_data = vpfe_cfg; - platform_device_register(&dm365_isif_dev); - platform_device_register(&vpfe_capture_dev); - } - if (vpbe_cfg) { - dm365_vpbe_dev.dev.platform_data = vpbe_cfg; - platform_device_register(&dm365_osd_dev); - platform_device_register(&dm365_venc_dev); - platform_device_register(&dm365_vpbe_dev); - platform_device_register(&dm365_vpbe_display); - } - - return 0; -} - -static const struct davinci_aintc_config dm365_aintc_config = { - .reg = { - .start = DAVINCI_ARM_INTC_BASE, - .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = 64, - .prios = dm365_default_priorities, -}; - -void __init dm365_init_irq(void) -{ - davinci_aintc_init(&dm365_aintc_config); -} - -static int __init dm365_init_devices(void) -{ - struct platform_device *edma_pdev; - int ret = 0; - - if (!cpu_is_davinci_dm365()) - return 0; - - davinci_cfg_reg(DM365_INT_EDMA_CC); - edma_pdev = platform_device_register_full(&dm365_edma_device); - if (IS_ERR(edma_pdev)) { - pr_warn("%s: Failed to register eDMA\n", __func__); - return PTR_ERR(edma_pdev); - } - - platform_device_register(&dm365_mdio_device); - platform_device_register(&dm365_emac_device); - - ret = davinci_init_wdt(); - if (ret) - pr_warn("%s: watchdog init failed: %d\n", __func__, ret); - - return ret; -} -postcore_initcall(dm365_init_devices); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c deleted file mode 100644 index 24988939ae46..000000000000 --- a/arch/arm/mach-davinci/dm644x.c +++ /dev/null @@ -1,767 +0,0 @@ -/* - * TI DaVinci DM644x chip specific setup - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/clk-provider.h> -#include <linux/clk/davinci.h> -#include <linux/clkdev.h> -#include <linux/dmaengine.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/irq-davinci-aintc.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/mux.h> -#include <mach/serial.h> - -#include <clocksource/timer-davinci.h> - -#include "asp.h" -#include "davinci.h" -#include "irqs.h" -#include "mux.h" - -/* - * Device specific clocks - */ -#define DM644X_REF_FREQ 27000000 - -#define DM644X_EMAC_BASE 0x01c80000 -#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) -#define DM644X_EMAC_CNTRL_OFFSET 0x0000 -#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000 -#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 -#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 - -static struct emac_platform_data dm644x_emac_pdata = { - .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, - .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, - .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, - .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, - .version = EMAC_VERSION_1, -}; - -static struct resource dm644x_emac_resources[] = { - { - .start = DM644X_EMAC_BASE, - .end = DM644X_EMAC_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_EMACINT), - .end = DAVINCI_INTC_IRQ(IRQ_EMACINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm644x_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &dm644x_emac_pdata, - }, - .num_resources = ARRAY_SIZE(dm644x_emac_resources), - .resource = dm644x_emac_resources, -}; - -static struct resource dm644x_mdio_resources[] = { - { - .start = DM644X_EMAC_MDIO_BASE, - .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm644x_mdio_device = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(dm644x_mdio_resources), - .resource = dm644x_mdio_resources, -}; - -/* - * Device specific mux setup - * - * soc description mux mode mode mux dbg - * reg offset mask mode - */ -static const struct mux_config dm644x_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) -MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) -MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) - -MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) - -MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) -MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true) -MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true) -MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true) -MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true) -MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true) - -MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) - -MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) - -MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) - -MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) -MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) - -MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) - -MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) - -MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) - -MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) -MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) -MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) - -MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) - -MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) - -MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) -MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) -MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) -MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) - -MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) - -MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) -MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) -#endif -}; - -/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_VDINT0] = 2, - [IRQ_VDINT1] = 6, - [IRQ_VDINT2] = 6, - [IRQ_HISTINT] = 6, - [IRQ_H3AINT] = 6, - [IRQ_PRVUINT] = 6, - [IRQ_RSZINT] = 6, - [7] = 7, - [IRQ_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_VLCDINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_EMACINT] = 4, - [14] = 7, - [15] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_PSCIN] = 7, - [21] = 7, - [IRQ_IDE] = 4, - [23] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_SDIOINT] = 7, - [28] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_VLQINT] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_UARTINT2] = 3, - [IRQ_SPINT0] = 3, - [IRQ_SPINT1] = 3, - [45] = 7, - [IRQ_DSP2ARM0] = 4, - [IRQ_DSP2ARM1] = 4, - [IRQ_GPIO0] = 7, - [IRQ_GPIO1] = 7, - [IRQ_GPIO2] = 7, - [IRQ_GPIO3] = 7, - [IRQ_GPIO4] = 7, - [IRQ_GPIO5] = 7, - [IRQ_GPIO6] = 7, - [IRQ_GPIO7] = 7, - [IRQ_GPIOBNK0] = 7, - [IRQ_GPIOBNK1] = 7, - [IRQ_GPIOBNK2] = 7, - [IRQ_GPIOBNK3] = 7, - [IRQ_GPIOBNK4] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -/*----------------------------------------------------------------------*/ - -static s8 queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1}, -}; - -static const struct dma_slave_map dm644x_edma_map[] = { - { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) }, - { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) }, - { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, - { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, - { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, - { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, -}; - -static struct edma_soc_info dm644x_edma_pdata = { - .queue_priority_mapping = queue_priority_mapping, - .default_queue = EVENTQ_1, - .slave_map = dm644x_edma_map, - .slavecnt = ARRAY_SIZE(dm644x_edma_map), -}; - -static struct resource edma_resources[] = { - { - .name = "edma3_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), - .flags = IORESOURCE_IRQ, - }, - /* not using TC*_ERR */ -}; - -static const struct platform_device_info dm644x_edma_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = edma_resources, - .num_res = ARRAY_SIZE(edma_resources), - .data = &dm644x_edma_pdata, - .size_data = sizeof(dm644x_edma_pdata), -}; - -/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ -static struct resource dm644x_asp_resources[] = { - { - .name = "mpu", - .start = DAVINCI_ASP0_BASE, - .end = DAVINCI_ASP0_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_DMA_ASP0_TX, - .end = DAVINCI_DMA_ASP0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = DAVINCI_DMA_ASP0_RX, - .end = DAVINCI_DMA_ASP0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device dm644x_asp_device = { - .name = "davinci-mcbsp", - .id = -1, - .num_resources = ARRAY_SIZE(dm644x_asp_resources), - .resource = dm644x_asp_resources, -}; - -#define DM644X_VPSS_BASE 0x01c73400 - -static struct resource dm644x_vpss_resources[] = { - { - /* VPSS Base address */ - .name = "vpss", - .start = DM644X_VPSS_BASE, - .end = DM644X_VPSS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm644x_vpss_device = { - .name = "vpss", - .id = -1, - .dev.platform_data = "dm644x_vpss", - .num_resources = ARRAY_SIZE(dm644x_vpss_resources), - .resource = dm644x_vpss_resources, -}; - -static struct resource dm644x_vpfe_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .end = DAVINCI_INTC_IRQ(IRQ_VDINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32); -static struct resource dm644x_ccdc_resource[] = { - /* CCDC Base address */ - { - .start = 0x01c70400, - .end = 0x01c70400 + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm644x_ccdc_dev = { - .name = "dm644x_ccdc", - .id = -1, - .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), - .resource = dm644x_ccdc_resource, - .dev = { - .dma_mask = &dm644x_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct platform_device dm644x_vpfe_dev = { - .name = CAPTURE_DRV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm644x_vpfe_resources), - .resource = dm644x_vpfe_resources, - .dev = { - .dma_mask = &dm644x_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -#define DM644X_OSD_BASE 0x01c72600 - -static struct resource dm644x_osd_resources[] = { - { - .start = DM644X_OSD_BASE, - .end = DM644X_OSD_BASE + 0x1ff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm644x_osd_dev = { - .name = DM644X_VPBE_OSD_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm644x_osd_resources), - .resource = dm644x_osd_resources, - .dev = { - .dma_mask = &dm644x_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -#define DM644X_VENC_BASE 0x01c72400 - -static struct resource dm644x_venc_resources[] = { - { - .start = DM644X_VENC_BASE, - .end = DM644X_VENC_BASE + 0x17f, - .flags = IORESOURCE_MEM, - }, -}; - -#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0) -#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1) -#define DM644X_VPSS_VENCLKEN BIT(3) -#define DM644X_VPSS_DACCLKEN BIT(4) - -static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int pclock) -{ - int ret = 0; - u32 v = DM644X_VPSS_VENCLKEN; - - switch (type) { - case VPBE_ENC_STD: - v |= DM644X_VPSS_DACCLKEN; - writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); - break; - case VPBE_ENC_DV_TIMINGS: - if (pclock <= 27000000) { - v |= DM644X_VPSS_DACCLKEN; - writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); - } else { - /* - * For HD, use external clock source since - * HD requires higher clock rate - */ - v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE; - writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); - } - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static struct resource dm644x_v4l2_disp_resources[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .end = DAVINCI_INTC_IRQ(IRQ_VENCINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm644x_vpbe_display = { - .name = "vpbe-v4l2", - .id = -1, - .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources), - .resource = dm644x_v4l2_disp_resources, - .dev = { - .dma_mask = &dm644x_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct venc_platform_data dm644x_venc_pdata = { - .setup_clock = dm644x_venc_setup_clock, -}; - -static struct platform_device dm644x_venc_dev = { - .name = DM644X_VPBE_VENC_SUBDEV_NAME, - .id = -1, - .num_resources = ARRAY_SIZE(dm644x_venc_resources), - .resource = dm644x_venc_resources, - .dev = { - .dma_mask = &dm644x_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dm644x_venc_pdata, - }, -}; - -static struct platform_device dm644x_vpbe_dev = { - .name = "vpbe_controller", - .id = -1, - .dev = { - .dma_mask = &dm644x_video_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dm644_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0), - .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1), - .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2), - .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3), - .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4), - .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm644_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 71, -}; - -int __init dm644x_gpio_register(void) -{ - return davinci_gpio_register(dm644_gpio_resources, - ARRAY_SIZE(dm644_gpio_resources), - &dm644_gpio_platform_data); -} -/*----------------------------------------------------------------------*/ - -static struct map_desc dm644x_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm644x_ids[] = { - { - .variant = 0x0, - .part_no = 0xb700, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM6446, - .name = "dm6446", - }, - { - .variant = 0x1, - .part_no = 0xb700, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM6446, - .name = "dm6446a", - }, -}; - -/* - * Bottom half of timer0 is used for clockevent, top half is used for - * clocksource. - */ -static const struct davinci_timer_cfg dm644x_timer_cfg = { - .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), - }, -}; - -static struct plat_serial8250_port dm644x_serial0_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm644x_serial1_platform_data[] = { - { - .mapbase = DAVINCI_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm644x_serial2_platform_data[] = { - { - .mapbase = DAVINCI_UART2_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device dm644x_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm644x_serial0_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dm644x_serial1_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = dm644x_serial2_platform_data, - } - }, - { - } -}; - -static const struct davinci_soc_info davinci_soc_info_dm644x = { - .io_desc = dm644x_io_desc, - .io_desc_num = ARRAY_SIZE(dm644x_io_desc), - .jtag_id_reg = 0x01c40028, - .ids = dm644x_ids, - .ids_num = ARRAY_SIZE(dm644x_ids), - .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, - .pinmux_pins = dm644x_pins, - .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), - .emac_pdata = &dm644x_emac_pdata, - .sram_dma = 0x00008000, - .sram_len = SZ_16K, -}; - -void __init dm644x_init_asp(void) -{ - davinci_cfg_reg(DM644X_MCBSP); - platform_device_register(&dm644x_asp_device); -} - -void __init dm644x_init(void) -{ - davinci_common_init(&davinci_soc_info_dm644x); - davinci_map_sysmod(); -} - -void __init dm644x_init_time(void) -{ - void __iomem *pll1, *psc; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); - - pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); - dm644x_pll1_init(NULL, pll1, NULL); - - psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); - dm644x_psc_init(NULL, psc); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &dm644x_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource dm644x_pll2_resources[] = { - { - .start = DAVINCI_PLL2_BASE, - .end = DAVINCI_PLL2_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm644x_pll2_device = { - .name = "dm644x-pll2", - .id = -1, - .resource = dm644x_pll2_resources, - .num_resources = ARRAY_SIZE(dm644x_pll2_resources), -}; - -void __init dm644x_register_clocks(void) -{ - /* PLL1 and PSC are registered in dm644x_init_time() */ - platform_device_register(&dm644x_pll2_device); -} - -int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, - struct vpbe_config *vpbe_cfg) -{ - if (vpfe_cfg || vpbe_cfg) - platform_device_register(&dm644x_vpss_device); - - if (vpfe_cfg) { - dm644x_vpfe_dev.dev.platform_data = vpfe_cfg; - platform_device_register(&dm644x_ccdc_dev); - platform_device_register(&dm644x_vpfe_dev); - } - - if (vpbe_cfg) { - dm644x_vpbe_dev.dev.platform_data = vpbe_cfg; - platform_device_register(&dm644x_osd_dev); - platform_device_register(&dm644x_venc_dev); - platform_device_register(&dm644x_vpbe_dev); - platform_device_register(&dm644x_vpbe_display); - } - - return 0; -} - -static const struct davinci_aintc_config dm644x_aintc_config = { - .reg = { - .start = DAVINCI_ARM_INTC_BASE, - .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = 64, - .prios = dm644x_default_priorities, -}; - -void __init dm644x_init_irq(void) -{ - davinci_aintc_init(&dm644x_aintc_config); -} - -void __init dm644x_init_devices(void) -{ - struct platform_device *edma_pdev; - int ret; - - edma_pdev = platform_device_register_full(&dm644x_edma_device); - if (IS_ERR(edma_pdev)) - pr_warn("%s: Failed to register eDMA\n", __func__); - - platform_device_register(&dm644x_mdio_device); - platform_device_register(&dm644x_emac_device); - - ret = davinci_init_wdt(); - if (ret) - pr_warn("%s: watchdog init failed: %d\n", __func__, ret); - -} diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c deleted file mode 100644 index 4ffd028ed997..000000000000 --- a/arch/arm/mach-davinci/dm646x.c +++ /dev/null @@ -1,728 +0,0 @@ -/* - * TI DaVinci DM646x chip specific setup - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/clk-provider.h> -#include <linux/clk/davinci.h> -#include <linux/clkdev.h> -#include <linux/dma-mapping.h> -#include <linux/dmaengine.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irqchip/irq-davinci-aintc.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/mux.h> -#include <mach/serial.h> - -#include <clocksource/timer-davinci.h> - -#include "asp.h" -#include "davinci.h" -#include "irqs.h" -#include "mux.h" - -#define DAVINCI_VPIF_BASE (0x01C12000) - -#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ - BIT_MASK(0)) -#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ - BIT_MASK(8)) - -#define DM646X_EMAC_BASE 0x01c80000 -#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) -#define DM646X_EMAC_CNTRL_OFFSET 0x0000 -#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000 -#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000 -#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000 - -static struct emac_platform_data dm646x_emac_pdata = { - .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, - .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, - .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, - .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, - .version = EMAC_VERSION_2, -}; - -static struct resource dm646x_emac_resources[] = { - { - .start = DM646X_EMAC_BASE, - .end = DM646X_EMAC_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm646x_emac_device = { - .name = "davinci_emac", - .id = 1, - .dev = { - .platform_data = &dm646x_emac_pdata, - }, - .num_resources = ARRAY_SIZE(dm646x_emac_resources), - .resource = dm646x_emac_resources, -}; - -static struct resource dm646x_mdio_resources[] = { - { - .start = DM646X_EMAC_MDIO_BASE, - .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm646x_mdio_device = { - .name = "davinci_mdio", - .id = 0, - .num_resources = ARRAY_SIZE(dm646x_mdio_resources), - .resource = dm646x_mdio_resources, -}; - -/* - * Device specific mux setup - * - * soc description mux mode mode mux dbg - * reg offset mask mode - */ -static const struct mux_config dm646x_pins[] = { -#ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) - -MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) - -MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) - -MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) - -MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) - -MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) - -MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) - -MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) - -MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) - -MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) - -MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) - -MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) - -MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) - -MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) -#endif -}; - -static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM646X_VP_VERTINT0] = 7, - [IRQ_DM646X_VP_VERTINT1] = 7, - [IRQ_DM646X_VP_VERTINT2] = 7, - [IRQ_DM646X_VP_VERTINT3] = 7, - [IRQ_DM646X_VP_ERRINT] = 7, - [IRQ_DM646X_RESERVED_1] = 7, - [IRQ_DM646X_RESERVED_2] = 7, - [IRQ_DM646X_WDINT] = 7, - [IRQ_DM646X_CRGENINT0] = 7, - [IRQ_DM646X_CRGENINT1] = 7, - [IRQ_DM646X_TSIFINT0] = 7, - [IRQ_DM646X_TSIFINT1] = 7, - [IRQ_DM646X_VDCEINT] = 7, - [IRQ_DM646X_USBINT] = 7, - [IRQ_DM646X_USBDMAINT] = 7, - [IRQ_DM646X_PCIINT] = 7, - [IRQ_CCINT0] = 7, /* dma */ - [IRQ_CCERRINT] = 7, /* dma */ - [IRQ_TCERRINT0] = 7, /* dma */ - [IRQ_TCERRINT] = 7, /* dma */ - [IRQ_DM646X_TCERRINT2] = 7, - [IRQ_DM646X_TCERRINT3] = 7, - [IRQ_DM646X_IDE] = 7, - [IRQ_DM646X_HPIINT] = 7, - [IRQ_DM646X_EMACRXTHINT] = 7, - [IRQ_DM646X_EMACRXINT] = 7, - [IRQ_DM646X_EMACTXINT] = 7, - [IRQ_DM646X_EMACMISCINT] = 7, - [IRQ_DM646X_MCASP0TXINT] = 7, - [IRQ_DM646X_MCASP0RXINT] = 7, - [IRQ_DM646X_RESERVED_3] = 7, - [IRQ_DM646X_MCASP1TXINT] = 7, - [IRQ_TINT0_TINT12] = 7, /* clockevent */ - [IRQ_TINT0_TINT34] = 7, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_DM646X_VLQINT] = 7, - [IRQ_I2C] = 7, - [IRQ_UARTINT0] = 7, - [IRQ_UARTINT1] = 7, - [IRQ_DM646X_UARTINT2] = 7, - [IRQ_DM646X_SPINT0] = 7, - [IRQ_DM646X_SPINT1] = 7, - [IRQ_DM646X_DSP2ARMINT] = 7, - [IRQ_DM646X_RESERVED_4] = 7, - [IRQ_DM646X_PSCINT] = 7, - [IRQ_DM646X_GPIO0] = 7, - [IRQ_DM646X_GPIO1] = 7, - [IRQ_DM646X_GPIO2] = 7, - [IRQ_DM646X_GPIO3] = 7, - [IRQ_DM646X_GPIO4] = 7, - [IRQ_DM646X_GPIO5] = 7, - [IRQ_DM646X_GPIO6] = 7, - [IRQ_DM646X_GPIO7] = 7, - [IRQ_DM646X_GPIOBNK0] = 7, - [IRQ_DM646X_GPIOBNK1] = 7, - [IRQ_DM646X_GPIOBNK2] = 7, - [IRQ_DM646X_DDRINT] = 7, - [IRQ_DM646X_AEMIFINT] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -/*----------------------------------------------------------------------*/ - -/* Four Transfer Controllers on DM646x */ -static s8 dm646x_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 4}, - {1, 0}, - {2, 5}, - {3, 1}, - {-1, -1}, -}; - -static const struct dma_slave_map dm646x_edma_map[] = { - { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) }, - { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) }, - { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) }, - { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, - { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, -}; - -static struct edma_soc_info dm646x_edma_pdata = { - .queue_priority_mapping = dm646x_queue_priority_mapping, - .default_queue = EVENTQ_1, - .slave_map = dm646x_edma_map, - .slavecnt = ARRAY_SIZE(dm646x_edma_map), -}; - -static struct resource edma_resources[] = { - { - .name = "edma3_cc", - .start = 0x01c00000, - .end = 0x01c00000 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc0", - .start = 0x01c10000, - .end = 0x01c10000 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc1", - .start = 0x01c10400, - .end = 0x01c10400 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc2", - .start = 0x01c10800, - .end = 0x01c10800 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_tc3", - .start = 0x01c10c00, - .end = 0x01c10c00 + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma3_ccint", - .start = DAVINCI_INTC_IRQ(IRQ_CCINT0), - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma3_ccerrint", - .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT), - .flags = IORESOURCE_IRQ, - }, - /* not using TC*_ERR */ -}; - -static const struct platform_device_info dm646x_edma_device __initconst = { - .name = "edma", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), - .res = edma_resources, - .num_res = ARRAY_SIZE(edma_resources), - .data = &dm646x_edma_pdata, - .size_data = sizeof(dm646x_edma_pdata), -}; - -static struct resource dm646x_mcasp0_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DM646X_MCASP0_REG_BASE, - .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, - .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, - .flags = IORESOURCE_DMA, - }, - { - .name = "rx", - .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, - .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT), - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT), - .flags = IORESOURCE_IRQ, - }, -}; - -/* DIT mode only, rx is not supported */ -static struct resource dm646x_mcasp1_resources[] = { - { - .name = "mpu", - .start = DAVINCI_DM646X_MCASP1_REG_BASE, - .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, - .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dm646x_mcasp0_device = { - .name = "davinci-mcasp", - .id = 0, - .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), - .resource = dm646x_mcasp0_resources, -}; - -static struct platform_device dm646x_mcasp1_device = { - .name = "davinci-mcasp", - .id = 1, - .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), - .resource = dm646x_mcasp1_resources, -}; - -static struct platform_device dm646x_dit_device = { - .name = "spdif-dit", - .id = -1, -}; - -static u64 vpif_dma_mask = DMA_BIT_MASK(32); - -static struct resource vpif_resource[] = { - { - .start = DAVINCI_VPIF_BASE, - .end = DAVINCI_VPIF_BASE + 0x03ff, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device vpif_dev = { - .name = "vpif", - .id = -1, - .dev = { - .dma_mask = &vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = vpif_resource, - .num_resources = ARRAY_SIZE(vpif_resource), -}; - -static struct resource vpif_display_resource[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device vpif_display_dev = { - .name = "vpif_display", - .id = -1, - .dev = { - .dma_mask = &vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = vpif_display_resource, - .num_resources = ARRAY_SIZE(vpif_display_resource), -}; - -static struct resource vpif_capture_resource[] = { - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device vpif_capture_dev = { - .name = "vpif_capture", - .id = -1, - .dev = { - .dma_mask = &vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = vpif_capture_resource, - .num_resources = ARRAY_SIZE(vpif_capture_resource), -}; - -static struct resource dm646x_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1), - .flags = IORESOURCE_IRQ, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2), - .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm646x_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 43, -}; - -int __init dm646x_gpio_register(void) -{ - return davinci_gpio_register(dm646x_gpio_resources, - ARRAY_SIZE(dm646x_gpio_resources), - &dm646x_gpio_platform_data); -} -/*----------------------------------------------------------------------*/ - -static struct map_desc dm646x_io_desc[] = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id dm646x_ids[] = { - { - .variant = 0x0, - .part_no = 0xb770, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM6467, - .name = "dm6467_rev1.x", - }, - { - .variant = 0x1, - .part_no = 0xb770, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_DM6467, - .name = "dm6467_rev3.x", - }, -}; - -/* - * Bottom half of timer0 is used for clockevent, top half is used for - * clocksource. - */ -static const struct davinci_timer_cfg dm646x_timer_cfg = { - .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)), - }, -}; - -static struct plat_serial8250_port dm646x_serial0_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm646x_serial1_platform_data[] = { - { - .mapbase = DAVINCI_UART1_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port dm646x_serial2_platform_data[] = { - { - .mapbase = DAVINCI_UART2_BASE, - .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2), - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; - -struct platform_device dm646x_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm646x_serial0_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = dm646x_serial1_platform_data, - } - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = dm646x_serial2_platform_data, - } - }, - { - } -}; - -static const struct davinci_soc_info davinci_soc_info_dm646x = { - .io_desc = dm646x_io_desc, - .io_desc_num = ARRAY_SIZE(dm646x_io_desc), - .jtag_id_reg = 0x01c40028, - .ids = dm646x_ids, - .ids_num = ARRAY_SIZE(dm646x_ids), - .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, - .pinmux_pins = dm646x_pins, - .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), - .emac_pdata = &dm646x_emac_pdata, - .sram_dma = 0x10010000, - .sram_len = SZ_32K, -}; - -void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) -{ - dm646x_mcasp0_device.dev.platform_data = pdata; - platform_device_register(&dm646x_mcasp0_device); -} - -void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) -{ - dm646x_mcasp1_device.dev.platform_data = pdata; - platform_device_register(&dm646x_mcasp1_device); - platform_device_register(&dm646x_dit_device); -} - -void dm646x_setup_vpif(struct vpif_display_config *display_config, - struct vpif_capture_config *capture_config) -{ - unsigned int value; - - value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); - value &= ~VSCLKDIS_MASK; - __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); - - value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); - value &= ~VDD3P3V_VID_MASK; - __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); - - davinci_cfg_reg(DM646X_STSOMUX_DISABLE); - davinci_cfg_reg(DM646X_STSIMUX_DISABLE); - davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); - davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); - - vpif_display_dev.dev.platform_data = display_config; - vpif_capture_dev.dev.platform_data = capture_config; - platform_device_register(&vpif_dev); - platform_device_register(&vpif_display_dev); - platform_device_register(&vpif_capture_dev); -} - -int __init dm646x_init_edma(struct edma_rsv_info *rsv) -{ - struct platform_device *edma_pdev; - - dm646x_edma_pdata.rsv = rsv; - - edma_pdev = platform_device_register_full(&dm646x_edma_device); - return PTR_ERR_OR_ZERO(edma_pdev); -} - -void __init dm646x_init(void) -{ - davinci_common_init(&davinci_soc_info_dm646x); - davinci_map_sysmod(); -} - -void __init dm646x_init_time(unsigned long ref_clk_rate, - unsigned long aux_clkin_rate) -{ - void __iomem *pll1, *psc; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); - clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); - - pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); - dm646x_pll1_init(NULL, pll1, NULL); - - psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); - dm646x_psc_init(NULL, psc); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &dm646x_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource dm646x_pll2_resources[] = { - { - .start = DAVINCI_PLL2_BASE, - .end = DAVINCI_PLL2_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dm646x_pll2_device = { - .name = "dm646x-pll2", - .id = -1, - .resource = dm646x_pll2_resources, - .num_resources = ARRAY_SIZE(dm646x_pll2_resources), -}; - -void __init dm646x_register_clocks(void) -{ - /* PLL1 and PSC are registered in dm646x_init_time() */ - platform_device_register(&dm646x_pll2_device); -} - -static const struct davinci_aintc_config dm646x_aintc_config = { - .reg = { - .start = DAVINCI_ARM_INTC_BASE, - .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = 64, - .prios = dm646x_default_priorities, -}; - -void __init dm646x_init_irq(void) -{ - davinci_aintc_init(&dm646x_aintc_config); -} - -static int __init dm646x_init_devices(void) -{ - int ret = 0; - - if (!cpu_is_davinci_dm646x()) - return 0; - - platform_device_register(&dm646x_mdio_device); - platform_device_register(&dm646x_emac_device); - - ret = davinci_init_wdt(); - if (ret) - pr_warn("%s: watchdog init failed: %d\n", __func__, ret); - - return ret; -} -postcore_initcall(dm646x_init_devices); diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/hardware.h index 16bb42291d39..7848b6a240b4 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/hardware.h @@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Hardware definitions common to all DaVinci family processors * * Author: Kevin Hilman, Deep Root Systems, LLC * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2007 (c) Deep Root Systems, LLC. */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h deleted file mode 100644 index 1fc84e21664d..000000000000 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * DaVinci CPU type detection - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Defines the cpu_is_*() macros for runtime detection of DaVinci - * device type. In addition, if support for a given device is not - * compiled in to the kernel, the macros return 0 so that - * resulting code can be optimized out. - * - * 2009 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef _ASM_ARCH_CPU_H -#define _ASM_ARCH_CPU_H - -#include <mach/common.h> - -struct davinci_id { - u8 variant; /* JTAG ID bits 31:28 */ - u16 part_no; /* JTAG ID bits 27:12 */ - u16 manufacturer; /* JTAG ID bits 11:1 */ - u32 cpu_id; - char *name; -}; - -/* Can use lower 16 bits of cpu id for a variant when required */ -#define DAVINCI_CPU_ID_DM6446 0x64460000 -#define DAVINCI_CPU_ID_DM6467 0x64670000 -#define DAVINCI_CPU_ID_DM355 0x03550000 -#define DAVINCI_CPU_ID_DM365 0x03650000 -#define DAVINCI_CPU_ID_DA830 0x08300000 -#define DAVINCI_CPU_ID_DA850 0x08500000 - -#define IS_DAVINCI_CPU(type, id) \ -static inline int is_davinci_ ##type(void) \ -{ \ - return (davinci_soc_info.cpu_id == (id)); \ -} - -IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) -IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) -IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) -IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) -IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) -IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) - -#ifdef CONFIG_ARCH_DAVINCI_DM644x -#define cpu_is_davinci_dm644x() is_davinci_dm644x() -#else -#define cpu_is_davinci_dm644x() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM646x -#define cpu_is_davinci_dm646x() is_davinci_dm646x() -#else -#define cpu_is_davinci_dm646x() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM355 -#define cpu_is_davinci_dm355() is_davinci_dm355() -#else -#define cpu_is_davinci_dm355() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM365 -#define cpu_is_davinci_dm365() is_davinci_dm365() -#else -#define cpu_is_davinci_dm365() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DA830 -#define cpu_is_davinci_da830() is_davinci_da830() -#else -#define cpu_is_davinci_da830() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DA850 -#define cpu_is_davinci_da850() is_davinci_da850() -#else -#define cpu_is_davinci_da850() 0 -#endif - -#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h deleted file mode 100644 index 1618b30661a9..000000000000 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Chip specific defines for DA8XX/OMAP L1XX SoC - * - * Author: Mark A. Greer <mgreer@mvista.com> - * - * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_DAVINCI_DA8XX_H -#define __ASM_ARCH_DAVINCI_DA8XX_H - -#include <video/da8xx-fb.h> - -#include <linux/platform_device.h> -#include <linux/davinci_emac.h> -#include <linux/spi/spi.h> -#include <linux/platform_data/davinci_asp.h> -#include <linux/reboot.h> -#include <linux/regmap.h> -#include <linux/videodev2.h> - -#include <mach/serial.h> -#include <mach/pm.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/usb-davinci.h> -#include <linux/platform_data/spi-davinci.h> -#include <linux/platform_data/uio_pruss.h> - -#include <media/davinci/vpif_types.h> - -extern void __iomem *da8xx_syscfg0_base; -extern void __iomem *da8xx_syscfg1_base; - -/* - * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade - * (than the regular 300MHz variant), the board code should set this up - * with the supported speed before calling da850_register_cpufreq(). - */ -extern unsigned int da850_max_speed; - -/* - * The cp_intc interrupt controller for the da8xx isn't in the same - * chunk of physical memory space as the other registers (like it is - * on the davincis) so it needs to be mapped separately. It will be - * mapped early on when the I/O space is mapped and we'll put it just - * before the I/O space in the processor's virtual memory space. - */ -#define DA8XX_CP_INTC_BASE 0xfffee000 -#define DA8XX_CP_INTC_SIZE SZ_8K -#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) - -#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) -#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) -#define DA8XX_JTAG_ID_REG 0x18 -#define DA8XX_HOST1CFG_REG 0x44 -#define DA8XX_CHIPSIG_REG 0x174 -#define DA8XX_CFGCHIP0_REG 0x17c -#define DA8XX_CFGCHIP1_REG 0x180 -#define DA8XX_CFGCHIP2_REG 0x184 -#define DA8XX_CFGCHIP3_REG 0x188 -#define DA8XX_CFGCHIP4_REG 0x18c - -#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) -#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) -#define DA8XX_DEEPSLEEP_REG 0x8 -#define DA8XX_PWRDN_REG 0x18 - -#define DA8XX_PSC0_BASE 0x01c10000 -#define DA8XX_PLL0_BASE 0x01c11000 -#define DA8XX_TIMER64P0_BASE 0x01c20000 -#define DA8XX_TIMER64P1_BASE 0x01c21000 -#define DA8XX_VPIF_BASE 0x01e17000 -#define DA8XX_GPIO_BASE 0x01e26000 -#define DA8XX_PSC1_BASE 0x01e27000 - -#define DA8XX_DSP_L2_RAM_BASE 0x11800000 -#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000) -#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000) - -#define DA8XX_AEMIF_CS2_BASE 0x60000000 -#define DA8XX_AEMIF_CS3_BASE 0x62000000 -#define DA8XX_AEMIF_CTL_BASE 0x68000000 -#define DA8XX_SHARED_RAM_BASE 0x80000000 -#define DA8XX_ARM_RAM_BASE 0xffff0000 - -void da830_init(void); -void da830_init_irq(void); -void da830_init_time(void); -void da830_register_clocks(void); - -void da850_init(void); -void da850_init_irq(void); -void da850_init_time(void); -void da850_register_clocks(void); - -int da830_register_edma(struct edma_rsv_info *rsv); -int da850_register_edma(struct edma_rsv_info *rsv[2]); -int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); -int da8xx_register_spi_bus(int instance, unsigned num_chipselect); -int da8xx_register_watchdog(void); -int da8xx_register_usb_phy(void); -int da8xx_register_usb20(unsigned mA, unsigned potpgt); -int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); -int da8xx_register_usb_phy_clocks(void); -int da850_register_sata_refclk(int rate); -int da8xx_register_emac(void); -int da8xx_register_uio_pruss(void); -int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); -int da8xx_register_mmcsd0(struct davinci_mmc_config *config); -int da850_register_mmcsd1(struct davinci_mmc_config *config); -void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); -int da8xx_register_rtc(void); -int da8xx_register_gpio(void *pdata); -int da850_register_cpufreq(char *async_clk); -int da8xx_register_cpuidle(void); -void __iomem *da8xx_get_mem_ctlr(void); -int da850_register_sata(unsigned long refclkpn); -int da850_register_vpif(void); -int da850_register_vpif_display - (struct vpif_display_config *display_config); -int da850_register_vpif_capture - (struct vpif_capture_config *capture_config); -void da8xx_rproc_reserve_cma(void); -int da8xx_register_rproc(void); -int da850_register_gpio(void); -int da830_register_gpio(void); -struct regmap *da8xx_get_cfgchip(void); - -extern struct platform_device da8xx_serial_device[]; -extern struct emac_platform_data da8xx_emac_pdata; -extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; -extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; - - -extern const short da830_emif25_pins[]; -extern const short da830_spi0_pins[]; -extern const short da830_spi1_pins[]; -extern const short da830_mmc_sd_pins[]; -extern const short da830_uart0_pins[]; -extern const short da830_uart1_pins[]; -extern const short da830_uart2_pins[]; -extern const short da830_usb20_pins[]; -extern const short da830_usb11_pins[]; -extern const short da830_uhpi_pins[]; -extern const short da830_cpgmac_pins[]; -extern const short da830_emif3c_pins[]; -extern const short da830_mcasp0_pins[]; -extern const short da830_mcasp1_pins[]; -extern const short da830_mcasp2_pins[]; -extern const short da830_i2c0_pins[]; -extern const short da830_i2c1_pins[]; -extern const short da830_lcdcntl_pins[]; -extern const short da830_pwm_pins[]; -extern const short da830_ecap0_pins[]; -extern const short da830_ecap1_pins[]; -extern const short da830_ecap2_pins[]; -extern const short da830_eqep0_pins[]; -extern const short da830_eqep1_pins[]; -extern const short da850_vpif_capture_pins[]; -extern const short da850_vpif_display_pins[]; - -extern const short da850_i2c0_pins[]; -extern const short da850_i2c1_pins[]; -extern const short da850_lcdcntl_pins[]; - -#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h deleted file mode 100644 index 631655e68ae0..000000000000 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ /dev/null @@ -1,990 +0,0 @@ -/* - * Table of the DAVINCI register configurations for the PINMUX combinations - * - * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> - * - * Based on linux/include/asm-arm/arch-omap/mux.h: - * Copyright (C) 2003 - 2005 Nokia Corporation - * - * Written by Tony Lindgren - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright (C) 2008 Texas Instruments. - */ - -#ifndef __INC_MACH_MUX_H -#define __INC_MACH_MUX_H - -struct mux_config { - const char *name; - const char *mux_reg_name; - const unsigned char mux_reg; - const unsigned char mask_offset; - const unsigned char mask; - const unsigned char mode; - bool debug; -}; - -enum davinci_dm644x_index { - /* ATA and HDDIR functions */ - DM644X_HDIREN, - DM644X_ATAEN, - DM644X_ATAEN_DISABLE, - - /* HPI functions */ - DM644X_HPIEN_DISABLE, - - /* AEAW functions */ - DM644X_AEAW, - DM644X_AEAW0, - DM644X_AEAW1, - DM644X_AEAW2, - DM644X_AEAW3, - DM644X_AEAW4, - - /* Memory Stick */ - DM644X_MSTK, - - /* I2C */ - DM644X_I2C, - - /* ASP function */ - DM644X_MCBSP, - - /* UART1 */ - DM644X_UART1, - - /* UART2 */ - DM644X_UART2, - - /* PWM0 */ - DM644X_PWM0, - - /* PWM1 */ - DM644X_PWM1, - - /* PWM2 */ - DM644X_PWM2, - - /* VLYNQ function */ - DM644X_VLYNQEN, - DM644X_VLSCREN, - DM644X_VLYNQWD, - - /* EMAC and MDIO function */ - DM644X_EMACEN, - - /* GPIO3V[0:16] pins */ - DM644X_GPIO3V, - - /* GPIO pins */ - DM644X_GPIO0, - DM644X_GPIO3, - DM644X_GPIO43_44, - DM644X_GPIO46_47, - - /* VPBE */ - DM644X_RGB666, - - /* LCD */ - DM644X_LOEEN, - DM644X_LFLDEN, -}; - -enum davinci_dm646x_index { - /* ATA function */ - DM646X_ATAEN, - - /* AUDIO Clock */ - DM646X_AUDCK1, - DM646X_AUDCK0, - - /* CRGEN Control */ - DM646X_CRGMUX, - - /* VPIF Control */ - DM646X_STSOMUX_DISABLE, - DM646X_STSIMUX_DISABLE, - DM646X_PTSOMUX_DISABLE, - DM646X_PTSIMUX_DISABLE, - - /* TSIF Control */ - DM646X_STSOMUX, - DM646X_STSIMUX, - DM646X_PTSOMUX_PARALLEL, - DM646X_PTSIMUX_PARALLEL, - DM646X_PTSOMUX_SERIAL, - DM646X_PTSIMUX_SERIAL, -}; - -enum davinci_dm355_index { - /* MMC/SD 0 */ - DM355_MMCSD0, - - /* MMC/SD 1 */ - DM355_SD1_CLK, - DM355_SD1_CMD, - DM355_SD1_DATA3, - DM355_SD1_DATA2, - DM355_SD1_DATA1, - DM355_SD1_DATA0, - - /* I2C */ - DM355_I2C_SDA, - DM355_I2C_SCL, - - /* ASP0 function */ - DM355_MCBSP0_BDX, - DM355_MCBSP0_X, - DM355_MCBSP0_BFSX, - DM355_MCBSP0_BDR, - DM355_MCBSP0_R, - DM355_MCBSP0_BFSR, - - /* SPI0 */ - DM355_SPI0_SDI, - DM355_SPI0_SDENA0, - DM355_SPI0_SDENA1, - - /* IRQ muxing */ - DM355_INT_EDMA_CC, - DM355_INT_EDMA_TC0_ERR, - DM355_INT_EDMA_TC1_ERR, - - /* EDMA event muxing */ - DM355_EVT8_ASP1_TX, - DM355_EVT9_ASP1_RX, - DM355_EVT26_MMC0_RX, - - /* Video Out */ - DM355_VOUT_FIELD, - DM355_VOUT_FIELD_G70, - DM355_VOUT_HVSYNC, - DM355_VOUT_COUTL_EN, - DM355_VOUT_COUTH_EN, - - /* Video In Pin Mux */ - DM355_VIN_PCLK, - DM355_VIN_CAM_WEN, - DM355_VIN_CAM_VD, - DM355_VIN_CAM_HD, - DM355_VIN_YIN_EN, - DM355_VIN_CINL_EN, - DM355_VIN_CINH_EN, -}; - -enum davinci_dm365_index { - /* MMC/SD 0 */ - DM365_MMCSD0, - - /* MMC/SD 1 */ - DM365_SD1_CLK, - DM365_SD1_CMD, - DM365_SD1_DATA3, - DM365_SD1_DATA2, - DM365_SD1_DATA1, - DM365_SD1_DATA0, - - /* I2C */ - DM365_I2C_SDA, - DM365_I2C_SCL, - - /* AEMIF */ - DM365_AEMIF_AR_A14, - DM365_AEMIF_AR_BA0, - DM365_AEMIF_A3, - DM365_AEMIF_A7, - DM365_AEMIF_D15_8, - DM365_AEMIF_CE0, - DM365_AEMIF_CE1, - DM365_AEMIF_WE_OE, - - /* ASP0 function */ - DM365_MCBSP0_BDX, - DM365_MCBSP0_X, - DM365_MCBSP0_BFSX, - DM365_MCBSP0_BDR, - DM365_MCBSP0_R, - DM365_MCBSP0_BFSR, - - /* SPI0 */ - DM365_SPI0_SCLK, - DM365_SPI0_SDI, - DM365_SPI0_SDO, - DM365_SPI0_SDENA0, - DM365_SPI0_SDENA1, - - /* UART */ - DM365_UART0_RXD, - DM365_UART0_TXD, - DM365_UART1_RXD, - DM365_UART1_TXD, - DM365_UART1_RTS, - DM365_UART1_CTS, - - /* EMAC */ - DM365_EMAC_TX_EN, - DM365_EMAC_TX_CLK, - DM365_EMAC_COL, - DM365_EMAC_TXD3, - DM365_EMAC_TXD2, - DM365_EMAC_TXD1, - DM365_EMAC_TXD0, - DM365_EMAC_RXD3, - DM365_EMAC_RXD2, - DM365_EMAC_RXD1, - DM365_EMAC_RXD0, - DM365_EMAC_RX_CLK, - DM365_EMAC_RX_DV, - DM365_EMAC_RX_ER, - DM365_EMAC_CRS, - DM365_EMAC_MDIO, - DM365_EMAC_MDCLK, - - /* Key Scan */ - DM365_KEYSCAN, - - /* PWM */ - DM365_PWM0, - DM365_PWM0_G23, - DM365_PWM1, - DM365_PWM1_G25, - DM365_PWM2_G87, - DM365_PWM2_G88, - DM365_PWM2_G89, - DM365_PWM2_G90, - DM365_PWM3_G80, - DM365_PWM3_G81, - DM365_PWM3_G85, - DM365_PWM3_G86, - - /* SPI1 */ - DM365_SPI1_SCLK, - DM365_SPI1_SDO, - DM365_SPI1_SDI, - DM365_SPI1_SDENA0, - DM365_SPI1_SDENA1, - - /* SPI2 */ - DM365_SPI2_SCLK, - DM365_SPI2_SDO, - DM365_SPI2_SDI, - DM365_SPI2_SDENA0, - DM365_SPI2_SDENA1, - - /* SPI3 */ - DM365_SPI3_SCLK, - DM365_SPI3_SDO, - DM365_SPI3_SDI, - DM365_SPI3_SDENA0, - DM365_SPI3_SDENA1, - - /* SPI4 */ - DM365_SPI4_SCLK, - DM365_SPI4_SDO, - DM365_SPI4_SDI, - DM365_SPI4_SDENA0, - DM365_SPI4_SDENA1, - - /* Clock */ - DM365_CLKOUT0, - DM365_CLKOUT1, - DM365_CLKOUT2, - - /* GPIO */ - DM365_GPIO20, - DM365_GPIO30, - DM365_GPIO31, - DM365_GPIO32, - DM365_GPIO33, - DM365_GPIO40, - DM365_GPIO64_57, - - /* Video */ - DM365_VOUT_FIELD, - DM365_VOUT_FIELD_G81, - DM365_VOUT_HVSYNC, - DM365_VOUT_COUTL_EN, - DM365_VOUT_COUTH_EN, - DM365_VIN_CAM_WEN, - DM365_VIN_CAM_VD, - DM365_VIN_CAM_HD, - DM365_VIN_YIN4_7_EN, - DM365_VIN_YIN0_3_EN, - - /* IRQ muxing */ - DM365_INT_EDMA_CC, - DM365_INT_EDMA_TC0_ERR, - DM365_INT_EDMA_TC1_ERR, - DM365_INT_EDMA_TC2_ERR, - DM365_INT_EDMA_TC3_ERR, - DM365_INT_PRTCSS, - DM365_INT_EMAC_RXTHRESH, - DM365_INT_EMAC_RXPULSE, - DM365_INT_EMAC_TXPULSE, - DM365_INT_EMAC_MISCPULSE, - DM365_INT_IMX0_ENABLE, - DM365_INT_IMX0_DISABLE, - DM365_INT_HDVICP_ENABLE, - DM365_INT_HDVICP_DISABLE, - DM365_INT_IMX1_ENABLE, - DM365_INT_IMX1_DISABLE, - DM365_INT_NSF_ENABLE, - DM365_INT_NSF_DISABLE, - - /* EDMA event muxing */ - DM365_EVT2_ASP_TX, - DM365_EVT3_ASP_RX, - DM365_EVT2_VC_TX, - DM365_EVT3_VC_RX, - DM365_EVT26_MMC0_RX, -}; - -enum da830_index { - DA830_GPIO7_14, - DA830_RTCK, - DA830_GPIO7_15, - DA830_EMU_0, - DA830_EMB_SDCKE, - DA830_EMB_CLK_GLUE, - DA830_EMB_CLK, - DA830_NEMB_CS_0, - DA830_NEMB_CAS, - DA830_NEMB_RAS, - DA830_NEMB_WE, - DA830_EMB_BA_1, - DA830_EMB_BA_0, - DA830_EMB_A_0, - DA830_EMB_A_1, - DA830_EMB_A_2, - DA830_EMB_A_3, - DA830_EMB_A_4, - DA830_EMB_A_5, - DA830_GPIO7_0, - DA830_GPIO7_1, - DA830_GPIO7_2, - DA830_GPIO7_3, - DA830_GPIO7_4, - DA830_GPIO7_5, - DA830_GPIO7_6, - DA830_GPIO7_7, - DA830_EMB_A_6, - DA830_EMB_A_7, - DA830_EMB_A_8, - DA830_EMB_A_9, - DA830_EMB_A_10, - DA830_EMB_A_11, - DA830_EMB_A_12, - DA830_EMB_D_31, - DA830_GPIO7_8, - DA830_GPIO7_9, - DA830_GPIO7_10, - DA830_GPIO7_11, - DA830_GPIO7_12, - DA830_GPIO7_13, - DA830_GPIO3_13, - DA830_EMB_D_30, - DA830_EMB_D_29, - DA830_EMB_D_28, - DA830_EMB_D_27, - DA830_EMB_D_26, - DA830_EMB_D_25, - DA830_EMB_D_24, - DA830_EMB_D_23, - DA830_EMB_D_22, - DA830_EMB_D_21, - DA830_EMB_D_20, - DA830_EMB_D_19, - DA830_EMB_D_18, - DA830_EMB_D_17, - DA830_EMB_D_16, - DA830_NEMB_WE_DQM_3, - DA830_NEMB_WE_DQM_2, - DA830_EMB_D_0, - DA830_EMB_D_1, - DA830_EMB_D_2, - DA830_EMB_D_3, - DA830_EMB_D_4, - DA830_EMB_D_5, - DA830_EMB_D_6, - DA830_GPIO6_0, - DA830_GPIO6_1, - DA830_GPIO6_2, - DA830_GPIO6_3, - DA830_GPIO6_4, - DA830_GPIO6_5, - DA830_GPIO6_6, - DA830_EMB_D_7, - DA830_EMB_D_8, - DA830_EMB_D_9, - DA830_EMB_D_10, - DA830_EMB_D_11, - DA830_EMB_D_12, - DA830_EMB_D_13, - DA830_EMB_D_14, - DA830_GPIO6_7, - DA830_GPIO6_8, - DA830_GPIO6_9, - DA830_GPIO6_10, - DA830_GPIO6_11, - DA830_GPIO6_12, - DA830_GPIO6_13, - DA830_GPIO6_14, - DA830_EMB_D_15, - DA830_NEMB_WE_DQM_1, - DA830_NEMB_WE_DQM_0, - DA830_SPI0_SOMI_0, - DA830_SPI0_SIMO_0, - DA830_SPI0_CLK, - DA830_NSPI0_ENA, - DA830_NSPI0_SCS_0, - DA830_EQEP0I, - DA830_EQEP0S, - DA830_EQEP1I, - DA830_NUART0_CTS, - DA830_NUART0_RTS, - DA830_EQEP0A, - DA830_EQEP0B, - DA830_GPIO6_15, - DA830_GPIO5_14, - DA830_GPIO5_15, - DA830_GPIO5_0, - DA830_GPIO5_1, - DA830_GPIO5_2, - DA830_GPIO5_3, - DA830_GPIO5_4, - DA830_SPI1_SOMI_0, - DA830_SPI1_SIMO_0, - DA830_SPI1_CLK, - DA830_UART0_RXD, - DA830_UART0_TXD, - DA830_AXR1_10, - DA830_AXR1_11, - DA830_NSPI1_ENA, - DA830_I2C1_SCL, - DA830_I2C1_SDA, - DA830_EQEP1S, - DA830_I2C0_SDA, - DA830_I2C0_SCL, - DA830_UART2_RXD, - DA830_TM64P0_IN12, - DA830_TM64P0_OUT12, - DA830_GPIO5_5, - DA830_GPIO5_6, - DA830_GPIO5_7, - DA830_GPIO5_8, - DA830_GPIO5_9, - DA830_GPIO5_10, - DA830_GPIO5_11, - DA830_GPIO5_12, - DA830_NSPI1_SCS_0, - DA830_USB0_DRVVBUS, - DA830_AHCLKX0, - DA830_ACLKX0, - DA830_AFSX0, - DA830_AHCLKR0, - DA830_ACLKR0, - DA830_AFSR0, - DA830_UART2_TXD, - DA830_AHCLKX2, - DA830_ECAP0_APWM0, - DA830_RMII_MHZ_50_CLK, - DA830_ECAP1_APWM1, - DA830_USB_REFCLKIN, - DA830_GPIO5_13, - DA830_GPIO4_15, - DA830_GPIO2_11, - DA830_GPIO2_12, - DA830_GPIO2_13, - DA830_GPIO2_14, - DA830_GPIO2_15, - DA830_GPIO3_12, - DA830_AMUTE0, - DA830_AXR0_0, - DA830_AXR0_1, - DA830_AXR0_2, - DA830_AXR0_3, - DA830_AXR0_4, - DA830_AXR0_5, - DA830_AXR0_6, - DA830_RMII_TXD_0, - DA830_RMII_TXD_1, - DA830_RMII_TXEN, - DA830_RMII_CRS_DV, - DA830_RMII_RXD_0, - DA830_RMII_RXD_1, - DA830_RMII_RXER, - DA830_AFSR2, - DA830_ACLKX2, - DA830_AXR2_3, - DA830_AXR2_2, - DA830_AXR2_1, - DA830_AFSX2, - DA830_ACLKR2, - DA830_NRESETOUT, - DA830_GPIO3_0, - DA830_GPIO3_1, - DA830_GPIO3_2, - DA830_GPIO3_3, - DA830_GPIO3_4, - DA830_GPIO3_5, - DA830_GPIO3_6, - DA830_AXR0_7, - DA830_AXR0_8, - DA830_UART1_RXD, - DA830_UART1_TXD, - DA830_AXR0_11, - DA830_AHCLKX1, - DA830_ACLKX1, - DA830_AFSX1, - DA830_MDIO_CLK, - DA830_MDIO_D, - DA830_AXR0_9, - DA830_AXR0_10, - DA830_EPWM0B, - DA830_EPWM0A, - DA830_EPWMSYNCI, - DA830_AXR2_0, - DA830_EPWMSYNC0, - DA830_GPIO3_7, - DA830_GPIO3_8, - DA830_GPIO3_9, - DA830_GPIO3_10, - DA830_GPIO3_11, - DA830_GPIO3_14, - DA830_GPIO3_15, - DA830_GPIO4_10, - DA830_AHCLKR1, - DA830_ACLKR1, - DA830_AFSR1, - DA830_AMUTE1, - DA830_AXR1_0, - DA830_AXR1_1, - DA830_AXR1_2, - DA830_AXR1_3, - DA830_ECAP2_APWM2, - DA830_EHRPWMGLUETZ, - DA830_EQEP1A, - DA830_GPIO4_11, - DA830_GPIO4_12, - DA830_GPIO4_13, - DA830_GPIO4_14, - DA830_GPIO4_0, - DA830_GPIO4_1, - DA830_GPIO4_2, - DA830_GPIO4_3, - DA830_AXR1_4, - DA830_AXR1_5, - DA830_AXR1_6, - DA830_AXR1_7, - DA830_AXR1_8, - DA830_AXR1_9, - DA830_EMA_D_0, - DA830_EMA_D_1, - DA830_EQEP1B, - DA830_EPWM2B, - DA830_EPWM2A, - DA830_EPWM1B, - DA830_EPWM1A, - DA830_MMCSD_DAT_0, - DA830_MMCSD_DAT_1, - DA830_UHPI_HD_0, - DA830_UHPI_HD_1, - DA830_GPIO4_4, - DA830_GPIO4_5, - DA830_GPIO4_6, - DA830_GPIO4_7, - DA830_GPIO4_8, - DA830_GPIO4_9, - DA830_GPIO0_0, - DA830_GPIO0_1, - DA830_EMA_D_2, - DA830_EMA_D_3, - DA830_EMA_D_4, - DA830_EMA_D_5, - DA830_EMA_D_6, - DA830_EMA_D_7, - DA830_EMA_D_8, - DA830_EMA_D_9, - DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, - DA830_MMCSD_DAT_4, - DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, - DA830_MMCSD_DAT_7, - DA830_UHPI_HD_8, - DA830_UHPI_HD_9, - DA830_UHPI_HD_2, - DA830_UHPI_HD_3, - DA830_UHPI_HD_4, - DA830_UHPI_HD_5, - DA830_UHPI_HD_6, - DA830_UHPI_HD_7, - DA830_LCD_D_8, - DA830_LCD_D_9, - DA830_GPIO0_2, - DA830_GPIO0_3, - DA830_GPIO0_4, - DA830_GPIO0_5, - DA830_GPIO0_6, - DA830_GPIO0_7, - DA830_GPIO0_8, - DA830_GPIO0_9, - DA830_EMA_D_10, - DA830_EMA_D_11, - DA830_EMA_D_12, - DA830_EMA_D_13, - DA830_EMA_D_14, - DA830_EMA_D_15, - DA830_EMA_A_0, - DA830_EMA_A_1, - DA830_UHPI_HD_10, - DA830_UHPI_HD_11, - DA830_UHPI_HD_12, - DA830_UHPI_HD_13, - DA830_UHPI_HD_14, - DA830_UHPI_HD_15, - DA830_LCD_D_7, - DA830_MMCSD_CLK, - DA830_LCD_D_10, - DA830_LCD_D_11, - DA830_LCD_D_12, - DA830_LCD_D_13, - DA830_LCD_D_14, - DA830_LCD_D_15, - DA830_UHPI_HCNTL0, - DA830_GPIO0_10, - DA830_GPIO0_11, - DA830_GPIO0_12, - DA830_GPIO0_13, - DA830_GPIO0_14, - DA830_GPIO0_15, - DA830_GPIO1_0, - DA830_GPIO1_1, - DA830_EMA_A_2, - DA830_EMA_A_3, - DA830_EMA_A_4, - DA830_EMA_A_5, - DA830_EMA_A_6, - DA830_EMA_A_7, - DA830_EMA_A_8, - DA830_EMA_A_9, - DA830_MMCSD_CMD, - DA830_LCD_D_6, - DA830_LCD_D_3, - DA830_LCD_D_2, - DA830_LCD_D_1, - DA830_LCD_D_0, - DA830_LCD_PCLK, - DA830_LCD_HSYNC, - DA830_UHPI_HCNTL1, - DA830_GPIO1_2, - DA830_GPIO1_3, - DA830_GPIO1_4, - DA830_GPIO1_5, - DA830_GPIO1_6, - DA830_GPIO1_7, - DA830_GPIO1_8, - DA830_GPIO1_9, - DA830_EMA_A_10, - DA830_EMA_A_11, - DA830_EMA_A_12, - DA830_EMA_BA_1, - DA830_EMA_BA_0, - DA830_EMA_CLK, - DA830_EMA_SDCKE, - DA830_NEMA_CAS, - DA830_LCD_VSYNC, - DA830_NLCD_AC_ENB_CS, - DA830_LCD_MCLK, - DA830_LCD_D_5, - DA830_LCD_D_4, - DA830_OBSCLK, - DA830_NEMA_CS_4, - DA830_UHPI_HHWIL, - DA830_AHCLKR2, - DA830_GPIO1_10, - DA830_GPIO1_11, - DA830_GPIO1_12, - DA830_GPIO1_13, - DA830_GPIO1_14, - DA830_GPIO1_15, - DA830_GPIO2_0, - DA830_GPIO2_1, - DA830_NEMA_RAS, - DA830_NEMA_WE, - DA830_NEMA_CS_0, - DA830_NEMA_CS_2, - DA830_NEMA_CS_3, - DA830_NEMA_OE, - DA830_NEMA_WE_DQM_1, - DA830_NEMA_WE_DQM_0, - DA830_NEMA_CS_5, - DA830_UHPI_HRNW, - DA830_NUHPI_HAS, - DA830_NUHPI_HCS, - DA830_NUHPI_HDS1, - DA830_NUHPI_HDS2, - DA830_NUHPI_HINT, - DA830_AXR0_12, - DA830_AMUTE2, - DA830_AXR0_13, - DA830_AXR0_14, - DA830_AXR0_15, - DA830_GPIO2_2, - DA830_GPIO2_3, - DA830_GPIO2_4, - DA830_GPIO2_5, - DA830_GPIO2_6, - DA830_GPIO2_7, - DA830_GPIO2_8, - DA830_GPIO2_9, - DA830_EMA_WAIT_0, - DA830_NUHPI_HRDY, - DA830_GPIO2_10, -}; - -enum davinci_da850_index { - /* UART0 function */ - DA850_NUART0_CTS, - DA850_NUART0_RTS, - DA850_UART0_RXD, - DA850_UART0_TXD, - - /* UART1 function */ - DA850_NUART1_CTS, - DA850_NUART1_RTS, - DA850_UART1_RXD, - DA850_UART1_TXD, - - /* UART2 function */ - DA850_NUART2_CTS, - DA850_NUART2_RTS, - DA850_UART2_RXD, - DA850_UART2_TXD, - - /* I2C1 function */ - DA850_I2C1_SCL, - DA850_I2C1_SDA, - - /* I2C0 function */ - DA850_I2C0_SDA, - DA850_I2C0_SCL, - - /* EMAC function */ - DA850_MII_TXEN, - DA850_MII_TXCLK, - DA850_MII_COL, - DA850_MII_TXD_3, - DA850_MII_TXD_2, - DA850_MII_TXD_1, - DA850_MII_TXD_0, - DA850_MII_RXER, - DA850_MII_CRS, - DA850_MII_RXCLK, - DA850_MII_RXDV, - DA850_MII_RXD_3, - DA850_MII_RXD_2, - DA850_MII_RXD_1, - DA850_MII_RXD_0, - DA850_MDIO_CLK, - DA850_MDIO_D, - DA850_RMII_TXD_0, - DA850_RMII_TXD_1, - DA850_RMII_TXEN, - DA850_RMII_CRS_DV, - DA850_RMII_RXD_0, - DA850_RMII_RXD_1, - DA850_RMII_RXER, - DA850_RMII_MHZ_50_CLK, - - /* McASP function */ - DA850_ACLKR, - DA850_ACLKX, - DA850_AFSR, - DA850_AFSX, - DA850_AHCLKR, - DA850_AHCLKX, - DA850_AMUTE, - DA850_AXR_15, - DA850_AXR_14, - DA850_AXR_13, - DA850_AXR_12, - DA850_AXR_11, - DA850_AXR_10, - DA850_AXR_9, - DA850_AXR_8, - DA850_AXR_7, - DA850_AXR_6, - DA850_AXR_5, - DA850_AXR_4, - DA850_AXR_3, - DA850_AXR_2, - DA850_AXR_1, - DA850_AXR_0, - - /* LCD function */ - DA850_LCD_D_7, - DA850_LCD_D_6, - DA850_LCD_D_5, - DA850_LCD_D_4, - DA850_LCD_D_3, - DA850_LCD_D_2, - DA850_LCD_D_1, - DA850_LCD_D_0, - DA850_LCD_D_15, - DA850_LCD_D_14, - DA850_LCD_D_13, - DA850_LCD_D_12, - DA850_LCD_D_11, - DA850_LCD_D_10, - DA850_LCD_D_9, - DA850_LCD_D_8, - DA850_LCD_PCLK, - DA850_LCD_HSYNC, - DA850_LCD_VSYNC, - DA850_NLCD_AC_ENB_CS, - - /* MMC/SD0 function */ - DA850_MMCSD0_DAT_0, - DA850_MMCSD0_DAT_1, - DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, - DA850_MMCSD0_CLK, - DA850_MMCSD0_CMD, - - /* MMC/SD1 function */ - DA850_MMCSD1_DAT_0, - DA850_MMCSD1_DAT_1, - DA850_MMCSD1_DAT_2, - DA850_MMCSD1_DAT_3, - DA850_MMCSD1_CLK, - DA850_MMCSD1_CMD, - - /* EMIF2.5/EMIFA function */ - DA850_EMA_D_7, - DA850_EMA_D_6, - DA850_EMA_D_5, - DA850_EMA_D_4, - DA850_EMA_D_3, - DA850_EMA_D_2, - DA850_EMA_D_1, - DA850_EMA_D_0, - DA850_EMA_A_1, - DA850_EMA_A_2, - DA850_NEMA_CS_3, - DA850_NEMA_CS_4, - DA850_NEMA_WE, - DA850_NEMA_OE, - DA850_EMA_D_15, - DA850_EMA_D_14, - DA850_EMA_D_13, - DA850_EMA_D_12, - DA850_EMA_D_11, - DA850_EMA_D_10, - DA850_EMA_D_9, - DA850_EMA_D_8, - DA850_EMA_A_0, - DA850_EMA_A_3, - DA850_EMA_A_4, - DA850_EMA_A_5, - DA850_EMA_A_6, - DA850_EMA_A_7, - DA850_EMA_A_8, - DA850_EMA_A_9, - DA850_EMA_A_10, - DA850_EMA_A_11, - DA850_EMA_A_12, - DA850_EMA_A_13, - DA850_EMA_A_14, - DA850_EMA_A_15, - DA850_EMA_A_16, - DA850_EMA_A_17, - DA850_EMA_A_18, - DA850_EMA_A_19, - DA850_EMA_A_20, - DA850_EMA_A_21, - DA850_EMA_A_22, - DA850_EMA_A_23, - DA850_EMA_BA_1, - DA850_EMA_CLK, - DA850_EMA_WAIT_1, - DA850_NEMA_CS_2, - - /* GPIO function */ - DA850_GPIO2_4, - DA850_GPIO2_6, - DA850_GPIO2_8, - DA850_GPIO2_15, - DA850_GPIO3_12, - DA850_GPIO3_13, - DA850_GPIO4_0, - DA850_GPIO4_1, - DA850_GPIO6_9, - DA850_GPIO6_10, - DA850_GPIO6_13, - DA850_RTC_ALARM, - - /* VPIF Capture */ - DA850_VPIF_DIN0, - DA850_VPIF_DIN1, - DA850_VPIF_DIN2, - DA850_VPIF_DIN3, - DA850_VPIF_DIN4, - DA850_VPIF_DIN5, - DA850_VPIF_DIN6, - DA850_VPIF_DIN7, - DA850_VPIF_DIN8, - DA850_VPIF_DIN9, - DA850_VPIF_DIN10, - DA850_VPIF_DIN11, - DA850_VPIF_DIN12, - DA850_VPIF_DIN13, - DA850_VPIF_DIN14, - DA850_VPIF_DIN15, - DA850_VPIF_CLKIN0, - DA850_VPIF_CLKIN1, - DA850_VPIF_CLKIN2, - DA850_VPIF_CLKIN3, - - /* VPIF Display */ - DA850_VPIF_DOUT0, - DA850_VPIF_DOUT1, - DA850_VPIF_DOUT2, - DA850_VPIF_DOUT3, - DA850_VPIF_DOUT4, - DA850_VPIF_DOUT5, - DA850_VPIF_DOUT6, - DA850_VPIF_DOUT7, - DA850_VPIF_DOUT8, - DA850_VPIF_DOUT9, - DA850_VPIF_DOUT10, - DA850_VPIF_DOUT11, - DA850_VPIF_DOUT12, - DA850_VPIF_DOUT13, - DA850_VPIF_DOUT14, - DA850_VPIF_DOUT15, - DA850_VPIF_CLKO2, - DA850_VPIF_CLKO3, -}; - -#define PINMUX(x) (4 * (x)) - -#ifdef CONFIG_DAVINCI_MUX -/* setup pin muxing */ -extern int davinci_cfg_reg(unsigned long reg_cfg); -extern int davinci_cfg_reg_list(const short pins[]); -#else -/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ -static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } -static inline int davinci_cfg_reg_list(const short pins[]) -{ - return 0; -} -#endif - -#endif /* __INC_MACH_MUX_H */ diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h deleted file mode 100644 index d4b4aa87964f..000000000000 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * DaVinci serial device definitions - * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_SERIAL_H -#define __ASM_ARCH_SERIAL_H - -#include <asm/memory.h> - -#include <mach/hardware.h> - -#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) -#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) -#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) - -#define DA8XX_UART0_BASE (IO_PHYS + 0x042000) -#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) -#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) - -/* DaVinci UART register offsets */ -#define UART_DAVINCI_PWREMU 0x0c -#define UART_DM646X_SCR 0x10 -#define UART_DM646X_SCR_TX_WATERMARK 0x08 - -#ifndef __ASSEMBLY__ -#include <linux/platform_device.h> - -extern int davinci_serial_init(struct platform_device *); -#endif - -#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h deleted file mode 100644 index ba913736990f..000000000000 --- a/arch/arm/mach-davinci/include/mach/time.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Local header file for DaVinci time code. - * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H -#define __ARCH_ARM_MACH_DAVINCI_TIME_H - -#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) - -enum { - T0_BOT, - T0_TOP, - T1_BOT, - T1_TOP, - NUM_TIMERS -}; - -#define IS_TIMER1(id) (id & 0x2) -#define IS_TIMER0(id) (!IS_TIMER1(id)) -#define IS_TIMER_TOP(id) ((id & 0x1)) -#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) - -#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0) - -extern struct davinci_timer_instance davinci_timer_instance[]; - -#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */ diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h deleted file mode 100644 index 53b456a5bbe0..000000000000 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Serial port stubs for kernel decompress status messages - * - * Initially based on: - * arch/arm/plat-omap/include/mach/uncompress.h - * - * Original copyrights follow. - * - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * Rewritten by: - * Author: <source@mvista.com> - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include <linux/types.h> -#include <linux/serial_reg.h> - -#include <asm/mach-types.h> - -#include <mach/serial.h> - -#define IOMEM(x) ((void __force __iomem *)(x)) - -u32 *uart; - -/* PORT_16C550A, in polled non-fifo mode */ -static inline void putc(char c) -{ - if (!uart) - return; - - while (!(uart[UART_LSR] & UART_LSR_THRE)) - barrier(); - uart[UART_TX] = c; -} - -static inline void flush(void) -{ - if (!uart) - return; - - while (!(uart[UART_LSR] & UART_LSR_THRE)) - barrier(); -} - -static inline void set_uart_info(u32 phys) -{ - uart = (u32 *)phys; -} - -#define _DEBUG_LL_ENTRY(machine, phys) \ - { \ - if (machine_is_##machine()) { \ - set_uart_info(phys); \ - break; \ - } \ - } - -#define DEBUG_LL_DAVINCI(machine, port) \ - _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE) - -#define DEBUG_LL_DA8XX(machine, port) \ - _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE) - -static inline void __arch_decomp_setup(unsigned long arch_id) -{ - /* - * Initialize the port based on the machine ID from the bootloader. - * Note that we're using macros here instead of switch statement - * as machine_is functions are optimized out for the boards that - * are not selected. - */ - do { - /* Davinci boards */ - DEBUG_LL_DAVINCI(davinci_evm, 0); - DEBUG_LL_DAVINCI(sffsdr, 0); - DEBUG_LL_DAVINCI(neuros_osd2, 0); - DEBUG_LL_DAVINCI(davinci_dm355_evm, 0); - DEBUG_LL_DAVINCI(dm355_leopard, 0); - DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0); - DEBUG_LL_DAVINCI(davinci_dm365_evm, 0); - - /* DA8xx boards */ - DEBUG_LL_DA8XX(davinci_da830_evm, 2); - DEBUG_LL_DA8XX(davinci_da850_evm, 2); - DEBUG_LL_DA8XX(mityomapl138, 1); - DEBUG_LL_DA8XX(omapl138_hawkboard, 2); - } while (0); -} - -#define arch_decomp_setup() __arch_decomp_setup(arch_id) diff --git a/arch/arm/mach-davinci/irqs.h b/arch/arm/mach-davinci/irqs.h index 8f9fc7a56ce8..b1ceed81e9fa 100644 --- a/arch/arm/mach-davinci/irqs.h +++ b/arch/arm/mach-davinci/irqs.h @@ -27,219 +27,6 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -/* Base address */ -#define DAVINCI_ARM_INTC_BASE 0x01C48000 - -/* Interrupt lines */ -#define IRQ_VDINT0 0 -#define IRQ_VDINT1 1 -#define IRQ_VDINT2 2 -#define IRQ_HISTINT 3 -#define IRQ_H3AINT 4 -#define IRQ_PRVUINT 5 -#define IRQ_RSZINT 6 -#define IRQ_VFOCINT 7 -#define IRQ_VENCINT 8 -#define IRQ_ASQINT 9 -#define IRQ_IMXINT 10 -#define IRQ_VLCDINT 11 -#define IRQ_USBINT 12 -#define IRQ_EMACINT 13 - -#define IRQ_CCINT0 16 -#define IRQ_CCERRINT 17 -#define IRQ_TCERRINT0 18 -#define IRQ_TCERRINT 19 -#define IRQ_PSCIN 20 - -#define IRQ_IDE 22 -#define IRQ_HPIINT 23 -#define IRQ_MBXINT 24 -#define IRQ_MBRINT 25 -#define IRQ_MMCINT 26 -#define IRQ_SDIOINT 27 -#define IRQ_MSINT 28 -#define IRQ_DDRINT 29 -#define IRQ_AEMIFINT 30 -#define IRQ_VLQINT 31 -#define IRQ_TINT0_TINT12 32 -#define IRQ_TINT0_TINT34 33 -#define IRQ_TINT1_TINT12 34 -#define IRQ_TINT1_TINT34 35 -#define IRQ_PWMINT0 36 -#define IRQ_PWMINT1 37 -#define IRQ_PWMINT2 38 -#define IRQ_I2C 39 -#define IRQ_UARTINT0 40 -#define IRQ_UARTINT1 41 -#define IRQ_UARTINT2 42 -#define IRQ_SPINT0 43 -#define IRQ_SPINT1 44 - -#define IRQ_DSP2ARM0 46 -#define IRQ_DSP2ARM1 47 -#define IRQ_GPIO0 48 -#define IRQ_GPIO1 49 -#define IRQ_GPIO2 50 -#define IRQ_GPIO3 51 -#define IRQ_GPIO4 52 -#define IRQ_GPIO5 53 -#define IRQ_GPIO6 54 -#define IRQ_GPIO7 55 -#define IRQ_GPIOBNK0 56 -#define IRQ_GPIOBNK1 57 -#define IRQ_GPIOBNK2 58 -#define IRQ_GPIOBNK3 59 -#define IRQ_GPIOBNK4 60 -#define IRQ_COMMTX 61 -#define IRQ_COMMRX 62 -#define IRQ_EMUINT 63 - -#define DAVINCI_N_AINTC_IRQ 64 - -#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 - -/* DaVinci DM6467-specific Interrupts */ -#define IRQ_DM646X_VP_VERTINT0 0 -#define IRQ_DM646X_VP_VERTINT1 1 -#define IRQ_DM646X_VP_VERTINT2 2 -#define IRQ_DM646X_VP_VERTINT3 3 -#define IRQ_DM646X_VP_ERRINT 4 -#define IRQ_DM646X_RESERVED_1 5 -#define IRQ_DM646X_RESERVED_2 6 -#define IRQ_DM646X_WDINT 7 -#define IRQ_DM646X_CRGENINT0 8 -#define IRQ_DM646X_CRGENINT1 9 -#define IRQ_DM646X_TSIFINT0 10 -#define IRQ_DM646X_TSIFINT1 11 -#define IRQ_DM646X_VDCEINT 12 -#define IRQ_DM646X_USBINT 13 -#define IRQ_DM646X_USBDMAINT 14 -#define IRQ_DM646X_PCIINT 15 -#define IRQ_DM646X_TCERRINT2 20 -#define IRQ_DM646X_TCERRINT3 21 -#define IRQ_DM646X_IDE 22 -#define IRQ_DM646X_HPIINT 23 -#define IRQ_DM646X_EMACRXTHINT 24 -#define IRQ_DM646X_EMACRXINT 25 -#define IRQ_DM646X_EMACTXINT 26 -#define IRQ_DM646X_EMACMISCINT 27 -#define IRQ_DM646X_MCASP0TXINT 28 -#define IRQ_DM646X_MCASP0RXINT 29 -#define IRQ_DM646X_MCASP1TXINT 30 -#define IRQ_DM646X_RESERVED_3 31 -#define IRQ_DM646X_VLQINT 38 -#define IRQ_DM646X_UARTINT2 42 -#define IRQ_DM646X_SPINT0 43 -#define IRQ_DM646X_SPINT1 44 -#define IRQ_DM646X_DSP2ARMINT 45 -#define IRQ_DM646X_RESERVED_4 46 -#define IRQ_DM646X_PSCINT 47 -#define IRQ_DM646X_GPIO0 48 -#define IRQ_DM646X_GPIO1 49 -#define IRQ_DM646X_GPIO2 50 -#define IRQ_DM646X_GPIO3 51 -#define IRQ_DM646X_GPIO4 52 -#define IRQ_DM646X_GPIO5 53 -#define IRQ_DM646X_GPIO6 54 -#define IRQ_DM646X_GPIO7 55 -#define IRQ_DM646X_GPIOBNK0 56 -#define IRQ_DM646X_GPIOBNK1 57 -#define IRQ_DM646X_GPIOBNK2 58 -#define IRQ_DM646X_DDRINT 59 -#define IRQ_DM646X_AEMIFINT 60 - -/* DaVinci DM355-specific Interrupts */ -#define IRQ_DM355_CCDC_VDINT0 0 -#define IRQ_DM355_CCDC_VDINT1 1 -#define IRQ_DM355_CCDC_VDINT2 2 -#define IRQ_DM355_IPIPE_HST 3 -#define IRQ_DM355_H3AINT 4 -#define IRQ_DM355_IPIPE_SDR 5 -#define IRQ_DM355_IPIPEIFINT 6 -#define IRQ_DM355_OSDINT 7 -#define IRQ_DM355_VENCINT 8 -#define IRQ_DM355_IMCOPINT 11 -#define IRQ_DM355_RTOINT 13 -#define IRQ_DM355_TINT4 13 -#define IRQ_DM355_TINT2_TINT12 13 -#define IRQ_DM355_UARTINT2 14 -#define IRQ_DM355_TINT5 14 -#define IRQ_DM355_TINT2_TINT34 14 -#define IRQ_DM355_TINT6 15 -#define IRQ_DM355_TINT3_TINT12 15 -#define IRQ_DM355_SPINT1_0 17 -#define IRQ_DM355_SPINT1_1 18 -#define IRQ_DM355_SPINT2_0 19 -#define IRQ_DM355_SPINT2_1 21 -#define IRQ_DM355_TINT7 22 -#define IRQ_DM355_TINT3_TINT34 22 -#define IRQ_DM355_SDIOINT0 23 -#define IRQ_DM355_MMCINT0 26 -#define IRQ_DM355_MSINT 26 -#define IRQ_DM355_MMCINT1 27 -#define IRQ_DM355_PWMINT3 28 -#define IRQ_DM355_SDIOINT1 31 -#define IRQ_DM355_SPINT0_0 42 -#define IRQ_DM355_SPINT0_1 43 -#define IRQ_DM355_GPIO0 44 -#define IRQ_DM355_GPIO1 45 -#define IRQ_DM355_GPIO2 46 -#define IRQ_DM355_GPIO3 47 -#define IRQ_DM355_GPIO4 48 -#define IRQ_DM355_GPIO5 49 -#define IRQ_DM355_GPIO6 50 -#define IRQ_DM355_GPIO7 51 -#define IRQ_DM355_GPIO8 52 -#define IRQ_DM355_GPIO9 53 -#define IRQ_DM355_GPIOBNK0 54 -#define IRQ_DM355_GPIOBNK1 55 -#define IRQ_DM355_GPIOBNK2 56 -#define IRQ_DM355_GPIOBNK3 57 -#define IRQ_DM355_GPIOBNK4 58 -#define IRQ_DM355_GPIOBNK5 59 -#define IRQ_DM355_GPIOBNK6 60 - -/* DaVinci DM365-specific Interrupts */ -#define IRQ_DM365_INSFINT 7 -#define IRQ_DM365_IMXINT1 8 -#define IRQ_DM365_IMXINT0 10 -#define IRQ_DM365_KLD_ARMINT 10 -#define IRQ_DM365_IMCOPINT 11 -#define IRQ_DM365_RTOINT 13 -#define IRQ_DM365_TINT5 14 -#define IRQ_DM365_TINT6 15 -#define IRQ_DM365_SPINT2_1 21 -#define IRQ_DM365_TINT7 22 -#define IRQ_DM365_SDIOINT0 23 -#define IRQ_DM365_MMCINT1 27 -#define IRQ_DM365_PWMINT3 28 -#define IRQ_DM365_RTCINT 29 -#define IRQ_DM365_SDIOINT1 31 -#define IRQ_DM365_SPIINT0_0 42 -#define IRQ_DM365_SPIINT3_0 43 -#define IRQ_DM365_GPIO0 44 -#define IRQ_DM365_GPIO1 45 -#define IRQ_DM365_GPIO2 46 -#define IRQ_DM365_GPIO3 47 -#define IRQ_DM365_GPIO4 48 -#define IRQ_DM365_GPIO5 49 -#define IRQ_DM365_GPIO6 50 -#define IRQ_DM365_GPIO7 51 -#define IRQ_DM365_EMAC_RXTHRESH 52 -#define IRQ_DM365_EMAC_RXPULSE 53 -#define IRQ_DM365_EMAC_TXPULSE 54 -#define IRQ_DM365_EMAC_MISCPULSE 55 -#define IRQ_DM365_GPIO12 56 -#define IRQ_DM365_GPIO13 57 -#define IRQ_DM365_GPIO14 58 -#define IRQ_DM365_GPIO15 59 -#define IRQ_DM365_ADCINT 59 -#define IRQ_DM365_KEYINT 60 -#define IRQ_DM365_TCERRINT2 61 -#define IRQ_DM365_TCERRINT3 62 -#define IRQ_DM365_EMUINT 63 - /* DA8XX interrupts */ #define IRQ_DA8XX_COMMTX 0 #define IRQ_DA8XX_COMMRX 1 @@ -398,8 +185,4 @@ #define DA850_N_CP_INTC_IRQ 101 -/* da850 currently has the most gpio pins (144) */ -#define DAVINCI_N_GPIO 144 -/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ - #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index 6a2ff0a654a5..37de35eb6e8b 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Utility to set the DAVINCI MUX register from a table in mux.h * @@ -8,10 +9,7 @@ * * Written by Tony Lindgren * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2007 (c) MontaVista Software, Inc. * * Copyright (C) 2008 Texas Instruments. */ @@ -22,8 +20,8 @@ #include <linux/module.h> #include <linux/spinlock.h> -#include <mach/mux.h> -#include <mach/common.h> +#include "mux.h" +#include "common.h" static void __iomem *pinmux_base; @@ -99,18 +97,3 @@ int davinci_cfg_reg(const unsigned long index) return 0; } -EXPORT_SYMBOL(davinci_cfg_reg); - -int davinci_cfg_reg_list(const short pins[]) -{ - int i, error = -EINVAL; - - if (pins) - for (i = 0; pins[i] >= 0; i++) { - error = davinci_cfg_reg(pins[i]); - if (error) - break; - } - - return error; -} diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h index 5aad1e7dd210..38f0e427291e 100644 --- a/arch/arm/mach-davinci/mux.h +++ b/arch/arm/mach-davinci/mux.h @@ -1,19 +1,669 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Pin-multiplex helper macros for TI DaVinci family devices * * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2007 (c) MontaVista Software, Inc. * * Copyright (C) 2008 Texas Instruments. */ #ifndef _MACH_DAVINCI_MUX_H_ #define _MACH_DAVINCI_MUX_H_ -#include <mach/mux.h> +struct mux_config { + const char *name; + const char *mux_reg_name; + const unsigned char mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + const unsigned char mode; + bool debug; +}; + +enum da830_index { + DA830_GPIO7_14, + DA830_RTCK, + DA830_GPIO7_15, + DA830_EMU_0, + DA830_EMB_SDCKE, + DA830_EMB_CLK_GLUE, + DA830_EMB_CLK, + DA830_NEMB_CS_0, + DA830_NEMB_CAS, + DA830_NEMB_RAS, + DA830_NEMB_WE, + DA830_EMB_BA_1, + DA830_EMB_BA_0, + DA830_EMB_A_0, + DA830_EMB_A_1, + DA830_EMB_A_2, + DA830_EMB_A_3, + DA830_EMB_A_4, + DA830_EMB_A_5, + DA830_GPIO7_0, + DA830_GPIO7_1, + DA830_GPIO7_2, + DA830_GPIO7_3, + DA830_GPIO7_4, + DA830_GPIO7_5, + DA830_GPIO7_6, + DA830_GPIO7_7, + DA830_EMB_A_6, + DA830_EMB_A_7, + DA830_EMB_A_8, + DA830_EMB_A_9, + DA830_EMB_A_10, + DA830_EMB_A_11, + DA830_EMB_A_12, + DA830_EMB_D_31, + DA830_GPIO7_8, + DA830_GPIO7_9, + DA830_GPIO7_10, + DA830_GPIO7_11, + DA830_GPIO7_12, + DA830_GPIO7_13, + DA830_GPIO3_13, + DA830_EMB_D_30, + DA830_EMB_D_29, + DA830_EMB_D_28, + DA830_EMB_D_27, + DA830_EMB_D_26, + DA830_EMB_D_25, + DA830_EMB_D_24, + DA830_EMB_D_23, + DA830_EMB_D_22, + DA830_EMB_D_21, + DA830_EMB_D_20, + DA830_EMB_D_19, + DA830_EMB_D_18, + DA830_EMB_D_17, + DA830_EMB_D_16, + DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, + DA830_EMB_D_0, + DA830_EMB_D_1, + DA830_EMB_D_2, + DA830_EMB_D_3, + DA830_EMB_D_4, + DA830_EMB_D_5, + DA830_EMB_D_6, + DA830_GPIO6_0, + DA830_GPIO6_1, + DA830_GPIO6_2, + DA830_GPIO6_3, + DA830_GPIO6_4, + DA830_GPIO6_5, + DA830_GPIO6_6, + DA830_EMB_D_7, + DA830_EMB_D_8, + DA830_EMB_D_9, + DA830_EMB_D_10, + DA830_EMB_D_11, + DA830_EMB_D_12, + DA830_EMB_D_13, + DA830_EMB_D_14, + DA830_GPIO6_7, + DA830_GPIO6_8, + DA830_GPIO6_9, + DA830_GPIO6_10, + DA830_GPIO6_11, + DA830_GPIO6_12, + DA830_GPIO6_13, + DA830_GPIO6_14, + DA830_EMB_D_15, + DA830_NEMB_WE_DQM_1, + DA830_NEMB_WE_DQM_0, + DA830_SPI0_SOMI_0, + DA830_SPI0_SIMO_0, + DA830_SPI0_CLK, + DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + DA830_EQEP0I, + DA830_EQEP0S, + DA830_EQEP1I, + DA830_NUART0_CTS, + DA830_NUART0_RTS, + DA830_EQEP0A, + DA830_EQEP0B, + DA830_GPIO6_15, + DA830_GPIO5_14, + DA830_GPIO5_15, + DA830_GPIO5_0, + DA830_GPIO5_1, + DA830_GPIO5_2, + DA830_GPIO5_3, + DA830_GPIO5_4, + DA830_SPI1_SOMI_0, + DA830_SPI1_SIMO_0, + DA830_SPI1_CLK, + DA830_UART0_RXD, + DA830_UART0_TXD, + DA830_AXR1_10, + DA830_AXR1_11, + DA830_NSPI1_ENA, + DA830_I2C1_SCL, + DA830_I2C1_SDA, + DA830_EQEP1S, + DA830_I2C0_SDA, + DA830_I2C0_SCL, + DA830_UART2_RXD, + DA830_TM64P0_IN12, + DA830_TM64P0_OUT12, + DA830_GPIO5_5, + DA830_GPIO5_6, + DA830_GPIO5_7, + DA830_GPIO5_8, + DA830_GPIO5_9, + DA830_GPIO5_10, + DA830_GPIO5_11, + DA830_GPIO5_12, + DA830_NSPI1_SCS_0, + DA830_USB0_DRVVBUS, + DA830_AHCLKX0, + DA830_ACLKX0, + DA830_AFSX0, + DA830_AHCLKR0, + DA830_ACLKR0, + DA830_AFSR0, + DA830_UART2_TXD, + DA830_AHCLKX2, + DA830_ECAP0_APWM0, + DA830_RMII_MHZ_50_CLK, + DA830_ECAP1_APWM1, + DA830_USB_REFCLKIN, + DA830_GPIO5_13, + DA830_GPIO4_15, + DA830_GPIO2_11, + DA830_GPIO2_12, + DA830_GPIO2_13, + DA830_GPIO2_14, + DA830_GPIO2_15, + DA830_GPIO3_12, + DA830_AMUTE0, + DA830_AXR0_0, + DA830_AXR0_1, + DA830_AXR0_2, + DA830_AXR0_3, + DA830_AXR0_4, + DA830_AXR0_5, + DA830_AXR0_6, + DA830_RMII_TXD_0, + DA830_RMII_TXD_1, + DA830_RMII_TXEN, + DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, + DA830_RMII_RXD_1, + DA830_RMII_RXER, + DA830_AFSR2, + DA830_ACLKX2, + DA830_AXR2_3, + DA830_AXR2_2, + DA830_AXR2_1, + DA830_AFSX2, + DA830_ACLKR2, + DA830_NRESETOUT, + DA830_GPIO3_0, + DA830_GPIO3_1, + DA830_GPIO3_2, + DA830_GPIO3_3, + DA830_GPIO3_4, + DA830_GPIO3_5, + DA830_GPIO3_6, + DA830_AXR0_7, + DA830_AXR0_8, + DA830_UART1_RXD, + DA830_UART1_TXD, + DA830_AXR0_11, + DA830_AHCLKX1, + DA830_ACLKX1, + DA830_AFSX1, + DA830_MDIO_CLK, + DA830_MDIO_D, + DA830_AXR0_9, + DA830_AXR0_10, + DA830_EPWM0B, + DA830_EPWM0A, + DA830_EPWMSYNCI, + DA830_AXR2_0, + DA830_EPWMSYNC0, + DA830_GPIO3_7, + DA830_GPIO3_8, + DA830_GPIO3_9, + DA830_GPIO3_10, + DA830_GPIO3_11, + DA830_GPIO3_14, + DA830_GPIO3_15, + DA830_GPIO4_10, + DA830_AHCLKR1, + DA830_ACLKR1, + DA830_AFSR1, + DA830_AMUTE1, + DA830_AXR1_0, + DA830_AXR1_1, + DA830_AXR1_2, + DA830_AXR1_3, + DA830_ECAP2_APWM2, + DA830_EHRPWMGLUETZ, + DA830_EQEP1A, + DA830_GPIO4_11, + DA830_GPIO4_12, + DA830_GPIO4_13, + DA830_GPIO4_14, + DA830_GPIO4_0, + DA830_GPIO4_1, + DA830_GPIO4_2, + DA830_GPIO4_3, + DA830_AXR1_4, + DA830_AXR1_5, + DA830_AXR1_6, + DA830_AXR1_7, + DA830_AXR1_8, + DA830_AXR1_9, + DA830_EMA_D_0, + DA830_EMA_D_1, + DA830_EQEP1B, + DA830_EPWM2B, + DA830_EPWM2A, + DA830_EPWM1B, + DA830_EPWM1A, + DA830_MMCSD_DAT_0, + DA830_MMCSD_DAT_1, + DA830_UHPI_HD_0, + DA830_UHPI_HD_1, + DA830_GPIO4_4, + DA830_GPIO4_5, + DA830_GPIO4_6, + DA830_GPIO4_7, + DA830_GPIO4_8, + DA830_GPIO4_9, + DA830_GPIO0_0, + DA830_GPIO0_1, + DA830_EMA_D_2, + DA830_EMA_D_3, + DA830_EMA_D_4, + DA830_EMA_D_5, + DA830_EMA_D_6, + DA830_EMA_D_7, + DA830_EMA_D_8, + DA830_EMA_D_9, + DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, + DA830_MMCSD_DAT_4, + DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, + DA830_MMCSD_DAT_7, + DA830_UHPI_HD_8, + DA830_UHPI_HD_9, + DA830_UHPI_HD_2, + DA830_UHPI_HD_3, + DA830_UHPI_HD_4, + DA830_UHPI_HD_5, + DA830_UHPI_HD_6, + DA830_UHPI_HD_7, + DA830_LCD_D_8, + DA830_LCD_D_9, + DA830_GPIO0_2, + DA830_GPIO0_3, + DA830_GPIO0_4, + DA830_GPIO0_5, + DA830_GPIO0_6, + DA830_GPIO0_7, + DA830_GPIO0_8, + DA830_GPIO0_9, + DA830_EMA_D_10, + DA830_EMA_D_11, + DA830_EMA_D_12, + DA830_EMA_D_13, + DA830_EMA_D_14, + DA830_EMA_D_15, + DA830_EMA_A_0, + DA830_EMA_A_1, + DA830_UHPI_HD_10, + DA830_UHPI_HD_11, + DA830_UHPI_HD_12, + DA830_UHPI_HD_13, + DA830_UHPI_HD_14, + DA830_UHPI_HD_15, + DA830_LCD_D_7, + DA830_MMCSD_CLK, + DA830_LCD_D_10, + DA830_LCD_D_11, + DA830_LCD_D_12, + DA830_LCD_D_13, + DA830_LCD_D_14, + DA830_LCD_D_15, + DA830_UHPI_HCNTL0, + DA830_GPIO0_10, + DA830_GPIO0_11, + DA830_GPIO0_12, + DA830_GPIO0_13, + DA830_GPIO0_14, + DA830_GPIO0_15, + DA830_GPIO1_0, + DA830_GPIO1_1, + DA830_EMA_A_2, + DA830_EMA_A_3, + DA830_EMA_A_4, + DA830_EMA_A_5, + DA830_EMA_A_6, + DA830_EMA_A_7, + DA830_EMA_A_8, + DA830_EMA_A_9, + DA830_MMCSD_CMD, + DA830_LCD_D_6, + DA830_LCD_D_3, + DA830_LCD_D_2, + DA830_LCD_D_1, + DA830_LCD_D_0, + DA830_LCD_PCLK, + DA830_LCD_HSYNC, + DA830_UHPI_HCNTL1, + DA830_GPIO1_2, + DA830_GPIO1_3, + DA830_GPIO1_4, + DA830_GPIO1_5, + DA830_GPIO1_6, + DA830_GPIO1_7, + DA830_GPIO1_8, + DA830_GPIO1_9, + DA830_EMA_A_10, + DA830_EMA_A_11, + DA830_EMA_A_12, + DA830_EMA_BA_1, + DA830_EMA_BA_0, + DA830_EMA_CLK, + DA830_EMA_SDCKE, + DA830_NEMA_CAS, + DA830_LCD_VSYNC, + DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + DA830_LCD_D_5, + DA830_LCD_D_4, + DA830_OBSCLK, + DA830_NEMA_CS_4, + DA830_UHPI_HHWIL, + DA830_AHCLKR2, + DA830_GPIO1_10, + DA830_GPIO1_11, + DA830_GPIO1_12, + DA830_GPIO1_13, + DA830_GPIO1_14, + DA830_GPIO1_15, + DA830_GPIO2_0, + DA830_GPIO2_1, + DA830_NEMA_RAS, + DA830_NEMA_WE, + DA830_NEMA_CS_0, + DA830_NEMA_CS_2, + DA830_NEMA_CS_3, + DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, + DA830_NEMA_WE_DQM_0, + DA830_NEMA_CS_5, + DA830_UHPI_HRNW, + DA830_NUHPI_HAS, + DA830_NUHPI_HCS, + DA830_NUHPI_HDS1, + DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, + DA830_AXR0_12, + DA830_AMUTE2, + DA830_AXR0_13, + DA830_AXR0_14, + DA830_AXR0_15, + DA830_GPIO2_2, + DA830_GPIO2_3, + DA830_GPIO2_4, + DA830_GPIO2_5, + DA830_GPIO2_6, + DA830_GPIO2_7, + DA830_GPIO2_8, + DA830_GPIO2_9, + DA830_EMA_WAIT_0, + DA830_NUHPI_HRDY, + DA830_GPIO2_10, +}; + +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, + + /* EMAC function */ + DA850_MII_TXEN, + DA850_MII_TXCLK, + DA850_MII_COL, + DA850_MII_TXD_3, + DA850_MII_TXD_2, + DA850_MII_TXD_1, + DA850_MII_TXD_0, + DA850_MII_RXER, + DA850_MII_CRS, + DA850_MII_RXCLK, + DA850_MII_RXDV, + DA850_MII_RXD_3, + DA850_MII_RXD_2, + DA850_MII_RXD_1, + DA850_MII_RXD_0, + DA850_MDIO_CLK, + DA850_MDIO_D, + DA850_RMII_TXD_0, + DA850_RMII_TXD_1, + DA850_RMII_TXEN, + DA850_RMII_CRS_DV, + DA850_RMII_RXD_0, + DA850_RMII_RXD_1, + DA850_RMII_RXER, + DA850_RMII_MHZ_50_CLK, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, + + /* LCD function */ + DA850_LCD_D_7, + DA850_LCD_D_6, + DA850_LCD_D_5, + DA850_LCD_D_4, + DA850_LCD_D_3, + DA850_LCD_D_2, + DA850_LCD_D_1, + DA850_LCD_D_0, + DA850_LCD_D_15, + DA850_LCD_D_14, + DA850_LCD_D_13, + DA850_LCD_D_12, + DA850_LCD_D_11, + DA850_LCD_D_10, + DA850_LCD_D_9, + DA850_LCD_D_8, + DA850_LCD_PCLK, + DA850_LCD_HSYNC, + DA850_LCD_VSYNC, + DA850_NLCD_AC_ENB_CS, + + /* MMC/SD0 function */ + DA850_MMCSD0_DAT_0, + DA850_MMCSD0_DAT_1, + DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, + DA850_MMCSD0_CLK, + DA850_MMCSD0_CMD, + + /* MMC/SD1 function */ + DA850_MMCSD1_DAT_0, + DA850_MMCSD1_DAT_1, + DA850_MMCSD1_DAT_2, + DA850_MMCSD1_DAT_3, + DA850_MMCSD1_CLK, + DA850_MMCSD1_CMD, + + /* EMIF2.5/EMIFA function */ + DA850_EMA_D_7, + DA850_EMA_D_6, + DA850_EMA_D_5, + DA850_EMA_D_4, + DA850_EMA_D_3, + DA850_EMA_D_2, + DA850_EMA_D_1, + DA850_EMA_D_0, + DA850_EMA_A_1, + DA850_EMA_A_2, + DA850_NEMA_CS_3, + DA850_NEMA_CS_4, + DA850_NEMA_WE, + DA850_NEMA_OE, + DA850_EMA_D_15, + DA850_EMA_D_14, + DA850_EMA_D_13, + DA850_EMA_D_12, + DA850_EMA_D_11, + DA850_EMA_D_10, + DA850_EMA_D_9, + DA850_EMA_D_8, + DA850_EMA_A_0, + DA850_EMA_A_3, + DA850_EMA_A_4, + DA850_EMA_A_5, + DA850_EMA_A_6, + DA850_EMA_A_7, + DA850_EMA_A_8, + DA850_EMA_A_9, + DA850_EMA_A_10, + DA850_EMA_A_11, + DA850_EMA_A_12, + DA850_EMA_A_13, + DA850_EMA_A_14, + DA850_EMA_A_15, + DA850_EMA_A_16, + DA850_EMA_A_17, + DA850_EMA_A_18, + DA850_EMA_A_19, + DA850_EMA_A_20, + DA850_EMA_A_21, + DA850_EMA_A_22, + DA850_EMA_A_23, + DA850_EMA_BA_1, + DA850_EMA_CLK, + DA850_EMA_WAIT_1, + DA850_NEMA_CS_2, + + /* GPIO function */ + DA850_GPIO2_4, + DA850_GPIO2_6, + DA850_GPIO2_8, + DA850_GPIO2_15, + DA850_GPIO3_12, + DA850_GPIO3_13, + DA850_GPIO4_0, + DA850_GPIO4_1, + DA850_GPIO6_9, + DA850_GPIO6_10, + DA850_GPIO6_13, + DA850_RTC_ALARM, + + /* VPIF Capture */ + DA850_VPIF_DIN0, + DA850_VPIF_DIN1, + DA850_VPIF_DIN2, + DA850_VPIF_DIN3, + DA850_VPIF_DIN4, + DA850_VPIF_DIN5, + DA850_VPIF_DIN6, + DA850_VPIF_DIN7, + DA850_VPIF_DIN8, + DA850_VPIF_DIN9, + DA850_VPIF_DIN10, + DA850_VPIF_DIN11, + DA850_VPIF_DIN12, + DA850_VPIF_DIN13, + DA850_VPIF_DIN14, + DA850_VPIF_DIN15, + DA850_VPIF_CLKIN0, + DA850_VPIF_CLKIN1, + DA850_VPIF_CLKIN2, + DA850_VPIF_CLKIN3, + + /* VPIF Display */ + DA850_VPIF_DOUT0, + DA850_VPIF_DOUT1, + DA850_VPIF_DOUT2, + DA850_VPIF_DOUT3, + DA850_VPIF_DOUT4, + DA850_VPIF_DOUT5, + DA850_VPIF_DOUT6, + DA850_VPIF_DOUT7, + DA850_VPIF_DOUT8, + DA850_VPIF_DOUT9, + DA850_VPIF_DOUT10, + DA850_VPIF_DOUT11, + DA850_VPIF_DOUT12, + DA850_VPIF_DOUT13, + DA850_VPIF_DOUT14, + DA850_VPIF_DOUT15, + DA850_VPIF_CLKO2, + DA850_VPIF_CLKO3, +}; + +#define PINMUX(x) (4 * (x)) + +#ifdef CONFIG_DAVINCI_MUX +/* setup pin muxing */ +extern int davinci_cfg_reg(unsigned long reg_cfg); +extern int davinci_cfg_reg_list(const short pins[]); +#else +/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ +static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } +static inline int davinci_cfg_reg_list(const short pins[]) +{ + return 0; +} +#endif + #define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ [soc##_##desc] = { \ diff --git a/arch/arm/mach-davinci/pdata-quirks.c b/arch/arm/mach-davinci/pdata-quirks.c index 67f1c8537354..b5b5c7bda61e 100644 --- a/arch/arm/mach-davinci/pdata-quirks.c +++ b/arch/arm/mach-davinci/pdata-quirks.c @@ -5,13 +5,13 @@ * Copyright (C) 2016 BayLibre, Inc */ #include <linux/kernel.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <media/i2c/tvp514x.h> #include <media/i2c/adv7343.h> -#include <mach/common.h> -#include <mach/da8xx.h> +#include "common.h" +#include "da8xx.h" struct pdata_init { const char *compatible; diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c index e33c6bcb4598..8aa39db095d7 100644 --- a/arch/arm/mach-davinci/pm.c +++ b/arch/arm/mach-davinci/pm.c @@ -2,7 +2,7 @@ /* * DaVinci Power Management Routines * - * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ */ #include <linux/pm.h> @@ -16,11 +16,10 @@ #include <asm/delay.h> #include <asm/io.h> -#include <mach/common.h> -#include <mach/da8xx.h> -#include <mach/mux.h> -#include <mach/pm.h> - +#include "common.h" +#include "da8xx.h" +#include "mux.h" +#include "pm.h" #include "clock.h" #include "psc.h" #include "sram.h" diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/pm.h index 37b19bf35a85..6f50d6eb8da8 100644 --- a/arch/arm/mach-davinci/include/mach/pm.h +++ b/arch/arm/mach-davinci/pm.h @@ -1,16 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * TI DaVinci platform support for power management. * - * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ */ #ifndef _MACH_DAVINCI_PM_H #define _MACH_DAVINCI_PM_H diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c index e251fd593bfd..6b21d5bd999c 100644 --- a/arch/arm/mach-davinci/pm_domain.c +++ b/arch/arm/mach-davinci/pm_domain.c @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Runtime PM support code for DaVinci * * Author: Kevin Hilman * * Copyright (C) 2012 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/init.h> #include <linux/pm_runtime.h> diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h index 68cd9d3fc82b..acfef063295f 100644 --- a/arch/arm/mach-davinci/psc.h +++ b/arch/arm/mach-davinci/psc.h @@ -70,70 +70,6 @@ #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 -#define DM355_LPSC_TIMER3 5 -#define DM355_LPSC_SPI1 6 -#define DM355_LPSC_MMC_SD1 7 -#define DM355_LPSC_McBSP1 8 -#define DM355_LPSC_PWM3 10 -#define DM355_LPSC_SPI2 11 -#define DM355_LPSC_RTO 12 -#define DM355_LPSC_VPSS_DAC 41 - -/* DM365 */ -#define DM365_LPSC_TIMER3 5 -#define DM365_LPSC_SPI1 6 -#define DM365_LPSC_MMC_SD1 7 -#define DM365_LPSC_McBSP1 8 -#define DM365_LPSC_PWM3 10 -#define DM365_LPSC_SPI2 11 -#define DM365_LPSC_RTO 12 -#define DM365_LPSC_TIMER4 17 -#define DM365_LPSC_SPI0 22 -#define DM365_LPSC_SPI3 38 -#define DM365_LPSC_SPI4 39 -#define DM365_LPSC_EMAC 40 -#define DM365_LPSC_VOICE_CODEC 44 -#define DM365_LPSC_DAC_CLK 46 -#define DM365_LPSC_VPSSMSTR 47 -#define DM365_LPSC_MJCP 50 - -/* - * LPSC Assignments - */ -#define DM646X_LPSC_ARM 0 -#define DM646X_LPSC_C64X_CPU 1 -#define DM646X_LPSC_HDVICP0 2 -#define DM646X_LPSC_HDVICP1 3 -#define DM646X_LPSC_TPCC 4 -#define DM646X_LPSC_TPTC0 5 -#define DM646X_LPSC_TPTC1 6 -#define DM646X_LPSC_TPTC2 7 -#define DM646X_LPSC_TPTC3 8 -#define DM646X_LPSC_PCI 13 -#define DM646X_LPSC_EMAC 14 -#define DM646X_LPSC_VDCE 15 -#define DM646X_LPSC_VPSSMSTR 16 -#define DM646X_LPSC_VPSSSLV 17 -#define DM646X_LPSC_TSIF0 18 -#define DM646X_LPSC_TSIF1 19 -#define DM646X_LPSC_DDR_EMIF 20 -#define DM646X_LPSC_AEMIF 21 -#define DM646X_LPSC_McASP0 22 -#define DM646X_LPSC_McASP1 23 -#define DM646X_LPSC_CRGEN0 24 -#define DM646X_LPSC_CRGEN1 25 -#define DM646X_LPSC_UART0 26 -#define DM646X_LPSC_UART1 27 -#define DM646X_LPSC_UART2 28 -#define DM646X_LPSC_PWM0 29 -#define DM646X_LPSC_PWM1 30 -#define DM646X_LPSC_I2C 31 -#define DM646X_LPSC_SPI 32 -#define DM646X_LPSC_GPIO 33 -#define DM646X_LPSC_TIMER0 34 -#define DM646X_LPSC_TIMER1 35 -#define DM646X_LPSC_ARM_INTC 45 - /* PSC0 defines */ #define DA8XX_LPSC0_TPCC 0 #define DA8XX_LPSC0_TPTC0 1 diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c deleted file mode 100644 index 127b62ce7b1e..000000000000 --- a/arch/arm/mach-davinci/serial.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * TI DaVinci serial driver - * - * Copyright (C) 2006 Texas Instruments. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/serial_8250.h> -#include <linux/serial_reg.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/serial.h> -#include <mach/cputype.h> - -static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, - int value) -{ - offset <<= p->regshift; - - WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset); - - __raw_writel(value, p->membase + offset); -} - -static void __init davinci_serial_reset(struct plat_serial8250_port *p) -{ - unsigned int pwremu = 0; - - serial_write_reg(p, UART_IER, 0); /* disable all interrupts */ - - /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ - serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); - mdelay(10); - - pwremu |= (0x3 << 13); - pwremu |= 0x1; - serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); - - if (cpu_is_davinci_dm646x()) - serial_write_reg(p, UART_DM646X_SCR, - UART_DM646X_SCR_TX_WATERMARK); -} - -int __init davinci_serial_init(struct platform_device *serial_dev) -{ - int i, ret = 0; - struct device *dev; - struct plat_serial8250_port *p; - struct clk *clk; - - /* - * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on if not needed. - */ - for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) { - dev = &serial_dev[i].dev; - p = dev->platform_data; - - ret = platform_device_register(&serial_dev[i]); - if (ret) - continue; - - clk = clk_get(dev, NULL); - if (IS_ERR(clk)) { - pr_err("%s:%d: failed to get UART%d clock\n", - __func__, __LINE__, i); - continue; - } - - clk_prepare_enable(clk); - - p->uartclk = clk_get_rate(clk); - - if (!p->membase && p->mapbase) { - p->membase = ioremap(p->mapbase, SZ_4K); - - if (p->membase) - p->flags &= ~UPF_IOREMAP; - else - pr_err("uart regs ioremap failed\n"); - } - - if (p->membase && p->type != PORT_AR7) - davinci_serial_reset(p); - } - return ret; -} diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S index 71262dcdbca3..d5affab4396d 100644 --- a/arch/arm/mach-davinci/sleep.S +++ b/arch/arm/mach-davinci/sleep.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/ + * (C) Copyright 2009, Texas Instruments, Inc. https://www.ti.com/ */ /* replicated define because linux/bitops.h cannot be included in assembly */ diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c index bbae190fd82c..d04f39fc84b6 100644 --- a/arch/arm/mach-davinci/sram.c +++ b/arch/arm/mach-davinci/sram.c @@ -9,7 +9,7 @@ #include <linux/io.h> #include <linux/genalloc.h> -#include <mach/common.h> +#include "common.h" #include "sram.h" static struct gen_pool *sram_pool; diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c deleted file mode 100644 index 740410a3bb6a..000000000000 --- a/arch/arm/mach-davinci/time.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * DaVinci timer subsystem - * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/sched_clock.h> - -#include <asm/mach/irq.h> -#include <asm/mach/time.h> - -#include <mach/cputype.h> -#include <mach/hardware.h> -#include <mach/time.h> - -static struct clock_event_device clockevent_davinci; -static unsigned int davinci_clock_tick_rate; - -/* - * This driver configures the 2 64-bit count-up timers as 4 independent - * 32-bit count-up timers used as follows: - */ - -enum { - TID_CLOCKEVENT, - TID_CLOCKSOURCE, -}; - -/* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 - -/* Offsets of the 8 compare registers */ -#define CMP12_0 0x60 -#define CMP12_1 0x64 -#define CMP12_2 0x68 -#define CMP12_3 0x6c -#define CMP12_4 0x70 -#define CMP12_5 0x74 -#define CMP12_6 0x78 -#define CMP12_7 0x7c - -/* Timer register bitfields */ -#define TCR_ENAMODE_DISABLE 0x0 -#define TCR_ENAMODE_ONESHOT 0x1 -#define TCR_ENAMODE_PERIODIC 0x2 -#define TCR_ENAMODE_MASK 0x3 - -#define TGCR_TIMMODE_SHIFT 2 -#define TGCR_TIMMODE_64BIT_GP 0x0 -#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 -#define TGCR_TIMMODE_64BIT_WDOG 0x2 -#define TGCR_TIMMODE_32BIT_CHAINED 0x3 - -#define TGCR_TIM12RS_SHIFT 0 -#define TGCR_TIM34RS_SHIFT 1 -#define TGCR_RESET 0x0 -#define TGCR_UNRESET 0x1 -#define TGCR_RESET_MASK 0x3 - -struct timer_s { - char *name; - unsigned int id; - unsigned long period; - unsigned long opts; - unsigned long flags; - void __iomem *base; - unsigned long tim_off; - unsigned long prd_off; - unsigned long enamode_shift; - struct irqaction irqaction; -}; -static struct timer_s timers[]; - -/* values for 'opts' field of struct timer_s */ -#define TIMER_OPTS_DISABLED 0x01 -#define TIMER_OPTS_ONESHOT 0x02 -#define TIMER_OPTS_PERIODIC 0x04 -#define TIMER_OPTS_STATE_MASK 0x07 - -#define TIMER_OPTS_USE_COMPARE 0x80000000 -#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE) - -static char *id_to_name[] = { - [T0_BOT] = "timer0_0", - [T0_TOP] = "timer0_1", - [T1_BOT] = "timer1_0", - [T1_TOP] = "timer1_1", -}; - -static int timer32_config(struct timer_s *t) -{ - u32 tcr; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - if (USING_COMPARE(t)) { - struct davinci_timer_instance *dtip = - soc_info->timer_info->timers; - int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id); - - /* - * Next interrupt should be the current time reg value plus - * the new period (using 32-bit unsigned addition/wrapping - * to 0 on overflow). This assumes that the clocksource - * is setup to count to 2^32-1 before wrapping around to 0. - */ - __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, - t->base + dtip[event_timer].cmp_off); - } else { - tcr = __raw_readl(t->base + TCR); - - /* disable timer */ - tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); - __raw_writel(tcr, t->base + TCR); - - /* reset counter to zero, set new period */ - __raw_writel(0, t->base + t->tim_off); - __raw_writel(t->period, t->base + t->prd_off); - - /* Set enable mode */ - if (t->opts & TIMER_OPTS_ONESHOT) - tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; - else if (t->opts & TIMER_OPTS_PERIODIC) - tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; - - __raw_writel(tcr, t->base + TCR); - } - return 0; -} - -static inline u32 timer32_read(struct timer_s *t) -{ - return __raw_readl(t->base + t->tim_off); -} - -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_davinci; - - evt->event_handler(evt); - return IRQ_HANDLED; -} - -/* called when 32-bit counter wraps */ -static irqreturn_t freerun_interrupt(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static struct timer_s timers[] = { - [TID_CLOCKEVENT] = { - .name = "clockevent", - .opts = TIMER_OPTS_DISABLED, - .irqaction = { - .flags = IRQF_TIMER, - .handler = timer_interrupt, - } - }, - [TID_CLOCKSOURCE] = { - .name = "free-run counter", - .period = ~0, - .opts = TIMER_OPTS_PERIODIC, - .irqaction = { - .flags = IRQF_TIMER, - .handler = freerun_interrupt, - } - }, -}; - -static void __init timer_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - struct davinci_timer_instance *dtip = soc_info->timer_info->timers; - void __iomem *base[2]; - int i; - - /* Global init of each 64-bit timer as a whole */ - for(i=0; i<2; i++) { - u32 tgcr; - - base[i] = ioremap(dtip[i].base, SZ_4K); - if (WARN_ON(!base[i])) - continue; - - /* Disabled, Internal clock source */ - __raw_writel(0, base[i] + TCR); - - /* reset both timers, no pre-scaler for timer34 */ - tgcr = 0; - __raw_writel(tgcr, base[i] + TGCR); - - /* Set both timers to unchained 32-bit */ - tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; - __raw_writel(tgcr, base[i] + TGCR); - - /* Unreset timers */ - tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | - (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - __raw_writel(tgcr, base[i] + TGCR); - - /* Init both counters to zero */ - __raw_writel(0, base[i] + TIM12); - __raw_writel(0, base[i] + TIM34); - } - - /* Init of each timer as a 32-bit timer */ - for (i=0; i< ARRAY_SIZE(timers); i++) { - struct timer_s *t = &timers[i]; - int timer = ID_TO_TIMER(t->id); - u32 irq; - - t->base = base[timer]; - if (!t->base) - continue; - - if (IS_TIMER_BOT(t->id)) { - t->enamode_shift = 6; - t->tim_off = TIM12; - t->prd_off = PRD12; - irq = dtip[timer].bottom_irq; - } else { - t->enamode_shift = 22; - t->tim_off = TIM34; - t->prd_off = PRD34; - irq = dtip[timer].top_irq; - } - - /* Register interrupt */ - t->irqaction.name = t->name; - t->irqaction.dev_id = (void *)t; - - if (t->irqaction.handler != NULL) { - irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq; - setup_irq(irq, &t->irqaction); - } - } -} - -/* - * clocksource - */ -static u64 read_cycles(struct clocksource *cs) -{ - struct timer_s *t = &timers[TID_CLOCKSOURCE]; - - return (cycles_t)timer32_read(t); -} - -static struct clocksource clocksource_davinci = { - .rating = 300, - .read = read_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * Overwrite weak default sched_clock with something more precise - */ -static u64 notrace davinci_read_sched_clock(void) -{ - return timer32_read(&timers[TID_CLOCKSOURCE]); -} - -/* - * clockevent - */ -static int davinci_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->period = cycles; - timer32_config(t); - return 0; -} - -static int davinci_shutdown(struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_DISABLED; - return 0; -} - -static int davinci_set_oneshot(struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_ONESHOT; - return 0; -} - -static int davinci_set_periodic(struct clock_event_device *evt) -{ - struct timer_s *t = &timers[TID_CLOCKEVENT]; - - t->period = davinci_clock_tick_rate / (HZ); - t->opts &= ~TIMER_OPTS_STATE_MASK; - t->opts |= TIMER_OPTS_PERIODIC; - timer32_config(t); - return 0; -} - -static struct clock_event_device clockevent_davinci = { - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = davinci_set_next_event, - .set_state_shutdown = davinci_shutdown, - .set_state_periodic = davinci_set_periodic, - .set_state_oneshot = davinci_set_oneshot, -}; - -void __init davinci_timer_init(struct clk *timer_clk) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - unsigned int clockevent_id; - unsigned int clocksource_id; - int i; - - clockevent_id = soc_info->timer_info->clockevent_id; - clocksource_id = soc_info->timer_info->clocksource_id; - - timers[TID_CLOCKEVENT].id = clockevent_id; - timers[TID_CLOCKSOURCE].id = clocksource_id; - - /* - * If using same timer for both clock events & clocksource, - * a compare register must be used to generate an event interrupt. - * This is equivalent to a oneshot timer only (not periodic). - */ - if (clockevent_id == clocksource_id) { - struct davinci_timer_instance *dtip = - soc_info->timer_info->timers; - int event_timer = ID_TO_TIMER(clockevent_id); - - /* Only bottom timers can use compare regs */ - if (IS_TIMER_TOP(clockevent_id)) - pr_warn("%s: Invalid use of system timers. Results unpredictable.\n", - __func__); - else if ((dtip[event_timer].cmp_off == 0) - || (dtip[event_timer].cmp_irq == 0)) - pr_warn("%s: Invalid timer instance setup. Results unpredictable.\n", - __func__); - else { - timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE; - clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT; - } - } - - BUG_ON(IS_ERR(timer_clk)); - clk_prepare_enable(timer_clk); - - /* init timer hw */ - timer_init(); - - davinci_clock_tick_rate = clk_get_rate(timer_clk); - - /* setup clocksource */ - clocksource_davinci.name = id_to_name[clocksource_id]; - if (clocksource_register_hz(&clocksource_davinci, - davinci_clock_tick_rate)) - pr_err("%s: can't register clocksource!\n", - clocksource_davinci.name); - - sched_clock_register(davinci_read_sched_clock, 32, - davinci_clock_tick_rate); - - /* setup clockevent */ - clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; - - clockevent_davinci.cpumask = cpumask_of(0); - clockevents_config_and_register(&clockevent_davinci, - davinci_clock_tick_rate, 1, 0xfffffffe); - - for (i=0; i< ARRAY_SIZE(timers); i++) - timer32_config(&timers[i]); -} diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c deleted file mode 100644 index 25f21ee86f1a..000000000000 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DA8xx USB - */ -#include <linux/clk-provider.h> -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/init.h> -#include <linux/mfd/da8xx-cfgchip.h> -#include <linux/mfd/syscon.h> -#include <linux/phy/phy.h> -#include <linux/platform_data/clk-da8xx-cfgchip.h> -#include <linux/platform_data/phy-da8xx-usb.h> -#include <linux/platform_data/usb-davinci.h> -#include <linux/platform_device.h> -#include <linux/usb/musb.h> - -#include <mach/common.h> -#include <mach/cputype.h> -#include <mach/da8xx.h> - -#include "irqs.h" - -#define DA8XX_USB0_BASE 0x01e00000 -#define DA8XX_USB1_BASE 0x01e25000 - -#ifndef CONFIG_COMMON_CLK -static struct clk *usb20_clk; -#endif - -static struct da8xx_usb_phy_platform_data da8xx_usb_phy_pdata; - -static struct platform_device da8xx_usb_phy = { - .name = "da8xx-usb-phy", - .id = -1, - .dev = { - /* - * Setting init_name so that clock lookup will work in - * da8xx_register_usb11_phy_clk() even if this device is not - * registered yet. - */ - .init_name = "da8xx-usb-phy", - .platform_data = &da8xx_usb_phy_pdata, - }, -}; - -int __init da8xx_register_usb_phy(void) -{ - da8xx_usb_phy_pdata.cfgchip = da8xx_get_cfgchip(); - - return platform_device_register(&da8xx_usb_phy); -} - -static struct musb_hdrc_config musb_config = { - .multipoint = true, - .num_eps = 5, - .ram_bits = 10, -}; - -static struct musb_hdrc_platform_data usb_data = { - /* OTG requires a Mini-AB connector */ - .mode = MUSB_OTG, - .clock = "usb20", - .config = &musb_config, -}; - -static struct resource da8xx_usb20_resources[] = { - { - .start = DA8XX_USB0_BASE, - .end = DA8XX_USB0_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_USB_INT), - .flags = IORESOURCE_IRQ, - .name = "mc", - }, -}; - -static u64 usb_dmamask = DMA_BIT_MASK(32); - -static struct platform_device da8xx_usb20_dev = { - .name = "musb-da8xx", - .id = -1, - .dev = { - .platform_data = &usb_data, - .dma_mask = &usb_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da8xx_usb20_resources, - .num_resources = ARRAY_SIZE(da8xx_usb20_resources), -}; - -int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) -{ - usb_data.power = mA > 510 ? 255 : mA / 2; - usb_data.potpgt = (potpgt + 1) / 2; - - return platform_device_register(&da8xx_usb20_dev); -} - -static struct resource da8xx_usb11_resources[] = { - [0] = { - .start = DA8XX_USB1_BASE, - .end = DA8XX_USB1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN), - .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device da8xx_usb11_device = { - .name = "ohci-da8xx", - .id = -1, - .dev = { - .dma_mask = &da8xx_usb11_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(da8xx_usb11_resources), - .resource = da8xx_usb11_resources, -}; - -int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) -{ - da8xx_usb11_device.dev.platform_data = pdata; - return platform_device_register(&da8xx_usb11_device); -} - -static struct platform_device da8xx_usb_phy_clks_device = { - .name = "da830-usb-phy-clks", - .id = -1, -}; - -int __init da8xx_register_usb_phy_clocks(void) -{ - struct da8xx_cfgchip_clk_platform_data pdata; - - pdata.cfgchip = da8xx_get_cfgchip(); - da8xx_usb_phy_clks_device.dev.platform_data = &pdata; - - return platform_device_register(&da8xx_usb_phy_clks_device); -} diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c deleted file mode 100644 index dd8db61cdd1c..000000000000 --- a/arch/arm/mach-davinci/usb.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * USB - */ -#include <linux/dma-mapping.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/platform_data/usb-davinci.h> -#include <linux/usb/musb.h> - -#include <mach/common.h> -#include <mach/cputype.h> - -#include "irqs.h" - -#define DAVINCI_USB_OTG_BASE 0x01c64000 - -#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) -static struct musb_hdrc_config musb_config = { - .multipoint = true, - - .num_eps = 5, - .ram_bits = 10, -}; - -static struct musb_hdrc_platform_data usb_data = { - /* OTG requires a Mini-AB connector */ - .mode = MUSB_OTG, - .clock = "usb", - .config = &musb_config, -}; - -static struct resource usb_resources[] = { - { - /* physical address */ - .start = DAVINCI_USB_OTG_BASE, - .end = DAVINCI_USB_OTG_BASE + 0x5ff, - .flags = IORESOURCE_MEM, - }, - { - .start = DAVINCI_INTC_IRQ(IRQ_USBINT), - .flags = IORESOURCE_IRQ, - .name = "mc" - }, - { - /* placeholder for the dedicated CPPI IRQ */ - .flags = IORESOURCE_IRQ, - .name = "dma" - }, -}; - -static u64 usb_dmamask = DMA_BIT_MASK(32); - -static struct platform_device usb_dev = { - .name = "musb-davinci", - .id = -1, - .dev = { - .platform_data = &usb_data, - .dma_mask = &usb_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) -{ - usb_data.power = mA > 510 ? 255 : mA / 2; - usb_data.potpgt = (potpgt_ms + 1) / 2; - - if (cpu_is_davinci_dm646x()) { - /* Override the defaults as DM6467 uses different IRQs. */ - usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT); - usb_dev.resource[2].start = DAVINCI_INTC_IRQ( - IRQ_DM646X_USBDMAINT); - } else /* other devices don't have dedicated CPPI IRQ */ - usb_dev.num_resources = 2; - - platform_device_register(&usb_dev); -} - -#else - -void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) -{ -} - -#endif /* CONFIG_USB_MUSB_HDRC */ |