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-rw-r--r--arch/arm/mach-exynos/Kconfig54
-rw-r--r--arch/arm/mach-exynos/Makefile4
-rw-r--r--arch/arm/mach-exynos/common.h18
-rw-r--r--arch/arm/mach-exynos/exynos.c45
-rw-r--r--arch/arm/mach-exynos/firmware.c10
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h18
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c16
-rw-r--r--arch/arm/mach-exynos/platsmp.c34
-rw-r--r--arch/arm/mach-exynos/pm.c12
-rw-r--r--arch/arm/mach-exynos/smc.h2
-rw-r--r--arch/arm/mach-exynos/suspend.c8
11 files changed, 118 insertions, 103 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4ef56571145b..b3d5df5225fe 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -3,28 +3,21 @@
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
-# Configuration options for the EXYNOS
+# Configuration options for the Samsung Exynos
menuconfig ARCH_EXYNOS
- bool "Samsung EXYNOS"
+ bool "Samsung Exynos"
depends on ARCH_MULTI_V7
- select ARCH_HAS_HOLES_MEMORYMODEL
- select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
+ select EXYNOS_IRQ_COMBINER
select COMMON_CLK_SAMSUNG
- select EXYNOS_ASV
- select EXYNOS_CHIPID
select EXYNOS_THERMAL
select EXYNOS_PMU
select EXYNOS_SROM
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
- select GPIOLIB
- select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 && VIRTUALIZATION
+ select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP
- select HAVE_S3C2410_I2C if I2C
- select HAVE_S3C2410_WATCHDOG if WATCHDOG
- select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM
@@ -41,7 +34,7 @@ menuconfig ARCH_EXYNOS
select POWER_RESET_SYSCON
select POWER_RESET_SYSCON_POWEROFF
help
- Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
+ Support for Samsung Exynos SoCs
if ARCH_EXYNOS
@@ -51,63 +44,67 @@ config S5P_DEV_MFC
Compile in setup memory (init) code for MFC
config ARCH_EXYNOS3
- bool "SAMSUNG EXYNOS3"
+ bool "Samsung Exynos3"
default y
select ARM_CPU_SUSPEND if PM
help
- Samsung EXYNOS3 (Cortex-A7) SoC based systems
+ Samsung Exynos3 (Cortex-A7) SoC based systems
config ARCH_EXYNOS4
- bool "SAMSUNG EXYNOS4"
+ bool "Samsung Exynos4"
default y
select ARM_CPU_SUSPEND if PM_SLEEP
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210
select GIC_NON_BANKED
- select MIGHT_HAVE_CACHE_L2X0
help
- Samsung EXYNOS4 (Cortex-A9) SoC based systems
+ Samsung Exynos4 (Cortex-A9) SoC based systems
config ARCH_EXYNOS5
- bool "SAMSUNG EXYNOS5"
+ bool "Samsung Exynos5"
default y
help
- Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
+ Samsung Exynos5 (Cortex-A15/A7) SoC based systems
-comment "EXYNOS SoCs"
+comment "Exynos SoCs"
config SOC_EXYNOS3250
- bool "SAMSUNG EXYNOS3250"
+ bool "Samsung Exynos3250"
default y
depends on ARCH_EXYNOS3
config CPU_EXYNOS4210
- bool "SAMSUNG EXYNOS4210"
+ bool "Samsung Exynos4210"
+ default y
+ depends on ARCH_EXYNOS4
+
+config SOC_EXYNOS4212
+ bool "Samsung Exynos4212"
default y
depends on ARCH_EXYNOS4
config SOC_EXYNOS4412
- bool "SAMSUNG EXYNOS4412"
+ bool "Samsung Exynos4412"
default y
depends on ARCH_EXYNOS4
config SOC_EXYNOS5250
- bool "SAMSUNG EXYNOS5250"
+ bool "Samsung Exynos5250"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5260
- bool "SAMSUNG EXYNOS5260"
+ bool "Samsung Exynos5260"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5410
- bool "SAMSUNG EXYNOS5410"
+ bool "Samsung Exynos5410"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5420
- bool "SAMSUNG EXYNOS5420"
+ bool "Samsung Exynos5420"
default y
depends on ARCH_EXYNOS5
select EXYNOS_MCPM if SMP
@@ -115,9 +112,10 @@ config SOC_EXYNOS5420
select ARM_CPU_SUSPEND
config SOC_EXYNOS5800
- bool "SAMSUNG EXYNOS5800"
+ bool "Samsung EXYNOS5800"
default y
depends on SOC_EXYNOS5420
+ select EXYNOS_REGULATOR_COUPLER
config EXYNOS_MCPM
bool
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 0fd3fcf8bfb0..53fa363c8e44 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -3,10 +3,6 @@
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
-
-# Core
-
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o exynos-smc.o firmware.o
obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 56411bb63d45..f4c0d33a29e2 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -3,7 +3,7 @@
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * Common Header for EXYNOS machines
+ * Common Header for Exynos machines
*/
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
@@ -15,6 +15,7 @@
#define EXYNOS3_SOC_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
+#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4412_CPU_ID 0xE4412200
#define EXYNOS4_CPU_MASK 0xFFFE0000
@@ -24,16 +25,17 @@
#define EXYNOS5800_SOC_ID 0xE5422000
#define EXYNOS5_SOC_MASK 0xFFFFF000
-extern unsigned long samsung_cpu_id;
+extern unsigned long exynos_cpu_id;
#define IS_SAMSUNG_CPU(name, id, mask) \
static inline int is_samsung_##name(void) \
{ \
- return ((samsung_cpu_id & mask) == (id & mask)); \
+ return ((exynos_cpu_id & mask) == (id & mask)); \
}
IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
@@ -52,6 +54,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos4210() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212() is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212() 0
+#endif
+
#if defined(CONFIG_SOC_EXYNOS4412)
# define soc_is_exynos4412() is_samsung_exynos4412()
#else
@@ -106,7 +114,7 @@ void exynos_firmware_init(void);
#define C2_STATE (1 << 3)
/*
* Magic values for bootloader indicating chosen low power mode.
- * See also Documentation/arm/samsung/bootloader-interface.rst
+ * See also Documentation/arch/arm/samsung/bootloader-interface.rst
*/
#define EXYNOS_SLEEP_MAGIC 0x00000bad
#define EXYNOS_AFTR_MAGIC 0xfcba0d10
@@ -147,7 +155,7 @@ extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
extern void exynos_set_delayed_reset_assertion(bool enable);
-extern unsigned int samsung_rev(void);
+extern unsigned int exynos_rev(void);
extern void exynos_core_restart(u32 core_id);
extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 9aa483366ebc..2e8099479ffa 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
-// SAMSUNG EXYNOS Flattened Device Tree enabled machine
+// Samsung Exynos Flattened Device Tree enabled machine
//
// Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
@@ -19,11 +19,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-#include <plat/cpu.h>
-
#include "common.h"
+#define S3C_ADDR_BASE 0xF6000000
+#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
+
static struct platform_device exynos_cpuidle = {
.name = "exynos_cpuidle",
#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@@ -36,16 +37,27 @@ void __iomem *sysram_base_addr __ro_after_init;
phys_addr_t sysram_base_phys __ro_after_init;
void __iomem *sysram_ns_base_addr __ro_after_init;
+unsigned long exynos_cpu_id;
+static unsigned int exynos_cpu_rev;
+
+unsigned int exynos_rev(void)
+{
+ return exynos_cpu_rev;
+}
+
void __init exynos_sysram_init(void)
{
struct device_node *node;
for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
+ struct resource res;
if (!of_device_is_available(node))
continue;
- sysram_base_addr = of_iomap(node, 0);
- sysram_base_phys = of_translate_address(node,
- of_get_address(node, 0, NULL, NULL));
+
+ of_address_to_resource(node, 0, &res);
+ sysram_base_addr = ioremap(res.start, resource_size(&res));
+ sysram_base_phys = res.start;
+ of_node_put(node);
break;
}
@@ -53,6 +65,7 @@ void __init exynos_sysram_init(void)
if (!of_device_is_available(node))
continue;
sysram_ns_base_addr = of_iomap(node, 0);
+ of_node_put(node);
break;
}
}
@@ -86,7 +99,11 @@ static void __init exynos_init_io(void)
of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
/* detect cpu id and rev. */
- s5p_init_cpu(S5P_VA_CHIPID);
+ exynos_cpu_id = readl_relaxed(S5P_VA_CHIPID);
+ exynos_cpu_rev = exynos_cpu_id & 0xFF;
+
+ pr_info("Samsung CPU ID: 0x%08lx\n", exynos_cpu_id);
+
}
/*
@@ -134,6 +151,7 @@ static void exynos_map_pmu(void)
np = of_find_matching_node(NULL, exynos_dt_pmu_match);
if (np)
pmu_base_addr = of_iomap(np, 0);
+ of_node_put(np);
}
static void __init exynos_init_irq(void)
@@ -162,9 +180,11 @@ static void __init exynos_dt_machine_init(void)
exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;
#endif
if (of_machine_is_compatible("samsung,exynos4210") ||
+ of_machine_is_compatible("samsung,exynos4212") ||
(of_machine_is_compatible("samsung,exynos4412") &&
(of_machine_is_compatible("samsung,trats2") ||
- of_machine_is_compatible("samsung,midas"))) ||
+ of_machine_is_compatible("samsung,midas") ||
+ of_machine_is_compatible("samsung,p4note"))) ||
of_machine_is_compatible("samsung,exynos3250") ||
of_machine_is_compatible("samsung,exynos5250"))
platform_device_register(&exynos_cpuidle);
@@ -175,6 +195,7 @@ static char const *const exynos_dt_compat[] __initconst = {
"samsung,exynos3250",
"samsung,exynos4",
"samsung,exynos4210",
+ "samsung,exynos4212",
"samsung,exynos4412",
"samsung,exynos5",
"samsung,exynos5250",
@@ -192,9 +213,9 @@ static void __init exynos_dt_fixup(void)
of_fdt_limit_memory(8);
}
-DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
- .l2c_aux_val = 0x3c400001,
- .l2c_aux_mask = 0xc20fffff,
+DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
+ .l2c_aux_val = 0x08400000,
+ .l2c_aux_mask = 0xf60fffff,
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 2eaf2dbb8e81..a5e22678e27b 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -60,13 +60,21 @@ static int exynos_cpu_boot(int cpu)
/*
* Exynos3250 doesn't need to send smc command for secondary CPU boot
* because Exynos3250 removes WFE in secure mode.
+ *
+ * On Exynos5 devices the call is ignored by trustzone firmware.
*/
- if (soc_is_exynos3250())
+ if (!soc_is_exynos4210() && !soc_is_exynos4212() &&
+ !soc_is_exynos4412())
return 0;
/*
* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
+ * But, Exynos4212 has only one secondary CPU so second parameter
+ * isn't used for informing secure firmware about CPU id.
*/
+ if (soc_is_exynos4212())
+ cpu = 0;
+
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0;
}
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
deleted file mode 100644
index 22ebe3654633..000000000000
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * EXYNOS - Memory map definitions
- */
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-
-#include <plat/map-s5p.h>
-
-#define EXYNOS_PA_CHIPID 0x10000000
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 9a681b421ae1..fd0dbeb93357 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -26,6 +26,7 @@
#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
static void __iomem *ns_sram_base_addr __ro_after_init;
+static bool secure_firmware __ro_after_init;
/*
* The common v7_exit_coherency_flush API could not be used because of the
@@ -34,7 +35,6 @@ static void __iomem *ns_sram_base_addr __ro_after_init;
*/
#define exynos_v7_exit_coherency_flush(level) \
asm volatile( \
- "stmfd sp!, {fp, ip}\n\t"\
"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
"bic r0, r0, #"__stringify(CR_C)"\n\t" \
"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
@@ -49,24 +49,24 @@ static void __iomem *ns_sram_base_addr __ro_after_init;
"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
"isb\n\t" \
"dsb\n\t" \
- "ldmfd sp!, {fp, ip}" \
: \
: "Ir" (pmu_base_addr + S5P_INFORM0) \
- : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "r9", "r10", "lr", "memory")
+ : "r0", "r1", "r2", "r3", "r4", "r5", "r6", \
+ "r9", "r10", "ip", "lr", "memory")
static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
{
unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+ bool state;
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
cluster >= EXYNOS5420_NR_CLUSTERS)
return -EINVAL;
- if (!exynos_cpu_power_state(cpunr)) {
- exynos_cpu_power_up(cpunr);
-
+ state = exynos_cpu_power_state(cpunr);
+ exynos_cpu_power_up(cpunr);
+ if (!state && secure_firmware) {
/*
* This assumes the cluster number of the big cores(Cortex A15)
* is 0 and the Little cores(Cortex A7) is 1.
@@ -258,6 +258,8 @@ static int __init exynos_mcpm_init(void)
return -ENOMEM;
}
+ secure_firmware = exynos_secure_firmware_available();
+
/*
* To increase the stability of KFC reset we need to program
* the PMU SPARE3 register
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0cbbae8bf1f8..fb4a394ece3a 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -22,8 +22,6 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
-#include <mach/map.h>
-
#include "common.h"
extern void exynos4_secondary_startup(void);
@@ -80,12 +78,11 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
#endif /* CONFIG_HOTPLUG_CPU */
/**
- * exynos_core_power_down : power down the specified cpu
- * @cpu : the cpu to power down
+ * exynos_cpu_power_down() - power down the specified cpu
+ * @cpu: the cpu to power down
*
* Power down the specified cpu. The sequence must be finished by a
* call to cpu_do_idle()
- *
*/
void exynos_cpu_power_down(int cpu)
{
@@ -109,8 +106,8 @@ void exynos_cpu_power_down(int cpu)
}
/**
- * exynos_cpu_power_up : power up the specified cpu
- * @cpu : the cpu to power up
+ * exynos_cpu_power_up() - power up the specified cpu
+ * @cpu: the cpu to power up
*
* Power up the specified cpu
*/
@@ -126,9 +123,8 @@ void exynos_cpu_power_up(int cpu)
}
/**
- * exynos_cpu_power_state : returns the power state of the cpu
- * @cpu : the cpu to retrieve the power state from
- *
+ * exynos_cpu_power_state() - returns the power state of the cpu
+ * @cpu: the cpu to retrieve the power state from
*/
int exynos_cpu_power_state(int cpu)
{
@@ -137,8 +133,8 @@ int exynos_cpu_power_state(int cpu)
}
/**
- * exynos_cluster_power_down : power down the specified cluster
- * @cluster : the cluster to power down
+ * exynos_cluster_power_down() - power down the specified cluster
+ * @cluster: the cluster to power down
*/
void exynos_cluster_power_down(int cluster)
{
@@ -146,8 +142,8 @@ void exynos_cluster_power_down(int cluster)
}
/**
- * exynos_cluster_power_up : power up the specified cluster
- * @cluster : the cluster to power up
+ * exynos_cluster_power_up() - power up the specified cluster
+ * @cluster: the cluster to power up
*/
void exynos_cluster_power_up(int cluster)
{
@@ -156,8 +152,8 @@ void exynos_cluster_power_up(int cluster)
}
/**
- * exynos_cluster_power_state : returns the power state of the cluster
- * @cluster : the cluster to retrieve the power state from
+ * exynos_cluster_power_state() - returns the power state of the cluster
+ * @cluster: the cluster to retrieve the power state from
*
*/
int exynos_cluster_power_state(int cluster)
@@ -167,7 +163,7 @@ int exynos_cluster_power_state(int cluster)
}
/**
- * exynos_scu_enable : enables SCU for Cortex-A9 based system
+ * exynos_scu_enable() - enables SCU for Cortex-A9 based system
*/
void exynos_scu_enable(void)
{
@@ -188,7 +184,7 @@ void exynos_scu_enable(void)
static void __iomem *cpu_boot_reg_base(void)
{
- if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+ if (soc_is_exynos4210() && exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM5;
return sysram_base_addr;
}
@@ -217,7 +213,7 @@ void exynos_core_restart(u32 core_id)
unsigned int timeout = 16;
u32 val;
- if (!of_machine_is_compatible("samsung,exynos3250"))
+ if (!soc_is_exynos3250())
return;
while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 48e7fb38613e..0019d21bff90 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
-// EXYNOS - Power Management support
+// Exynos - Power Management support
//
// Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics
@@ -26,18 +26,18 @@
static inline void __iomem *exynos_boot_vector_addr(void)
{
- if (samsung_rev() == EXYNOS4210_REV_1_1)
+ if (exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM7;
- else if (samsung_rev() == EXYNOS4210_REV_1_0)
+ else if (exynos_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x24;
return pmu_base_addr + S5P_INFORM0;
}
static inline void __iomem *exynos_boot_vector_flag(void)
{
- if (samsung_rev() == EXYNOS4210_REV_1_1)
+ if (exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM6;
- else if (samsung_rev() == EXYNOS4210_REV_1_0)
+ else if (exynos_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x20;
return pmu_base_addr + S5P_INFORM1;
}
@@ -161,7 +161,7 @@ void exynos_enter_aftr(void)
exynos_pm_central_suspend();
- if (soc_is_exynos4412()) {
+ if (soc_is_exynos4212() || soc_is_exynos4412()) {
/* Setting SEQ_OPTION register */
pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
S5P_CENTRAL_SEQ_OPTION);
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index 98832e50852d..5c30feb8f07d 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -2,7 +2,7 @@
/*
* Copyright (c) 2012 Samsung Electronics.
*
- * EXYNOS - SMC Call
+ * Exynos - SMC Call
*/
#ifndef __ASM_ARCH_EXYNOS_SMC_H
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 6a0d3448ea00..cac4e82f6c82 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
-// EXYNOS - Suspend support
+// Exynos - Suspend support
//
// Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics
@@ -231,6 +231,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node,
EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
+EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
@@ -641,6 +642,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
.compatible = "samsung,exynos4210-pmu",
.data = &exynos4_pm_data,
}, {
+ .compatible = "samsung,exynos4212-pmu",
+ .data = &exynos4_pm_data,
+ }, {
.compatible = "samsung,exynos4412-pmu",
.data = &exynos4_pm_data,
}, {
@@ -667,7 +671,7 @@ void __init exynos_pm_init(void)
return;
}
- if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
+ if (WARN_ON(!of_property_read_bool(np, "interrupt-controller"))) {
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
of_node_put(np);
return;