diff options
Diffstat (limited to 'arch/arm/mach-mmp/time.c')
| -rw-r--r-- | arch/arm/mach-mmp/time.c | 34 |
1 files changed, 13 insertions, 21 deletions
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 110dcb3314d1..fcb190826dd1 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -29,33 +29,30 @@ #include <linux/sched_clock.h> #include <asm/mach/time.h> -#include "addr-map.h" #include "regs-timers.h" -#include "regs-apbc.h" -#include "irqs.h" #include <linux/soc/mmp/cputype.h> -#include "clock.h" - -#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE #define MAX_DELTA (0xfffffffe) #define MIN_DELTA (16) -static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; +static void __iomem *mmp_timer_base; /* - * FIXME: the timer needs some delay to stablize the counter capture + * Read the timer through the CVWR register. Delay is required after requesting + * a read. The CR register cannot be directly read due to metastability issues + * documented in the PXA168 software manual. */ static inline uint32_t timer_read(void) { - int delay = 100; + uint32_t val; + int delay = 3; __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); while (delay--) - cpu_relax(); + val = __raw_readl(mmp_timer_base + TMR_CVWR(1)); - return __raw_readl(mmp_timer_base + TMR_CVWR(1)); + return val; } static u64 notrace mmp_read_sched_clock(void) @@ -175,14 +172,7 @@ static void __init timer_config(void) __raw_writel(0x2, mmp_timer_base + TMR_CER); } -static struct irqaction timer_irq = { - .name = "timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .handler = timer_interrupt, - .dev_id = &ckevt, -}; - -void __init mmp_timer_init(int irq, unsigned long rate) +static void __init mmp_timer_init(int irq, unsigned long rate) { timer_config(); @@ -190,7 +180,9 @@ void __init mmp_timer_init(int irq, unsigned long rate) ckevt.cpumask = cpumask_of(0); - setup_irq(irq, &timer_irq); + if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, + "timer", &ckevt)) + pr_err("Failed to request irq %d (timer)\n", irq); clocksource_register_hz(&cksrc, rate); clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA); @@ -207,7 +199,7 @@ static int __init mmp_dt_init_timer(struct device_node *np) ret = clk_prepare_enable(clk); if (ret) return ret; - rate = clk_get_rate(clk) / 2; + rate = clk_get_rate(clk); } else if (cpu_is_pj4()) { rate = 6500000; } else { |