diff options
Diffstat (limited to 'arch/arm/mach-orion5x/include')
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/bridge-regs.h | 37 | ||||
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/entry-macro.S | 25 | ||||
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/hardware.h | 14 | ||||
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/irqs.h | 60 | ||||
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h | 146 | ||||
| -rw-r--r-- | arch/arm/mach-orion5x/include/mach/uncompress.h | 48 |
6 files changed, 0 insertions, 330 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h deleted file mode 100644 index 5766e3fbff69..000000000000 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/bridge-regs.h - * - * Orion CPU Bridge Registers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include <mach/orion5x.h> - -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) - -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) - -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) -#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) - -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) - -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) - -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) - -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) - -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) - -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) -#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) -#endif diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S deleted file mode 100644 index 73919a36b577..000000000000 --- a/arch/arm/mach-orion5x/include/mach/entry-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Orion platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <mach/bridge-regs.h> - - .macro get_irqnr_preamble, base, tmp - ldr \base, =MAIN_IRQ_CAUSE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #0] @ main cause - ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask - mov \irqnr, #0 @ default irqnr - @ find cause bits that are unmasked - ands \irqstat, \irqstat, \tmp @ clear Z flag if any - clzne \irqnr, \irqstat @ calc irqnr - rsbne \irqnr, \irqnr, #32 - .endm diff --git a/arch/arm/mach-orion5x/include/mach/hardware.h b/arch/arm/mach-orion5x/include/mach/hardware.h deleted file mode 100644 index 395735482473..000000000000 --- a/arch/arm/mach-orion5x/include/mach/hardware.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/hardware.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "orion5x.h" - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h deleted file mode 100644 index 2431d9923427..000000000000 --- a/arch/arm/mach-orion5x/include/mach/irqs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION5X_BRIDGE (1 + 0) -#define IRQ_ORION5X_DOORBELL_H2C (1 + 1) -#define IRQ_ORION5X_DOORBELL_C2H (1 + 2) -#define IRQ_ORION5X_UART0 (1 + 3) -#define IRQ_ORION5X_UART1 (1 + 4) -#define IRQ_ORION5X_I2C (1 + 5) -#define IRQ_ORION5X_GPIO_0_7 (1 + 6) -#define IRQ_ORION5X_GPIO_8_15 (1 + 7) -#define IRQ_ORION5X_GPIO_16_23 (1 + 8) -#define IRQ_ORION5X_GPIO_24_31 (1 + 9) -#define IRQ_ORION5X_PCIE0_ERR (1 + 10) -#define IRQ_ORION5X_PCIE0_INT (1 + 11) -#define IRQ_ORION5X_USB1_CTRL (1 + 12) -#define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) -#define IRQ_ORION5X_PCI_ERR (1 + 15) -#define IRQ_ORION5X_USB_BR_ERR (1 + 16) -#define IRQ_ORION5X_USB0_CTRL (1 + 17) -#define IRQ_ORION5X_ETH_RX (1 + 18) -#define IRQ_ORION5X_ETH_TX (1 + 19) -#define IRQ_ORION5X_ETH_MISC (1 + 20) -#define IRQ_ORION5X_ETH_SUM (1 + 21) -#define IRQ_ORION5X_ETH_ERR (1 + 22) -#define IRQ_ORION5X_IDMA_ERR (1 + 23) -#define IRQ_ORION5X_IDMA_0 (1 + 24) -#define IRQ_ORION5X_IDMA_1 (1 + 25) -#define IRQ_ORION5X_IDMA_2 (1 + 26) -#define IRQ_ORION5X_IDMA_3 (1 + 27) -#define IRQ_ORION5X_CESA (1 + 28) -#define IRQ_ORION5X_SATA (1 + 29) -#define IRQ_ORION5X_XOR0 (1 + 30) -#define IRQ_ORION5X_XOR1 (1 + 31) - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION5X_GPIO_START 33 -#define NR_GPIO_IRQS 32 - -#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h deleted file mode 100644 index b78ff3248868..000000000000 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/orion5x.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION5X_H -#define __ASM_ARCH_ORION5X_H - -/***************************************************************************** - * Orion Address Maps - * - * phys - * e0000000 PCIe MEM space - * e8000000 PCI MEM space - * f0000000 PCIe WA space (Orion-1/Orion-NAS only) - * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f2100000 PCI I/O space - * f2200000 SRAM dedicated for the crypto unit - * f4000000 device bus mappings (boot) - * fa000000 device bus mappings (cs0) - * fa800000 device bus mappings (cs2) - * fc000000 device bus mappings (cs0/cs1) - * - * virt phys size - * fe000000 f1000000 1M on-chip peripheral registers - * fee00000 f2000000 64K PCIe I/O space - * fee10000 f2100000 64K PCI I/O space - * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) - ****************************************************************************/ -#define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) -#define ORION5X_REGS_SIZE SZ_1M - -#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_64K - -#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_BUS_BASE 0x00010000 -#define ORION5X_PCI_IO_SIZE SZ_64K - -#define ORION5X_SRAM_PHYS_BASE (0xf2200000) -#define ORION5X_SRAM_SIZE SZ_8K - -/* Relevant only for Orion-1/Orion-NAS */ -#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) -#define ORION5X_PCIE_WA_SIZE SZ_16M - -#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION5X_PCIE_MEM_SIZE SZ_128M - -#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION5X_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ - -#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) -#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) -#define ORION5X_DDR_WINS_SZ (0x10) -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) -#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) -#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) - -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) -#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) -#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) -#define ORION5X_BRIDGE_WINS_SZ (0x80) - -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) - -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) - -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) - -#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) -#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) - -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) - -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) - -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) - -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) -#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -#define MV88F5181L_REV_A0 8 -#define MV88F5181L_REV_A1 9 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D0 4 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 -/* Orion-1-90 (88F6183) */ -#define MV88F6183_DEV_ID 0x6183 -#define MV88F6183_REV_B0 3 - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h deleted file mode 100644 index abd26b542c3c..000000000000 --- a/arch/arm/mach-orion5x/include/mach/uncompress.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/uncompress.h - * - * Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/serial_reg.h> -#include <mach/orion5x.h> - -#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) - -static void putc(const char c) -{ - unsigned char *base = SERIAL_BASE; - int i; - - for (i = 0; i < 0x1000; i++) { - if (base[UART_LSR << 2] & UART_LSR_THRE) - break; - barrier(); - } - - base[UART_TX << 2] = c; -} - -static void flush(void) -{ - unsigned char *base = SERIAL_BASE; - unsigned char mask; - int i; - - mask = UART_LSR_TEMT | UART_LSR_THRE; - - for (i = 0; i < 0x1000; i++) { - if ((base[UART_LSR << 2] & mask) == mask) - break; - barrier(); - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() |