diff options
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/pxa3xx-regs.h')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 8eb1ba533e1c..4b11cf81a9e6 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -131,73 +131,4 @@ #define CKENC __REG(0x41340024) /* C Clock Enable Register */ #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ -#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ -#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ -#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ -#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ -#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ - -#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ -#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ -#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ -#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ -#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ -#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ -#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ - -#define ACCR_SMCFS(x) (((x) & 0x7) << 23) -#define ACCR_SFLFS(x) (((x) & 0x3) << 18) -#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) -#define ACCR_HSS(x) (((x) & 0x3) << 14) -#define ACCR_DMCFS(x) (((x) & 0x3) << 12) -#define ACCR_XN(x) (((x) & 0x7) << 8) -#define ACCR_XL(x) ((x) & 0x1f) - -/* - * Clock Enable Bit - */ -#define CKEN_LCD 1 /* < LCD Clock Enable */ -#define CKEN_USBH 2 /* < USB host clock enable */ -#define CKEN_CAMERA 3 /* < Camera interface clock enable */ -#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ -#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ -#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ -#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ -#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ -#define CKEN_BOOT 11 /* < Boot rom clock enable */ -#define CKEN_MMC1 12 /* < MMC1 Clock enable */ -#define CKEN_MMC2 13 /* < MMC2 clock enable */ -#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ -#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ -#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ -#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ -#define CKEN_TPM 19 /* < TPM clock enable */ -#define CKEN_UDC 20 /* < UDC clock enable */ -#define CKEN_BTUART 21 /* < BTUART clock enable */ -#define CKEN_FFUART 22 /* < FFUART clock enable */ -#define CKEN_STUART 23 /* < STUART clock enable */ -#define CKEN_AC97 24 /* < AC97 clock enable */ -#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ -#define CKEN_SSP1 26 /* < SSP1 clock enable */ -#define CKEN_SSP2 27 /* < SSP2 clock enable */ -#define CKEN_SSP3 28 /* < SSP3 clock enable */ -#define CKEN_SSP4 29 /* < SSP4 clock enable */ -#define CKEN_MSL0 30 /* < MSL0 clock enable */ -#define CKEN_PWM0 32 /* < PWM[0] clock enable */ -#define CKEN_PWM1 33 /* < PWM[1] clock enable */ -#define CKEN_I2C 36 /* < I2C clock enable */ -#define CKEN_INTC 38 /* < Interrupt controller clock enable */ -#define CKEN_GPIO 39 /* < GPIO clock enable */ -#define CKEN_1WIRE 40 /* < 1-wire clock enable */ -#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ -#define CKEN_MINI_IM 48 /* < Mini-IM */ -#define CKEN_MINI_LCD 49 /* < Mini LCD */ - -#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ -#define CKEN_MVED 43 /* < MVED clock enable */ - -/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ -#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ -#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ - #endif /* __ASM_ARCH_PXA3XX_REGS_H */ |