diff options
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-tegra30.S | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 9942265ed650..2667bcdb5dc6 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -361,7 +361,6 @@ _no_pll_iddq_exit: pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC - pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC _pll_m_c_x_done: pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC @@ -371,12 +370,18 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLP_BASE pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE - pll_locked r1, r0, CLK_RESET_PLLX_BASE + /* + * CPUFreq driver could select other PLL for CPU. PLLX will be + * enabled by the Tegra30 CLK driver on an as-needed basis, see + * tegra30_cpu_clock_resume(). + */ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 cmp r1, #TEGRA30 beq 1f + pll_locked r1, r0, CLK_RESET_PLLX_BASE + ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass str r1, [r0, #CLK_RESET_PLLP_BASE] |