diff options
Diffstat (limited to 'arch/arm/mach-vexpress/tc2_pm.c')
| -rw-r--r-- | arch/arm/mach-vexpress/tc2_pm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index 54a9fff77c7d..2fb78b4648cb 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -152,7 +152,7 @@ static void tc2_pm_down(u64 residency) if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { arch_spin_unlock(&tc2_pm_lock); - if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { /* * On the Cortex-A15 we need to disable * L2 prefetching before flushing the cache. @@ -326,7 +326,7 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) static void __init tc2_cache_off(void) { pr_info("TC2: disabling cache during MCPM loopback test\n"); - if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { /* disable L2 prefetching on the Cortex-A15 */ asm volatile( "mcr p15, 1, %0, c15, c0, 3 \n\t" |