diff options
Diffstat (limited to 'arch/arm64/boot/dts/altera')
-rw-r--r-- | arch/arm64/boot/dts/altera/Makefile | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 195 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 64 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 201 | ||||
-rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts | 115 |
5 files changed, 470 insertions, 109 deletions
diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 27bb925adc8d..1bf0c472f6b4 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ + socfpga_stratix10_socdk_nand.dtb \ + socfpga_stratix10_swvp.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 144a2c19ac02..072fe20cfca0 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -59,12 +59,31 @@ }; }; + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + + fpga-region { + compatible = "fpga-region"; + #address-cells = <0x2>; + #size-cells = <0x2>; + fpga-mgr = <&fpga_mgr>; + }; + pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <0 120 8>, - <0 121 8>, - <0 122 8>, - <0 123 8>; + interrupts = <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -77,7 +96,17 @@ method = "smc"; }; - intc: intc@fffc1000 { + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + interrupt-parent = <&intc>; + }; + + intc: interrupt-controller@fffc1000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -87,7 +116,35 @@ <0x0 0xfffc6000 0x0 0x2000>; }; - soc { + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + soc@0 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -95,48 +152,12 @@ interrupt-parent = <&intc>; ranges = <0 0 0 0xffffffff>; - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - clkmgr: clock-controller@ffd10000 { compatible = "intel,stratix10-clkmgr"; reg = <0xffd10000 0x1000>; #clock-cells = <1>; }; - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; @@ -144,9 +165,9 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC0_CLK>; - clock-names = "stmmaceth"; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -162,9 +183,9 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC1_CLK>; - clock-names = "stmmaceth"; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -180,9 +201,9 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC2_CLK>; - clock-names = "stmmaceth"; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -203,7 +224,7 @@ compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - snps,nr-gpios = <24>; + ngpios = <24>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -223,7 +244,7 @@ compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - snps,nr-gpios = <24>; + ngpios = <24>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -286,7 +307,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; @@ -299,10 +320,11 @@ <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; - nand: nand@ffb90000 { + nand: nand-controller@ffb90000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-denali-nand"; @@ -321,9 +343,12 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xffe00000 0x100000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = <0 81 4>, @@ -336,14 +361,28 @@ <0 88 4>, <0 89 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; reset-names = "dma", "dma-ocp"; }; + pinctrl0: pinctrl@ffd13000 { + compatible = "pinctrl-single"; + reg = <0xffd13000 0xA0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + + pinctrl1: pinctrl@ffd13100 { + compatible = "pinctrl-single"; + reg = <0xffd13100 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,stratix10-rst-mgr"; @@ -380,6 +419,7 @@ reg = <0xffda4000 0x1000>; interrupts = <0 99 4>; resets = <&rst SPIM0_RESET>; + reset-names = "spi"; reg-io-width = <4>; num-cs = <4>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; @@ -393,6 +433,7 @@ reg = <0xffda5000 0x1000>; interrupts = <0 100 4>; resets = <&rst SPIM1_RESET>; + reset-names = "spi"; reg-io-width = <4>; num-cs = <4>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; @@ -404,15 +445,6 @@ reg = <0xffd12000 0x228>; }; - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - timer0: timer0@ffc03000 { compatible = "snps,dw-apb-timer"; interrupts = <0 113 4>; @@ -445,7 +477,7 @@ clock-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x100>; interrupts = <0 108 4>; @@ -456,7 +488,7 @@ status = "disabled"; }; - uart1: serial1@ffc02100 { + uart1: serial@ffc02100 { compatible = "snps,dw-apb-uart"; reg = <0xffc02100 0x100>; interrupts = <0 109 4>; @@ -467,12 +499,6 @@ status = "disabled"; }; - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - usb0: usb@ffb00000 { compatible = "snps,dwc2"; reg = <0xffb00000 0x40000>; @@ -482,6 +508,7 @@ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr STRATIX10_USB_CLK>; + clock-names = "otg"; iommus = <&smmu 6>; status = "disabled"; }; @@ -495,6 +522,7 @@ resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr STRATIX10_USB_CLK>; + clock-names = "otg"; iommus = <&smmu 7>; status = "disabled"; }; @@ -592,7 +620,7 @@ }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, @@ -605,17 +633,10 @@ status = "disabled"; }; + }; - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index fb11ef05d556..26173f0b0051 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; @@ -21,42 +22,36 @@ leds { compatible = "gpio-leds"; - hps0 { + led-hps0 { label = "hps_led0"; gpios = <&portb 20 GPIO_ACTIVE_HIGH>; }; - hps1 { + led-hps1 { label = "hps_led1"; gpios = <&portb 19 GPIO_ACTIVE_HIGH>; }; - hps2 { + led-hps2 { label = "hps_led2"; gpios = <&portb 21 GPIO_ACTIVE_HIGH>; }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; regulator-max-microvolt = <330000>; }; - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - + soc@0 { eccmgr { sdmmca-ecc@ff8c8c00 { compatible = "altr,socfpga-s10-sdmmc-ecc", @@ -70,6 +65,22 @@ }; }; +&pinctrl0 { + i2c1_pmx_func: i2c1-pmx-func-pins { + pinctrl-single,pins = < + 0x78 0x4 /* I2C1_SDA (IO6-B) PIN30SEL) */ + 0x7c 0x4 /* I2C1_SCL (IO7-B) PIN31SEL */ + >; + }; + + i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins { + pinctrl-single,pins = < + 0x78 0x8 /* I2C1_SDA (IO6-B) PIN30SEL) */ + 0x7c 0x8 /* I2C1_SCL (IO7-B) PIN31SEL */ + >; + }; +}; + &gpio1 { status = "okay"; }; @@ -110,6 +121,11 @@ cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; }; &uart0 { @@ -129,7 +145,14 @@ status = "okay"; clock-frequency = <100000>; i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ + i2c-scl-falling-time-ns = <890>; /* lcnt */ + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pmx_func>; + pinctrl-1 = <&i2c1_pmx_func_gpio>; + + scl-gpios = <&portb 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&portb 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; adc@14 { compatible = "lltc,ltc2497"; @@ -155,16 +178,15 @@ }; &qspi { + status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00a"; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; cdns,read-delay = <1>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; @@ -178,12 +200,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; + reg = <0x0 0x04200000>; }; - qspi_rootfs: partition@4000000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; + root: partition@4200000 { + label = "Root Filesystem - UBIFS"; + reg = <0x04200000 0x0BE00000>; }; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts new file mode 100644 index 000000000000..81d0e914a77c --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright Altera Corporation (C) 2015. All rights reserved. + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led-hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led-hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led-hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; + + ref_033v: regulator-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + + soc@0 { + eccmgr { + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 4>, + <15 4>; + }; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <16>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + i2c-sda-falling-time-ns = <890>; /* hcnt */ + i2c-scl-falling-time-ns = <890>; /* lcnt */ + + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x03FE0000>; + }; + + qspi_rootfs: partition@3fe0000 { + label = "Root Filesystem - JFFS2"; + reg = <0x03FE0000 0x0C020000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts new file mode 100644 index 000000000000..0d837d3e65a5 --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SOCFPGA Stratix 10 SWVP"; + compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + linux,initrd-start = <0x10000000>; + linux,initrd-end = <0x125c8324>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&cpu0 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu1 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu2 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu3 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; + snps,max-mtu = <0x0>; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&usb1 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&rst { + altr,modrst-offset = <0x20>; +}; + +&sysmgr { + reg = <0xffd12000 0x1000>; + interrupts = <0x0 0x10 0x4>; + cpu1-start-addr = <0xffd06230>; +}; |