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Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos5433-tm2.dts')
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2.dts34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index ddba2f889326..dea0a6f5bc18 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -18,6 +18,40 @@
compatible = "samsung,tm2", "samsung,exynos5433";
};
+&cmu_disp {
+ /*
+ * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
+ * clocks properties for DISP CMU for each board to keep them together
+ * for easier review and maintenance.
+ */
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <250000000>, <400000000>;
+};
+
&hsi2c_9 {
status = "okay";