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Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts70
1 files changed, 69 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d1ccc000d05a..5dc2782e2a58 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
- * Copyright 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
*
* Mingkai Hu <mingkai.hu@nxp.com>
*
@@ -72,6 +72,14 @@
status = "okay";
};
+&esdhc {
+ mmc-hs200-1_8v;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+};
+
&i2c0 {
status = "okay";
@@ -148,3 +156,63 @@
reg = <1>;
};
};
+
+#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&sgmii_phy1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 { /* 10GEC1 */
+ phy-handle = <&aqr106_phy>;
+ phy-connection-type = "xgmii";
+ };
+
+ ethernet@f2000 { /* 10GEC2 */
+ fixed-link = <0 1 1000 0 0>;
+ phy-connection-type = "xgmii";
+ };
+
+ mdio@fc000 {
+ rgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ rgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sgmii_phy1: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ sgmii_phy2: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ };
+
+ mdio@fd000 {
+ aqr106_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 131 4>;
+ reg = <0x0>;
+ };
+ };
+};