diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 0a477f6318f1..72434529f78e 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -3,6 +3,63 @@ * Copyright 2019~2020, 2022 NXP */ +/delete-node/ &asrc1; +/delete-node/ &asrc1_lpcg; +/delete-node/ &adc1; +/delete-node/ &adc1_lpcg; +/delete-node/ &amix; +/delete-node/ &amix_lpcg; +/delete-node/ &edma1; +/delete-node/ &esai0; +/delete-node/ &esai0_lpcg; +/delete-node/ &sai4; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5; +/delete-node/ &sai5_lpcg; + +&acm { + compatible = "fsl,imx8dxl-acm"; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk"; +}; + &audio_ipg_clk { clock-frequency = <160000000>; }; @@ -15,6 +72,63 @@ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; }; +&edma0 { + reg = <0x591f0000 0x1a0000>; + #dma-cells = <3>; + dma-channels = <25>; + dma-channel-mask = <0x1c0cc0>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; +}; + &edma2 { interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, @@ -45,24 +159,44 @@ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; }; +&flexcan1 { + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan2 { + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan3 { + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; }; &i2c1 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; }; &i2c2 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; }; &i2c3 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; }; &lpuart0 { @@ -100,3 +234,24 @@ &lpspi3 { interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; }; + +&sai0 { + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai1 { + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai2 { + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai3 { + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; +}; + +&spdif0 { + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */ +}; |