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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
index ea6e8b85169f..b941c8c4f7bb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
#include "imx8mm-tqma8mqml.dtsi"
#include "mba8mx.dtsi"
@@ -73,20 +75,29 @@
};
};
+&mipi_dsi {
+ samsung,burst-clock-frequency = <891000000>;
+ samsung,esc-clock-frequency = <20000000>;
+};
+
&pcie_phy {
- clocks = <&pcie0_refclk>;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcieclk 2>;
+ clock-names = "ref";
status = "okay";
};
+/* PCIe slot on X36 */
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
+ <&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};