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Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hip06.dtsi')
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi124
1 files changed, 65 insertions, 59 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 50ceaa959bdc..3d7285e6700e 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -211,18 +211,26 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
@@ -242,7 +250,7 @@
<0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- its_dsa: interrupt-controller@c6000000 {
+ its_dsa: msi-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
@@ -250,6 +258,48 @@
};
};
+ eth2: ethernet-0 {
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth3: ethernet-1 {
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <1>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth0: ethernet-4 {
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <4>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth1: ethernet-5 {
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <5>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ refclk: refclk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
@@ -330,12 +380,11 @@
* when iommu-map entry is used along with the PCIe node.
* Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
*/
- smmu0: smmu_pcie {
+ smmu0: iommu@a0040000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xa0040000 0x0 0x20000>;
#iommu-cells = <1>;
dma-coherent;
- smmu-cb-memtype = <0x0 0x1>;
hisilicon,broken-prefetch-cmd;
status = "disabled";
};
@@ -359,7 +408,7 @@
status = "disabled";
};
- uart0: lpc-uart@2f8 {
+ uart0: serial@2f8 {
compatible = "ns16550a";
clock-frequency = <1843200>;
reg = <0x01 0x2f8 0x08>;
@@ -367,13 +416,7 @@
};
};
- refclk: refclk {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- #clock-cells = <0>;
- };
-
- usb_ohci: ohci@a7030000 {
+ usb_ohci: usb@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
@@ -382,7 +425,7 @@
status = "disabled";
};
- usb_ehci: ehci@a7020000 {
+ usb_ehci: usb@a7020000 {
compatible = "generic-ehci";
reg = <0x0 0xa7020000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
@@ -429,13 +472,13 @@
};
};
- dsaf0: dsa@c7000000 {
+ dsaf0: dsa@c5000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
- reg = <0x0 0xc5000000 0x0 0x890000
- 0x0 0xc7000000 0x0 0x600000>;
+ reg = <0x0 0xc5000000 0x0 0x890000>,
+ <0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;
@@ -538,7 +581,7 @@
port@1 {
reg = <1>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <1>;
port-mode-offset = <1>;
media-type = "fiber";
@@ -547,7 +590,7 @@
port@4 {
reg = <4>;
phy-handle = <&phy0>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
media-type = "copper";
@@ -556,49 +599,13 @@
port@5 {
reg = <5>;
phy-handle = <&phy1>;
- serdes-syscon= <&serdes_ctrl>;
+ serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
media-type = "copper";
};
};
- eth0: ethernet-4{
- compatible = "hisilicon,hns-nic-v2";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <4>;
- local-mac-address = [00 00 00 00 00 00];
- status = "disabled";
- dma-coherent;
- };
-
- eth1: ethernet-5{
- compatible = "hisilicon,hns-nic-v2";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <5>;
- local-mac-address = [00 00 00 00 00 00];
- status = "disabled";
- dma-coherent;
- };
-
- eth2: ethernet-0{
- compatible = "hisilicon,hns-nic-v2";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <0>;
- local-mac-address = [00 00 00 00 00 00];
- status = "disabled";
- dma-coherent;
- };
-
- eth3: ethernet-1{
- compatible = "hisilicon,hns-nic-v2";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <1>;
- local-mac-address = [00 00 00 00 00 00];
- status = "disabled";
- dma-coherent;
- };
-
sas0: sas@c3000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xc3000000 0 0x10000>;
@@ -726,7 +733,7 @@
status = "disabled";
};
- pcie0: pcie@a0090000 {
+ pcie0: pcie@b0000000 {
compatible = "hisilicon,hip06-pcie-ecam";
reg = <0 0xb0000000 0 0x2000000>,
<0 0xa0090000 0 0x10000>;
@@ -737,9 +744,8 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
- 0x5ff0000 0x01000000 0 0 0 0xb7ff0000
- 0 0x10000>;
+ ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
+ <0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
generated by cgit (git 2.34.1) at 2025-08-03 01:10:43 +0000