diff options
Diffstat (limited to 'arch/arm64/boot/dts/intel')
| -rw-r--r-- | arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 28 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 |
5 files changed, 30 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi index 781761d2942b..ae00e9e54e82 100644 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -70,7 +70,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 76aafa172eb0..1235ba5a9865 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -80,7 +80,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, @@ -101,10 +101,13 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x0 0xfffc1000 0x0 0x1000>, <0x0 0xfffc2000 0x0 0x2000>, <0x0 0xfffc4000 0x0 0x2000>, <0x0 0xfffc6000 0x0 0x2000>; + /* VGIC maintenance interrupt */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; clocks { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index d66d425e45b7..51c6e19e40b8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -202,7 +202,7 @@ status = "disabled"; }; - i3c0: i3c-master@10da0000 { + i3c0: i3c@10da0000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0x10da0000 0x1000>; #address-cells = <3>; @@ -212,7 +212,7 @@ status = "disabled"; }; - i3c1: i3c-master@10da1000 { + i3c1: i3c@10da1000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0x10da1000 0x1000>; #address-cells = <3>; @@ -222,6 +222,26 @@ status = "disabled"; }; + gpio0: gpio@ffc03200 { + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03200 0x100>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + gpio1: gpio@10c03300 { compatible = "snps,dw-apb-gpio"; reg = <0x10c03300 0x100>; @@ -314,7 +334,7 @@ reg-io-width = <4>; num-cs = <4>; clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; - dmas = <&dmac0 2>, <&dmac0 3>; + dmas = <&dmac0 16>, <&dmac0 17>; dma-names = "tx", "rx"; status = "disabled"; @@ -331,6 +351,8 @@ reg-io-width = <4>; num-cs = <4>; clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index ad99aefeb185..b31cfa6b802d 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -106,8 +106,6 @@ &qspi { status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 2d70a92c2090..7952c7f47cc2 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -83,8 +83,6 @@ &qspi { status = "okay"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <100000000>; |