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-rw-r--r--arch/arm64/boot/dts/marvell/Makefile1
-rw-r--r--arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts44
-rw-r--r--arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi34
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts14
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi20
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts20
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts99
-rw-r--r--arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts24
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts22
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap80x.dtsi1
-rw-r--r--arch/arm64/boot/dts/marvell/cn9130-crb.dtsi42
-rw-r--r--arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi96
-rw-r--r--arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi108
13 files changed, 405 insertions, 120 deletions
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 55b50261b712..090d2da6999e 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -27,4 +27,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
new file mode 100644
index 000000000000..2a0b07000089
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * Utilizing the CN913x COM Express CPU module board.
+ * This specific carrier board in this mode of operation (external)
+ * only maintains a PCIe link with the CPU module,
+ * which does not require any special DTS definitions.
+ *
+ * AC5X RD works here in external mode (switch selectable at the back of the
+ * board), and connect via an external cable a kit
+ * which would allow it to use an external CN9131 CPU COM Express module,
+ * mounted on top of an interposer kit.
+ *
+ * So in this case, once the switch is set to external mode as explained above,
+ * the AC5X RD becomes part of the carrier solution.
+ *
+ * When the board boots in the external CPU mode, the internal CPU is disabled,
+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
+ * is no need to describe this internal (disabled CPU) in the device tree.
+ *
+ * There is no CPU booting in this mode on the carrier, only on the
+ * CN9131 COM Express CPU module.
+ * What runs the Linux is the CN9131 on the COM Express CPU module,
+ * And it accesses the switch end-point on the AC5X RD portion of the carrier
+ * via PCIe.
+ */
+
+#include "cn9131-db-comexpress.dtsi"
+#include "ac5x-rd-carrier.dtsi"
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
+ compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier",
+ "marvell,cn9131-cpu-module", "marvell,cn9131",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x2 0x00000000>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
new file mode 100644
index 000000000000..f98629abb58b
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * This specific board in external mode (see below) only maintains
+ * a PCIe link with the COM Express CPU module, which does not
+ * require any special DTS definitions.
+ *
+ * AC5X RD can either work as you would expect, as a complete standalone
+ * box using the internal CPU, or you can move the switch on the back of
+ * the box to "external" mode, and connect via an external cable a kit
+ * which would allow it to use an external CPU COM Express module,
+ * mounted on top of an interposer kit.
+ *
+ * So in this case, once the switch is set to external mode as explained above,
+ * the AC5X RD becomes part of the carrier solution.
+ * This is a development/reference solution, not a full commercial solution,
+ * hence it was designed with the flexibility to be configured in different
+ * modes of operation.
+ *
+ * When the board boots in the external CPU mode, the internal CPU is disabled,
+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
+ * is no need to describe this internal (disabled CPU) in the device tree.
+ *
+ * There is no CPU booting in this mode on the carrier,
+ * only on the COM Express CPU module.
+ */
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
+ compatible = "marvell,rd-ac5x-carrier";
+
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
index f9abef8dcc94..870bb380a40a 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
@@ -126,32 +126,32 @@
reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
- ports {
- switch0port1: port@1 {
+ ethernet-ports {
+ switch0port1: ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy0>;
};
- switch0port2: port@2 {
+ switch0port2: ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- switch0port3: port@3 {
+ switch0port3: ethernet-port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
- switch0port4: port@4 {
+ switch0port4: ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- switch0port5: port@5 {
+ switch0port5: ethernet-port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
@@ -160,7 +160,7 @@
};
mdio {
- switch0phy3: switch0phy3@14 {
+ switch0phy3: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index 49cbdb55b4b3..fed2dcecb323 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -145,19 +145,17 @@
};
&mdio {
- switch0: switch0@1 {
+ switch0: ethernet-switch@1 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- switch0port0: port@0 {
+ switch0port0: ethernet-port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
@@ -168,19 +166,19 @@
};
};
- switch0port1: port@1 {
+ switch0port1: ethernet-port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
- switch0port2: port@2 {
+ switch0port2: ethernet-port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
- switch0port3: port@3 {
+ switch0port3: ethernet-port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
@@ -192,13 +190,13 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
index b1b45b4fa9d4..63fbc8352161 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
@@ -152,31 +152,29 @@
};
&mdio {
- switch0: switch0@1 {
+ switch0: ethernet-switch@1 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
- ports: ports {
+ ports: ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
@@ -185,7 +183,7 @@
nvmem-cell-names = "mac-address";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
@@ -199,13 +197,13 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
index 9eab2bb22134..f1a9f2234359 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -130,7 +130,7 @@
compatible = "microchip,mcp7940x";
reg = <0x6f>;
interrupt-parent = <&gpiosb>;
- interrupts = <5 0>; /* GPIO2_5 */
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */
};
};
@@ -304,9 +304,15 @@
reg = <1>;
};
- /* switch nodes are enabled by U-Boot if modules are present */
+ /*
+ * NOTE: switch nodes are enabled by U-Boot if modules are present
+ * DO NOT change this node name (switch0@10) even if it is not following
+ * conventions! Deployed U-Boot binaries are explicitly looking for
+ * this node in order to augment the device tree!
+ * Also do not touch the "ports" or "port@n" nodes. These are also ABI.
+ */
switch0@10 {
- compatible = "marvell,mv88e6190";
+ compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
reg = <0x10>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
@@ -317,35 +323,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -430,8 +436,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch0@2 {
- compatible = "marvell,mv88e6085";
+ compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
@@ -442,19 +449,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1_topaz: switch0phy1@11 {
+ switch0phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy2_topaz: switch0phy2@12 {
+ switch0phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy3_topaz: switch0phy3@13 {
+ switch0phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch0phy4_topaz: switch0phy4@14 {
+ switch0phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
@@ -497,8 +504,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch1@11 {
- compatible = "marvell,mv88e6190";
+ compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
reg = <0x11>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
@@ -509,35 +517,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1: switch1phy1@1 {
+ switch1phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch1phy2: switch1phy2@2 {
+ switch1phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch1phy3: switch1phy3@3 {
+ switch1phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch1phy4: switch1phy4@4 {
+ switch1phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch1phy5: switch1phy5@5 {
+ switch1phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch1phy6: switch1phy6@6 {
+ switch1phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch1phy7: switch1phy7@7 {
+ switch1phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch1phy8: switch1phy8@8 {
+ switch1phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -622,8 +630,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch1@2 {
- compatible = "marvell,mv88e6085";
+ compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
@@ -634,19 +643,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1_topaz: switch1phy1@11 {
+ switch1phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch1phy2_topaz: switch1phy2@12 {
+ switch1phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch1phy3_topaz: switch1phy3@13 {
+ switch1phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch1phy4_topaz: switch1phy4@14 {
+ switch1phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
@@ -689,8 +698,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch2@12 {
- compatible = "marvell,mv88e6190";
+ compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
reg = <0x12>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
@@ -701,35 +711,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1: switch2phy1@1 {
+ switch2phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch2phy2: switch2phy2@2 {
+ switch2phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch2phy3: switch2phy3@3 {
+ switch2phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch2phy4: switch2phy4@4 {
+ switch2phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch2phy5: switch2phy5@5 {
+ switch2phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch2phy6: switch2phy6@6 {
+ switch2phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch2phy7: switch2phy7@7 {
+ switch2phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch2phy8: switch2phy8@8 {
+ switch2phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -805,8 +815,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch2@2 {
- compatible = "marvell,mv88e6085";
+ compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
@@ -817,19 +828,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1_topaz: switch2phy1@11 {
+ switch2phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch2phy2_topaz: switch2phy2@12 {
+ switch2phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch2phy3_topaz: switch2phy3@13 {
+ switch2phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch2phy4_topaz: switch2phy4@14 {
+ switch2phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
index 48202810bf78..40b7ee7ead72 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
@@ -301,10 +301,8 @@
};
/* 88E6141 Topaz switch */
- switch: switch@3 {
+ switch: ethernet-switch@3 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
@@ -314,35 +312,35 @@
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- swport1: port@1 {
+ swport1: ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
- swport2: port@2 {
+ swport2: ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
- swport3: port@3 {
+ swport3: ethernet-port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
- swport4: port@4 {
+ swport4: ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
@@ -355,19 +353,19 @@
#address-cells = <1>;
#size-cells = <0>;
- swphy1: swphy1@17 {
+ swphy1: ethernet-phy@17 {
reg = <17>;
};
- swphy2: swphy2@18 {
+ swphy2: ethernet-phy@18 {
reg = <18>;
};
- swphy3: swphy3@19 {
+ swphy3: ethernet-phy@19 {
reg = <19>;
};
- swphy4: swphy4@20 {
+ swphy4: ethernet-phy@20 {
reg = <20>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 4125202028c8..67892f0d2863 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -497,42 +497,42 @@
reset-deassert-us = <10000>;
};
- switch0: switch0@4 {
+ switch0: ethernet-switch@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_switch_reset_pins>;
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
@@ -545,19 +545,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
- switch0phy3: switch0phy3@14 {
+ switch0phy3: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 2c920e22cec2..7ec7c789d87e 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -138,7 +138,6 @@
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
- interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index 47d45ff3d6f5..6fcc34f7b464 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -207,11 +207,9 @@
reg = <0>;
};
- switch6: switch0@6 {
+ switch6: ethernet-switch@6 {
/* Actual device is MV88E6393X */
compatible = "marvell,mv88e6190";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <6>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
@@ -220,59 +218,59 @@
dsa,member = <0 0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "p1";
phy-handle = <&switch0phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "p2";
phy-handle = <&switch0phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "p3";
phy-handle = <&switch0phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "p4";
phy-handle = <&switch0phy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "p5";
phy-handle = <&switch0phy5>;
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "p6";
phy-handle = <&switch0phy6>;
};
- port@7 {
+ ethernet-port@7 {
reg = <7>;
label = "p7";
phy-handle = <&switch0phy7>;
};
- port@8 {
+ ethernet-port@8 {
reg = <8>;
label = "p8";
phy-handle = <&switch0phy8>;
};
- port@9 {
+ ethernet-port@9 {
reg = <9>;
label = "p9";
phy-mode = "10gbase-r";
@@ -280,7 +278,7 @@
managed = "in-band-status";
};
- port@a {
+ ethernet-port@a {
reg = <10>;
ethernet = <&cp0_eth0>;
phy-mode = "10gbase-r";
@@ -293,35 +291,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
new file mode 100644
index 000000000000..028496ebc473
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB Com Express CPU module board.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
new file mode 100644
index 000000000000..6f3914bcfd01
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB Com Express CPU module board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp1_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
generated by cgit (git 2.34.1) at 2024-05-27 13:14:48 +0000