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Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8192.dtsi')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8192.dtsi107
1 files changed, 86 insertions, 21 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 424fc89cc6f7..87b91c8feaf9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -29,6 +29,15 @@
rdma4 = &rdma4;
};
+ clk13m: fixed-factor-clock-13m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "clk13m";
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -53,7 +62,13 @@
reg = <0x000>;
enable-method = "psci";
clock-frequency = <1701000000>;
- cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -64,7 +79,13 @@
reg = <0x100>;
enable-method = "psci";
clock-frequency = <1701000000>;
- cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -75,7 +96,13 @@
reg = <0x200>;
enable-method = "psci";
clock-frequency = <1701000000>;
- cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -86,7 +113,13 @@
reg = <0x300>;
enable-method = "psci";
clock-frequency = <1701000000>;
- cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -97,7 +130,13 @@
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2171000000>;
- cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -108,7 +147,13 @@
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2171000000>;
- cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -119,7 +164,13 @@
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2171000000>;
- cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -130,7 +181,13 @@
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2171000000>;
- cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -149,19 +206,16 @@
core3 {
cpu = <&cpu3>;
};
- };
-
- cluster1 {
- core0 {
+ core4 {
cpu = <&cpu4>;
};
- core1 {
+ core5 {
cpu = <&cpu5>;
};
- core2 {
+ core6 {
cpu = <&cpu6>;
};
- core3 {
+ core7 {
cpu = <&cpu7>;
};
};
@@ -170,23 +224,33 @@
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
idle-states {
entry-method = "psci";
- cpu_sleep_l: cpu-sleep-l {
+ cpu_ret_l: cpu-retention-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
@@ -194,7 +258,7 @@
exit-latency-us = <140>;
min-residency-us = <780>;
};
- cpu_sleep_b: cpu-sleep-b {
+ cpu_ret_b: cpu-retention-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
@@ -202,7 +266,7 @@
exit-latency-us = <145>;
min-residency-us = <720>;
};
- cluster_sleep_l: cluster-sleep-l {
+ cpu_off_l: cpu-off-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
@@ -210,7 +274,7 @@
exit-latency-us = <155>;
min-residency-us = <860>;
};
- cluster_sleep_b: cluster-sleep-b {
+ cpu_off_b: cpu-off-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
@@ -534,8 +598,7 @@
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
- clock-names = "clk13m";
+ clocks = <&clk13m>;
};
pwrap: pwrap@10026000 {
@@ -578,6 +641,8 @@
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
#clock-cells = <1>;
+ /* power domain dependency not upstreamed */
+ status = "fail";
};
uart0: serial@11002000 {
generated by cgit (git 2.34.1) at 2024-06-14 04:48:11 +0000