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Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8939.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8939.dtsi139
1 files changed, 69 insertions, 70 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
index 82d85ff61045..7cd5660de1b3 100644
--- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -34,7 +34,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <32768>;
+ clock-frequency = <32764>;
};
};
@@ -42,122 +42,122 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@100 {
+ cpu0: cpu@100 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x100>;
- next-level-cache = <&L2_1>;
+ next-level-cache = <&l2_1>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
- L2_1: l2-cache {
+ l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
- CPU1: cpu@101 {
+ cpu1: cpu@101 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x101>;
- next-level-cache = <&L2_1>;
+ next-level-cache = <&l2_1>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
};
- CPU2: cpu@102 {
+ cpu2: cpu@102 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x102>;
- next-level-cache = <&L2_1>;
+ next-level-cache = <&l2_1>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
};
- CPU3: cpu@103 {
+ cpu3: cpu@103 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x103>;
- next-level-cache = <&L2_1>;
+ next-level-cache = <&l2_1>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs1_mbox>;
#cooling-cells = <2>;
};
- CPU4: cpu@0 {
+ cpu4: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x0>;
qcom,acc = <&acc4>;
qcom,saw = <&saw4>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
- next-level-cache = <&L2_0>;
- L2_0: l2-cache {
+ next-level-cache = <&l2_0>;
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
- CPU5: cpu@1 {
+ cpu5: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
qcom,acc = <&acc5>;
qcom,saw = <&saw5>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
};
- CPU6: cpu@2 {
+ cpu6: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
qcom,acc = <&acc6>;
qcom,saw = <&saw6>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
};
- CPU7: cpu@3 {
+ cpu7: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
qcom,acc = <&acc7>;
qcom,saw = <&saw7>;
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
clocks = <&apcs0_mbox>;
#cooling-cells = <2>;
};
idle-states {
- CPU_SLEEP_0: cpu-sleep-0 {
+ cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
entry-latency-us = <130>;
exit-latency-us = <150>;
@@ -182,19 +182,19 @@
/* LITTLE (efficiency) cluster */
cluster0 {
core0 {
- cpu = <&CPU4>;
+ cpu = <&cpu4>;
};
core1 {
- cpu = <&CPU5>;
+ cpu = <&cpu5>;
};
core2 {
- cpu = <&CPU6>;
+ cpu = <&cpu6>;
};
core3 {
- cpu = <&CPU7>;
+ cpu = <&cpu7>;
};
};
@@ -202,19 +202,19 @@
/* Boot CPU is cluster 1 core 0 */
cluster1 {
core0 {
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
core1 {
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
core2 {
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
core3 {
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
};
};
@@ -252,7 +252,7 @@
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8936";
+ compatible = "qcom,rpm-msm8936", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
@@ -443,8 +443,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs1_mbox 8 13>;
- qcom,ipc-3 = <&apcs1_mbox 8 19>;
+ mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -1427,6 +1426,8 @@
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ #cooling-cells = <2>;
+
status = "disabled";
opp_table: opp-table {
@@ -2065,7 +2066,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs1_mbox 8 17>;
+ mboxes = <&apcs1_mbox 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
@@ -2297,7 +2298,6 @@
thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -2318,17 +2318,16 @@
cooling-maps {
map0 {
trip = <&cpu0_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@@ -2349,17 +2348,16 @@
cooling-maps {
map0 {
trip = <&cpu1_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@@ -2380,17 +2378,16 @@
cooling-maps {
map0 {
trip = <&cpu2_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@@ -2411,17 +2408,16 @@
cooling-maps {
map0 {
trip = <&cpu3_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4567-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
@@ -2442,20 +2438,26 @@
cooling-maps {
map0 {
trip = <&cpu4567_alert>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
gpu_alert0: trip-point0 {
temperature = <75000>;
@@ -2463,7 +2465,7 @@
type = "passive";
};
- gpu_crit: gpu_crit {
+ gpu_crit: gpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -2473,7 +2475,6 @@
modem1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
@@ -2488,7 +2489,6 @@
modem2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
@@ -2503,7 +2503,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
generated by cgit (git 2.34.1) at 2025-07-24 06:10:24 +0000