diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sa8775p.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sa8775p.dtsi | 3273 |
1 files changed, 3133 insertions, 140 deletions
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a7eaca33d326..3394ae2d1300 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1,15 +1,20 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -35,19 +40,23 @@ #address-cells = <2>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; - L3_0: l3-cache { + next-level-cache = <&l3_0>; + l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; @@ -55,64 +64,80 @@ }; }; - CPU1: cpu@100 { + cpu1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_1: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU2: cpu@200 { + cpu2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - next-level-cache = <&L2_2>; - L2_2: l2-cache { + next-level-cache = <&l2_2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU3: cpu@300 { + cpu3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - next-level-cache = <&L2_3>; - L2_3: l2-cache { + next-level-cache = <&l2_3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_3: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU4: cpu@10000 { + cpu4: cpu@10000 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10000>; enable-method = "psci"; + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - next-level-cache = <&L2_4>; - L2_4: l2-cache { + next-level-cache = <&l2_4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_4: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_1>; - L3_1: l3-cache { + next-level-cache = <&l3_1>; + l3_1: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; @@ -121,85 +146,152 @@ }; }; - CPU5: cpu@10100 { + cpu5: cpu@10100 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10100>; enable-method = "psci"; + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - next-level-cache = <&L2_5>; - L2_5: l2-cache { + next-level-cache = <&l2_5>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_5: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_1>; + next-level-cache = <&l3_1>; }; }; - CPU6: cpu@10200 { + cpu6: cpu@10200 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10200>; enable-method = "psci"; + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - next-level-cache = <&L2_6>; - L2_6: l2-cache { + next-level-cache = <&l2_6>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_6: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_1>; + next-level-cache = <&l3_1>; }; }; - CPU7: cpu@10300 { + cpu7: cpu@10300 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10300>; enable-method = "psci"; + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - next-level-cache = <&L2_7>; - L2_7: l2-cache { + next-level-cache = <&l2_7>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + l2_7: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_1>; + next-level-cache = <&l3_1>; }; }; cpu-map { cluster0 { core0 { - cpu = <&CPU0>; + cpu = <&cpu0>; }; core1 { - cpu = <&CPU1>; + cpu = <&cpu1>; }; core2 { - cpu = <&CPU2>; + cpu = <&cpu2>; }; core3 { - cpu = <&CPU3>; + cpu = <&cpu3>; }; }; cluster1 { core0 { - cpu = <&CPU4>; + cpu = <&cpu4>; }; core1 { - cpu = <&CPU5>; + cpu = <&cpu5>; }; core2 { - cpu = <&CPU6>; + cpu = <&cpu6>; }; core3 { - cpu = <&CPU7>; + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + gold_cpu_sleep_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + gold_rail_cpu_sleep_0: cpu-sleep-1 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_gold: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + cluster_sleep_apss_rsc_pc: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x42000144>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + }; + + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = + <&swao_rep_out1>; }; }; }; @@ -208,6 +300,8 @@ firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + memory-region = <&tz_ffi_mem>; }; }; @@ -318,6 +412,79 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_0_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_0_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_0_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_0_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_1_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_1_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_1_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_1_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; + }; + + cluster_0_pd: power-domain-cluster0 { + #power-domain-cells = <0>; + power-domains = <&cluster_2_pd>; + domain-idle-states = <&cluster_sleep_gold>; + }; + + cluster_1_pd: power-domain-cluster1 { + #power-domain-cells = <0>; + power-domains = <&cluster_2_pd>; + domain-idle-states = <&cluster_sleep_gold>; + }; + + cluster_2_pd: power-domain-cluster2 { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_apss_rsc_pc>; + }; }; reserved-memory { @@ -356,13 +523,18 @@ no-map; }; + ddr_training_checksum: ddr-training-checksum@908c0000 { + reg = <0x0 0x908c0000 0x0 0x1000>; + no-map; + }; + reserved_mem: reserved@908f0000 { - reg = <0x0 0x908f0000 0x0 0xf000>; + reg = <0x0 0x908f0000 0x0 0xe000>; no-map; }; - secdata_apss_mem: secdata-apss@908ff000 { - reg = <0x0 0x908ff000 0x0 0x1000>; + secdata_apss_mem: secdata-apss@908fe000 { + reg = <0x0 0x908fe000 0x0 0x2000>; no-map; }; @@ -373,8 +545,49 @@ hwlocks = <&tcsr_mutex 3>; }; - cpucp_fw_mem: cpucp-fw@90b00000 { - reg = <0x0 0x90b00000 0x0 0x100000>; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + + aoss_backup_mem: aoss-backup@91b00000 { + reg = <0x0 0x91b00000 0x0 0x40000>; + no-map; + }; + + cpucp_backup_mem: cpucp-backup@91b40000 { + reg = <0x0 0x91b40000 0x0 0x40000>; + no-map; + }; + + tz_config_backup_mem: tz-config-backup@91b80000 { + reg = <0x0 0x91b80000 0x0 0x10000>; + no-map; + }; + + ddr_training_data_mem: ddr-training-data@91b90000 { + reg = <0x0 0x91b90000 0x0 0x10000>; + no-map; + }; + + cdt_data_backup_mem: cdt-data-backup@91ba0000 { + reg = <0x0 0x91ba0000 0x0 0x1000>; + no-map; + }; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x91c00000 0x0 0x1400000>; no-map; }; @@ -433,13 +646,43 @@ no-map; }; + audio_mdf_mem: audio-mdf-region@ae000000 { + reg = <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg = <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + hyptz_reserved_mem: hyptz-reserved@beb00000 { reg = <0x0 0xbeb00000 0x0 0x11500000>; no-map; }; - tz_stat_mem: tz-stat@d0000000 { - reg = <0x0 0xd0000000 0x0 0x100000>; + scmi_mem: scmi-region@d0000000 { + reg = <0x0 0xd0000000 0x0 0x40000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg = <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg = <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_reserved_mem: firmware-reserved@d0054000 { + reg = <0x0 0xd0054000 0x0 0x9c000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg = <0x0 0xd00f0000 0x0 0x10000>; no-map; }; @@ -453,10 +696,140 @@ no-map; }; - trusted_apps_mem: trusted-apps@d1800000 { - reg = <0x0 0xd1800000 0x0 0x3900000>; + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg = <0x0 0xd1800000 0x0 0x100000>; no-map; }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg = <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg = <0x0 0xdb200000 0x0 0x100000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp0 { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp0_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp0_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp1 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <12>; + + smp2p_cdsp1_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp1_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-gpdsp0 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <17>; + + smp2p_gpdsp0_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_gpdsp0_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-gpdsp1 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <18>; + + smp2p_gpdsp1_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_gpdsp1_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; soc: soc@0 { @@ -498,6 +871,28 @@ #mbox-cells = <2>; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0xfff>; + iommus = <&apps_smmu 0x5b6 0x0>; + status = "disabled"; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -528,6 +923,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -549,6 +948,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart14: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -570,6 +988,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -591,6 +1013,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart15: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -612,6 +1053,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -631,11 +1076,30 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + uart16: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c17: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x88c000 0x0 0x4000>; @@ -654,6 +1118,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -675,6 +1143,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -709,6 +1181,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -732,6 +1208,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -753,6 +1248,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -774,6 +1273,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart19: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -795,6 +1313,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -816,8 +1338,50 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart20: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00900000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0xfff>; + iommus = <&apps_smmu 0x416 0x0>; + status = "disabled"; }; qupv3_id_0: geniqup@9c0000 { @@ -850,6 +1414,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -871,6 +1439,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -892,6 +1479,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -913,6 +1504,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart1: serial@984000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x984000 0x0 0x4000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -934,6 +1544,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -955,6 +1569,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x988000 0x0 0x4000>; + interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -976,6 +1609,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -997,6 +1634,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart3: serial@98c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x98c000 0x0 0x4000>; + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -1018,6 +1674,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1039,6 +1699,25 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x990000 0x0 0x4000>; + interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; @@ -1060,6 +1739,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1081,6 +1764,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1100,6 +1787,28 @@ }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x456 0x0>; + dma-channels = <12>; + dma-channel-mask = <0xfff>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -1130,6 +1839,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1151,6 +1864,26 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart7: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1172,6 +1905,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1193,6 +1930,26 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart8: serial@a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1214,6 +1971,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1235,6 +1996,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1271,6 +2036,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1292,6 +2061,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1329,6 +2102,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1350,6 +2127,26 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart11: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1371,6 +2168,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1392,6 +2193,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1428,10 +2233,29 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; + }; }; + gpi_dma3: dma-controller@b00000 { + compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00b00000 0x0 0x58000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x056 0x0>; + dma-channels = <4>; + dma-channel-mask = <0xf>; + status = "disabled"; + }; + qupv3_id_3: geniqup@bc0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0xbc0000 0x0 0x6000>; @@ -1462,6 +2286,10 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; status = "disabled"; }; @@ -1483,6 +2311,26 @@ "qup-config", "qup-memory"; power-domains = <&rpmhpd SA8775P_CX>; + dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, + <&gpi_dma3 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart21: serial@b80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; }; @@ -1492,7 +2340,7 @@ reg = <0 0x010d2000 0 0x1000>; }; - ufs_mem_hc: ufs@1d84000 { + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; @@ -1555,10 +2403,946 @@ ice: crypto@1d88000 { compatible = "qcom,sa8775p-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0x0 0x01d88000 0x0 0x8000>; + reg = <0x0 0x01d88000 0x0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x480 0x00>, + <&apps_smmu 0x481 0x00>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sa8775p-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x00>, + <&apps_smmu 0x481 0x00>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + + stm: stm@4002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x4002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + tpdm@4003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4003000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + status = "disabled"; + + out-ports { + port { + qdss_tpdm0_out: endpoint { + remote-endpoint = + <&qdss_tpda_in0>; + }; + }; + }; + }; + + tpda@4004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = + <&funnel0_in6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_tpda_in0: endpoint { + remote-endpoint = + <&qdss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + qdss_tpda_in1: endpoint { + remote-endpoint = + <&qdss_tpdm1_out>; + }; + }; + }; + }; + + tpdm@400f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x400f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qdss_tpdm1_out: endpoint { + remote-endpoint = + <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@4041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&qdss_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel0_in6: endpoint { + remote-endpoint = + <&qdss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + }; + + funnel@4042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4042000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&qdss_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + }; + + funnel@4045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4045000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_funnel_out: endpoint { + remote-endpoint = + <&aoss_funnel_in7>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + qdss_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + }; + + funnel@4b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = + <&etf0_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + aoss_funnel_in6: endpoint { + remote-endpoint = + <&aoss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + aoss_funnel_in7: endpoint { + remote-endpoint = + <&qdss_funnel_out>; + }; + }; + }; + }; + + tmc_etf: tmc@4b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = + <&swao_rep_in>; + }; + }; + }; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = + <&aoss_funnel_out>; + }; + }; + }; + }; + + replicator@4b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4b06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + swao_rep_out1: endpoint { + remote-endpoint = + <&eud_in>; + }; + }; + }; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = + <&etf0_out>; + }; + }; + }; + }; + + tpda@4b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = + <&aoss_funnel_in6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aoss_tpda_in0: endpoint { + remote-endpoint = + <&aoss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + aoss_tpda_in1: endpoint { + remote-endpoint = + <&aoss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + aoss_tpda_in2: endpoint { + remote-endpoint = + <&aoss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + aoss_tpda_in3: endpoint { + remote-endpoint = + <&aoss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + aoss_tpda_in4: endpoint { + remote-endpoint = + <&aoss_tpdm4_out>; + }; + }; + }; + }; + + tpdm@4b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm0_out: endpoint { + remote-endpoint = + <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@4b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm1_out: endpoint { + remote-endpoint = + <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@4b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm2_out: endpoint { + remote-endpoint = + <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@4b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm3_out: endpoint { + remote-endpoint = + <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@4b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm4_out: endpoint { + remote-endpoint = + <&aoss_tpda_in4>; + }; + }; + }; + }; + + aoss_cti: cti@4b13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x4b13000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + etm@6040000 { + compatible = "arm,primecell"; + reg = <0x0 0x6040000 0x0 0x1000>; + cpu = <&cpu0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + etm@6140000 { + compatible = "arm,primecell"; + reg = <0x0 0x6140000 0x0 0x1000>; + cpu = <&cpu1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + etm@6240000 { + compatible = "arm,primecell"; + reg = <0x0 0x6240000 0x0 0x1000>; + cpu = <&cpu2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel0_in2>; + }; + }; + }; + }; + + etm@6340000 { + compatible = "arm,primecell"; + reg = <0x0 0x6340000 0x0 0x1000>; + cpu = <&cpu3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel0_in3>; + }; + }; + }; + }; + + etm@6440000 { + compatible = "arm,primecell"; + reg = <0x0 0x6440000 0x0 0x1000>; + cpu = <&cpu4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel0_in4>; + }; + }; + }; + }; + + etm@6540000 { + compatible = "arm,primecell"; + reg = <0x0 0x6540000 0x0 0x1000>; + cpu = <&cpu5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel0_in5>; + }; + }; + }; + }; + + etm@6640000 { + compatible = "arm,primecell"; + reg = <0x0 0x6640000 0x0 0x1000>; + cpu = <&cpu6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel0_in6>; + }; + }; + }; + }; + + etm@6740000 { + compatible = "arm,primecell"; + reg = <0x0 0x6740000 0x0 0x1000>; + cpu = <&cpu7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel0_in7>; + }; + }; + }; + }; + + funnel@6800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x6800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel0_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel0_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel0_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel0_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel0_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel0_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@6810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x6810000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&funnel1_in4>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel1_in3: endpoint { + remote-endpoint = + <&apss_tpda_out>; + }; + }; + }; + }; + + tpdm@6860000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x6860000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm3_out: endpoint { + remote-endpoint = + <&apss_tpda_in3>; + }; + }; + }; + }; + + tpdm@6861000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x6861000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm4_out: endpoint { + remote-endpoint = + <&apss_tpda_in4>; + }; + }; + }; + }; + + tpda@6863000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x6863000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_tpda_out: endpoint { + remote-endpoint = + <&apss_funnel1_in3>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_tpda_in0: endpoint { + remote-endpoint = + <&apss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_tpda_in1: endpoint { + remote-endpoint = + <&apss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_tpda_in2: endpoint { + remote-endpoint = + <&apss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_tpda_in3: endpoint { + remote-endpoint = + <&apss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_tpda_in4: endpoint { + remote-endpoint = + <&apss_tpdm4_out>; + }; + }; + }; + }; + + tpdm@68a0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm0_out: endpoint { + remote-endpoint = + <&apss_tpda_in0>; + }; + }; + }; + }; + + tpdm@68b0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm1_out: endpoint { + remote-endpoint = + <&apss_tpda_in1>; + }; + }; + }; + }; + + tpdm@68c0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm2_out: endpoint { + remote-endpoint = + <&apss_tpda_in2>; + }; + }; + }; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -1615,10 +3399,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1643,6 +3429,8 @@ iommus = <&apps_smmu 0x080 0x0>; phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; }; @@ -1702,10 +3490,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 7 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1730,6 +3520,8 @@ iommus = <&apps_smmu 0x0a0 0x0>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; }; @@ -1765,9 +3557,11 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -1791,6 +3585,8 @@ iommus = <&apps_smmu 0x020 0x0>; phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; }; }; @@ -1800,6 +3596,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sa8775p-tcsr", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sa8775p-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>; @@ -1868,6 +3669,467 @@ status = "disabled"; }; + pmu@9091000 { + compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x9091000 0x0 0x1000>; + interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <762000>; + }; + + opp-1 { + opp-peak-kBps = <1720000>; + }; + + opp-2 { + opp-peak-kBps = <2086000>; + }; + + opp-3 { + opp-peak-kBps = <2601000>; + }; + + opp-4 { + opp-peak-kBps = <2929000>; + }; + + opp-5 { + opp-peak-kBps = <5931000>; + }; + + opp-6 { + opp-peak-kBps = <6515000>; + }; + + opp-7 { + opp-peak-kBps = <7984000>; + }; + + opp-8 { + opp-peak-kBps = <10437000>; + }; + + opp-9 { + opp-peak-kBps = <12195000>; + }; + }; + }; + + pmu@90b5400 { + compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x90b5400 0x0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <9155000>; + }; + + opp-1 { + opp-peak-kBps = <12298000>; + }; + + opp-2 { + opp-peak-kBps = <14236000>; + }; + + opp-3 { + opp-peak-kBps = <16265000>; + }; + }; + + }; + + pmu@90b6400 { + compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x90b6400 0x0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + llcc: system-cache-controller@9200000 { + compatible = "qcom,sa8775p-llcc"; + reg = <0x0 0x09200000 0x0 0x80000>, + <0x0 0x09300000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x80000>, + <0x0 0x09500000 0x0 0x80000>, + <0x0 0x09600000 0x0 0x80000>, + <0x0 0x09700000 0x0 0x80000>, + <0x0 0x09a00000 0x0 0x80000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc_broadcast_base"; + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + }; + + videocc: clock-controller@abf0000 { + compatible = "qcom,sa8775p-videocc"; + reg = <0x0 0x0abf0000 0x0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sa8775p-camcc"; + reg = <0x0 0x0ade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + mdss0: display-subsystem@ae00000 { + compatible = "qcom,sa8775p-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + /* same path used twice */ + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible = "qcom,sa8775p-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf4_out: endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + }; + + mdss0_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss0_dp0_phy: phy@aec2a00 { + compatible = "qcom,sa8775p-edp-phy"; + + reg = <0x0 0x0aec2a00 0x0 0x200>, + <0x0 0x0aec2200 0x0 0xd0>, + <0x0 0x0aec2600 0x0 0xd0>, + <0x0 0x0aec2000 0x0 0x1c8>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss0_dp1_phy: phy@aec5a00 { + compatible = "qcom,sa8775p-edp-phy"; + + reg = <0x0 0x0aec5a00 0x0 0x200>, + <0x0 0x0aec5200 0x0 0xd0>, + <0x0 0x0aec5600 0x0 0xd0>, + <0x0 0x0aec5000 0x0 0x1c8>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss0_dp0: displayport-controller@af54000 { + compatible = "qcom,sa8775p-dp"; + + reg = <0x0 0x0af54000 0x0 0x104>, + <0x0 0x0af54200 0x0 0x0c0>, + <0x0 0x0af55000 0x0 0x770>, + <0x0 0x0af56000 0x0 0x09c>, + <0x0 0x0af57000 0x0 0x09c>; + + interrupt-parent = <&mdss0>; + interrupts = <12>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + phys = <&mdss0_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss0_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss0_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp1: displayport-controller@af5c000 { + compatible = "qcom,sa8775p-dp"; + + reg = <0x0 0x0af5c000 0x0 0x104>, + <0x0 0x0af5c200 0x0 0x0c0>, + <0x0 0x0af5d000 0x0 0x770>, + <0x0 0x0af5e000 0x0 0x09c>, + <0x0 0x0af5f000 0x0 0x09c>; + + interrupt-parent = <&mdss0>; + interrupts = <13>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; + phys = <&mdss0_dp1_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp1_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss0_dp1_in: endpoint { + remote-endpoint = <&dpu_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss0_dp1_out: endpoint { }; + }; + }; + + dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,sa8775p-dispcc0"; + reg = <0x0 0x0af00000 0x0 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, + <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, + <0>, <0>, <0>, <0>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, @@ -2008,11 +4270,26 @@ wakeup-parent = <&pdc>; }; + sram: sram@146d8000 { + compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; + reg = <0x0 0x146d8000 0x0 0x1000>; + ranges = <0x0 0x0 0x146d8000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; + dma-coherent; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, @@ -2151,6 +4428,7 @@ reg = <0x0 0x15200000 0x0 0x80000>; #iommu-cells = <2>; #global-interrupts = <2>; + dma-coherent; interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, @@ -2388,14 +4666,117 @@ #freq-domain-cells = <1>; }; + remoteproc_gpdsp0: remoteproc@20c00000 { + compatible = "qcom,sa8775p-gpdsp0-pas"; + reg = <0x0 0x20c00000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, + <&smp2p_gpdsp0_in 0 0>, + <&smp2p_gpdsp0_in 2 0>, + <&smp2p_gpdsp0_in 1 0>, + <&smp2p_gpdsp0_in 3 0>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "cx", "mxc"; + + interconnects = <&gpdsp_anoc MASTER_DSP0 0 + &config_noc SLAVE_CLK_CTL 0>; + + memory-region = <&pil_gdsp0_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_gpdsp0_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "gpdsp0"; + qcom,remote-pid = <17>; + }; + }; + + remoteproc_gpdsp1: remoteproc@21c00000 { + compatible = "qcom,sa8775p-gpdsp1-pas"; + reg = <0x0 0x21c00000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, + <&smp2p_gpdsp1_in 0 0>, + <&smp2p_gpdsp1_in 2 0>, + <&smp2p_gpdsp1_in 1 0>, + <&smp2p_gpdsp1_in 3 0>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "cx", "mxc"; + + interconnects = <&gpdsp_anoc MASTER_DSP1 0 + &config_noc SLAVE_CLK_CTL 0>; + + memory-region = <&pil_gdsp1_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_gpdsp1_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_GPDSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "gpdsp1"; + qcom,remote-pid = <18>; + }; + }; + + dispcc1: clock-controller@22100000 { + compatible = "qcom,sa8775p-dispcc1"; + reg = <0x0 0x22100000 0x0 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + ethernet1: ethernet@23000000 { compatible = "qcom,sa8775p-ethqos"; reg = <0x0 0x23000000 0x0 0x10000>, <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, @@ -2406,12 +4787,19 @@ "ptp_ref", "phyaux"; + interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "mac-mem", "cpu-mac"; + power-domains = <&gcc EMAC1_GDSC>; phys = <&serdes1>; phy-names = "serdes"; iommus = <&apps_smmu 0x140 0xf>; + dma-coherent; snps,tso; snps,pbl = <32>; @@ -2427,8 +4815,9 @@ <0x0 0x23056000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, @@ -2439,12 +4828,19 @@ "ptp_ref", "phyaux"; + interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "mac-mem", "cpu-mac"; + power-domains = <&gcc EMAC0_GDSC>; phys = <&serdes0>; phy-names = "serdes"; iommus = <&apps_smmu 0x120 0xf>; + dma-coherent; snps,tso; snps,pbl = <32>; @@ -2453,13 +4849,573 @@ status = "disabled"; }; + + remoteproc_cdsp0: remoteproc@26300000 { + compatible = "qcom,sa8775p-cdsp0-pas"; + reg = <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP0>; + power-domain-names = "cx", "mxc", "nsp"; + + interconnects = <&nspa_noc MASTER_CDSP_PROC 0 + &mc_virt SLAVE_EBI1 0>; + + memory-region = <&pil_cdsp0_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp0_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x2141 0x04a0>, + <&apps_smmu 0x2161 0x04a0>, + <&apps_smmu 0x2181 0x0400>, + <&apps_smmu 0x21c1 0x04a0>, + <&apps_smmu 0x21e1 0x04a0>, + <&apps_smmu 0x2541 0x04a0>, + <&apps_smmu 0x2561 0x04a0>, + <&apps_smmu 0x2581 0x0400>, + <&apps_smmu 0x25c1 0x04a0>, + <&apps_smmu 0x25e1 0x04a0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x2142 0x04a0>, + <&apps_smmu 0x2162 0x04a0>, + <&apps_smmu 0x2182 0x0400>, + <&apps_smmu 0x21c2 0x04a0>, + <&apps_smmu 0x21e2 0x04a0>, + <&apps_smmu 0x2542 0x04a0>, + <&apps_smmu 0x2562 0x04a0>, + <&apps_smmu 0x2582 0x0400>, + <&apps_smmu 0x25c2 0x04a0>, + <&apps_smmu 0x25e2 0x04a0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x2143 0x04a0>, + <&apps_smmu 0x2163 0x04a0>, + <&apps_smmu 0x2183 0x0400>, + <&apps_smmu 0x21c3 0x04a0>, + <&apps_smmu 0x21e3 0x04a0>, + <&apps_smmu 0x2543 0x04a0>, + <&apps_smmu 0x2563 0x04a0>, + <&apps_smmu 0x2583 0x0400>, + <&apps_smmu 0x25c3 0x04a0>, + <&apps_smmu 0x25e3 0x04a0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x2144 0x04a0>, + <&apps_smmu 0x2164 0x04a0>, + <&apps_smmu 0x2184 0x0400>, + <&apps_smmu 0x21c4 0x04a0>, + <&apps_smmu 0x21e4 0x04a0>, + <&apps_smmu 0x2544 0x04a0>, + <&apps_smmu 0x2564 0x04a0>, + <&apps_smmu 0x2584 0x0400>, + <&apps_smmu 0x25c4 0x04a0>, + <&apps_smmu 0x25e4 0x04a0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x2145 0x04a0>, + <&apps_smmu 0x2165 0x04a0>, + <&apps_smmu 0x2185 0x0400>, + <&apps_smmu 0x21c5 0x04a0>, + <&apps_smmu 0x21e5 0x04a0>, + <&apps_smmu 0x2545 0x04a0>, + <&apps_smmu 0x2565 0x04a0>, + <&apps_smmu 0x2585 0x0400>, + <&apps_smmu 0x25c5 0x04a0>, + <&apps_smmu 0x25e5 0x04a0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x2146 0x04a0>, + <&apps_smmu 0x2166 0x04a0>, + <&apps_smmu 0x2186 0x0400>, + <&apps_smmu 0x21c6 0x04a0>, + <&apps_smmu 0x21e6 0x04a0>, + <&apps_smmu 0x2546 0x04a0>, + <&apps_smmu 0x2566 0x04a0>, + <&apps_smmu 0x2586 0x0400>, + <&apps_smmu 0x25c6 0x04a0>, + <&apps_smmu 0x25e6 0x04a0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x2147 0x04a0>, + <&apps_smmu 0x2167 0x04a0>, + <&apps_smmu 0x2187 0x0400>, + <&apps_smmu 0x21c7 0x04a0>, + <&apps_smmu 0x21e7 0x04a0>, + <&apps_smmu 0x2547 0x04a0>, + <&apps_smmu 0x2567 0x04a0>, + <&apps_smmu 0x2587 0x0400>, + <&apps_smmu 0x25c7 0x04a0>, + <&apps_smmu 0x25e7 0x04a0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x2148 0x04a0>, + <&apps_smmu 0x2168 0x04a0>, + <&apps_smmu 0x2188 0x0400>, + <&apps_smmu 0x21c8 0x04a0>, + <&apps_smmu 0x21e8 0x04a0>, + <&apps_smmu 0x2548 0x04a0>, + <&apps_smmu 0x2568 0x04a0>, + <&apps_smmu 0x2588 0x0400>, + <&apps_smmu 0x25c8 0x04a0>, + <&apps_smmu 0x25e8 0x04a0>; + dma-coherent; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x2149 0x04a0>, + <&apps_smmu 0x2169 0x04a0>, + <&apps_smmu 0x2189 0x0400>, + <&apps_smmu 0x21c9 0x04a0>, + <&apps_smmu 0x21e9 0x04a0>, + <&apps_smmu 0x2549 0x04a0>, + <&apps_smmu 0x2569 0x04a0>, + <&apps_smmu 0x2589 0x0400>, + <&apps_smmu 0x25c9 0x04a0>, + <&apps_smmu 0x25e9 0x04a0>; + dma-coherent; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x214a 0x04a0>, + <&apps_smmu 0x216a 0x04a0>, + <&apps_smmu 0x218a 0x0400>, + <&apps_smmu 0x21ca 0x04a0>, + <&apps_smmu 0x21ea 0x04a0>, + <&apps_smmu 0x254a 0x04a0>, + <&apps_smmu 0x256a 0x04a0>, + <&apps_smmu 0x258a 0x0400>, + <&apps_smmu 0x25ca 0x04a0>, + <&apps_smmu 0x25ea 0x04a0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x214b 0x04a0>, + <&apps_smmu 0x216b 0x04a0>, + <&apps_smmu 0x218b 0x0400>, + <&apps_smmu 0x21cb 0x04a0>, + <&apps_smmu 0x21eb 0x04a0>, + <&apps_smmu 0x254b 0x04a0>, + <&apps_smmu 0x256b 0x04a0>, + <&apps_smmu 0x258b 0x0400>, + <&apps_smmu 0x25cb 0x04a0>, + <&apps_smmu 0x25eb 0x04a0>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_cdsp1: remoteproc@2a300000 { + compatible = "qcom,sa8775p-cdsp1-pas"; + reg = <0x0 0x2A300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP1>; + power-domain-names = "cx", "mxc", "nsp"; + + interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 + &mc_virt SLAVE_EBI1 0>; + + memory-region = <&pil_cdsp1_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp1_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <12>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp1"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x2941 0x04a0>, + <&apps_smmu 0x2961 0x04a0>, + <&apps_smmu 0x2981 0x0400>, + <&apps_smmu 0x29c1 0x04a0>, + <&apps_smmu 0x29e1 0x04a0>, + <&apps_smmu 0x2d41 0x04a0>, + <&apps_smmu 0x2d61 0x04a0>, + <&apps_smmu 0x2d81 0x0400>, + <&apps_smmu 0x2dc1 0x04a0>, + <&apps_smmu 0x2de1 0x04a0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x2942 0x04a0>, + <&apps_smmu 0x2962 0x04a0>, + <&apps_smmu 0x2982 0x0400>, + <&apps_smmu 0x29c2 0x04a0>, + <&apps_smmu 0x29e2 0x04a0>, + <&apps_smmu 0x2d42 0x04a0>, + <&apps_smmu 0x2d62 0x04a0>, + <&apps_smmu 0x2d82 0x0400>, + <&apps_smmu 0x2dc2 0x04a0>, + <&apps_smmu 0x2de2 0x04a0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x2943 0x04a0>, + <&apps_smmu 0x2963 0x04a0>, + <&apps_smmu 0x2983 0x0400>, + <&apps_smmu 0x29c3 0x04a0>, + <&apps_smmu 0x29e3 0x04a0>, + <&apps_smmu 0x2d43 0x04a0>, + <&apps_smmu 0x2d63 0x04a0>, + <&apps_smmu 0x2d83 0x0400>, + <&apps_smmu 0x2dc3 0x04a0>, + <&apps_smmu 0x2de3 0x04a0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x2944 0x04a0>, + <&apps_smmu 0x2964 0x04a0>, + <&apps_smmu 0x2984 0x0400>, + <&apps_smmu 0x29c4 0x04a0>, + <&apps_smmu 0x29e4 0x04a0>, + <&apps_smmu 0x2d44 0x04a0>, + <&apps_smmu 0x2d64 0x04a0>, + <&apps_smmu 0x2d84 0x0400>, + <&apps_smmu 0x2dc4 0x04a0>, + <&apps_smmu 0x2de4 0x04a0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x2945 0x04a0>, + <&apps_smmu 0x2965 0x04a0>, + <&apps_smmu 0x2985 0x0400>, + <&apps_smmu 0x29c5 0x04a0>, + <&apps_smmu 0x29e5 0x04a0>, + <&apps_smmu 0x2d45 0x04a0>, + <&apps_smmu 0x2d65 0x04a0>, + <&apps_smmu 0x2d85 0x0400>, + <&apps_smmu 0x2dc5 0x04a0>, + <&apps_smmu 0x2de5 0x04a0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x2946 0x04a0>, + <&apps_smmu 0x2966 0x04a0>, + <&apps_smmu 0x2986 0x0400>, + <&apps_smmu 0x29c6 0x04a0>, + <&apps_smmu 0x29e6 0x04a0>, + <&apps_smmu 0x2d46 0x04a0>, + <&apps_smmu 0x2d66 0x04a0>, + <&apps_smmu 0x2d86 0x0400>, + <&apps_smmu 0x2dc6 0x04a0>, + <&apps_smmu 0x2de6 0x04a0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x2947 0x04a0>, + <&apps_smmu 0x2967 0x04a0>, + <&apps_smmu 0x2987 0x0400>, + <&apps_smmu 0x29c7 0x04a0>, + <&apps_smmu 0x29e7 0x04a0>, + <&apps_smmu 0x2d47 0x04a0>, + <&apps_smmu 0x2d67 0x04a0>, + <&apps_smmu 0x2d87 0x0400>, + <&apps_smmu 0x2dc7 0x04a0>, + <&apps_smmu 0x2de7 0x04a0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x2948 0x04a0>, + <&apps_smmu 0x2968 0x04a0>, + <&apps_smmu 0x2988 0x0400>, + <&apps_smmu 0x29c8 0x04a0>, + <&apps_smmu 0x29e8 0x04a0>, + <&apps_smmu 0x2d48 0x04a0>, + <&apps_smmu 0x2d68 0x04a0>, + <&apps_smmu 0x2d88 0x0400>, + <&apps_smmu 0x2dc8 0x04a0>, + <&apps_smmu 0x2de8 0x04a0>; + dma-coherent; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x2949 0x04a0>, + <&apps_smmu 0x2969 0x04a0>, + <&apps_smmu 0x2989 0x0400>, + <&apps_smmu 0x29c9 0x04a0>, + <&apps_smmu 0x29e9 0x04a0>, + <&apps_smmu 0x2d49 0x04a0>, + <&apps_smmu 0x2d69 0x04a0>, + <&apps_smmu 0x2d89 0x0400>, + <&apps_smmu 0x2dc9 0x04a0>, + <&apps_smmu 0x2de9 0x04a0>; + dma-coherent; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x294a 0x04a0>, + <&apps_smmu 0x296a 0x04a0>, + <&apps_smmu 0x298a 0x0400>, + <&apps_smmu 0x29ca 0x04a0>, + <&apps_smmu 0x29ea 0x04a0>, + <&apps_smmu 0x2d4a 0x04a0>, + <&apps_smmu 0x2d6a 0x04a0>, + <&apps_smmu 0x2d8a 0x0400>, + <&apps_smmu 0x2dca 0x04a0>, + <&apps_smmu 0x2dea 0x04a0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x294b 0x04a0>, + <&apps_smmu 0x296b 0x04a0>, + <&apps_smmu 0x298b 0x0400>, + <&apps_smmu 0x29cb 0x04a0>, + <&apps_smmu 0x29eb 0x04a0>, + <&apps_smmu 0x2d4b 0x04a0>, + <&apps_smmu 0x2d6b 0x04a0>, + <&apps_smmu 0x2d8b 0x0400>, + <&apps_smmu 0x2dcb 0x04a0>, + <&apps_smmu 0x2deb 0x04a0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x294c 0x04a0>, + <&apps_smmu 0x296c 0x04a0>, + <&apps_smmu 0x298c 0x0400>, + <&apps_smmu 0x29cc 0x04a0>, + <&apps_smmu 0x29ec 0x04a0>, + <&apps_smmu 0x2d4c 0x04a0>, + <&apps_smmu 0x2d6c 0x04a0>, + <&apps_smmu 0x2d8c 0x0400>, + <&apps_smmu 0x2dcc 0x04a0>, + <&apps_smmu 0x2dec 0x04a0>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x294d 0x04a0>, + <&apps_smmu 0x296d 0x04a0>, + <&apps_smmu 0x298d 0x0400>, + <&apps_smmu 0x29Cd 0x04a0>, + <&apps_smmu 0x29ed 0x04a0>, + <&apps_smmu 0x2d4d 0x04a0>, + <&apps_smmu 0x2d6d 0x04a0>, + <&apps_smmu 0x2d8d 0x0400>, + <&apps_smmu 0x2dcd 0x04a0>, + <&apps_smmu 0x2ded 0x04a0>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sa8775p-adsp-pas"; + reg = <0x0 0x30000000 0x0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", "lmx"; + + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = <QCOM_SCM_VMID_LPASS + QCOM_SCM_VMID_ADSP_HEAP>; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x3003 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x3004 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x3005 0x0>; + qcom,nsessions = <5>; + dma-coherent; + }; + }; + }; + }; }; thermal-zones { aoss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -2479,7 +5435,6 @@ cpu-0-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -2500,7 +5455,6 @@ cpu-0-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -2521,7 +5475,6 @@ cpu-0-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -2542,7 +5495,6 @@ cpu-0-3-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -2563,7 +5515,6 @@ gpuss-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -2584,7 +5535,6 @@ gpuss-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -2605,7 +5555,6 @@ gpuss-2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -2625,9 +5574,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -2646,9 +5592,6 @@ }; camss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -2667,9 +5610,6 @@ }; pcie-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -2688,9 +5628,6 @@ }; cpuss-0-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -2709,9 +5646,6 @@ }; aoss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -2731,7 +5665,6 @@ cpu-0-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -2752,7 +5685,6 @@ cpu-0-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -2773,7 +5705,6 @@ cpu-0-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -2794,7 +5725,6 @@ cpu-0-3-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -2815,7 +5745,6 @@ gpuss-3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -2836,7 +5765,6 @@ gpuss-4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -2857,7 +5785,6 @@ gpuss-5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -2877,9 +5804,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -2898,9 +5822,6 @@ }; camss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -2919,9 +5840,6 @@ }; pcie-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -2940,9 +5858,6 @@ }; cpuss-0-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { @@ -2961,9 +5876,6 @@ }; aoss-2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 0>; trips { @@ -2983,7 +5895,6 @@ cpu-1-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 1>; @@ -3004,7 +5915,6 @@ cpu-1-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 2>; @@ -3025,7 +5935,6 @@ cpu-1-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 3>; @@ -3046,7 +5955,6 @@ cpu-1-3-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 4>; @@ -3067,7 +5975,6 @@ nsp-0-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 5>; @@ -3088,7 +5995,6 @@ nsp-0-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 6>; @@ -3109,7 +6015,6 @@ nsp-0-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 7>; @@ -3130,7 +6035,6 @@ nsp-1-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 8>; @@ -3151,7 +6055,6 @@ nsp-1-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; @@ -3172,7 +6075,6 @@ nsp-1-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; @@ -3192,9 +6094,6 @@ }; ddrss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 11>; trips { @@ -3213,9 +6112,6 @@ }; cpuss-1-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 12>; trips { @@ -3234,9 +6130,6 @@ }; aoss-3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 0>; trips { @@ -3256,7 +6149,6 @@ cpu-1-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 1>; @@ -3277,7 +6169,6 @@ cpu-1-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 2>; @@ -3298,7 +6189,6 @@ cpu-1-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 3>; @@ -3319,7 +6209,6 @@ cpu-1-3-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 4>; @@ -3340,7 +6229,6 @@ nsp-0-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 5>; @@ -3361,7 +6249,6 @@ nsp-0-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 6>; @@ -3382,7 +6269,6 @@ nsp-0-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 7>; @@ -3403,7 +6289,6 @@ nsp-1-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 8>; @@ -3424,7 +6309,6 @@ nsp-1-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 9>; @@ -3445,7 +6329,6 @@ nsp-1-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 10>; @@ -3465,9 +6348,6 @@ }; ddrss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 11>; trips { @@ -3486,9 +6366,6 @@ }; cpuss-1-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 12>; trips { @@ -3512,7 +6389,7 @@ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; pcie0: pcie@1c00000 { @@ -3584,6 +6461,64 @@ phy-names = "pciephy"; status = "disabled"; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <2>; + linux,pci-domain = <0>; + + status = "disabled"; }; pcie0_phy: phy@1c04000 { @@ -3684,6 +6619,64 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <4>; + linux,pci-domain = <1>; + + status = "disabled"; }; pcie1_phy: phy@1c14000 { |