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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sdm845.dtsi177
1 files changed, 149 insertions, 28 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d761da47220d..65032b94b46d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -767,13 +767,13 @@
#size-cells = <0>;
qcom,intents = <512 20>;
- apr-service@3 {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
- q6afe: apr-service@4 {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -785,7 +785,7 @@
};
};
- q6asm: apr-service@7 {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -798,7 +798,7 @@
};
};
- q6adm: apr-service@8 {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -3008,6 +3008,28 @@
};
};
+ qup_uart6_4pin: qup-uart6-4pin-state {
+
+ cts-pins {
+ pins = "gpio45";
+ function = "qup6";
+ bias-pull-down;
+ };
+
+ rts-tx-pins {
+ pins = "gpio46", "gpio47";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio48";
+ function = "qup6";
+ bias-pull-up;
+ };
+ };
+
qup_uart7_default: qup-uart7-default {
pinmux {
pins = "gpio95", "gpio96";
@@ -3823,33 +3845,29 @@
status = "disabled";
};
- slim: slim@171c0000 {
+ slim: slim-ngd@171c0000 {
compatible = "qcom,slim-ngd-v2.1.0";
reg = <0 0x171c0000 0 0x2c000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- qcom,apps-ch-pipes = <0x780000>;
- qcom,ea-pc = <0x270>;
- status = "okay";
- dmas = <&slimbam 3>, <&slimbam 4>,
- <&slimbam 5>, <&slimbam 6>;
- dma-names = "rx", "tx", "tx2", "rx2";
+ dmas = <&slimbam 3>, <&slimbam 4>;
+ dma-names = "rx", "tx";
iommus = <&apps_smmu 0x1806 0x0>;
#address-cells = <1>;
#size-cells = <0>;
- ngd@1 {
+ slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
- wcd9340_ifd: ifd@0{
+ wcd9340_ifd: ifd@0,0 {
compatible = "slim217,250";
reg = <0 0>;
};
- wcd9340: codec@1{
+ wcd9340: codec@1,0 {
compatible = "slim217,250";
reg = <1 0>;
slim-ifc-dev = <&wcd9340_ifd>;
@@ -3959,9 +3977,10 @@
};
usb_1_qmpphy: phy@88e9000 {
- compatible = "qcom,sdm845-qmp-usb3-phy";
+ compatible = "qcom,sdm845-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x10>;
+ <0 0x088e8000 0 0x38>,
+ <0 0x088ea000 0 0x40>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -3973,11 +3992,11 @@
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: phy@88e9200 {
+ usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
@@ -3990,6 +4009,16 @@
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
+
+ dp_phy: dp-phy@88ea200 {
+ reg = <0 0x088ea200 0 0x200>,
+ <0 0x088ea400 0 0x200>,
+ <0 0x088eaa00 0 0x200>,
+ <0 0x088ea600 0 0x200>,
+ <0 0x088ea800 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
usb_2_qmpphy: phy@88eb000 {
@@ -4339,6 +4368,22 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
};
};
@@ -4483,13 +4528,20 @@
port@0 {
reg = <0>;
- dpu_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
};
};
port@1 {
reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
@@ -4521,6 +4573,77 @@
};
};
+ mdss_dp: displayport-controller@ae90000 {
+ status = "disabled";
+ compatible = "qcom,sdm845-dp";
+
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae90a00 0 0x600>,
+ <0 0xae91000 0 0x600>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux", "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SDM845_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: dp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
@@ -4548,7 +4671,6 @@
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi0_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -4574,7 +4696,7 @@
};
};
- dsi0_phy: dsi-phy@ae94400 {
+ dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -4620,7 +4742,6 @@
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi1_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -4646,7 +4767,7 @@
};
};
- dsi1_phy: dsi-phy@ae96400 {
+ dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
@@ -4812,8 +4933,8 @@
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
- <0>,
- <0>;
+ <&dp_phy 0>,
+ <&dp_phy 1>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
@@ -5197,7 +5318,7 @@
};
osm_l3: interconnect@17d41000 {
- compatible = "qcom,sdm845-osm-l3";
+ compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
reg = <0 0x17d41000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
generated by cgit (git 2.34.1) at 2024-06-08 08:22:39 +0000