diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6125.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6125.dtsi | 85 |
1 files changed, 47 insertions, 38 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 1dd3a4056e26..350d807a622f 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -28,7 +28,7 @@ sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; }; @@ -37,122 +37,122 @@ #address-cells = <2>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { + next-level-cache = <&l2_0>; + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; - CPU1: cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x3>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; }; - CPU4: cpu@100 { + cpu4: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1638>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { + next-level-cache = <&l2_1>; + l2_1: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; - CPU5: cpu@101 { + cpu5: cpu@101 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1638>; - next-level-cache = <&L2_1>; + next-level-cache = <&l2_1>; }; - CPU6: cpu@102 { + cpu6: cpu@102 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1638>; - next-level-cache = <&L2_1>; + next-level-cache = <&l2_1>; }; - CPU7: cpu@103 { + cpu7: cpu@103 { device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1638>; - next-level-cache = <&L2_1>; + next-level-cache = <&l2_1>; }; cpu-map { cluster0 { core0 { - cpu = <&CPU0>; + cpu = <&cpu0>; }; core1 { - cpu = <&CPU1>; + cpu = <&cpu1>; }; core2 { - cpu = <&CPU2>; + cpu = <&cpu2>; }; core3 { - cpu = <&CPU3>; + cpu = <&cpu3>; }; }; cluster1 { core0 { - cpu = <&CPU4>; + cpu = <&cpu4>; }; core1 { - cpu = <&CPU5>; + cpu = <&cpu5>; }; core2 { - cpu = <&CPU6>; + cpu = <&cpu6>; }; core3 { - cpu = <&CPU7>; + cpu = <&cpu7>; }; }; }; @@ -192,7 +192,7 @@ mboxes = <&apcs_glb 0>; rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6125"; + compatible = "qcom,rpm-sm6125", "qcom,glink-smd-rpm"; qcom,glink-channels = "rpm_requests"; rpmcc: clock-controller { @@ -763,7 +763,7 @@ status = "disabled"; }; - ufs_mem_hc: ufs@4804000 { + ufs_mem_hc: ufshc@4804000 { compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x04804000 0x3000>, <0x04810000 0x8000>; reg-names = "std", "ice"; @@ -812,10 +812,12 @@ compatible = "qcom,sm6125-qmp-ufs-phy"; reg = <0x04807000 0xdb8>; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1185,9 +1187,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; qcom,select-utmi-as-pipe-clk; @@ -1202,6 +1209,8 @@ phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; maximum-speed = "high-speed"; dr_mode = "peripheral"; }; @@ -1581,10 +1590,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 0xf08 - GIC_PPI 2 0xf08 - GIC_PPI 3 0xf08 - GIC_PPI 0 0xf08>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <19200000>; }; }; |