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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8150.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm8150.dtsi88
1 files changed, 64 insertions, 24 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 13e0ce828606..2273fa571988 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -48,6 +48,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
@@ -74,6 +75,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
@@ -90,13 +92,13 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
-
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
@@ -119,6 +121,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
@@ -141,6 +144,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
@@ -163,6 +167,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
@@ -185,6 +190,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
@@ -207,6 +213,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
+ clocks = <&cpufreq_hw 2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <421>;
@@ -288,12 +295,10 @@
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
- idle-state-name = "cluster-power-collapse";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
- local-timer-stop;
};
};
};
@@ -945,6 +950,17 @@
status = "disabled";
};
+ qfprom: efuse@784000 {
+ compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
+ };
+ };
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
@@ -1334,6 +1350,20 @@
status = "disabled";
};
+ uart9: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+ reg-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
@@ -1772,8 +1802,11 @@
system-cache-controller@9200000 {
compatible = "qcom,sm8150-llcc";
- reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
+ reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
+ <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
+ <0 0x09600000 0 0x50000>;
+ reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+ "llcc3_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -1799,8 +1832,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@@ -1826,7 +1859,6 @@
"slave_q2a",
"tbu";
- iommus = <&apps_smmu 0x1d80 0x3f>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
@@ -1895,7 +1927,7 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
@@ -1925,7 +1957,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1e00 0x3f>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
@@ -2133,15 +2164,7 @@
};
gpu: gpu@2c00000 {
- /*
- * note: the amd,imageon compatible makes it possible
- * to use the drm/msm driver without the display node,
- * make sure to remove it when display node is added
- */
- compatible = "qcom,adreno-640.1",
- "qcom,adreno",
- "amd,imageon";
-
+ compatible = "qcom,adreno-640.1", "qcom,adreno";
reg = <0 0x02c00000 0 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
@@ -2153,44 +2176,52 @@
qcom,gmu = <&gmu>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
status = "disabled";
zap-shader {
memory-region = <&gpu_mem>;
};
- /* note: downstream checks gpu binning for 675 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-675000000 {
opp-hz = /bits/ 64 <675000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-supported-hw = <0x2>;
};
opp-585000000 {
opp-hz = /bits/ 64 <585000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-supported-hw = <0x3>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-supported-hw = <0x3>;
};
opp-427000000 {
opp-hz = /bits/ 64 <427000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-supported-hw = <0x3>;
};
opp-345000000 {
opp-hz = /bits/ 64 <345000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-supported-hw = <0x3>;
};
opp-257000000 {
opp-hz = /bits/ 64 <257000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-supported-hw = <0x3>;
};
};
};
@@ -2249,7 +2280,8 @@
};
adreno_smmu: iommu@2ca0000 {
- compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x02ca0000 0 0x10000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
@@ -2425,6 +2457,13 @@
bias-disable;
};
+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio41", "gpio42";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_i2c10_default: qup-i2c10-default-state {
pins = "gpio9", "gpio10";
function = "qup10";
@@ -3935,7 +3974,6 @@
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
- cell-index = <0>;
};
apps_smmu: iommu@15000000 {
@@ -4097,7 +4135,8 @@
};
apss_shared: mailbox@17c00000 {
- compatible = "qcom,sm8150-apss-shared";
+ compatible = "qcom,sm8150-apss-shared",
+ "qcom,sdm845-apss-shared";
reg = <0x0 0x17c00000 0x0 0x1000>;
#mbox-cells = <1>;
};
@@ -4263,7 +4302,7 @@
};
cpufreq_hw: cpufreq@18323000 {
- compatible = "qcom,cpufreq-hw";
+ compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
<0 0x18327800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1",
@@ -4273,6 +4312,7 @@
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
+ #clock-cells = <1>;
};
lmh_cluster1: lmh@18350800 {
generated by cgit (git 2.34.1) at 2024-06-15 13:13:39 +0000