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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8250.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm8250.dtsi257
1 files changed, 217 insertions, 40 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 2f0e460acccd..7bea916900e2 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -97,6 +97,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
@@ -127,6 +128,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
@@ -151,6 +153,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
@@ -175,6 +178,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
@@ -199,6 +203,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
@@ -223,6 +228,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
@@ -241,13 +247,13 @@
cache-unified;
next-level-cache = <&L3_0>;
};
-
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
@@ -272,6 +278,7 @@
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
+ clocks = <&cpufreq_hw 2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <444>;
@@ -355,12 +362,10 @@
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
- idle-state-name = "cluster-llcc-off";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3264>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
- local-timer-stop;
};
};
};
@@ -955,6 +960,18 @@
#mbox-cells = <2>;
};
+ qfprom: efuse@784000 {
+ compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@19b {
+ reg = <0x19b 0x1>;
+ bits = <5 3>;
+ };
+ };
+
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
@@ -1824,8 +1841,9 @@
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
- <0 0x60100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
@@ -1834,8 +1852,8 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
@@ -1871,7 +1889,6 @@
"tbu",
"ddrss_sf_tbu";
- iommus = <&apps_smmu 0x1c00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
@@ -1933,8 +1950,9 @@
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
<0 0x40001000 0 0x1000>,
- <0 0x40100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x40100000 0 0x100000>,
+ <0 0x01c0b000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
@@ -1943,7 +1961,7 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
@@ -1977,7 +1995,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1c80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
@@ -2041,8 +2058,9 @@
<0 0x64000000 0 0xf1d>,
<0 0x64000f20 0 0xa8>,
<0 0x64001000 0 0x1000>,
- <0 0x64100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x64100000 0 0x100000>,
+ <0 0x01c13000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
@@ -2051,7 +2069,7 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
@@ -2085,7 +2103,6 @@
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1d00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
<0x100 &apps_smmu 0x1d01 0x1>;
@@ -2359,7 +2376,7 @@
swr2: soundwire-controller@3230000 {
reg = <0 0x03230000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
- interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core";
status = "disabled";
@@ -2420,7 +2437,6 @@
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
-
};
};
@@ -2429,7 +2445,6 @@
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
- input-enable;
bias-pull-down;
};
@@ -2437,9 +2452,7 @@
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
- input-enable;
bias-pull-down;
-
};
};
@@ -2454,7 +2467,6 @@
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
- input-enable;
};
};
@@ -2472,7 +2484,6 @@
function = "dmic1_data";
drive-strength = <2>;
bias-pull-down;
- input-enable;
};
};
@@ -2517,7 +2528,6 @@
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
- input-enable;
bias-pull-down;
};
@@ -2525,7 +2535,6 @@
pins = "gpio1";
function = "swr_tx_data";
drive-strength = <2>;
- input-enable;
bias-bus-hold;
};
@@ -2533,7 +2542,6 @@
pins = "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
- input-enable;
bias-pull-down;
};
};
@@ -2554,49 +2562,58 @@
qcom,gmu = <&gmu>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
status = "disabled";
zap-shader {
memory-region = <&gpu_mem>;
};
- /* note: downstream checks gpu binning for 670 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-670000000 {
opp-hz = /bits/ 64 <670000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-supported-hw = <0xa>;
};
opp-587000000 {
opp-hz = /bits/ 64 <587000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-supported-hw = <0xb>;
};
opp-525000000 {
opp-hz = /bits/ 64 <525000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-supported-hw = <0xf>;
};
opp-490000000 {
opp-hz = /bits/ 64 <490000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-supported-hw = <0xf>;
};
opp-441600000 {
opp-hz = /bits/ 64 <441600000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ opp-supported-hw = <0xf>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-supported-hw = <0xf>;
};
opp-305000000 {
opp-hz = /bits/ 64 <305000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-supported-hw = <0xf>;
};
};
};
@@ -2656,7 +2673,8 @@
};
adreno_smmu: iommu@3da0000 {
- compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x03da0000 0 0x10000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
@@ -2763,6 +2781,73 @@
};
};
+ tpda@6004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0 0x06004000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint = <&funnel_qatb_in_tpda>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@9 {
+ reg = <9>;
+ tpda_9_in_tpdm_mm: endpoint {
+ remote-endpoint = <&tpdm_mm_out_tpda9>;
+ };
+ };
+
+ port@17 {
+ reg = <23>;
+ tpda_23_in_tpdm_prng: endpoint {
+ remote-endpoint = <&tpdm_prng_out_tpda_23>;
+ };
+ };
+ };
+ };
+
+ funnel@6005000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06005000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ remote-endpoint = <&tpda_out_funnel_qatb>;
+ };
+ };
+ };
+ };
+
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06041000 0 0x1000>;
@@ -2782,6 +2867,13 @@
#address-cells = <1>;
#size-cells = <0>;
+ port@6 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ remote-endpoint = <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
port@7 {
reg = <7>;
funnel0_in7: endpoint {
@@ -2799,11 +2891,7 @@
clock-names = "apb_pclk";
out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ port {
funnel_in1_out_funnel_merg: endpoint {
remote-endpoint = <&funnel_merg_in_funnel_in1>;
};
@@ -2899,12 +2987,27 @@
};
};
+ tpdm@684c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0 0x0684c000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_prng_out_tpda_23: endpoint {
+ remote-endpoint = <&tpda_23_in_tpdm_prng>;
+ };
+ };
+ };
+ };
+
funnel@6b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
arm,primecell-periphid = <0x000bb908>;
reg = <0 0x06b04000 0 0x1000>;
- reg-names = "funnel-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2928,7 +3031,6 @@
};
};
};
-
};
etf@6b05000 {
@@ -2983,6 +3085,80 @@
};
};
+ tpdm@6c08000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0 0x06c08000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_mm_out_funnel_dl_mm: endpoint {
+ remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
+ };
+ };
+ };
+ };
+
+ funnel@6c0b000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06c0b000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_dl_mm_out_funnel_dl_center: endpoint {
+ remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_mm_in_tpdm_mm: endpoint {
+ remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
+ };
+ };
+ };
+ };
+
+ funnel@6c2d000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06c2d000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port {
+ tpdm_mm_out_tpda9: endpoint {
+ remote-endpoint = <&tpda_9_in_tpdm_mm>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+ funnel_dl_center_in_funnel_dl_mm: endpoint {
+ remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
+ };
+ };
+ };
+ };
+
etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
@@ -3220,9 +3396,6 @@
clock-names = "apb_pclk";
out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
port {
funnel_apss_merg_out_funnel_in1: endpoint {
remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
@@ -3559,8 +3732,11 @@
system-cache-controller@9200000 {
compatible = "qcom,sm8250-llcc";
- reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
+ reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
+ <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
+ <0 0x09600000 0 0x50000>;
+ reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+ "llcc3_base", "llcc_broadcast_base";
};
usb_2: usb@a8f8800 {
@@ -5481,6 +5657,7 @@
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
#freq-domain-cells = <1>;
+ #clock-cells = <1>;
};
};
generated by cgit (git 2.34.1) at 2024-06-18 03:04:12 +0000