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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8650.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm8650.dtsi1590
1 files changed, 1223 insertions, 367 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..86684cb9a932 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4,10 +4,12 @@
*/
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8650-camcc.h>
#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
@@ -60,29 +62,24 @@
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a520";
reg = <0 0>;
clocks = <&cpufreq_hw 0>;
- power-domains = <&CPU_PD0>;
+ power-domains = <&cpu_pd0>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@@ -90,13 +87,13 @@
#cooling-cells = <2>;
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
- L3_0: l3-cache {
+ l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@@ -104,18 +101,18 @@
};
};
- CPU1: cpu@100 {
+ cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a520";
reg = <0 0x100>;
clocks = <&cpufreq_hw 0>;
- power-domains = <&CPU_PD1>;
+ power-domains = <&cpu_pd1>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@@ -124,18 +121,18 @@
#cooling-cells = <2>;
};
- CPU2: cpu@200 {
+ cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x200>;
clocks = <&cpufreq_hw 3>;
- power-domains = <&CPU_PD2>;
+ power-domains = <&cpu_pd2>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_200>;
+ next-level-cache = <&l2_200>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@@ -143,26 +140,26 @@
#cooling-cells = <2>;
- L2_200: l2-cache {
+ l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU3: cpu@300 {
+ cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x300>;
clocks = <&cpufreq_hw 3>;
- power-domains = <&CPU_PD3>;
+ power-domains = <&cpu_pd3>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_200>;
+ next-level-cache = <&l2_200>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@@ -171,18 +168,18 @@
#cooling-cells = <2>;
};
- CPU4: cpu@400 {
+ cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x400>;
clocks = <&cpufreq_hw 3>;
- power-domains = <&CPU_PD4>;
+ power-domains = <&cpu_pd4>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_400>;
+ next-level-cache = <&l2_400>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@@ -190,26 +187,26 @@
#cooling-cells = <2>;
- L2_400: l2-cache {
+ l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU5: cpu@500 {
+ cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x500>;
clocks = <&cpufreq_hw 1>;
- power-domains = <&CPU_PD5>;
+ power-domains = <&cpu_pd5>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_500>;
+ next-level-cache = <&l2_500>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@@ -217,26 +214,26 @@
#cooling-cells = <2>;
- L2_500: l2-cache {
+ l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU6: cpu@600 {
+ cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a720";
reg = <0 0x600>;
clocks = <&cpufreq_hw 1>;
- power-domains = <&CPU_PD6>;
+ power-domains = <&cpu_pd6>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_600>;
+ next-level-cache = <&l2_600>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@@ -244,26 +241,26 @@
#cooling-cells = <2>;
- L2_600: l2-cache {
+ l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU7: cpu@700 {
+ cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x4";
reg = <0 0x700>;
clocks = <&cpufreq_hw 2>;
- power-domains = <&CPU_PD7>;
+ power-domains = <&cpu_pd7>;
power-domain-names = "psci";
enable-method = "psci";
- next-level-cache = <&L2_700>;
+ next-level-cache = <&l2_700>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
@@ -271,46 +268,46 @@
#cooling-cells = <2>;
- L2_700: l2-cache {
+ l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
core1 {
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
core2 {
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
core3 {
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
core4 {
- cpu = <&CPU4>;
+ cpu = <&cpu4>;
};
core5 {
- cpu = <&CPU5>;
+ cpu = <&cpu5>;
};
core6 {
- cpu = <&CPU6>;
+ cpu = <&cpu6>;
};
core7 {
- cpu = <&CPU7>;
+ cpu = <&cpu7>;
};
};
};
@@ -318,7 +315,7 @@
idle-states {
entry-method = "psci";
- SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
+ silver_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -328,7 +325,7 @@
local-timer-stop;
};
- GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
+ gold_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -338,7 +335,7 @@
local-timer-stop;
};
- GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
+ gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-plus-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -350,7 +347,7 @@
};
domain-idle-states {
- CLUSTER_SLEEP_0: cluster-sleep-0 {
+ cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <750>;
@@ -358,7 +355,7 @@
min-residency-us = <9144>;
};
- CLUSTER_SLEEP_1: cluster-sleep-1 {
+ cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2800>;
@@ -368,9 +365,44 @@
};
};
+ ete0 {
+ compatible = "arm,embedded-trace-extension";
+
+ cpu = <&cpu0>;
+
+ out-ports {
+ port {
+ ete0_out_funnel_ete: endpoint {
+ remote-endpoint = <&funnel_ete_in_ete0>;
+ };
+ };
+ };
+ };
+
+ funnel-ete {
+ compatible = "arm,coresight-static-funnel";
+
+ in-ports {
+ port {
+ funnel_ete_in_ete0: endpoint {
+ remote-endpoint = <&ete0_out_funnel_ete>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_ete_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_funnel_ete>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-sm8650", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
@@ -394,8 +426,18 @@
reg = <0 0xa0000000 0 0>;
};
- pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu-a520 {
+ compatible = "arm,cortex-a520-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu-a720 {
+ compatible = "arm,cortex-a720-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu-x4 {
+ compatible = "arm,cortex-x4-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
@@ -403,58 +445,58 @@
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: power-domain-cpu0 {
+ cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>;
};
- CPU_PD1: power-domain-cpu1 {
+ cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>;
};
- CPU_PD2: power-domain-cpu2 {
+ cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>;
};
- CPU_PD3: power-domain-cpu3 {
+ cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>;
};
- CPU_PD4: power-domain-cpu4 {
+ cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>;
};
- CPU_PD5: power-domain-cpu5 {
+ cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>;
};
- CPU_PD6: power-domain-cpu6 {
+ cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>;
};
- CPU_PD7: power-domain-cpu7 {
+ cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_plus_cpu_sleep_0>;
};
- CLUSTER_PD: power-domain-cluster {
+ cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_SLEEP_0>,
- <&CLUSTER_SLEEP_1>;
+ domain-idle-states = <&cluster_sleep_0>,
+ <&cluster_sleep_1>;
};
};
@@ -485,9 +527,9 @@
no-map;
};
- /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
+ /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */
aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
- reg = <0 0x81c80000 0 0x74000>;
+ reg = <0 0x81c80000 0 0x75000>;
no-map;
};
@@ -525,6 +567,11 @@
no-map;
};
+ qlink_logging_mem: qlink-logging@84800000 {
+ reg = <0 0x84800000 0 0x200000>;
+ no-map;
+ };
+
mpss_dsm_mem: mpss-dsm@86b00000 {
reg = <0 0x86b00000 0 0x4900000>;
no-map;
@@ -753,8 +800,8 @@
<&bi_tcxo_ao_div2>,
<&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1228,7 +1275,7 @@
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
@@ -1250,7 +1297,7 @@
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
- interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
@@ -2203,7 +2250,7 @@
reg = <0 0x010c3000 0 0x1000>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c00000 0 0x3000>,
@@ -2213,8 +2260,24 @@
<0 0x60100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@@ -2255,6 +2318,10 @@
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
+ msi-map = <0x0 &gic_its 0x1400 0x1>,
+ <0x100 &gic_its 0x1401 0x1>;
+ msi-map-mask = <0xff00>;
+
linux,pci-domain = <0>;
num-lanes = <2>;
bus-range = <0 0xff>;
@@ -2270,6 +2337,16 @@
dma-coherent;
status = "disabled";
+
+ pcieport0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -2303,7 +2380,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c08000 0 0x3000>,
@@ -2317,8 +2394,24 @@
"atu",
"config";
- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@@ -2364,6 +2457,10 @@
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
+ msi-map = <0x0 &gic_its 0x1480 0x1>,
+ <0x100 &gic_its 0x1481 0x1>;
+ msi-map-mask = <0xff00>;
+
linux,pci-domain = <1>;
num-lanes = <2>;
bus-range = <0 0xff>;
@@ -2379,6 +2476,16 @@
<0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
@@ -2406,7 +2513,7 @@
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
+ #clock-cells = <1>;
clock-output-names = "pcie1_pipe_clk";
#phy-cells = <0>;
@@ -2448,10 +2555,12 @@
compatible = "qcom,sm8650-qmp-ufs-phy";
reg = <0 0x01d80000 0 0x2000>;
- clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_CLKREF_EN>;
clock-names = "ref",
- "ref_aux";
+ "ref_aux",
+ "qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@@ -2464,7 +2573,7 @@
status = "disabled";
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
@@ -2524,7 +2633,7 @@
ice: crypto@1d88000 {
compatible = "qcom,sm8650-inline-crypto-engine",
"qcom,inline-crypto-engine";
- reg = <0 0x01d88000 0 0x8000>;
+ reg = <0 0x01d88000 0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
@@ -2546,6 +2655,159 @@
#reset-cells = <1>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-43051401", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x2000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x0>,
+ <&adreno_smmu 1 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&gpu_micro_code_mem>;
+ };
+
+ /* Speedbin needs more work on A740+, keep only lower freqs */
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-231000000 {
+ opp-hz = /bits/ 64 <231000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ opp-peak-kBps = <2136718>;
+ };
+
+ opp-310000000 {
+ opp-hz = /bits/ 64 <310000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <2136718>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ opp-peak-kBps = <6074218>;
+ };
+
+ opp-422000000 {
+ opp-hz = /bits/ 64 <422000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-578000000 {
+ opp-hz = /bits/ 64 <578000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-629000000 {
+ opp-hz = /bits/ 64 <629000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ opp-peak-kBps = <10687500>;
+ };
+
+ opp-680000000 {
+ opp-hz = /bits/ 64 <680000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <12449218>;
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <12449218>;
+ };
+
+ opp-770000000 {
+ opp-hz = /bits/ 64 <770000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <12449218>;
+ };
+
+ opp-834000000 {
+ opp-hz = /bits/ 64 <834000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <14398437>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x35000>,
+ <0x0 0x03d50000 0x0 0x10000>,
+ <0x0 0x0b280000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_DEMET_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "hub",
+ "demet";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-260000000 {
+ opp-hz = /bits/ 64 <260000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-625000000 {
+ opp-hz = /bits/ 64 <625000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sm8650-gpucc";
reg = <0 0x03d90000 0 0xa000>;
@@ -2559,6 +2821,50 @@
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "hlos",
+ "bus",
+ "iface",
+ "ahb";
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ dma-coherent;
+ };
+
ipa: ipa@3f40000 {
compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
@@ -2600,7 +2906,7 @@
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8650-mpss-pas";
- reg = <0 0x04080000 0 0x4040>;
+ reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2627,7 +2933,8 @@
"mss";
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
- <&mpss_dsm_mem>, <&mpss_dsm_mem_2>;
+ <&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
+ <&qlink_logging_mem>;
qcom,qmp = <&aoss_qmp>;
@@ -2650,6 +2957,154 @@
};
};
+ remoteproc_adsp: remoteproc@6800000 {
+ compatible = "qcom,sm8650-adsp-pas";
+ reg = <0x0 0x06800000 0x0 0x10000>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ remoteproc_adsp_glink: glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <2>;
+
+ label = "lpass";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ label = "adsp";
+
+ qcom,non-secure-domain;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+
+ iommus = <&apps_smmu 0x1003 0x80>,
+ <&apps_smmu 0x1043 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+
+ iommus = <&apps_smmu 0x1004 0x80>,
+ <&apps_smmu 0x1044 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+
+ iommus = <&apps_smmu 0x1005 0x80>,
+ <&apps_smmu 0x1045 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+
+ iommus = <&apps_smmu 0x1006 0x80>,
+ <&apps_smmu 0x1046 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+
+ iommus = <&apps_smmu 0x1007 0x40>,
+ <&apps_smmu 0x1067 0x0>,
+ <&apps_smmu 0x1087 0x0>;
+ dma-coherent;
+ };
+ };
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1061 0x0>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+ };
+ };
+
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06aa0000 0 0x1000>;
@@ -2919,7 +3374,7 @@
};
};
- dmic02_default: dmic02-default-state {
+ dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
@@ -3064,6 +3519,129 @@
};
};
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8650-videocc";
+ reg = <0 0x0aaf0000 0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ cci0: cci@ac15000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac15000 0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac16000 0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac17000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac17000 0 0x1000>;
+ interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci2_0_default &cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,sm8650-camcc";
+ reg = <0 0x0ade0000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8650-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@@ -3078,11 +3656,8 @@
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
- &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
- <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
- interconnect-names = "mdp0-mem",
- "mdp1-mem";
+ interconnect-names = "mdp0-mem";
power-domains = <&dispcc MDSS_GDSC>;
@@ -3430,6 +4005,7 @@
reg = <1>;
mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
};
};
@@ -3463,8 +4039,6 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
-
- status = "disabled";
};
usb_1_hsphy: phy@88e3000 {
@@ -3505,6 +4079,8 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
status = "disabled";
ports {
@@ -3522,6 +4098,7 @@
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -3529,6 +4106,7 @@
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
};
};
};
@@ -3538,14 +4116,16 @@
compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
- <&pdc 14 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -3617,6 +4197,7 @@
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
@@ -3703,7 +4284,7 @@
spmi_bus: spmi@c400000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c400000 0 0x3000>,
- <0 0x0c500000 0 0x4000000>,
+ <0 0x0c500000 0 0x400000>,
<0 0x0c440000 0 0x80000>,
<0 0x0c4c0000 0 0x20000>,
<0 0x0c42d000 0 0x4000>;
@@ -3743,6 +4324,198 @@
wakeup-parent = <&pdc>;
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio12";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio13";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio12";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio13";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio64", "gpio65";
@@ -4279,6 +5052,138 @@
};
};
+ funnel@10042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0x0 0x10042000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+
+ funnel_in1_in_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_out_funnel_in1>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in1_out_funnel_qdss: endpoint {
+ remote-endpoint = <&funnel_qdss_in_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@10045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0x0 0x10045000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ funnel_qdss_in_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_out_funnel_qdss>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_qdss_out_funnel_aoss: endpoint {
+ remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
+ };
+ };
+ };
+ };
+
+ funnel@10b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0x0 0x10b04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+
+ funnel_aoss_in_funnel_qdss: endpoint {
+ remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_aoss_out_tmc_etf: endpoint {
+ remote-endpoint = <&tmc_etf_in_funnel_aoss>;
+ };
+ };
+ };
+ };
+
+ tmc@10b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+
+ reg = <0x0 0x10b05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmc_etf_in_funnel_aoss: endpoint {
+ remote-endpoint = <&funnel_aoss_out_tmc_etf>;
+ };
+ };
+ };
+ };
+
+ funnel@13810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0x0 0x13810000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_apss_in_funnel_ete: endpoint {
+ remote-endpoint = <&funnel_ete_out_funnel_apss>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_apss_out_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_in_funnel_apss>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
@@ -4506,7 +5411,7 @@
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&cluster_pd>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
@@ -4735,157 +5640,18 @@
<0 0x25400000 0 0x200000>,
<0 0x25200000 0 0x200000>,
<0 0x25600000 0 0x200000>,
- <0 0x25800000 0 0x200000>;
+ <0 0x25800000 0 0x200000>,
+ <0 0x25a00000 0 0x200000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
- "llcc_broadcast_base";
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
- remoteproc_adsp: remoteproc@30000000 {
- compatible = "qcom,sm8650-adsp-pas";
- reg = <0 0x30000000 0 0x100>;
-
- interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog",
- "fatal",
- "ready",
- "handover",
- "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-
- power-domains = <&rpmhpd RPMHPD_LCX>,
- <&rpmhpd RPMHPD_LMX>;
- power-domain-names = "lcx",
- "lmx";
-
- memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
-
- qcom,qmp = <&aoss_qmp>;
-
- qcom,smem-states = <&smp2p_adsp_out 0>;
- qcom,smem-state-names = "stop";
-
- status = "disabled";
-
- remoteproc_adsp_glink: glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
-
- mboxes = <&ipcc IPCC_CLIENT_LPASS
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
- qcom,remote-pid = <2>;
-
- label = "lpass";
-
- fastrpc {
- compatible = "qcom,fastrpc";
-
- qcom,glink-channels = "fastrpcglink-apps-dsp";
-
- label = "adsp";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- compute-cb@3 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <3>;
-
- iommus = <&apps_smmu 0x1003 0x80>,
- <&apps_smmu 0x1043 0x20>;
- };
-
- compute-cb@4 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <4>;
-
- iommus = <&apps_smmu 0x1004 0x80>,
- <&apps_smmu 0x1044 0x20>;
- };
-
- compute-cb@5 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <5>;
-
- iommus = <&apps_smmu 0x1005 0x80>,
- <&apps_smmu 0x1045 0x20>;
- };
-
- compute-cb@6 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <6>;
-
- iommus = <&apps_smmu 0x1006 0x80>,
- <&apps_smmu 0x1046 0x20>;
- };
-
- compute-cb@7 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <7>;
-
- iommus = <&apps_smmu 0x1007 0x40>,
- <&apps_smmu 0x1067 0x0>,
- <&apps_smmu 0x1087 0x0>;
- };
- };
-
- gpr {
- compatible = "qcom,gpr";
- qcom,glink-channels = "adsp_apps";
- qcom,domain = <GPR_DOMAIN_ID_ADSP>;
- qcom,intents = <512 20>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- q6apm: service@1 {
- compatible = "qcom,q6apm";
- reg = <GPR_APM_MODULE_IID>;
- #sound-dai-cells = <0>;
- qcom,protection-domain = "avs/audio",
- "msm/adsp/audio_pd";
-
- q6apmbedai: bedais {
- compatible = "qcom,q6apm-lpass-dais";
- #sound-dai-cells = <1>;
- };
-
- q6apmdai: dais {
- compatible = "qcom,q6apm-dais";
- iommus = <&apps_smmu 0x1001 0x80>,
- <&apps_smmu 0x1061 0x0>;
- };
- };
-
- q6prm: service@2 {
- compatible = "qcom,q6prm";
- reg = <GPR_PRM_MODULE_IID>;
- qcom,protection-domain = "avs/audio",
- "msm/adsp/audio_pd";
-
- q6prmcc: clock-controller {
- compatible = "qcom,q6prm-lpass-clocks";
- #clock-cells = <2>;
- };
- };
- };
- };
- };
-
nsp_noc: interconnect@320c0000 {
compatible = "qcom,sm8650-nsp-noc";
reg = <0 0x320c0000 0 0xf080>;
@@ -4897,7 +5663,7 @@
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8650-cdsp-pas";
- reg = <0 0x32300000 0 0x1400000>;
+ reg = <0x0 0x32300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -4951,6 +5717,8 @@
label = "cdsp";
+ qcom,non-secure-domain;
+
#address-cells = <1>;
#size-cells = <0>;
@@ -4961,6 +5729,7 @@
iommus = <&apps_smmu 0x1961 0x0>,
<&apps_smmu 0x0c01 0x20>,
<&apps_smmu 0x19c1 0x0>;
+ dma-coherent;
};
compute-cb@2 {
@@ -4970,6 +5739,7 @@
iommus = <&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x0c02 0x20>,
<&apps_smmu 0x19c2 0x0>;
+ dma-coherent;
};
compute-cb@3 {
@@ -4979,6 +5749,7 @@
iommus = <&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x0c03 0x20>,
<&apps_smmu 0x19c3 0x0>;
+ dma-coherent;
};
compute-cb@4 {
@@ -4988,6 +5759,7 @@
iommus = <&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x0c04 0x20>,
<&apps_smmu 0x19c4 0x0>;
+ dma-coherent;
};
compute-cb@5 {
@@ -4997,6 +5769,7 @@
iommus = <&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x0c05 0x20>,
<&apps_smmu 0x19c5 0x0>;
+ dma-coherent;
};
compute-cb@6 {
@@ -5006,6 +5779,7 @@
iommus = <&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x0c06 0x20>,
<&apps_smmu 0x19c6 0x0>;
+ dma-coherent;
};
compute-cb@7 {
@@ -5015,6 +5789,7 @@
iommus = <&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x0c07 0x20>,
<&apps_smmu 0x19c7 0x0>;
+ dma-coherent;
};
compute-cb@8 {
@@ -5024,6 +5799,39 @@
iommus = <&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x0c08 0x20>,
<&apps_smmu 0x19c8 0x0>;
+ dma-coherent;
+ };
+
+ /* note: secure cb9 in downstream */
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+
+ iommus = <&apps_smmu 0x196c 0x0>,
+ <&apps_smmu 0x0c0c 0x20>,
+ <&apps_smmu 0x19cc 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+
+ iommus = <&apps_smmu 0x196d 0x0>,
+ <&apps_smmu 0x0c0d 0x20>,
+ <&apps_smmu 0x19cd 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@14 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <14>;
+
+ iommus = <&apps_smmu 0x196e 0x0>,
+ <&apps_smmu 0x0c0e 0x20>,
+ <&apps_smmu 0x19ce 0x0>;
+ dma-coherent;
};
};
};
@@ -5032,8 +5840,6 @@
thermal-zones {
aoss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
@@ -5052,8 +5858,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
@@ -5072,8 +5876,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
@@ -5092,8 +5894,6 @@
};
cpuss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
@@ -5112,8 +5912,6 @@
};
cpuss3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
@@ -5132,8 +5930,6 @@
};
cpu2-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
@@ -5158,8 +5954,6 @@
};
cpu2-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
@@ -5184,8 +5978,6 @@
};
cpu3-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
@@ -5210,8 +6002,6 @@
};
cpu3-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
@@ -5236,8 +6026,6 @@
};
cpu4-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
@@ -5262,8 +6050,6 @@
};
cpu4-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
@@ -5288,8 +6074,6 @@
};
cpu5-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
@@ -5314,8 +6098,6 @@
};
cpu5-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
@@ -5340,8 +6122,6 @@
};
cpu6-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
@@ -5366,8 +6146,6 @@
};
cpu6-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
@@ -5392,8 +6170,6 @@
};
aoss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
@@ -5412,8 +6188,6 @@
};
cpu7-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
@@ -5438,8 +6212,6 @@
};
cpu7-middle-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
@@ -5464,8 +6236,6 @@
};
cpu7-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
@@ -5490,8 +6260,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
trips {
@@ -5516,8 +6284,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
trips {
@@ -5543,7 +6309,7 @@
nsphvx0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
trips {
@@ -5563,7 +6329,7 @@
nsphvx1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
trips {
@@ -5583,7 +6349,7 @@
nsphmx0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 8>;
trips {
@@ -5603,7 +6369,7 @@
nsphmx1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 9>;
trips {
@@ -5623,7 +6389,7 @@
nsphmx2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 10>;
trips {
@@ -5643,7 +6409,7 @@
nsphmx3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 11>;
trips {
@@ -5663,7 +6429,7 @@
video-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 12>;
trips {
@@ -5683,7 +6449,7 @@
ddr-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 13>;
trips {
@@ -5702,8 +6468,6 @@
};
camera0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 14>;
trips {
@@ -5722,8 +6486,6 @@
};
camera1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 15>;
trips {
@@ -5742,8 +6504,6 @@
};
aoss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 0>;
trips {
@@ -5763,19 +6523,32 @@
gpuss0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 1>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu0_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss0-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5783,19 +6556,32 @@
gpuss1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu1_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss1-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5803,19 +6589,32 @@
gpuss2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 3>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu2_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu2_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss2-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5823,19 +6622,32 @@
gpuss3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 4>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu3_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu3_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss3-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5843,19 +6655,32 @@
gpuss4-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 5>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu4_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu4_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss4-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5863,19 +6688,32 @@
gpuss5-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu5_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu5_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss5-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5883,19 +6721,32 @@
gpuss6-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu6_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu6_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss6-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -5903,27 +6754,38 @@
gpuss7-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 8>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu7_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu7_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss7-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
};
modem0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 9>;
trips {
@@ -5942,8 +6804,6 @@
};
modem1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 10>;
trips {
@@ -5962,8 +6822,6 @@
};
modem2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 11>;
trips {
@@ -5982,8 +6840,6 @@
};
modem3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 12>;
trips {
generated by cgit (git 2.34.1) at 2025-07-24 06:19:05 +0000