diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g043u.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 143 |
1 files changed, 134 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 2ab231572d95..a3998e5928f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -50,17 +50,134 @@ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; }; -&pinctrl { - interrupt-parent = <&irqc>; -}; - &soc { interrupt-parent = <&gic>; + cru: video@10830000 { + compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>, + <&cpg CPG_MOD R9A07G043_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + + vspd: vsp@10870000 { + compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + }; + + du: display@10890000 { + compatible = "renesas,r9a07g043u-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; @@ -109,7 +226,13 @@ <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>; + <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -121,7 +244,9 @@ "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", "tint28", "tint29", "tint30", "tint31", - "bus-err"; + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, <&cpg CPG_MOD R9A07G043_IA55_PCLK>; clock-names = "clk", "pclk"; @@ -134,8 +259,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; }; |