diff options
Diffstat (limited to 'arch/arm64/boot/dts/sprd')
-rw-r--r-- | arch/arm64/boot/dts/sprd/Makefile | 5 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/sc9836.dtsi | 10 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/sc9863a.dtsi | 589 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/sharkl3.dtsi | 242 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/sp9863a-1h10.dts | 39 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/ums512-1h10.dts | 61 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/ums512.dtsi | 912 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/ums9620-2h10.dts | 38 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/ums9620.dtsi | 245 | ||||
-rw-r--r-- | arch/arm64/boot/dts/sprd/whale2.dtsi | 6 |
10 files changed, 2140 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile index 2bdc23804f40..3ce81ad7116f 100644 --- a/arch/arm64/boot/dts/sprd/Makefile +++ b/arch/arm64/boot/dts/sprd/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ - sp9860g-1h10.dtb + sp9860g-1h10.dtb \ + sp9863a-1h10.dtb \ + ums512-1h10.dtb \ + ums9620-2h10.dtb diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index 231436be0e3f..8bb8a70966d2 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -207,11 +207,11 @@ }; psci { - compatible = "arm,psci"; - method = "smc"; - cpu_on = <0xc4000003>; - cpu_off = <0x84000002>; - cpu_suspend = <0xc4000001>; + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; }; timer { diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi new file mode 100644 index 000000000000..22d81ace740a --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Unisoc SC9863A SoC DTS file + * + * Copyright (C) 2019, Unisoc Inc. + */ + +#include <dt-bindings/clock/sprd,sc9863a-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "sharkl3.dtsi" + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + }; + + idle-states { + entry-method = "psci"; + CORE_PD: core-pd { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + gic: interrupt-controller@14000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + reg = <0x0 0x14000000 0 0x20000>, /* GICD */ + <0x0 0x14040000 0 0x100000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + ap_clk: clock-controller@21500000 { + compatible = "sprd,sc9863a-ap-clk"; + reg = <0 0x21500000 0 0x1000>; + clocks = <&ext_32k>, <&ext_26m>; + clock-names = "ext-32k", "ext-26m"; + #clock-cells = <1>; + }; + + aon_clk: clock-controller@402d0000 { + compatible = "sprd,sc9863a-aon-clk"; + reg = <0 0x402d0000 0 0x1000>; + clocks = <&ext_26m>, <&rco_100m>, + <&ext_32k>, <&ext_4m>; + clock-names = "ext-26m", "rco-100m", + "ext-32k", "ext-4m"; + #clock-cells = <1>; + }; + + mm_clk: clock-controller@60900000 { + compatible = "sprd,sc9863a-mm-clk"; + reg = <0 0x60900000 0 0x1000>; + #clock-cells = <1>; + }; + + funnel@10001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x10001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_soc_out_port: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + + in-ports { + port { + funnel_soc_in_port: endpoint { + remote-endpoint = + <&funnel_ca55_out_port>; + }; + }; + }; + }; + + etb@10003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x10003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = + <&funnel_soc_out_port>; + }; + }; + }; + }; + + funnel@12001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x12001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_little_out_port: endpoint { + remote-endpoint = + <&etf_little_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_little_in_port0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_little_in_port1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_little_in_port2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_little_in_port3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + }; + + etf@12002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x12002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_little_out: endpoint { + remote-endpoint = + <&funnel_ca55_in_port0>; + }; + }; + }; + + in-port { + port { + etf_little_in: endpoint { + remote-endpoint = + <&funnel_little_out_port>; + }; + }; + }; + }; + + etf@12003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x12003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_big_out: endpoint { + remote-endpoint = + <&funnel_ca55_in_port1>; + }; + }; + }; + + in-ports { + port { + etf_big_in: endpoint { + remote-endpoint = + <&funnel_big_out_port>; + }; + }; + }; + }; + + funnel@12004000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x12004000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ca55_out_port: endpoint { + remote-endpoint = + <&funnel_soc_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ca55_in_port0: endpoint { + remote-endpoint = + <&etf_little_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_ca55_in_port1: endpoint { + remote-endpoint = + <&etf_big_out>; + }; + }; + }; + }; + + funnel@12005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x12005000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_big_out_port: endpoint { + remote-endpoint = + <&etf_big_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_big_in_port0: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_big_in_port1: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_big_in_port2: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_big_in_port3: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + etm@13040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13040000 0 0x1000>; + cpu = <&CPU0>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&funnel_little_in_port0>; + }; + }; + }; + }; + + etm@13140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13140000 0 0x1000>; + cpu = <&CPU1>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&funnel_little_in_port1>; + }; + }; + }; + }; + + etm@13240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13240000 0 0x1000>; + cpu = <&CPU2>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&funnel_little_in_port2>; + }; + }; + }; + }; + + etm@13340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13340000 0 0x1000>; + cpu = <&CPU3>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&funnel_little_in_port3>; + }; + }; + }; + }; + + etm@13440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13440000 0 0x1000>; + cpu = <&CPU4>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&funnel_big_in_port0>; + }; + }; + }; + }; + + etm@13540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13540000 0 0x1000>; + cpu = <&CPU5>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&funnel_big_in_port1>; + }; + }; + }; + }; + + etm@13640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13640000 0 0x1000>; + cpu = <&CPU6>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&funnel_big_in_port2>; + }; + }; + }; + }; + + etm@13740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13740000 0 0x1000>; + cpu = <&CPU7>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&funnel_big_in_port3>; + }; + }; + }; + }; + + ap-ahb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdio0: sdio@20300000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_SDIO0_2X>, + <&apahb_gate CLK_SDIO0_EB>; + assigned-clocks = <&aon_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <4>; + no-sdio; + no-mmc; + }; + + sdio3: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&aon_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi new file mode 100644 index 000000000000..206a4afdab1c --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Unisoc Sharkl3 platform DTS file + * + * Copyright (C) 2019, Unisoc Inc. + */ + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ap_ahb_regs: syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x20e00000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20e00000 0x4000>; + + apahb_gate: apahb-gate { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + + pmu_regs: syscon@402b0000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x402b0000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x402b0000 0x4000>; + + pmu_gate: pmu-gate { + compatible = "sprd,sc9863a-pmu-gate"; + reg = <0 0x1200>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + aon_apb_regs: syscon@402e0000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x402e0000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x402e0000 0x4000>; + + aonapb_gate: aonapb-gate { + compatible = "sprd,sc9863a-aonapb-gate"; + reg = <0 0x1100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g2_regs: syscon@40353000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40353000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40353000 0x3000>; + + pll: pll { + compatible = "sprd,sc9863a-pll"; + reg = <0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g4_regs: syscon@40359000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40359000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40359000 0x3000>; + + mpll: mpll { + compatible = "sprd,sc9863a-mpll"; + reg = <0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g5_regs: syscon@4035c000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x4035c000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4035c000 0x3000>; + + rpll: rpll { + compatible = "sprd,sc9863a-rpll"; + reg = <0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g7_regs: syscon@40363000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40363000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40363000 0x3000>; + + dpll: dpll { + compatible = "sprd,sc9863a-dpll"; + reg = <0 0x100>; + #clock-cells = <1>; + }; + }; + + mm_ahb_regs: syscon@60800000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60800000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60800000 0x3000>; + + mm_gate: mm-gate { + compatible = "sprd,sc9863a-mm-gate"; + reg = <0 0x1100>; + #clock-cells = <1>; + }; + }; + + ap_apb_regs: syscon@71300000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x71300000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x71300000 0x4000>; + + apapb_gate: apapb-gate { + compatible = "sprd,sc9863a-apapb-gate"; + reg = <0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + apb@70000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x70000000 0x10000000>; + + uart0: serial@0 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@100000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x100000 0x100>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart2: serial@200000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x200000 0x100>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart3: serial@300000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x300000 0x100>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart4: serial@400000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x400000 0x100>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + }; + }; + + ext_26m: ext-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_32k: ext-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_4m: ext-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + rco_100m: rco-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts new file mode 100644 index 000000000000..5c32c1596337 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Unisoc SP9863A-1h10 boards DTS file + * + * Copyright (C) 2019, Unisoc Inc. + */ + +/dts-v1/; + +#include "sc9863a.dtsi" + +/ { + model = "Spreadtrum SP9863A-1H10 Board"; + + compatible = "sprd,sp9863a-1h10", "sprd,sc9863a"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + bootargs = "earlycon"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/sprd/ums512-1h10.dts b/arch/arm64/boot/dts/sprd/ums512-1h10.dts new file mode 100644 index 000000000000..46890f6d140d --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums512-1h10.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS512-1h10 boards DTS file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +/dts-v1/; + +#include "ums512.dtsi" + +/ { + model = "Unisoc UMS512-1H10 Board"; + + compatible = "sprd,ums512-1h10", "sprd,ums512"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* SD card */ +&sdio0 { + bus-width = <4>; + no-sdio; + no-mmc; + sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>; + sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>; + sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>; + sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>; + sd-uhs-sdr104; + sd-uhs-sdr50; +}; + +/* EMMC storage */ +&sdio3 { + status = "okay"; + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + cap-mmc-hw-reset; +}; diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi new file mode 100644 index 000000000000..dbdb79f8e959 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS512 SoC DTS file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +#include <dt-bindings/clock/sprd,ums512-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + }; + + idle-states { + entry-method = "psci"; + CORE_PD: cpu-pd { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@12000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x12000000 0 0x20000>, /* GICD */ + <0x0 0x12040000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + ap_ahb_regs: syscon@20100000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x20100000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20100000 0x4000>; + + apahb_gate: clock-controller@0 { + compatible = "sprd,ums512-apahb-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + pub_apb_regs: syscon@31050000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x31050000 0 0x9000>; + }; + + top_dvfs_apb_regs: syscon@322a0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x322a0000 0 0x8000>; + }; + + ap_intc0_regs: syscon@32310000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32310000 0 0x1000>; + }; + + ap_intc1_regs: syscon@32320000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32320000 0 0x1000>; + }; + + ap_intc2_regs: syscon@32330000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32330000 0 0x1000>; + }; + + ap_intc3_regs: syscon@32340000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32340000 0 0x1000>; + }; + + ap_intc4_regs: syscon@32350000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32350000 0 0x1000>; + }; + + ap_intc5_regs: syscon@32360000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32360000 0 0x1000>; + }; + + anlg_phy_g0_regs: syscon@32390000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32390000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x32390000 0x3000>; + + dpll0: clock-controller@0 { + compatible = "sprd,ums512-g0-pll"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g2_regs: syscon@323b0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323b0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323b0000 0x3000>; + + mpll1: clock-controller@0 { + compatible = "sprd,ums512-g2-pll"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g3_regs: syscon@323c0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323c0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323c0000 0x3000>; + + pll1: clock-controller@0 { + compatible = "sprd,ums512-g3-pll"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_gc_regs: syscon@323e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323e0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323e0000 0x3000>; + + pll2: clock-controller@0 { + compatible = "sprd,ums512-gc-pll"; + reg = <0x0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g10_regs: syscon@323f0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323f0000 0 0x3000>; + }; + + aon_apb_regs: syscon@327d0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x327d0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x327d0000 0x3000>; + + aonapb_gate: clock-controller@0 { + compatible = "sprd,ums512-aon-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + pmu_apb_regs: syscon@327e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x327e0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x327e0000 0x3000>; + + pmu_gate: clock-controller@0 { + compatible = "sprd,ums512-pmu-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + audcp_apb_regs: syscon@3350d000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x3350d000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x3350d000 0x1000>; + + audcpapb_gate: clock-controller@0 { + compatible = "sprd,ums512-audcpapb-gate"; + reg = <0x0 0x300>; + #clock-cells = <1>; + }; + }; + + audcp_ahb_regs: syscon@335e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x335e0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x335e0000 0x1000>; + + audcpahb_gate: clock-controller@0 { + compatible = "sprd,ums512-audcpahb-gate"; + reg = <0x0 0x300>; + #clock-cells = <1>; + }; + }; + + gpu_apb_regs: syscon@60100000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60100000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60100000 0x3000>; + + gpu_clk: clock-controller@0 { + compatible = "sprd,ums512-gpu-clk"; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + gpu_dvfs_apb_regs: syscon@60110000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60110000 0 0x3000>; + }; + + mm_ahb_regs: syscon@62200000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x62200000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x62200000 0x3000>; + + mm_gate: clock-controller@0 { + compatible = "sprd,ums512-mm-gate-clk"; + reg = <0x0 0x3000>; + #clock-cells = <1>; + }; + }; + + ap_apb_regs: syscon@71000000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x71000000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x71000000 0x3000>; + + apapb_gate: clock-controller@0 { + compatible = "sprd,ums512-apapb-gate"; + reg = <0x0 0x3000>; + #clock-cells = <1>; + }; + }; + + ap_clk: clock-controller@20200000 { + compatible = "sprd,ums512-ap-clk"; + reg = <0 0x20200000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + + aon_clk: clock-controller@32080000 { + compatible = "sprd,ums512-aonapb-clk"; + reg = <0 0x32080000 0 0x1000>; + clocks = <&ext_26m>, <&ext_32k>, + <&ext_4m>, <&rco_100m>; + clock-names = "ext-26m", "ext-32k", + "ext-4m", "rco-100m"; + #clock-cells = <1>; + }; + + mm_clk: clock-controller@62100000 { + compatible = "sprd,ums512-mm-clk"; + reg = <0 0x62100000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + + /* SoC Funnel */ + funnel@3c002000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3c002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_soc_out_port: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_soc_in_port: endpoint { + remote-endpoint = + <&funnel_corinth_out_port>; + }; + }; + }; + }; + + /* SoC ETF */ + soc_etb: etb@3c003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3c003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = + <&funnel_soc_out_port>; + }; + }; + }; + }; + + /* AP-CPU Funnel for core3/4/5/7 */ + funnel@3e001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_lit_out_port: endpoint { + remote-endpoint = + <&corinth_etf_lit_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_core_in_port3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_core_in_port4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_core_in_port5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_core_in_port7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + /* AP-CPU ETF for little cores */ + etf@3e002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3e002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + corinth_etf_lit_out: endpoint { + remote-endpoint = + <&funnel_corinth_from_lit_in_port>; + }; + }; + }; + + in-ports { + port { + corinth_etf_lit_in: endpoint { + remote-endpoint = + <&funnel_corinth_lit_out_port>; + }; + }; + }; + }; + + /* AP-CPU ETF for big cores */ + etf@3e003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3e003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + corinth_etf_big_out: endpoint { + remote-endpoint = + <&funnel_corinth_from_big_in_port>; + }; + }; + }; + + in-ports { + port { + corinth_etf_big_in: endpoint { + remote-endpoint = + <&funnel_corinth_big_out_port>; + }; + }; + }; + }; + + /* Funnel to SoC */ + funnel@3e004000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e004000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_out_port: endpoint { + remote-endpoint = + <&funnel_soc_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_corinth_from_lit_in_port: endpoint { + remote-endpoint = <&corinth_etf_lit_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_corinth_from_big_in_port: endpoint { + remote-endpoint = <&corinth_etf_big_out>; + }; + }; + }; + }; + + /* AP-CPU Funnel for core0/1/2/6 */ + funnel@3e005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e005000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_big_out_port: endpoint { + remote-endpoint = <&corinth_etf_big_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_core_in_port0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_core_in_port1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_core_in_port2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_core_in_port6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + }; + }; + + etm0: etm@3f040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f040000 0 0x1000>; + cpu = <&CPU0>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&funnel_core_in_port0>; + }; + }; + }; + }; + + etm1: etm@3f140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f140000 0 0x1000>; + cpu = <&CPU1>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&funnel_core_in_port1>; + }; + }; + }; + }; + + etm2: etm@3f240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f240000 0 0x1000>; + cpu = <&CPU2>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&funnel_core_in_port2>; + }; + }; + }; + }; + + etm3: etm@3f340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f340000 0 0x1000>; + cpu = <&CPU3>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&funnel_core_in_port3>; + }; + }; + }; + }; + + etm4: etm@3f440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f440000 0 0x1000>; + cpu = <&CPU4>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&funnel_core_in_port4>; + }; + }; + }; + }; + + etm5: etm@3f540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f540000 0 0x1000>; + cpu = <&CPU5>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&funnel_core_in_port5>; + }; + }; + }; + }; + + etm6: etm@3f640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f640000 0 0x1000>; + cpu = <&CPU6>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&funnel_core_in_port6>; + }; + }; + }; + }; + + etm7: etm@3f740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f740000 0 0x1000>; + cpu = <&CPU7>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&funnel_core_in_port7>; + }; + }; + }; + }; + + apb@70000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x70000000 0x10000000>; + + uart0: serial@0 { + compatible = "sprd,ums512-uart", + "sprd,sc9836-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@100000 { + compatible = "sprd,ums512-uart", + "sprd,sc9836-uart"; + reg = <0x100000 0x100>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + sdio0: mmc@1100000 { + compatible = "sprd,sdhci-r11"; + reg = <0x1100000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_SDIO0_2X>, + <&apapb_gate CLK_SDIO0_EB>; + assigned-clocks = <&ap_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&pll1 CLK_RPLL>; + status = "disabled"; + }; + + sdio3: mmc@1400000 { + compatible = "sprd,sdhci-r11"; + reg = <0x1400000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apapb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&pll1 CLK_RPLL>; + status = "disabled"; + }; + }; + + aon: bus@32000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x32000000 0x1000000>; + + adi_bus: spi@100000 { + compatible = "sprd,ums512-adi"; + reg = <0x100000 0x100000>; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>, + <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>, + <35 0x19b8>, <39 0x19ac>; + }; + }; + }; + + ext_26m: clk-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_32k: clk-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_4m: clk-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + rco_100m: clk-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/ums9620-2h10.dts b/arch/arm64/boot/dts/sprd/ums9620-2h10.dts new file mode 100644 index 000000000000..b35671192a72 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums9620-2h10.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS9620-2h10 board DTS file + * + * Copyright (C) 2023, Unisoc Inc. + */ + +/dts-v1/; + +#include "ums9620.dtsi" + +/ { + model = "Unisoc UMS9620-2H10 Board"; + + compatible = "sprd,ums9620-2h10", "sprd,ums9620"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + chosen { + stdout-path = "serial1:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/sprd/ums9620.dtsi b/arch/arm64/boot/dts/sprd/ums9620.dtsi new file mode 100644 index 000000000000..2191f0a4811b --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums9620.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS9620 DTS file + * + * Copyright (C) 2023, Unisoc Inc. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + }; + + idle-states { + entry-method = "psci"; + LIT_CORE_PD: cpu-pd-lit { + compatible = "arm,idle-state"; + entry-latency-us = <1000>; + exit-latency-us = <500>; + min-residency-us = <2500>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + + BIG_CORE_PD: cpu-pd-big { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc: soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@12000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x12000000 0 0x20000>, /* GICD */ + <0x0 0x12040000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + apb@20200000 { + compatible = "simple-bus"; + ranges = <0 0 0x20200000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@0 { + compatible = "sprd,ums9620-uart", + "sprd,sc9836-uart"; + reg = <0 0x100>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@10000 { + compatible = "sprd,ums9620-uart", + "sprd,sc9836-uart"; + reg = <0x10000 0x100>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_26m>; + status = "disabled"; + }; + }; + }; + + ext_26m: clk-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_4m: clk-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + ext_32k: clk-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + rco_100m: clk-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; + + dphy_312m5: dphy-312m5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <312500000>; + clock-output-names = "dphy-312m5"; + }; + + dphy_416m7: dphy-416m7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <416700000>; + clock-output-names = "dphy-416m7"; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 79b9591c37aa..fece49704b5c 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -126,13 +126,15 @@ reg = <0 0x20100000 0 0x4000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; + /* For backwards compatibility: */ #dma-channels = <32>; + dma-channels = <32>; clock-names = "enable"; clocks = <&apahb_gate CLK_DMA_EB>; }; sdio3: sdio@50430000 { - compatible = "sprd,sdhci-r11"; + compatible = "sprd,sdhci-r11"; reg = <0 0x50430000 0 0x1000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; @@ -272,7 +274,9 @@ compatible = "sprd,sc9860-dma"; reg = <0 0x41580000 0 0x4000>; #dma-cells = <1>; + /* For backwards compatibility: */ #dma-channels = <32>; + dma-channels = <32>; clock-names = "enable", "ashb_eb"; clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, <&agcp_gate CLK_AGCP_AP_ASHB_EB>; |