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-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi271
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diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
new file mode 100644
index 000000000000..ccaca29200bb
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+/ {
+ pss_ref_clk: pss_ref_clk {
+ bootph-all;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ video_clk: video_clk {
+ bootph-all;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ pss_alt_ref_clk: pss_alt_ref_clk {
+ bootph-all;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ gt_crx_ref_clk: gt_crx_ref_clk {
+ bootph-all;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <108000000>;
+ };
+
+ aux_ref_clk: aux_ref_clk {
+ bootph-all;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+&zynqmp_firmware {
+ zynqmp_clk: clock-controller {
+ bootph-all;
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
+ <&aux_ref_clk>, <&gt_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
+ "aux_ref_clk", "gt_crx_ref_clk";
+ };
+};
+
+&can0 {
+ clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&can1 {
+ clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&cpu0 {
+ clocks = <&zynqmp_clk ACPU>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&gpu {
+ clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&nand0 {
+ clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&gem0 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
+ <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
+};
+
+&gem1 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+ <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
+};
+
+&gem2 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
+ <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
+};
+
+&gem3 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
+ <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
+};
+
+&gpio {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&i2c0 {
+ clocks = <&zynqmp_clk I2C0_REF>;
+};
+
+&i2c1 {
+ clocks = <&zynqmp_clk I2C1_REF>;
+};
+
+&pcie {
+ clocks = <&zynqmp_clk PCIE_REF>;
+};
+
+&qspi {
+ clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&sata {
+ clocks = <&zynqmp_clk SATA_REF>;
+};
+
+&sdhci0 {
+ clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+ assigned-clocks = <&zynqmp_clk SDIO0_REF>;
+};
+
+&sdhci1 {
+ clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+ assigned-clocks = <&zynqmp_clk SDIO1_REF>;
+};
+
+&spi0 {
+ clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&spi1 {
+ clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc0 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc1 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc2 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc3 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&uart0 {
+ clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&uart1 {
+ clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&dwc3_0 {
+ clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&dwc3_1 {
+ clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&watchdog0 {
+ clocks = <&zynqmp_clk WDT>;
+};
+
+&lpd_watchdog {
+ clocks = <&zynqmp_clk LPD_WDT>;
+};
+
+&xilinx_ams {
+ clocks = <&zynqmp_clk AMS_REF>;
+};
+
+&zynqmp_dpdma {
+ clocks = <&zynqmp_clk DPDMA_REF>;
+ assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
+};
+
+&zynqmp_dpsub {
+ clocks = <&zynqmp_clk TOPSW_LSBUS>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+ assigned-clocks = <&zynqmp_clk DP_STC_REF>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
+};